JP6586247B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus.

  In an electronic endoscope or an electronic endoscope system, image data acquired by an image sensor is transmitted and processed. The processing of the image data is executed by, for example, an embedded clock method that is a cheap algorithm using clock embedding in addition to a high-speed serial transfer method using an encoding algorithm such as 8b / 10b.

  In the embedded clock method, a data bit string that is packetized including a start bit and an end bit is transmitted, and on the receiving side, a data decoding process that removes the start bit and the end bit according to a word alignment pattern suitable for the data bit string ( Word alignment processing) is executed. A data decoding circuit (word alignment circuit) that executes data decoding processing (word alignment processing) is mounted, for example, in a user area of an FPGA (Field Programmable Gate Array).

JP 2009-201540 A JP 2014-110443 A JP 2014-110855 A

  In such data decoding processing (word alignment processing), it is necessary to accurately detect the synchronization code from the data to be processed and output reliable data (word aligned data).

  The present disclosure has been made in view of such a situation, and provides a data processing technique that can accurately perform data decoding processing (word alignment processing) and improve data quality.

  In order to solve the above-described problem, the data processing apparatus according to the present embodiment receives a data bit string, an oversampling unit that oversamples and outputs each data bit of the data bit string, and each data bit string after oversampling. A demodulator that demodulates the data bit sequence after oversampling by selecting a part of the data bits, a data holding unit that has at least a bit width corresponding to the word alignment pattern of the data bit sequence and stores the data bit sequence, and data While the data bit string is shifted in the holding unit, the synchronization code detection unit that detects the synchronization code from the word alignment pattern by comparing the word alignment pattern and the synchronization code, and the word alignment locked state according to the synchronization code The day And a word alignment processor removing the start bit and the end bit from the bit string.

Further features related to the present disclosure will become apparent from the description of the present specification and the accompanying drawings. In addition, the present disclosure is achieved and realized by elements and combinations of various elements and the following detailed description and appended claims.
It should be understood that the description herein is merely exemplary and is not intended to limit the scope of the claims or the application in any way.

  According to the present disclosure, data decoding processing (word alignment processing) can be performed with high accuracy, and data quality can be improved.

It is a conceptual diagram which shows an example of the format of the image data input into the data processor by embodiment. It is a block diagram showing an example of composition of data processor 1 of a 1st embodiment. 3 is a conceptual diagram illustrating an example of oversampling by an oversampling unit 10. FIG. 3 is a conceptual diagram illustrating an example of demodulation of a data bit string after oversampling by an edge selection circuit 20. FIG. 6 is a first conceptual diagram illustrating an example of data input / output processing by an output data generation unit 30. FIG. 6 is a second conceptual diagram illustrating an example of data input / output processing by the output data generation unit 30. FIG. FIG. 10 is a third conceptual diagram illustrating an example of data input / output processing by the output data generation unit 30. 6 is a first conceptual diagram illustrating an example of a shift concatenated data bit string (a demodulated data bit string) held by a data holding unit 40. FIG. Second conceptual diagram showing an example of a shift concatenated data bit string (demodulated data bit string) held by the data holding unit 40 (a schematic diagram of a shift register in which 22-bit data output from the output data generating unit is held in the data holding unit) Figure). It is a conceptual diagram which shows the example which a data selection pattern changes by a bit shift process. 4 is a conceptual diagram illustrating an example of a steady state by an error detection unit 80. FIG. It is a conceptual diagram which shows an example of the bit excessive state by the error detection part 80, respectively. It is a conceptual diagram which shows an example of the bit shortage state by the error detection part 80, respectively. It is a conceptual diagram which shows an example of the bit indefinite state by the error detection part 80, respectively. It is a flowchart which shows an example of the data processing by the data processing apparatus 1 of 1st Embodiment. 5 is a flowchart showing bit excess processing by an error detection unit 80. 5 is a flowchart showing a bit shortage process by an error detection unit 80. It is a block diagram which shows the structural example of the data processor 2 by 2nd Embodiment. It is a conceptual diagram which shows an example of the shift connection data bit sequence which data holding | maintenance part 40 'hold | maintains. It is a conceptual diagram (1) which shows an example of the AV code detection pattern by the AV code detection part. It is a conceptual diagram (2) which shows an example of the AV code detection pattern by the AV code detection part. It is a conceptual diagram which shows an example of selection and extraction of the shift connection data bit string which data holding | maintenance part 40 'hold | maintains, the AV code detection pattern by AV code detection part 50, and the word alignment pattern (AV code) by a data selection part. FIG. 18A is a conceptual diagram showing an example of selection and extraction of the shift concatenated data bit string held by the data holding unit 40 ′, the AV code detection pattern by the AV code detection unit 50, and the word alignment pattern (AV code) by the data selection unit (FIG. 18A). (Continued)

(1) First Embodiment In the data decoding process (word alignment process) described above, each data bit of the data bit string is oversampled and output, and a part of each data bit of the data bit string after the oversampling is selected. As a result, the data bit string after oversampling may be demodulated. For example, an adjacent 2-bit data bit string is oversampled by a factor of 4 to obtain an 8-bit data bit string, and a relatively reliable 2-bit data bit string obtained by removing the edge portion from the 8-bit data bit string is selected. The However, in the conventional data decoding process (word alignment process), in a series of processes from oversampling to demodulation of a data bit string, an erroneous bit (bit error) is caused by the influence of jitter and noise between the transmitting device and the receiving device. Excessive or inadequate) may occur. In this case, correct data decoding processing (word alignment processing) becomes difficult, and deterioration of data quality cannot be avoided.

  The first embodiment is, for example, a data processing apparatus 1 that is built in an electronic endoscope (not shown) and that processes image data acquired by an imaging device (not shown), and oversampling a data bit string. Provided is a data processing device capable of reducing the influence of jitter and noise in a series of processes from to demodulation and performing correct data decoding processing (word alignment processing) to improve data quality. For example, the data processing apparatus 1 detects, for example, a synchronization code from output data and performs word alignment processing, detects an error from the word aligned data, eliminates the influence of the error, and performs word aligned data (start Bit and end bit (SE bit) are excluded). According to the data processing device 1 of the first embodiment, in a series of processing from oversampling of a data bit string to demodulation, the influence of jitter and noise is reduced, and correct data decoding processing (word alignment processing) is performed. Data quality can be improved.

<Configuration example of image data to be decoded>
FIG. 1 shows an example of the format of image data to be demodulated that is input to the data processing apparatus 1 of the present embodiment. The image data in FIG. 1 is transmitted, for example, in the LVDS format (serial data). The image data is packetized by embedding a start bit (S) and an end bit (E) of 1 bit at the beginning and end of a 20-bit data bit string (D0, D1,..., D18, D19). As a unit, this is continuous over a plurality of cycles. That is, in each cycle, a 20-bit data bit string is divided by a start bit and an end bit, thereby defining a word boundary. Such image data is, for example, data generated in an image sensor such as a CMOS or CCD or its processing unit (transmission side).

  The start bit (S) and the end bit (E) are also called synchronous clocks. The data value of the start bit is represented by “1” and the data value of the end bit is represented by “0”. Pixel data can be extracted on the receiving side by detecting and removing transition edges of the start bit and end bit signals having a constant period.

  Embedding of the start bit (S) and the end bit (E) can be executed by, for example, a bit count by a counter on the transmission side or an output selection operation by a selector. Specifically, every time 20 bits of serial pixel data to be transmitted are counted, a synchronous clock is output from the edge output unit and bit data is inserted, thereby generating embedded clock serial data. This serial data is transmitted at a high transmission rate (for example, 600 Mbps).

<Configuration example of data processing device>
FIG. 2 is a diagram illustrating a schematic configuration example of the data processing apparatus 1 according to the present embodiment. As shown in FIG. 2, the data processing apparatus 1 includes an oversampling unit 10, an edge selection circuit (demodulation unit) 20, an output data generation unit 30, a data holding unit 40, and an AV code detection unit (synchronization code detection). Section) 50, an alignment selection signal output section 60, a data selection section (word alignment processing section) 70, and an error detection section 80.

  A data bit string (FIG. 1) of image data is input to the oversampling unit 10. The oversampling unit 10 oversamples and outputs each data bit of the input data bit string. For example, the oversampling unit 10 executes the oversampling process by setting an integer multiple of the input serial data rate for the receiver.

  The edge selection circuit 20 demodulates the data bit sequence after oversampling by selecting a part of each data bit of the data bit sequence after oversampling by the oversampling unit 10. The edge selection circuit 20 demodulates the data bit string after oversampling, for example, by selecting 2-bit data from 8-bit data obtained by multiplying the data bit (D0) and the data bit (D1) by four. .

  The output data generation unit 30 constitutes a “RAM I / F unit” and a “data enable generation unit”. Although not shown, a RAM is provided between the edge selection circuit 20 and the output data generation unit 30 in FIG. 2 in which data from the edge selection circuit 20 is written and data is read by the output data generation unit 30. ing. The RAM I / F unit accesses this RAM, delivers the data acquired from the RAM to the data enable generation unit, acquires a data enable signal from the data enable generation unit, and shift-concatenated data bit string (see FIG. 7), A function of transmitting to the data holding unit 40 is provided. Further, the data enable generation unit has a function of generating a later-stage data enable signal described later (FIG. 7).

The data holding unit 40 is composed of, for example, a shift register, and holds data acquired from the output data generation unit in the shift register. The data holding unit 40 transmits the held data to the AV code detection unit 50 and the data selection unit 70.
The AV code detection unit 50 detects an AV code (synchronization code) corresponding to the word alignment pattern in the demodulated image data.

  The alignment selection signal output unit 60 generates and outputs an alignment selection signal corresponding to the AV code (synchronization code) detected by the AV code detection unit (synchronization code detection unit) 50.

  The data selection unit (word alignment processing unit) 70 extracts one word alignment pattern optimum for word alignment processing from the data held by the data holding unit 40 based on the alignment selection signal.

  The error detection unit 80 detects an error in word alignment processing by the data selection unit (word alignment processing unit) 70 and outputs the result to the alignment selection signal output unit 60.

  The data holding unit 40, AV code detection unit 50, alignment selection signal output unit 60, and data selection unit (word alignment processing unit) 70 are data received from the output data generation unit (RAM I / F unit) 30. The “core circuit section” for performing alignment is configured.

<Oversampling process>
FIG. 3 is a diagram for explaining an overview of oversampling processing by the oversampling unit 10. FIG. 3 shows, as an example, a case where output data of 4 Gbps is obtained by setting the sampling clock to 4 GHz when the data rate of the input serial signal is 1 GHz. That is, the oversampling unit 10 functions as a 4-times oversampling unit, and the data bit (D0) and the data bit (D1) are each quadrupled to form 8-bit data. For example, when D0 is 1, it is converted to 1111 by oversampling processing, and when D1 is 0, it is converted to 0000 by oversampling processing. In FIG. 3, the output data is shifted by one clock compared to the input serial signal, which indicates that the delay time by sampling processing is one clock. Also, D0 may not be a clean waveform due to the influence of jitter and noise. In this case, all the generated 4-bit data is not “1”. For example, the rightmost bit may be “0”.

  As described above, the oversampling unit 10 oversamples the input serial signal data, and outputs the oversampling data with the bit length expanded to the edge selection circuit 20.

<Edge selection processing>
FIG. 4 is a diagram for explaining the outline of the demodulation processing of the data bit string after oversampling by the edge selection circuit 20. The edge selection circuit 20 changes the change point (edge position: 0 to 1 or 1 to 0 in the data bit string) from 8-bit data obtained by multiplying the data bit (D0) and the data bit (D1) by 4 times. Data demodulation is executed by estimating the data bit far from the change point as a highly reliable data bit and acquiring it. In order to detect the change point, the edge selection circuit 20 performs an exclusive OR operation on adjacent bits in 8-bit data obtained by multiplying the data bit (D0) and the data bit (D1) by four. Comparison operation) is performed. By this exclusive OR operation, eight change points (change point 0, change point 1, change point 2, change point 3 of the same phase in two each) are acquired at two serial data rates. Based on these eight change points, 2 bits are selected from 8 bits (2 serial data rates). If both D0 and D1 are 1 or 0, for example, 11111111 or 00000000, the change point (edge position) cannot be determined. Therefore, in such a case, the change point (edge position) is determined by estimating the change point from the previous information. That is, the change point (edge position) is detected (estimated) on the assumption that it is the same as the previous information.

  Here, when a transition state (for example, E0, E1, E2, E3) is defined depending on which adjacent bit has a clock edge, a positive bit skip or a negative bit when transitioning between specific transition states Skip occurs (for example, positive bit skip occurs when transitioning from E0 to E3, and negative bit skip occurs when transitioning from E3 to E0). When positive bit skip occurs, 3-bit data is selected in one cycle, and when negative bit skip occurs, 1-bit data is selected in one cycle. When positive bit skip and negative bit skip do not occur, 2-bit data is selected in one cycle. For example, an error may occur when determining whether to perform positive bit skip or negative bit skip due to the influence of jitter or noise. Due to this determination error, excessive bits or insufficient bits occur in the data bit string.

<Output data generation processing>
A data bit string of image data that has been oversampled by the oversampling unit 10 and demodulated by the edge selection circuit 20 is input to the output data generation unit 30. This image data is a data string (a data string in which n-cycle data bit strings are connected) configured as a unit of data bit strings of n cycles (n is a positive integer).

  The output data generation unit 30 connects the adjacent two-cycle data bit sequences among the n-cycle data bit sequences while shifting each other to form an n-1 cycle shift-concatenated data bit sequence, and the n-1 cycle shift-concatenated data bit sequence 1 cycle, no data bit string is output or an invalid data bit string is output in one cycle. Here, the two-cycle data bit string is connected in order to determine the actual data sandwiched between the S (start) bit and the E (end) bit, and when the SE bit is removed in the subsequent processing, FIG. This is because the state as shown in FIG. That is, unless the data bit strings are concatenated, it is impossible to determine where the SE bit exists.

  The output data generation unit 30 receives a 20-bit data bit string for 11 cycles and outputs a 22-bit shift concatenated data bit string for 10 cycles. The output data of the output data generation unit 30 is obtained, for example, by selecting 22 bits from 40 bits of data input from the previous stage RAM and data obtained by delaying the input data by one cycle. In addition, since the bit assignment selected in 11 cycles changes, 11 patterns are generated.

  5 to 7 are conceptual diagrams illustrating an example of data input / output processing by the output data generation unit 30. FIG. As shown in FIG. 5 to FIG. 7, a 20-bit data bit string over 11 cycles (C0, C1,..., C9, C10) is input to the output data generation unit 30. The output data generation unit 30 performs an operation based on the input 20-bit data bit string over 11 cycles (C0, C1,..., C9, C10) and a shift (delay) of this by one cycle. Hereinafter, for convenience of explanation, the former may be referred to as “basic cycle data” and the latter may be referred to as “delayed cycle data”.

  The output data generation unit 30 connects the entire data bit string (20 bits) of the first cycle (C0) of the delay cycle data and the data bit string of the second half of the second cycle (C1) of the basic cycle data, A shift concatenated data bit string (22 bits obtained by concatenating C1 and C0) in the first cycle is generated.

  The output data generation unit 30 connects the data bit string of the first half 18 bits of the second cycle (C1) of the delay cycle data and the data bit string of the second half 4 bits of the third cycle (C2) of the basic cycle data to obtain 2 A shift concatenated data bit string in the cycle (22 bits obtained by concatenating C2 and C1) is generated.

  The output data generation unit 30 connects the first 16-bit data bit string of the third cycle (C2) of the delay cycle data and the latter 6-bit data bit string of the fourth cycle (C3) of the basic cycle data to obtain 3 A shift-concatenated data bit string in the cycle (22 bits obtained by concatenating C3 and C2) is generated.

  The output data generation unit 30 connects the first 14 bits of the data cycle of the fourth cycle (C3) of the delay cycle data with the latter half of the 8 bits of the data cycle of the fifth cycle (C4) of the basic cycle data. A shift-concatenated data bit string (22 bits obtained by concatenating C4 and C3) is generated in the cycle.

  The output data generation unit 30 connects the data bit string of the first half 12 bits of the fifth cycle (C4) of the delay cycle data and the data bit string of the latter half 10 bits of the sixth cycle (C5) of the basic cycle data. A shift concatenated data bit string (22 bits obtained by concatenating C5 and C4) is generated in the cycle.

  The output data generation unit 30 connects the data bit string of the first half 10 bits of the sixth cycle (C5) of the delay cycle data and the data bit string of the second half 12 bits of the seventh cycle (C6) of the basic cycle data to obtain 6 A shift concatenated data bit string in the cycle (22 bits obtained by concatenating C6 and C5) is generated.

  The output data generation unit 30 connects the data bit string of the first half 8 bits of the seventh cycle (C6) of the delay cycle data and the data bit string of the latter half 14 bits of the eighth cycle (C6) of the basic cycle data, A shift concatenated data bit string in the cycle (22 bits obtained by concatenating C7 and C6) is generated.

  The output data generation unit 30 connects the data bit string of the first half 6 bits of the eighth cycle (C7) of the delay cycle data and the data bit string of the second half 16 bits of the ninth cycle (C8) of the basic cycle data, A shift-concatenated data bit string (22 bits obtained by concatenating C8 and C7) is generated in the cycle.

  The output data generation unit 30 connects the data bit string of the first half 4 bits of the ninth cycle (C8) of the delay cycle data and the data bit string of the second half 18 bits of the 10th cycle (C9) of the basic cycle data, A shift concatenated data bit string in the cycle (22 bits obtained by concatenating C9 and C8) is generated.

  The output data generation unit 30 connects the data bit string of the first half of the 10th cycle (C9) of the delay cycle data and all the data bit strings (20 bits) of the basic cycle data, and shift-concatenated data of the 10th cycle. A bit string (22 bits obtained by concatenating C10 and C9) is generated.

  The output data generation unit 30 does not output the shift concatenated data bit string or outputs the invalid data bit string in the eleventh cycle. That is, the shift concatenated data bit string is not latched at the subsequent stage. Thus, the output to the subsequent stage of the shift concatenated data bit string catches up with the word aligner output (to match the output timing from the output data generation unit 30 and the read timing of the data selection unit (word alignment processing unit) 70) for one cycle. (This is because the reading side needs only 20 bits excluding SE), and 11 words can be processed in 10 cycles.

  As described above, the output data generation unit 30 receives 20 bits and 11 cycles of data (total of 220 bits), and outputs 22 cycles of 10 cycles of data (total of 220 bits). Stop the output of. Note that the latter-stage data enable changes from the off state to the on state when the output of the shift concatenated data bit string is started, and changes from the on state to the off state when the output of the shift concatenated data bit string ends (FIG. 7). reference).

  The data holding unit 40 stores the shift concatenated data bit sequence (the data bit sequence of the image data that has been oversampled by the oversampling unit 10 and demodulated by the edge selection circuit 20) output from the output data generation unit 30. It is. That is, the data holding unit 40 prevents the position of the word alignment from becoming unspecified by the data acquisition timing, and can always detect the word alignment pattern regardless of the data acquisition timing. Sequentially store the shift concatenated data bit string (demodulated data bit string).

<Operation in Core Circuit Unit: Data Holding Operation, AV Code Detection Operation, Alignment Signal Output Operation, Error Detection Operation, and Data Selection Operation>
(I) Data Holding Operation FIGS. 8 and 9 are conceptual diagrams showing an example of a shift concatenated data bit string (demodulated data bit string) held by the data holding unit 40. FIG. In other words, FIG. 9 is a schematic diagram of a shift register in which 22-bit data output from the output data generation unit 30 is held in the data holding unit 40. As shown in FIG. 8, in the present embodiment, the data holding unit 40 has 32 data selection patterns on the vertical axis. As shown in FIGS. 8 and 9, in this embodiment, the horizontal axis has a bit width of 54 bits. In each cycle, the data selection pattern shown in FIG. 8 or FIG. 9 is generated, and only one is selected as the word alignment pattern. By detecting the word alignment pattern, the SE bit can be removed from the input data bit string.

  For example, of the 32 data selection patterns on the vertical axis, 21 data selection patterns are “steady state”, 10 data selection patterns are “full state”, and 1 data selection pattern is “empty state”. Can be. In addition, a total of 22 data selection patterns of “steady state” and “empty state” (22 patterns exist because one cycle is composed of 22 bits) can correspond to 22 word alignment patterns.

  “Steady state” means that no error has occurred and 2 bits of data for error determination, 2 bits of data of start bit and end bit, and 20 bits of image data of 24 bits in total are included. This means that alignment is possible even if “excess error (10 right shift)” occurs for 10 consecutive cycles. Since data is continuously input, if one word alignment pattern is determined, data alignment processing can be executed using the word alignment pattern as long as it is in a steady state.

  The “full state” means a state in which the word alignment pattern cannot be continuously shifted to the right by 10 bits. In this “full state”, a 22-bit left shift is performed during a one-cycle stop period, and the state shifts to a state where continuous alignment is possible. The middle and lower parts of FIG. 10 depict an example in which the data selection pattern transitions from 1 to 23 and a data selection pattern transitions from 10 to 32 by performing a 22-bit left shift during one cycle stop period. ing.

  The “empty state” means a state where the word alignment pattern cannot be shifted to the left, that is, a state where there is no data for alignment in the data holding unit 40. In this “empty state”, the data enable signal output from the word aligner to the subsequent stage is disabled (this period is referred to as a disable period), and data output is stopped for one cycle. During this period, the currently held data is shifted to the right by 21 bits, and at the same time, new 22-bit data from the data holding unit 40 is held. Since data for 2 words (44 bits) is held, alignment is possible. The upper part of FIG. 10 illustrates an example in which the data selection pattern transitions from 32 to 11 by the processing during the one-cycle stop period.

  For example, out of the bit width of 54 bits on the horizontal axis, 43 bits are “steady state (possible area)”, 10 bits are “full state”, and 1 bit is “empty state”. it can. The 24 bits included in the 43 bits of the “steady state” can constitute a “specific data bit string” used for error detection described later.

  For example, in FIG. 8, when operating with the word alignment pattern of the data selection pattern 1 (bottom pattern), an excessive bit is generated due to some error, and at the position shown in the upper pattern. When the SE bit is shifted, the word alignment pattern is converted to the next higher pattern. In this way, each time an excessive bit is generated, the word alignment pattern is converted. However, since the pattern cannot be shifted in the empty state, the process is stopped once (forcibly stopped separately from the disable period) to shift the data bit string and again select the data selection pattern 1 ( (Bottom pattern) (the upper part of FIG. 10), the word alignment pattern can be appropriately detected. In the full state, the steady state is desirably originally, but since the data bit string can be shifted to the right side of the shift register, it is not necessary to forcibly stop the processing unlike the empty state. Therefore, in the full state, the shift operation is executed when the disable period comes (see the middle and subsequent stages in FIG. 10).

  Here, the reason why the bit width of the data holding unit 40 is 54 bits is as follows. Since 20-bit data is aligned in 22 patterns, 41 bits are required. And since the data enable becomes 1 for 10 consecutive bits and the alignment may change in the same direction during that time, 10 bits are necessary (adding 10b bit registers to support continuous right 10-bit shift) This corresponds to the case where an excessive error continues for 10 consecutive cycles in the locked state of pattern 11. Continuous transition from pattern 11 to pattern 1 is possible). Further, in addition to the 20-bit data, 3 bits of a start bit, an end bit, and an error determination bit are required. These total 54 bits. Further, when the data enable condition is satisfied and the data enable input is 1, 22 bits from the MSB (most significant bit) are latched.

(Ii) AV Code Detection Operation The AV code detection unit 50 generates an AV code (synchronization code) corresponding to the word alignment pattern of the data bit string of the image data that has been oversampled by the oversampling unit 10 and demodulated by the edge selection circuit 20. To detect.

  The AV code detection unit 50 shifts the shift concatenated data bit sequence (demodulated data bit sequence) stored in the data holding unit 40 with a predetermined bit width (54 bits in this embodiment), while the word alignment pattern (22 in this embodiment). The AV code (synchronization code) is detected from the word alignment pattern by comparing the pattern) with the synchronization code. The AV code can be composed of, for example, 20 bits of data and a total of 24 bits of data including a start bit and an end bit added to the MSB (most significant bit) and LSB (least significant bit), respectively. The AV code detection unit 50 detects an AV code detection pattern (for example, “24′h800ffe”) in order to detect an AV code sandwiched between a start bit and an end bit, and confirms any of the 22 word alignment patterns. A detection signal indicating whether or not

(Iii) Alignment Selection Signal Output Operation The alignment selection signal output unit 60 includes an alignment selection signal corresponding to the AV code (synchronization code) detected by the AV code detection unit (synchronization code detection unit) 50 (which pattern is correct (synchronization) A signal indicating whether the word alignment pattern is obtained).

(Iv) Data Selection Operation The data selection unit 70 follows the AV code (synchronization code) detected by the AV code detection unit (synchronization code detection unit) 50 and the alignment selection signal output from the alignment selection signal output unit 60 based on the AV code (synchronization code). From the data held by the data holding unit 40, one word alignment pattern optimal for word alignment processing is selected and extracted. The data selection unit 70 sets a word alignment lock state according to the extracted word alignment pattern (AV code), and in this word alignment lock state, removes the start bit and the end bit from the shift concatenated data bit string (demodulated data bit string). Execute the alignment process. Data after word alignment with the start bit and end bit removed is output to a subsequent circuit unit (eg, image processing unit) (not shown), and various patterns such as pattern detection, synchronization code detection, selection and replacement Processing is performed.

(V) Error Detection Operation The error detection unit 80 performs error detection of word alignment processing by the data selection unit (word alignment processing unit) 70. In other words, in a series of processes from oversampling to data bit sequence, there is a possibility that erroneous bits (excessive or inadequate bits) may occur due to the influence of jitter and noise between the transmitting device and the receiving device. Furthermore, an error may occur in the word alignment processing by the data selection unit (word alignment processing unit) 70 due to the erroneous bit. The error detection unit 80 plays a role of quickly detecting the occurrence of erroneous bits due to the influence of jitter and noise, and thus the occurrence of an error in word alignment processing, and executing accurate word alignment return processing.

  The error detection unit 80 is a data selection unit based on 4-bit data including a start bit and an end bit of the shift concatenated data bit sequence (demodulation data bit sequence) and 2 bits of the error determination bit corresponding thereto. (Word alignment processing unit) 70 performs error detection in word alignment processing.

  When the error detection unit 80 does not detect an error in word alignment processing based on the 4-bit data, the word alignment in which the AV code detection unit (synchronization code detection unit) 50 detects the AV code (synchronization code). When the locked state is maintained and an error in word alignment processing is detected based on the 4-bit data, the word aligned locked state is released.

  After detecting the word alignment lock state, the error detection unit 80 changes the word alignment pattern when an error in the word alignment process is detected (the pattern is changed when there is an excessive or insufficient error. If the word alignment processing error is no longer detected after releasing the word alignment lock state, the AV code detection unit (synchronization code detection unit) is performed without changing the word alignment pattern. ) 50 returns to the word aligned lock state in which the AV code (synchronization code) is detected. Specifically, when the operation from the error detection to the re-word aligned lock state is described, error detection → align lock release → AV code re-detection → align lock → word-aligned pattern data re-detected AV code is selected.

  In the word alignment lock state, the AV code detection unit (synchronization code detection unit) 50 detects the erroneous synchronization code erroneously generated by the preceding circuit including the oversampling unit 10 without changing the word alignment pattern. Can be prevented. In other words, in the word aligned lock state, even if the synchronization code is input to the AV code detection unit (synchronization code detection unit) 50, the AV code detection unit (synchronization code detection unit) 50 detects this as an erroneous synchronization code. The detection of the synchronization code is avoided by assuming that it exists (synchronization code detection is not executed). Since the synchronization code is not detected, the word alignment pattern in the word alignment lock state is maintained without being changed.

  In the word alignment unlock state, the AV code detection unit (synchronization code detection unit) 50 can detect the AV code (synchronization code) to determine the word alignment pattern.

  The error detection unit 80 is a shift concatenated data bit string (demodulated data bit string) obtained by adding the start bit and end bit of the adjacent data bit string sandwiching the specific data bit string to the specific data bit string including the start bit and the end bit. As a reference, error detection in the word alignment processing by the data selection unit (word alignment processing unit) 70 is executed.

  The error detection unit 80 includes 4-bit data including a start bit and an end bit of a specific data bit sequence, and a start bit and an end bit of an adjacent data bit sequence, out of the shift concatenated data bit sequence (demodulated data bit sequence). Based on the above, error detection of the word alignment processing by the data selection unit (word alignment processing unit) 70 is executed.

  The error detection unit 80 performs error detection of the data selection pattern described above. The error detection unit 80 outputs the data of the same word alignment pattern as that of the previous cycle if no error has occurred, and changes the word alignment pattern from the previous cycle data according to the error if an error has occurred. Output.

  The error detection unit 80 performs the above-described “steady state” detection. As described above, in the “steady state”, no error has occurred, and 2 bits of data for error determination, 2 bits of data of start bit and end bit, and 20 bits of image data of 24 bits in total. This means that alignment is possible even if “excessive error (10 right shift)” occurs for 10 consecutive cycles.

  A shift concatenated data bit string (demodulated data bit string) is input to the error detection unit 80 every moment, and “error detection 4-bit data (start bit) input to the data selection unit 70 for each cycle. Whether or not there is an error is determined based on the state of "4 bits data including 2 bits of the end bit and 2 bits of the error determination bit corresponding thereto"). That is, the error detection unit 80 performs error determination by comparing the previous cycle data with the current cycle data.

  When the number of bits of the previous cycle data is excessive, insufficient, or indefinite with respect to the number of bits of the current cycle data, the error detection unit 80 cancels the word alignment lock state as an error state, and then the AV code detection unit (Synchronization code detection unit) 50 re-detects the AV code (synchronization code), and in the word alignment lock state according to the re-detected AV code (synchronization code), the data selection unit (word alignment processing unit) 70 receives the word. Execute the alignment process.

  FIG. 11A is a conceptual diagram showing a steady state by the error detection unit 80. After reset release, start bit and end bit in two places of data LSB (least significant bit) and MSB (most significant bit), and the value of the first cycle of AV code (synchronous code) (for example, 24'h80_0FFE) Word alignment is performed with the detected pattern, and a steady state is obtained. In the steady state, the error detection unit 80 continues to confirm that the pattern of the start bit and the end bit is not broken (the position of the SE bit is not changed and is fixed). At this time, when the pattern of the start bit and the end bit collapses, bit indefinite or bit indefinite has occurred (see FIGS. 11B and 11C). In the steady state, the error detection unit 80 does not detect the synchronization code in other patterns (following patterns), and continues to maintain the word alignment pattern in the steady state.

  Here, the above-described “bit excess” and “bit shortage” states occur due to erroneous detection of edge selection by the edge selection circuit 20. That is, "excessive acquisition of bits" and "acquisition of insufficient bits" occur with respect to the required number of acquisition bits. The outline of the operation of the edge selection circuit 20 is as described above. The main causes of erroneous detection are jitter and noise. When jitter of a level that cannot be absorbed by the demodulator in the previous stage occurs, “excess bit” and “bit “Insufficient” may occur. For example, while the necessary number of acquisition bits is originally 2 bits, “bit excess” or “bit shortage” occurs when 3 bits or 1 bit is acquired by the above-described positive skip or negative skip. For this reason, in the transition of the word alignment pattern, it is assumed that the current pattern is shifted only 1 bit left (when excessive) or 1 bit right (when insufficient).

  FIG. 11B is a conceptual diagram showing a bit excess state by the error detection unit 80. The condition for determining that the bit excess has occurred is, for example, that the MSB + 1 bit from the MSB + 1 bit in the pattern of 24 bits including the 20 bits of data and the 4 bits of 2 sets of the start bit and the end bit is {1,0, {x1, x2}! = {1, 0} (meaning that the combination of x1 and x2 is not {1, 0}). By looking at the states of x1 and x2, it is possible to determine whether it is excessive or insufficient.

  When the bit excess state as shown in FIG. 11B is entered, the word alignment lock state is released. In this word alignment unlock state, data output is continued in a word alignment pattern corresponding to the error state of each cycle data, and the word alignment pattern is determined when a synchronization code is detected. In other words, when an error is detected, the word alignment lock state is canceled and the state shifts to the synchronization code detection state. When the synchronization code is detected, the current word alignment pattern is changed to the word alignment pattern in which the synchronization code is detected, and the word alignment lock is performed. It becomes a steady state with a state. Since the SE bits are {0, 1}, in the case of FIG. 11B, it can be determined that the SE bits (0 and 1) are shifted to 41 and 41, respectively.

  FIG. 11C is a conceptual diagram showing a bit shortage state by the error detection unit 80. The condition for determining that a shortage of bits has occurred is, for example, that 4 bits from the MSB + 1 bit of a total of 24 bits pattern including 20 bits of data and 4 bits of 2 sets of start bit and end bit are {x1, x2, {X1, x2}! = {1, 0}, which becomes 1,0}. When the bit shortage state as shown in FIG. 11C occurs, the word alignment lock state is released. In this word alignment unlock state, data output is continued in a word alignment pattern corresponding to the error state of each cycle data, and the word alignment pattern is determined when a synchronization code is detected. In other words, when an error is detected, the word alignment lock state is canceled and the state shifts to the synchronization code detection state. When the synchronization code is detected, the current word alignment pattern is changed to the word alignment pattern in which the synchronization code is detected, and the word alignment lock is performed. It becomes a steady state with a state. In the case of FIG. 11C, it can be determined that the SE bits (0 and 1) are shifted to 40 and 39, respectively.

  FIG. 11D is a conceptual diagram showing a bit indefinite state by the error detection unit 80. The bit indefinite state means a state in which it is impossible to determine whether the state is a steady state, a bit excess state, or a bit shortage state (a state in which the SE bit cannot be determined). When either a bit excess state or a bit shortage state occurs, 4 bits from the MSB + 1 bit of the pattern become {1, 0, 1, 0}. If the bit is undefined, the error detection unit 80 does not change the alignment, continues to output the current word alignment pattern (maintains the current word alignment pattern), and changes to the word alignment pattern in which the synchronization code is detected. Then, the stationary state is set together with the word aligned lock state.

<Data processing contents>
FIG. 12 is a flowchart for explaining an example of data processing by the data processing apparatus 1 of this embodiment.
In step ST1, the AV code detection unit (synchronization code detection unit) 50 detects the AV code (synchronization code).

  In step ST2, the data selection unit (word alignment processing unit) 70 sets a word alignment lock state according to the AV code (synchronization code) detected by the AV code detection unit (synchronization code detection unit) 50.

  In step ST3, the data selection unit (word alignment processing unit) 70 determines the word alignment pattern. For example, the data selection unit (word alignment processing unit) 70 determines one word alignment pattern from the data selection patterns 11 to 32 (22 patterns) of FIG.

  In step ST4, a steady state (because the word alignment pattern has been determined) is entered, and the data selection unit (word alignment processing unit) 70 executes word alignment processing that removes the start bit and end bit from the shift concatenated data bit sequence (demodulated data bit sequence). To do.

  In step ST <b> 5, the error detection unit 80 determines whether or not an error has been detected in the word alignment processing by the data selection unit (word alignment processing unit) 70. If an excessive bit error is detected, the process proceeds to step ST6. If a bit shortage error is detected, the process proceeds to step ST8. If a bit indefinite error is detected, the process proceeds to step ST10. When no error is detected (when the steady state is maintained), the process returns to step ST4.

  In step ST6, since an excessive bit error has occurred, in step ST7, the error detection unit 80 executes a bit excess process. The bit excess processing by the error detection unit 80 will be described later.

  In step ST8, since a bit shortage error has occurred, in step ST9, the error detection unit 80 executes a bit shortage process. The bit shortage process by the error detection unit 80 will be described later.

  In step ST10, an indefinite bit error has occurred. In step ST11, the error detection unit 80 maintains the word alignment pattern. That is, when a bit indefinite error has occurred, it is unclear whether it is actually in a steady state, a bit excess state, or a bit shortage state, so the error detection unit 80 tentatively performs step ST3. Maintain the word-aligned pattern confirmed with.

  In step ST12, the error detection unit 80 releases the word alignment lock state set in step ST2, and returns to the process of step ST1. That is, the error detection unit 80 releases the word alignment lock state, causes the AV code detection unit (synchronization code detection unit) 50 to re-detect the AV code (synchronization code), and re-detects the AV code (synchronization code). The data selection unit (word alignment processing unit) 70 is caused to execute word alignment processing in the word alignment locked state according to (1).

<Bit excess processing>
FIG. 13 is a flowchart for explaining bit excess processing by the error detection unit 80.

In step ST21, the error detection unit 80 determines whether or not the data is empty (whether or not the data in the data holding unit 40 is empty with respect to word alignment). If it is data empty, the process proceeds to step ST22. If it is not data empty, the process proceeds to step ST24.
In step ST22, the error detection unit 80 shifts the word alignment pattern determined in step ST3 of FIG. 12 to the right by 21 bits (see FIG. 10).
In step ST23, the error detection unit 80 forcibly stops the subsequent stage output for one cycle and disables (enables) the data enable.
In step ST24, the error detection unit 80 shifts the word alignment pattern determined in step ST3 of FIG. 12 to the left by 1 bit.

<Bit shortage processing>
FIG. 14 is a flowchart for explaining the bit shortage process by the error detection unit 80.

  In step ST31, the error detection unit 80 determines whether or not the data is in a full state (whether or not the data in the data holding unit 40 is full with respect to word alignment). If the data is full, the process proceeds to step ST32. If the data is not full, the process proceeds to step ST34.

  In step ST32, the error detection unit 80 determines whether or not the data enable input is “0”. If the data enable input is “0”, the process proceeds to step ST34. If the data enable input is not “0”, the process proceeds to step ST33.

  In step ST33, the error detection unit 80 shifts the word alignment pattern determined in step ST3 of FIG. 12 to the left by 22 bits during the disable period (see FIG. 6) (see FIG. 10).

  In step ST34, since it is not the disable period, the error detection unit 80 shifts the word alignment pattern determined in step ST3 of FIG. 12 to the right by 1 bit. As shown in FIG. 5, the basic operation is to perform a series of processes in 11 cycles. Here, 11 cycles are composed of a 10-cycle continuous processing period and a 1-cycle pause period. Therefore, it has a word alignment pattern configuration capable of 10-cycle continuous full state processing (continuous 10-bit right shift). In addition, since the disable period is reached until the state where the right shift cannot be performed (the state where the beginning of the word alignment pattern is at the rightmost end of the holding unit 40), there is no operational problem.

<Summary of First Embodiment>
As described above, the data processing apparatus 1 according to the present embodiment includes the data selection unit (word alignment processing unit) 70 and the error detection unit 80. The data selection unit (word alignment processing unit) 70 removes the start bit and the end bit from the demodulated data bit string in the word alignment locked state according to the AV code (synchronization code). The error detection unit 80 detects an error in the word alignment process based on 4-bit data including a start bit and an end bit of the demodulated data bit string and 2 bits of the error determination bit corresponding thereto. Execute. This makes it possible to improve the data quality by reducing the influence of jitter and noise and performing correct data decoding processing (word alignment processing) in a series of processing from oversampling to demodulation of the data bit string. Become.

(2) Second Embodiment Since a conventional data decoding circuit (word alignment circuit) requires a word alignment pattern detection circuit for packetized bits, there is a problem that the circuit scale is remarkably increased. For example, if the start bit and the end bit are 1 bit each and the image data sandwiched between them is 20 bits, the packetized data bit string is 22 bits in total, and 22 word alignment pattern detection circuits are required. End up. When the circuit scale of the data decoding circuit (word alignment circuit) increases, the user area of the FPGA is occupied, and it becomes difficult to use a small-scale FPGA.

  According to the second embodiment, data decoding processing (word alignment processing) can be performed with high accuracy, data quality can be improved, and the circuit scale of the data decoding circuit (word alignment circuit) can be suppressed. A data processing device 2 is provided.

The data processing device 2 according to the second embodiment employs a configuration in which error detection processing is removed from the data processing device 1 according to the first embodiment. For example, the data processing device 2 according to the second embodiment detects a synchronization code from output data including a start bit and an end bit (SE bit), and outputs word-aligned data (from which the SE bit is removed). To do.
According to the second embodiment, the circuit scale of the data decoding circuit (word align circuit) can be suppressed.

<Configuration example of data processing device>
FIG. 15 is a diagram illustrating a schematic configuration example of the data processing device 2 according to the second embodiment. As shown in FIG. 15, the data processing device 2 has a configuration in which the error detection unit 80 is excluded from the data processing device 1 as compared with the data processing device 1 according to the first embodiment. Therefore, in FIG. 15, the oversampling unit 10, the edge selection circuit (demodulation unit) 20, the output data generation unit 30, the AV code detection unit (synchronization code detection unit) 50, and the data selection unit (word alignment processing unit) 70. Since the operation is the same as that of the data processing apparatus 1 of the first embodiment, a detailed description thereof will be omitted (see the description of the first embodiment).

  The data processing device 2 does not include an error detection unit. For this reason, the alignment selection signal output unit 60 ′ does not generate an alignment selection signal by reflecting the result of error detection, but generates and outputs an alignment selection signal based only on the detection of the synchronization code. .

  Since the data processing apparatus 2 does not assume error detection, the data holding configuration and operation in the data holding unit 40 'are different from those in the data holding unit 40 in the first embodiment. That is, the data holding unit 40 in the second embodiment is similar to the first embodiment in that the shift concatenated data bit string output by the output data generation unit 30 (oversampled by the oversampling unit 10 that is the basis thereof and the edge) The data bit string of the image data demodulated by the selection circuit 20 is stored, and has a bit width corresponding to the word alignment pattern of the shift concatenated data bit string (demodulated data bit string). The data holding unit 40 ′ according to the second embodiment can prevent the position of the word alignment from being specified by the data acquisition timing, and can always reliably detect the word alignment pattern regardless of the data acquisition timing. As described above, the shift concatenated data bit string (demodulated data bit string) is sequentially stored in the shift register having a predetermined bit width or more. However, as will be described later, the data holding unit 40 ′ has a bit width (as a shift register) having a length different from that of the data holding unit 40 of the first embodiment.

<Example of shift concatenated data bit string>
FIG. 16 is a conceptual diagram showing an example of the shift concatenated data bit string held by the data holding unit 40 ′. As shown in FIG. 8, in the present embodiment, the data holding unit 40 ′ has a bit width of 45 bits corresponding to 22 word alignment patterns. That is, in order to remove the start bit and the end bit from the data bit string of one cycle, it is necessary to select an optimum one from the 22 word alignment patterns, and the data holding unit 40 stores the data for that purpose. It is.

Here, 45 bits, which is the bit width of the data holding unit 40 ′, is expressed by the following equation when the data format of one word is 12 bits in total of image data (10 bits) + start / end bits (2 bits). Is calculated by
[{Data width + (start / end bit)} × 2] + (number of patterns−1)
= [{10 + 2} × 2] + (22-1) = [{12} × 2] + (21) = 45

  In the first embodiment, a margin of 10 bits is provided so as to withstand even if errors (excessive or insufficient bits) appear for 10 consecutive cycles (FIG. 8). However, since no error detection is assumed, the bit width of the data holding unit 40 ′ is 45 bits as described above.

  The AV code detection unit 50 detects an AV code (synchronization code) corresponding to the word alignment pattern of the data bit string of the image data that has been oversampled by the oversampling unit 10 and demodulated by the edge selection circuit 20.

  The AV code detection unit 50 synchronizes with the word alignment pattern (22 patterns in this embodiment) while shifting the shift concatenated data bit string stored in the data holding unit 40 ′ with a predetermined bit width (45 bits in this embodiment). By comparing the codes, an AV code (synchronization code) is detected from the word alignment pattern.

  More specifically, the AV code detection unit 50 converts the specific shift concatenated data into a 22-bit specific shift concatenated data bit string including a start bit and an end bit within a range of 45 bits of the data holding unit 40 ′. The AV code is detected while shifting 24-bit data, which is obtained by adding 2 bits of the start bit and the end bit of the adjacent shift concatenated data bit sequence sandwiching the bit sequence as a unit.

9A and 9B are conceptual diagrams illustrating an example of an AV code detection pattern by the AV code detection unit 50. FIG. The AV code can be composed of, for example, 20 bits of data and a total of 24 bits of data including a start bit and an end bit added to the MSB (most significant bit) and LSB (least significant bit), respectively. The AV code detection unit 50 detects an AV code detection pattern (for example, “24′h800ffe”) in order to detect an AV code sandwiched between a start bit and an end bit, and confirms any of the 22 word alignment patterns. A detection signal indicating whether or not
The alignment selection signal output unit 60 ′ outputs an alignment selection signal corresponding to the AV code (synchronization code) detected by the AV code detection unit (synchronization code detection unit) 50.

  The data selection unit 70 includes the data holding unit 40 according to the AV code (synchronization code) detected by the AV code detection unit (synchronization code detection unit) 50 and the alignment selection signal output from the alignment selection signal output unit 60 ′ based on the AV code. One word alignment pattern that is most suitable for word alignment processing is selected from the data held by and extracted. The data selection unit 70 executes word alignment processing for removing the start bit and the end bit from the shift concatenated data bit string according to the extracted word alignment pattern (AV code). Data after word alignment with the start bit and end bit removed is output to a synchronization compensation circuit (not shown) and subjected to various processes such as pattern detection and synchronization code detection, selection and replacement.

  FIG. 10 shows an example of selection and extraction of the shift concatenated data bit string held by the data holding unit 40 ′, the AV code detection pattern by the AV code detection unit 50, and the word alignment pattern (AV code) by the data selection unit 70. It is a conceptual diagram. As shown in FIG. 10, detection of alignment of 11 pixels D0 to D10 is started in the shift-concatenated data bit string in the first cycle, and detection of alignment of 11 pixels D0 to D10 is detected by the shift-concatenated data bit string in the 10th cycle. Is completed. In the shift concatenated data bit string in the 11th cycle, data enable (previous stage) is disabled, so data latch is not performed (pauses once). When the above 11 cycles are completed, detection of alignment of 11 pixels D11 to D21 is started.

<Summary of Second Embodiment>
As described above, the data processing device 2 according to the present embodiment includes the output data generation unit 30, the data holding unit 40 ′, the AV code detection unit (synchronization code detection unit) 50, and the data selection unit (word alignment processing unit). 70). The output data generation unit 30 receives n cycle (n is a positive integer) data bit string and connects two adjacent data bit strings among n cycle data bit strings while shifting each other to n-1 cycles. N-1 cycles of the shift concatenated data bit string are output, and one cycle outputs no data bit string or an invalid data bit string. The data holding unit 40 ′ has a bit width corresponding to the word alignment pattern of the shift concatenated data bit string and stores the shift concatenated data bit string. The AV code detection unit (synchronization code detection unit) 50 compares the word alignment pattern with the synchronization code while shifting the shift concatenated data bit string stored in the bit width by the data holding unit 40 ′, thereby determining the middle of the word alignment pattern. The AV code (synchronization code) is detected from. The data selection unit (word alignment processing unit) 70 executes word alignment processing for removing the start bit and end bit from the shift concatenated data bit string according to the synchronization code. As a result, since the word alignment pattern detection circuit for packetized bits is not required to detect the word alignment pattern, the circuit scale of the data decoding circuit (word alignment circuit) can be suppressed (severely reduced).

(3) Summary of specific items of this disclosure (i) Specific items 1
An oversampling unit that inputs a data bit string and oversamples and outputs each data bit of the data bit string;
A demodulator that demodulates the data bit sequence after oversampling by selecting a part of each data bit of the data bit sequence after oversampling;
A data holding unit having at least a bit width corresponding to a word alignment pattern of the data bit string and storing the data bit string;
A synchronization code detector that detects the synchronization code from the word alignment pattern by comparing the word alignment pattern and the synchronization code while shifting the data bit string in the data holding unit;
A word alignment processing unit for removing a start bit and an end bit from the data bit string in a word alignment locked state according to the synchronization code;
A data processing apparatus.

(Ii) Specific matter 2
In specific matter 1,
The demodulated data bit sequence of n cycles (n is a positive integer) is acquired, and two adjacent data bit sequences of the demodulated data bit sequences of n cycles are connected to each other while being shifted to each other to obtain n-1 cycles. A data processing apparatus comprising: an output data generation unit that outputs the n-1 cycle data bit sequence and outputs no data bit sequence or outputs an invalid data bit sequence to the data holding unit .

(Iii) Specific matter 3
In specific matter 1 or 2,
A data processing apparatus comprising: an error detection unit that performs error detection of the word alignment process based on a start bit and an end bit of the data bit string and an error determination bit corresponding to the start bit and the end bit.

(Iv) Specific matter 4
In specific matter 3,
When the error detection unit has not detected an error in the word alignment process based on the error determination bit, the error detection unit maintains the word alignment lock state in which the synchronization code detection unit has detected the synchronization code, and the error A data processing device that releases the word alignment lock state when an error in the word alignment processing is detected based on a determination bit.

(V) Specific matter 5
In specific matter 4,
The error detection unit
(1) After the word alignment lock state is released, when the error in the word alignment process is detected continuously, the word alignment pattern is changed,
(2) When the error of the word alignment process is not detected after releasing the word alignment lock state, the synchronization code detection unit detects the synchronization code without changing the word alignment pattern. A data processing device that returns to the word aligned lock state.

(Vi) Specific matter 6
In specific matter 4 or 5,
The data processing device, wherein the synchronization code detection unit avoids detection of the input synchronization code in the word alignment lock state and maintains the word alignment pattern in the word alignment lock state.

(Vii) Specific matter 7
In any one of the specific items 4 to 6, the synchronization code detection unit determines the word alignment pattern by detecting the synchronization code in the word alignment unlock state.

(Viii) Specific matter 8
In any one of Specific Items 1 to 7,
The error detection unit detects an error in the word alignment process based on a specific data bit string including the start bit and the end bit plus a start bit and an end bit of an adjacent data bit string sandwiching the specific data bit string. A data processing device for executing

(Ix) Specific matter 9
In specific matter 8,
The error detection unit performs error detection in the word alignment process based on data obtained by combining a start bit and an end bit of the specific data bit string and a start bit and an end bit of the adjacent data bit string apparatus.

(X) Specific matter 10
A data bit sequence of n cycles (n is a positive integer) is input, and two adjacent data bit sequences of the n cycle data bit sequences are connected while being shifted to each other to form an n-1 cycle shift concatenated data bit sequence. Outputting an n-1 cycle shift concatenated data bit string and outputting an invalid data bit string in one cycle without outputting a data bit string; and
A data holding unit having a bit width corresponding to a word alignment pattern of the shift concatenated data bit string and storing the shift concatenated data bit string;
Synchronization code detection for detecting the synchronization code from the word alignment pattern by comparing the synchronization code with the word alignment pattern while shifting the shift concatenated data bit string stored in the bit width by the data holding unit And
In accordance with the synchronization code, a word alignment processing unit that removes a start bit and an end bit from the shift concatenated data bit string,
A data processing apparatus.

(Xi) Specific matter 11
In specific matter 10,
The output data generation unit receives a 20-bit data bit string for 11 cycles and outputs a 22-bit shift concatenated data bit string for 10 cycles.
(Xii) Specific matter 12
In specific matter 11,
The data processing unit is a data processing device having a bit width of 45 bits corresponding to 22 word alignment patterns.

(Xiii) Specific matter 13
In the specific matter 12, the synchronization code detection unit converts the specific shift concatenated data bit string into a 22-bit specific shift concatenated data bit string including a start bit and an end bit within a 45-bit bit width of the data holding unit. A data processing device for detecting the synchronization code while shifting one bit at a time, with 24 bits of data including a start bit and an end bit of two adjacent shift concatenated data bit strings sandwiched therebetween as one unit.

(Xiv) Specific matter 14
An oversampling unit that inputs a data bit string and oversamples and outputs each data bit of the data bit string;
A demodulator that demodulates the data bit sequence after oversampling by selecting a part of each data bit of the data bit sequence after oversampling;
A synchronization code detector for detecting a synchronization code according to the word alignment pattern of the demodulated data bit string;
A word alignment processing unit that removes a start bit and an end bit from a demodulated data bit string in a word aligned lock state according to the synchronization code;
Error detection for executing error detection in the word alignment processing based on 4-bit data including 2 bits of the start bit and end bit of the demodulated data bit string and 2 bits of the error determination bit corresponding thereto And
A data processing apparatus comprising:

(Xv) Specific matter 15
In specific matter 14,
When the error detection unit has not detected an error in the word alignment processing based on the 4-bit data, the error detection unit maintains the word alignment lock state in which the synchronization code detection unit has detected the synchronization code, and the 4 A data processing device that releases the word alignment lock state when an error in the word alignment processing is detected based on bit data.

1 Data processing device 10 Oversampling unit 20 Edge selection circuit (demodulation unit)
30 Output data generation unit (RAM I / F unit, data enable generation unit)
40, 40 'data holding unit (core circuit unit)
50 AV code detector (synchronous code detector, core circuit)
60, 60 'align selection signal output section (core circuit section)
70 Data selection unit (word alignment processing unit, core circuit unit)
80 Error detector

Claims (8)

An oversampling unit that inputs a data bit string and oversamples and outputs each data bit of the data bit string;
A demodulator that demodulates the data bit sequence after oversampling by selecting a part of each data bit of the data bit sequence after oversampling;
The demodulated data bit sequence of n cycles (n is a positive integer) is acquired, and two adjacent data bit sequences of the demodulated data bit sequences of n cycles are connected to each other while being shifted to each other to obtain n-1 cycles. An output data generation unit that outputs the n-1 cycle data bit sequence and outputs no data bit sequence or an invalid data bit sequence in one cycle;
A data holding unit that has at least a bit width corresponding to a word alignment pattern of the data bit sequence, receives the data bit sequence from the output data generation unit, and stores the data bit sequence;
A synchronization code detector that detects the synchronization code from the word alignment pattern by comparing the word alignment pattern and the synchronization code while shifting the data bit string in the data holding unit;
A word alignment processing unit for removing a start bit and an end bit from the data bit string in a word alignment locked state according to the synchronization code;
A data processing apparatus. Oite to claim 1, further
A data processing apparatus comprising: an error detection unit that performs error detection of the word alignment process based on a start bit and an end bit of the data bit string and an error determination bit corresponding thereto. In claim 2 ,
When the error detection unit has not detected an error in the word alignment process based on the error determination bit, the error detection unit maintains the word alignment lock state in which the synchronization code detection unit has detected the synchronization code, and the error A data processing device that releases the word alignment lock state when an error in the word alignment processing is detected based on a determination bit. In claim 3 ,
The error detection unit
(I) After the release of the word alignment lock state, when an error in the word alignment process is detected, the word alignment pattern is changed,
(Ii) When an error in the word alignment process is no longer detected after releasing the word alignment lock state, the synchronization code detection unit detects the synchronization code without changing the word alignment pattern. A data processing device that returns to the word aligned lock state. In claim 3 or 4 ,
The data processing device, wherein the synchronization code detection unit avoids detection of the input synchronization code in the word alignment lock state and maintains the word alignment pattern in the word alignment lock state. The synchronization code detector in any one of claims 3 to 5, in the word alignment unlocked state, by performing the synchronization code detection, to determine the word alignment pattern, the data processing device. In any one of Claims 1-6 ,
The error detection unit detects an error in the word alignment process based on a specific data bit string including the start bit and the end bit plus a start bit and an end bit of an adjacent data bit string sandwiching the specific data bit string. A data processing device for executing In claim 7 ,
The error detection unit performs error detection in the word alignment process based on data obtained by combining a start bit and an end bit of the specific data bit string and a start bit and an end bit of the adjacent data bit string apparatus.

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