JP6560407B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a technique effective when applied to a semiconductor device in which a plurality of semiconductor chips are mounted on a ceramic substrate via a plurality of metal patterns.

  Japanese Patent Laying-Open No. 2001-85611 (Patent Document 1) describes a power module in which a plurality of power elements are mounted on a ceramic substrate via a plurality of conductor layers.

  In Japanese Patent Application Laid-Open No. 2003-332481 (Patent Document 2) and Japanese Patent Application Laid-Open No. 2011-77087 (Patent Document 3), a copper plate for a wiring circuit is provided on the upper surface of the ceramic substrate, and a heat radiation is provided on the lower surface of the ceramic substrate. A substrate for a semiconductor module to which a copper plate is bonded is described.

JP 2001-85611 A JP 2003-332481 A JP 2011-77087 A

  There is a semiconductor device in which a plurality of semiconductor chips are mounted on a ceramic substrate via a conductor pattern. The ceramic substrate is excellent in high-frequency characteristics and thermal conductivity, and is used, for example, in a power system (power control system) semiconductor device such as a power converter.

  However, when a plurality of semiconductor chips are mounted side by side in one semiconductor device, the plane area of the ceramic substrate increases. In this case, it has been found that if an external force is applied to the ceramic substrate when the semiconductor device is mounted, the ceramic substrate may be damaged such as cracks due to the external force.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a plurality of metal patterns formed on a ceramic substrate and a plurality of semiconductor chips mounted on the plurality of metal patterns. The plurality of metal patterns include a first metal pattern and a second metal pattern that face each other. In addition, the first region provided between the first metal pattern and the second metal pattern and exposed from the plurality of metal patterns extends in a zigzag manner along the extending direction of the first metal pattern. Is.

  According to the one embodiment, the reliability of the semiconductor device can be improved.

It is explanatory drawing which shows the structural example of the power conversion system with which the semiconductor device which is embodiment is integrated. It is a perspective view which shows the external appearance of the semiconductor device shown in FIG. FIG. 3 is a plan view showing a back side of the semiconductor device shown in FIG. 2. It is sectional drawing along the AA line of FIG. FIG. 4 is a plan view showing a layout on the upper surface side of the ceramic substrate shown in FIG. 3. It is explanatory drawing which shows typically the inverter circuit which the some semiconductor chip shown in FIG. 5 comprises. FIG. 6 is an enlarged plan view showing the periphery of the semiconductor chip shown in FIG. 5 in an enlarged manner. It is an expanded sectional view along the AA line of FIG. FIG. 6 is a plan view showing a layout of a plurality of metal patterns shown in FIG. 5. It is a top view which shows the modification with respect to FIG. FIG. 3 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIG. 2. It is a top view which shows the state which mounted the several semiconductor chip on the ceramic substrate at the die-bonding process shown in FIG. FIG. 13 is a plan view showing a state where a plurality of semiconductor chips and a plurality of metal patterns shown in FIG. 12 are electrically connected via wires. It is a top view which shows the example of examination with respect to FIG.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. In addition, the term “gold plating”, “Cu layer”, “nickel plating”, etc. includes not only pure materials, but also members mainly composed of gold, Cu, nickel, etc. unless otherwise specified. Shall be.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

<Configuration example of power conversion system>
In this embodiment, which will be described in detail below with reference to the drawings, as an example of a semiconductor device in which a plurality of semiconductor chips are mounted side by side on a ceramic substrate, power conversion that converts input DC power into AC power and outputs the power The device (inverter device) will be described.

  FIG. 1 is an explanatory diagram illustrating a configuration example of a power conversion system in which the semiconductor device of the present embodiment is incorporated.

  The power conversion system shown in FIG. 1 is a system that converts DC power output from a plurality of solar cell modules SCM into AC power by an inverter circuit INV and outputs the AC power to a power distribution circuit DTC.

  Each of the plurality of solar cell modules SCM is a photoelectric conversion device that converts light energy into electrical energy. Each of the plurality of solar cell modules SCM has a plurality of solar cells, and outputs electric power converted into electric energy by each of the plurality of solar cells as DC power.

  A converter circuit CNV is connected between the plurality of solar cell modules SCM shown in FIG. 1 and the inverter circuit INV. In the example shown in FIG. 1, the DC power output from the plurality of solar cell modules SCM is boosted by the converter circuit CNV and boosted to a high voltage DC power. That is, the converter circuit CNV shown in FIG. 1 is a so-called DC / DC converter that converts DC power into DC power having a relatively high voltage.

  The AC power converted by the inverter circuit INV is output to the power distribution circuit DTC. In the example illustrated in FIG. 1, the inverter circuit INV is converted into three-phase AC power of U phase, V phase, and W phase, and the three-phase AC power is output to the distribution circuit DTC.

  Further, the power conversion system shown in FIG. 1 includes a control circuit CMD that controls the above-described power conversion operation. The control circuit CMD outputs a control signal to each switching element of the converter circuit CNV and the inverter circuit INV.

  The inverter circuit INV shown in FIG. 1 is a power conversion circuit that converts DC power into AC power using a plurality of switching elements. In the example shown in FIG. 1, each of the six transistors Q1 functions as a switching element.

  When DC power is converted into AC power using a switching element, a circuit in which a high-side switch connected to a relatively high potential and a low-side switch connected to a relatively low potential are connected in series is used. . The high-side switch and the low-side switch are turned on and off as a pair. When one of the pair of high-side switch and low-side switch is on, the other switch is off. The pair of high-side switches and low-side switches perform an on-off operation (hereinafter referred to as switching operation) at high speed, so that single-phase AC power is output.

  Further, the example shown in FIG. 1 shows an inverter circuit INV that converts DC power into three-phase AC power, and a switch pair composed of a high-side switch and a low-side switch has three phases of U phase, V phase, and W phase. Three pairs are provided corresponding to the phases. Also, the output nodes of the three phases U phase, V phase, and W phase are connected between the high-side switch and the low-side switch connected in series so that each switch pair has a phase difference of 120 degrees. Switching operation is performed. Thereby, DC power can be converted into three-phase AC power having three phases of U phase, V phase, and W phase.

  For example, in the example shown in FIG. 1, a positive potential E1 is applied to the high-side terminal HT, and a potential E2 is applied to the low-side terminal LT. At this time, the potentials of the U-phase node, the V-phase node, and the W-phase node change to 0 and E1 according to the switching operation of the three switch pairs. For example, since the line voltage between the U phase and the V phase is obtained by subtracting the V phase potential from the U phase potential, + E1 [V], 0 [V], -E1 [V ] Will change. The line voltage between the V phase and the W phase is a voltage waveform whose phase is shifted by 120 degrees with respect to the line voltage between the U phase and the V phase. The line voltage between them has a voltage waveform whose phase is shifted by 120 degrees with respect to the line voltage between the V phase and the W phase. That is, when DC power is input to the inverter circuit INV, a voltage waveform of three-phase AC power is obtained.

  The transistor Q1 constituting the switching element of the inverter circuit INV shown in FIG. 1 is an insulated gate bipolar transistor (hereinafter referred to as IGBT (Insulated Gate Bipolar Transistor)). A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be used as the transistor Q1 which is a switching element. According to this power MOSFET, since the switching operation is controlled by the voltage applied to the gate electrode, there is an advantage that high-speed switching is possible.

  However, the power MOSFET has a property that the on-resistance increases and the heat generation amount increases as the breakdown voltage is increased. Therefore, the IGBT is preferable as the transistor Q1 used in applications that require a high power and high speed switching operation. This IGBT is composed of a combination of a power MOSFET and a bipolar transistor, and is a semiconductor element that combines the high-speed switching characteristics of the power MOSFET and the high breakdown voltage of the bipolar transistor. As described above, the inverter circuit INV in the first embodiment employs an IGBT as a switching element.

  In the inverter circuit INV, the transistor Q1 and the diode D1 are connected in antiparallel between the high-side terminal HT and each of the three-phase AC phases (U phase, V phase, W phase), and A transistor Q1 and a diode D1 are also connected in antiparallel between each phase of the three-phase alternating current and the low-side terminal LT. That is, two transistors Q1 and two diodes D1 are provided for each single phase, and six transistors Q1 and six diodes D1 are provided for three phases. A control circuit CMD is connected to the gate electrode of each transistor Q1, and the switching operation of the transistor Q1 is controlled by the control circuit CMD. The diode D1 has a function of flowing a return current in order to release electric energy stored in an inductance connected to the output side of the inverter circuit INV.

<Semiconductor device>
Next, a configuration example of the semiconductor device PKG1 configuring the inverter circuit INV illustrated in FIG. 1 will be described. FIG. 2 is a perspective view showing an appearance of the semiconductor device shown in FIG. FIG. 3 is a plan view showing the back side of the semiconductor device shown in FIG. 4 is a cross-sectional view taken along the line AA in FIG. FIG. 5 is a plan view showing a layout on the upper surface side of the ceramic substrate shown in FIG. FIG. 6 is an explanatory diagram schematically showing a circuit configured by the semiconductor device shown in FIG. FIG. 7 is an enlarged plan view showing the periphery of the semiconductor chip shown in FIG. FIG. 8 is an enlarged sectional view taken along line AA in FIG.

  In FIG. 7, as a representative example of the plurality of semiconductor chips CP illustrated in FIG. 5, one semiconductor chip CP including a transistor and one semiconductor chip CD including a diode are illustrated. Since the semiconductor chip CTH and the semiconductor chip CTL shown in FIG. 5 have the same structure, one semiconductor chip CP is typically shown.

  As shown in FIG. 2, the semiconductor device PKG1 of the present embodiment that constitutes the inverter circuit INV shown in FIG. 1 is covered with a cover material (cap, cover member) CV on the upper surface side. As shown in FIG. 4, the lid member CV has a housing part (pocket) PKT that houses a plurality of semiconductor chips CP. The lid member CV covers the upper surface CSt of the ceramic substrate CS1, which is a base material on which a plurality of semiconductor chips CP are mounted. The peripheral edge portion of the upper surface CSt of the ceramic substrate CS1 is bonded and fixed to the lid material CV via the adhesive material BD1. The lid member CV is a resin member, and is made of, for example, an epoxy resin.

  A plurality of terminals LD protrude from the upper surface CVt of the lid member CV. A plurality of through holes THL are formed in the upper surface CVt of the lid member CV, and the plurality of terminals LD are inserted into the plurality of through holes THL, respectively. Each of the plurality of terminals LD is an external terminal of the semiconductor device PKG1, and is electrically connected to the plurality of semiconductor chips CP mounted on the ceramic substrate CS1 shown in FIG.

  Further, as shown in FIG. 3, the lid member CV of the semiconductor device PKG1 has a side CVs1 extending along the X direction in the plan view, a side CVs2 positioned on the opposite side of the side CVs1, and Y orthogonal to the X direction. A side CVs3 extending along the direction and a side CVs4 located on the opposite side of the side CVs3 are included. Further, the side CVs1 and the side CVs2 are relatively longer than the side CVs3 and the side CVs4. In the example illustrated in FIG. 3, the lid member CV of the semiconductor device PKG1 has a quadrangular shape (rectangular shape in FIG. 3) in plan view. However, the planar shape of the semiconductor device PKG1 has various modifications other than a quadrangle. For example, among the four corners of a quadrilateral, an intersection portion where the side CVs3 and the side CVs1 intersect may be cut obliquely with respect to the X direction and the Y direction to form a pentagon. In this case, the diagonally cut corners can be used as alignment marks for identifying the orientation of the semiconductor device PKG.

  As shown in FIGS. 2 and 3, the lid member CV has a flange portion FLG that is an attachment portion for fixing the semiconductor device PKG1 to, for example, a heat sink or a support member. As shown in FIG. 3, the flange portion FLG is provided on both sides of the accommodating portion PKT along the X direction which is the longitudinal direction. In addition, through holes THH are formed at the centers of the plurality of flange portions FLG, respectively. The through hole THH is an opening that penetrates the flange portion FLG of the lid material CV in the thickness direction. When the semiconductor device PKG1 is fixed to, for example, a heat sink or a support member, a screw (not shown) is inserted into the through hole THH. The semiconductor device PKG1 can be fixed with screws by inserting (omitted).

  In the example shown in FIG. 3, two through holes THH are formed along an imaginary line VL1 extending in the X direction, which is the longitudinal direction. However, there are various modifications in the positions where the through holes THH are formed. For example, you may provide the through-hole THH in each of the four corner | angular parts by the side of the lower surface CVb of the cover material CV shown in FIG.

  Next, the ceramic substrate CS1 accommodated in the accommodating part PKT of the lid member CV of the semiconductor device PKG1 and each member fixed to the ceramic substrate CS1 will be described.

  As shown in FIGS. 4 and 5, the semiconductor device PKG1 is mounted on the ceramic substrate CS1, the plurality of metal patterns MP formed on the upper surface CSt of the ceramic substrate CS1, and a part of the plurality of metal patterns MP. A plurality of semiconductor chips CP.

As shown in FIG. 4, the ceramic substrate CS1 has an upper surface CSt which is a chip mounting surface on which a plurality of semiconductor chips CP are mounted, and a lower surface CSb located on the opposite side of the upper surface CSt. The ceramic substrate CS1 is made of a ceramic material, and is a plate-like member made of, for example, alumina (aluminum oxide: Al ₂ O ₃ ) in the present embodiment.

  As shown in FIG. 5, the ceramic substrate CS1 has a substrate side CSs1 extending along the X direction, a substrate side CSs2 positioned on the opposite side of the substrate side CSs1, and a Y direction perpendicular to the X direction in plan view. And a substrate side CSs4 located on the opposite side of the substrate side CSs3. Further, the substrate side CSs1 and the substrate side CSs2 are relatively longer than the substrate side CSs3 and the substrate side CSs4. In the example shown in FIG. 5, the ceramic substrate CS1 has a quadrangular shape (rectangular shape in FIG. 5) in plan view.

  Further, as shown in FIG. 4, a plurality of metal patterns MP are bonded to the upper surface CSt and the lower surface CSb of the ceramic substrate CS1. The plurality of metal patterns MP are, for example, a laminated film in which a nickel (Ni) film is laminated on the surface of a copper (Cu) film, and the copper film is directly bonded to the upper surface CSt or the lower surface CSb of the ceramic substrate CS1. Has been. When a copper film is bonded to a plate made of ceramic such as alumina, the bonding is performed using a eutectic reaction. Further, as a method of laminating a nickel film on the surface of the copper film, for example, an electroplating method can be used.

  The metal pattern MPB posted on the lower surface CSb side of the ceramic substrate CS1 is a terminal for heat dissipation, and is uniformly formed so as to cover most of the lower surface CSb of the ceramic substrate CS1.

  Further, as shown in FIG. 6, the plurality of metal patterns MP formed on the upper surface CSt of the ceramic substrate CS1 are wiring patterns constituting a part of the wiring path of the inverter circuit INV, and are separated from each other. A metal pattern MP is formed.

  The plurality of metal patterns MP have a metal pattern MPH to which a high-side potential E1 is supplied. The plurality of metal patterns MP have metal patterns MPL to which a low-side potential E2 lower than the potential E1 is supplied. The plurality of metal patterns MP have metal patterns MPU, MPV, and MPW to which a potential that changes according to the switching operation of the transistor Q1 is supplied. The plurality of metal patterns MP have a plurality of metal patterns MPT for connecting the terminals LD.

  Each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is supplied with a different potential so as to have a phase difference of 120 degrees as described above. For this reason, each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is a metal pattern MP separated from each other. Each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is connected to the metal pattern MPT to which the output terminal LD is connected via a plurality of wires BW, as shown in FIG. Therefore, the U-phase, V-phase, and W-phase output transmission paths shown in FIG. 1 include the wire BW shown in FIG.

  In addition, the same potential (high-side potential E1 (see FIG. 6)) is supplied to the metal pattern MPH in each of the U phase, the V phase, and the W phase (see FIG. 1). Therefore, the metal pattern MPH is not divided in accordance with the distinction between the U phase, the V phase, and the W phase, and is integrally formed. In other words, the high-side potential E1 is supplied to each of the plurality of transistors Q1 without passing through the wire BW. As a modification to FIG. 5, the metal pattern MPH shown in FIG. 5 is divided according to the distinction between the U phase, the V phase, and the W phase, and each of the divided metal patterns MPH is made of a wire or the like. A method of electrically connecting via a conductor pattern (not shown) is also conceivable. However, the impedance of the supply path of the potential E1 can be reduced by forming the metal pattern MPH to which the same potential is supplied, without being divided, as in the present embodiment, and forming them integrally. For this reason, the electrical characteristics of the supply path of the potential E1 can be improved. In addition, the amount of heat generated in the metal pattern MPH can be reduced.

  Further, the same potential (low-side potential E2 (see FIG. 6)) is supplied to the metal pattern MPL in each of the U phase, the V phase, and the W phase (see FIG. 1). Therefore, the metal pattern MPL is not divided according to the distinction between the U phase, the V phase, and the W phase, and is formed integrally. As a modification to FIG. 5, the metal pattern MPL shown in FIG. 5 is divided in accordance with the distinction between the U phase, the V phase, and the W phase, and each of the divided metal patterns MPL is made of a wire or the like. A method of electrically connecting via a conductive member (not shown) is also conceivable. In the case of the low-side metal pattern MPL, as shown in FIG. 5, the semiconductor chip CP and the metal pattern MPL are electrically connected via a wire BW. Therefore, even if the metal pattern MPL is formed without being divided, the wire BW is not excluded from the supply path of the potential E2 (see FIG. 6). However, by forming the metal pattern MPL integrally without dividing, the supply path of the potential E2 can be stabilized, so that the electrical characteristics of the supply path of the potential E2 can be improved. In addition, the amount of heat generated when a reflux current flows through the metal pattern MPL can be reduced.

  Moreover, as shown in FIG. 5, one terminal LD is mounted in each of the plurality of metal patterns MPT among the plurality of metal patterns MP described above. Of the plurality of metal patterns MP, the metal pattern MPH and the metal pattern MPL are each provided with a plurality of terminals LD. In the example shown in FIG. 5, each of the metal pattern MPH and the metal pattern MPL includes terminals LD one by one along the substrate side CSs3 and the substrate side CSs4 which are short sides among the four sides of the upper surface CSt of the ceramic substrate CS1. Is installed.

  Further, as shown in FIG. 5, the terminal LD is not directly connected to each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW among the plurality of metal patterns MP described above. In other words, the terminal LD is not mounted on each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW. Each of metal pattern MPU, metal pattern MPV, and metal pattern MPW is electrically connected to metal pattern MPT via a plurality of wires BW. That is, each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is electrically connected to the terminal LD via the plurality of wires BW and the metal pattern MPT.

  A plurality of semiconductor chips CP are mounted on some of the plurality of metal patterns MP (metal pattern MPH, metal pattern MPU, metal pattern MPV, and metal pattern MPW). Some of the plurality of semiconductor chips CP shown in FIG. 5 are semiconductor chips CTH and CTL for switching elements in which the transistor Q1 shown in FIG. 6 is formed. In the present embodiment, IGBTs are formed in the semiconductor chips CTH and CTL, respectively. Further, another part of the plurality of semiconductor chips CP shown in FIG. 5 is a semiconductor chip CD in which the diode D1 shown in FIG. 6 is formed.

  As described above, when the inductance is connected to the output side of the inverter circuit INV (see FIG. 6), the diode D1 (see FIG. 6) is connected in reverse parallel to the transistor Q1 (FIG. 6) as a switching element. The When the circuit of the transistor Q1 that performs the switching operation and the circuit of the diode D1 that flows the reflux current are built in one semiconductor chip CP like a MOSFET, one semiconductor chip CP is formed according to the number of switching elements. It only has to be installed. However, when the IGBT is used as the transistor Q1, it is necessary to make the semiconductor chip CP for the diode D1 easy. Therefore, in the present embodiment, as shown in FIG. 5, for each of the semiconductor chip CTH including a high-side transistor and the semiconductor chip CTL including a low-side transistor, a semiconductor chip CD including a diode is provided. Mounted in a set.

  As shown in FIGS. 7 and 8, each of the plurality of semiconductor chips CP has an upper surface CPt and a lower surface CPb (see FIG. 8) located on the opposite side of the upper surface. The semiconductor chip CTH and the semiconductor chip CTL each including a transistor have an emitter electrode PDE and a gate electrode PDG that are exposed on the upper surface CPt. In addition, the semiconductor chip CTH and the semiconductor chip CTL including transistors have a collector electrode PDC on the lower surface CPb. The collector electrode PDC is fixed to the upper surface MPm of the metal pattern MP via the solder SD which is a bonding material. Further, the collector electrode PDC is electrically connected to the metal pattern MP through the solder SD.

  Specifically, as shown in FIG. 5, a plurality of semiconductor chips CTH are mounted on the metal pattern MPH. In other words, collector electrodes PDC (see FIG. 8) of the plurality of semiconductor chips CTH are electrically connected to the integrally formed metal pattern MPH. In addition, one semiconductor chip CTL is mounted on each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW. In other words, the collector electrode PDC (see FIG. 8) of the semiconductor chip CTL is electrically connected to each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW.

  Further, a plurality of wires BW are connected to the electrode PDE as shown in FIG. Specifically, as shown in FIG. 5, the electrode PDE (see FIG. 7) of the high-side semiconductor chip CTH is connected to one of the metal pattern MPU, the metal pattern MPV, or the metal pattern MPW via a plurality of wires BW. Has been. That is, the electrode PDE of the high-side semiconductor chip CTH is the U-phase output terminal UT (see FIG. 6), the V-phase output terminal VT (see FIG. 6), or the W-phase output terminal WT (see FIG. 6). Connected to one of them. Further, as shown in FIG. 5, the electrode PDE (see FIG. 7) of the low-side semiconductor chip CTL is connected to the metal pattern MPL via a plurality of wires BW. That is, the electrode PDE of the low-side semiconductor chip CTL is electrically connected to the terminal LT to which the low-side potential E2 shown in FIG. 6 is supplied.

  Further, as shown in FIG. 5, one wire BW is connected to the electrode PDG. Specifically, as shown in FIG. 5, each of the electrodes PDG (see FIG. 7) included in each of the high-side semiconductor chip CTH and the low-side semiconductor chip CTL is electrically connected to the metal pattern MPT via the wire BW. It is connected to the. From the metal pattern MPT, a drive signal for driving the switching operation of the semiconductor chip CTH and the transistor Q1 (see FIG. 6) included in the semiconductor chip CTL is supplied.

  Further, as shown in FIGS. 7 and 8, the semiconductor chip CD including a diode has an anode electrode PDA exposed on the upper surface CPt. As shown in FIG. 8, the semiconductor chip CD has a cathode electrode PDK on the lower surface CPb. The cathode electrode PDK is fixed to the upper surface MPm of the metal pattern MP through the solder SD which is a bonding material. The cathode electrode PDK is electrically connected to the metal pattern MP through the solder SD.

  Specifically, as shown in FIG. 5, a plurality of semiconductor chips CD are mounted on the metal pattern MPH. In other words, cathode electrodes PDK (see FIG. 8) of the plurality of semiconductor chips CD are electrically connected to the integrally formed metal pattern MPH. In addition, one semiconductor chip CD is mounted on each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW. In other words, a cathode electrode PDK (see FIG. 8) of the semiconductor chip CD is electrically connected to each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW.

  In addition, a plurality of wires BW are connected to the electrode PDA as shown in FIG. Specifically, as shown in FIG. 5, the electrode PDA (see FIG. 7) of the high-side semiconductor chip CD is connected to any one of the metal pattern MPU, the metal pattern MPV, or the metal pattern MPW via a plurality of wires BW. It is connected. The electrode PDA (see FIG. 7) of the high-side semiconductor chip CD is also connected to the output metal pattern MPT via a plurality of wires BW. That is, the electrode PDA of the high-side semiconductor chip CD is a U-phase output terminal UT (see FIG. 6), a V-phase output terminal VT (see FIG. 6), or a W-phase output terminal WT (see FIG. 6). Connected to one of them. Further, as shown in FIG. 5, the electrode PDA (see FIG. 7) of the low-side semiconductor chip CD is connected to the metal pattern MPL via a plurality of wires BW. That is, the electrode PDA of the low-side semiconductor chip CD is electrically connected to the terminal LT to which the low-side potential E2 shown in FIG. 6 is supplied.

  The plurality of wires BW shown in FIG. 5 are metal wires, and are made of, for example, aluminum in the present embodiment. However, there are various modifications to the material of the wire BW, and gold or copper can be used in addition to aluminum.

  Further, as shown in FIG. 4, the space between the lid material CV and the ceramic substrate CS1 is filled with a sealing material MG. Each of the plurality of semiconductor chips CP and the plurality of wires BW is sealed with the sealing material MG. The sealing material MG is a member that protects part of the semiconductor chip CP, the wire BW, and the terminal LD. As a sealing member, for example, there is a method of using a resin material that can be cured by heating and ensure a certain degree of strength, such as an epoxy resin. However, when the sealing material MG is cured, stress is generated inside the semiconductor device PKG1 due to a difference in linear expansion coefficient between the ceramic substrate CS1 and the sealing material MG when a temperature cycle load is applied to the semiconductor device PKG1. To do. Therefore, in the present embodiment, the sealing material MG is formed using a resin material softer than the epoxy resin. Specifically, in the present embodiment, the sealing material MG is a silicone resin that is a high molecular compound having a main skeleton formed by a siloxane bond.

  Silicone resins have softer properties than epoxy resins. The stress generated when the temperature cycle load is applied to the semiconductor device PKG1 is reduced by the deformation of the sealing material MG that is a silicone resin.

<Planar shape of metal pattern>
Next, the details of the planar shape of the metal pattern shown in FIG. 5 will be described. FIG. 9 is a plan view showing a layout of a plurality of metal patterns shown in FIG. FIG. 14 is a plan view showing a study example for FIG. FIG. 10 is a plan view showing a modification to FIG.

  In FIG. 9, FIG. 10, and FIG. 14, the region EX1 and the region EX2 are shown with patterns in order to make the range of the region exposed from the metal pattern easy to understand. Further, in FIGS. 9 and 10, in order to clearly indicate the range of the convex portion and the concave portion facing the region EX1 and the region EX2, the portions surrounding the convex portion and the concave portion are hatched. A convex part and a recessed part are the area | regions surrounded by the part which attached | subjects and hatches in FIG.9 and FIG.10.

  First, as described above, in the present embodiment, the metal pattern MPH (see FIG. 9) to which the high-side potential E1 (see FIG. 6) is supplied corresponds to the division of the U phase, the V phase, or the W phase. They are not divided and formed as one piece. Similarly to the metal pattern MPH, the metal pattern MPL (see FIG. 9) to which the low-side potential E2 (see FIG. 6) is supplied is not divided according to the division of the U phase, the V phase, or the W phase. , Integrally formed. Also, different potentials are supplied to the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW so as to have a phase difference of 120 degrees as described above. For this reason, each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is divided according to the division of the U phase, the V phase, or the W phase.

  Here, when the above configuration is simplified, the layout and planar shape of the plurality of metal patterns MP are as in the ceramic substrate CSh1 in the examination example shown in FIG. The ceramic substrate CSh1 of the present embodiment shown in FIG. 9 is that the sides extending along the X direction out of the sides of each of the plurality of metal patterns MP in a plan view extend linearly. Is different.

  Also in the case of the ceramic substrate CSh1, the metal pattern MPH is not divided according to the division of the U phase, the V phase, or the W phase, and is formed integrally, so that the potential is similar to the ceramic substrate CS1 shown in FIG. The electrical characteristics of the supply path of E1 (see FIG. 6) can be improved. In addition, the amount of heat generated in the metal pattern MPH can be reduced.

  However, as a result of examination by the inventors of the present application, it has been found that in the case of a semiconductor device using the ceramic substrate CSh1, a crack is generated in the ceramic substrate CSh1 due to an external force when the semiconductor device is attached. Specifically, the crack is likely to occur in a region EX1 that is provided between the metal pattern MPH and the metal patterns MPU, MPV, and MPW shown in FIG. 14 and is exposed from the metal pattern MP, and is generated in the side MHs1 of the metal pattern MPH. It turns out that it progresses so that it may extend along. Further, the crack is likely to occur in a region EX2 provided between the metal pattern MPL and the metal patterns MPU, MPV, and MPW shown in FIG. 14 and exposed from the metal pattern MP, along the side MHs2 of the metal pattern MPH. It turns out that it progresses so that it may extend.

  On the other hand, it was found that the cracks hardly occur in the region extending along the Y direction among the regions exposed from the metal pattern MP shown in FIG. For example, in the region provided between each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW, the crack is unlikely to occur. Moreover, even if it is the area | region exposed from the metal pattern MP shown in FIG. 14, and is an area | region extended linearly along a X direction, the area | region between edge | side MHs2 of the metal pattern MPH and several metal pattern MPT, In addition, it has been found that the crack is difficult to occur in the region between the side MLs1 of the metal pattern MPL and the plurality of metal patterns MPT.

  From the above findings, it is considered that the crack is likely to occur in a region that is not covered with the metal pattern MP and extends linearly. Further, it is considered that the cracks are more likely to occur as the length of the linearly extending region becomes longer. Therefore, in the case of a substrate having a long side and a short side, such as the ceramic substrate CSh1, the crack is not generated in the region extending along the extending direction (X direction in FIG. 14) of the long sides (the substrate side CSs1 and the substrate side CSs2). It is preferable to take measures to suppress the occurrence.

  In addition, even in the region extending in the X direction as described above, cracks are unlikely to occur at positions close to either the substrate side CSs1 or the substrate side CSs2. Therefore, in the case of having a plurality of regions extending in the X direction, the distance to the center line (virtual line VL1 shown in FIG. 14) connecting the centers of the short sides (substrate side CSs3 and substrate side CSs4) is relatively short. The crack is likely to occur. That is, in the example shown in FIG. 14, the crack is most likely to occur in the region EX1, and then the crack is likely to occur in the region EX2.

  Further, the crack is likely to occur when the semiconductor device is fixed to, for example, a heat sink or a support member. Note that the force that causes the cracks may be a force that is caused by the fact that the tightening force when the semiconductor device is fixed with, for example, a screw varies depending on the fixing location. When the through holes THH for fixing at both ends in the longitudinal direction are provided as shown in FIG. 3, the force resulting from the variation in the tightening force acts mainly along the short side direction (Y direction in FIG. 14). However, when the variation in the tightening force occurs, a force that twists the ceramic substrate CSh1 in the out-of-plane direction acts, and a part of the external force also acts in the long side direction.

  Although not shown, each of the metal pattern MPH and the metal pattern MPL is divided according to the division of the U phase, the V phase, or the W phase, such as the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW. In this case, it was found that the cracks hardly occur in the regions EX1 and EX2. Considering this, it is considered that the occurrence of the cracks can be suppressed by dispersing the stress generated due to the external force when the external force is applied.

  Therefore, the inventor of the present application has studied a technique for suppressing the occurrence of cracks in the region EX1 (and the region EX2), and has found the configuration of the present embodiment. That is, as shown in FIG. 9, the region EX1 provided in the ceramic substrate CS1 of the present embodiment extends in a zigzag manner along the X direction that is the extending direction (longitudinal direction) of the metal pattern MPH. The region EX1 is a region that is provided between the metal pattern MPH and the metal patterns MPU, MPV, and MPW and is exposed from the metal pattern MP. When the region EX1 extends in a zigzag manner, even if an external force is applied to the ceramic substrate CS1, it is difficult for stress to concentrate on a specific location. That is, the stress can be dispersed. As a result, the occurrence of the crack in the region EX1 can be suppressed.

  In the example shown in FIG. 9, the region EX2 that is provided between the metal pattern MPL and the metal patterns MPU, MPV, and MPW and is exposed from the metal pattern MP is the longitudinal direction of the ceramic substrate CS1. It extends zigzag along the X direction. Thereby, generation | occurrence | production of the said crack in area | region EX2 can be suppressed.

  The above-mentioned “extend zigzag along the X direction” means that the line or region does not extend linearly with respect to the X direction, which is the extending direction, and has a bent portion or a curved portion in the extending path. Means that. Accordingly, the embodiment described as “the region EX1 (or the region EX2) extends in a zigzag manner along the X direction” includes various modifications in addition to the embodiment extending so as to draw a rectangular wave as shown in FIG. Is included. For example, the region EX1 (or the region EX2) may extend while meandering along the X direction. For example, the region EX1 (or the region EX2) may extend so as to draw a triangular wave along the X direction.

  Further, the structure of the ceramic substrate CS1 of the present embodiment shown in FIG. 9 can be expressed as follows.

  The metal pattern MPH of the ceramic substrate CS1 of the present embodiment has a side MHs1 extending in the X direction and a side MHs2 located on the opposite side of the side MHs1 in plan view. The sides MHs1 and MHs2 are the long sides of the metal pattern MPH. The side MHs1 is a side facing each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW, and the side MHs2 is a side facing the plurality of metal patterns MPT.

  In addition, each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW included in the ceramic substrate CS1 of the present embodiment is a metal pattern MP arranged between the metal pattern MPH and the metal pattern MPL. The metal pattern MPU, the metal pattern MPV, and the metal pattern MPW are arranged so as to be aligned along the X direction. In addition, each area of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is relatively smaller than the area of the metal pattern MPH.

  The metal pattern MPU has a side MUs1 extending in the X direction and a side MUs2 located on the opposite side of the side MUs1 in plan view. Further, the side MUs1 is a side facing the metal pattern MPL, and the side MUs2 is a side facing the metal pattern MPH.

  The metal pattern MPV has a side MVs1 extending in the X direction and a side MVs2 located on the opposite side of the side MVs1 in plan view. The side MVs1 is a side facing the metal pattern MPL, and the side MVs2 is a side facing the metal pattern MPH.

  The metal pattern MPW has a side MWs1 extending in the X direction and a side MWs2 located on the opposite side of the side MWs1 in plan view. The side MWs1 is a side facing the metal pattern MPL, and the side MWs2 is a side facing the metal pattern MPH.

  Moreover, the metal pattern MPL of the ceramic substrate CS1 of the present embodiment has a side MLs1 extending in the X direction and a side MLs2 located on the opposite side of the side MLs1 in plan view. The sides MLs1 and MLs2 are the long sides of the metal pattern MPL. The side MLs2 is a side facing each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW, and the side MLs1 is a side facing the plurality of metal patterns MPT.

  Here, the side MHs1 of the metal pattern MPH has a convex part PR1 protruding toward the side MUs2 of the metal pattern MPU and a plurality of concave parts DT1 formed on both sides of the convex part PR1 in plan view. Further, the side MHs1 of the metal pattern MPH has a convex part PR1 projecting toward the side MVs2 of the metal pattern MPV and a plurality of concave parts DT1 formed on both sides of the convex part PR1 in plan view. Further, the side MHs1 of the metal pattern MPH has a convex part PR1 projecting toward the side MWs2 of the metal pattern MPW and a plurality of concave parts DT1 formed on both sides of the convex part PR1 in plan view.

  Further, the side MUs2 of the metal pattern MPU has a convex part PR2 projecting toward the side MHs1 of the metal pattern MPH and a concave part DT2 formed between the plurality of convex parts PR2 in plan view. Further, the side MVs2 of the metal pattern MPV has a convex part PR2 projecting toward the side MHs1 of the metal pattern MPH and a concave part DT2 formed between the plurality of convex parts PR2 in plan view. Further, the side MWs2 of the metal pattern MPW has a convex part PR2 projecting toward the side MHs1 of the metal pattern MPH and a concave part DT2 formed between the plurality of convex parts PR2 in plan view.

  Further, the protrusion PR2 included in each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is arranged so as to protrude toward a region surrounded by the plurality of recesses DT1 in plan view.

  By providing the above configuration, the region EX1 provided in the ceramic substrate CS1 can be extended in a zigzag manner along the X direction which is the longitudinal direction of the ceramic substrate CS1.

  Further, in the example shown in FIG. 9, the convex part PR2 included in each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is provided in a region surrounded by the plurality of concave parts DT1 in plan view. In other words, in plan view, the plurality of protrusions PR1 are provided in the plurality of recesses DT2, and the plurality of protrusions PR2 are provided in the plurality of recesses DT1. Thereby, the following effects are acquired. That is, as shown in FIG. 9, the width WEX1 in the Y direction of the region EX1 can be shortened. For this reason, as shown in FIG. 5, the length of the wire BW that electrically connects the semiconductor chip CTH, which is a high-side switching element, and each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is shortened. it can. Specifically, one end of the wire BW that electrically connects the semiconductor chip CTH and each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW is joined to the protrusion PR2 (see FIG. 9). .

  In the case of the ceramic substrate CS2 of the modification shown in FIG. 10, the region EX1 is similar to the ceramic substrate CS1 shown in FIG. 9 in that the region EX1 extends zigzag along the X direction which is the longitudinal direction of the ceramic substrate CS1. Therefore, the occurrence of the crack in the region EX1 can be suppressed. However, paying attention to the width WEX1 of the region EX1 in the Y direction, the ceramic substrate CS2 is not provided with the convex portion PR2 in the region surrounded by the concave portion DT1 in plan view, so the width WEX1 of the region EX1 is as shown in FIG. It is larger than the region EX1 of the ceramic substrate CS1 shown in FIG.

  When the width WEX1 is reduced, as described above, the length of the wire BW that electrically connects the semiconductor chip CTH and each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW can be shortened. In this case, in the circuit shown in FIG. 6, the impedance component of the transmission path connecting the high-side transistor Q1 and the output node can be reduced. Therefore, as shown in FIG. 9, the protrusion PR2 is provided in the region surrounded by the recess DT1 in plan view, so that the impedance of the transmission path that connects the switching element on the high side and the output node. The component can be reduced and the output from the inverter circuit can be stabilized. That is, the electrical characteristics of the inverter circuit can be improved.

  In view of reducing the impedance component of the transmission path connecting the switching element on the high side and the output node, the following configuration is more preferable. That is, as shown in FIG. 5, the semiconductor chip CTH and the metal pattern MPU are electrically connected by a plurality of wires BW, and the semiconductor chip CTH and the metal pattern MPV are electrically connected by a plurality of wires BW. It is preferable to electrically connect CTH and the metal pattern MPW with a plurality of wires BW. Thus, by using a plurality of wires BW, the cross-sectional area of the transmission path connecting the switching element on the high side and the output node can be increased, so that the impedance component can be reduced.

  In the present embodiment, an example in which the wire BW is used as a member for electrically connecting the semiconductor chip CP and the metal pattern MP is shown. However, as a modified example, a metal (for example, an aluminum ribbon) formed in a band shape is shown. ) Can be used. Alternatively, a patterned metal plate (copper clip) can be used to connect via solder. In this case, the impedance can be further reduced as compared with the case where a plurality of wires BW are used.

  As described above, when the high-side switching element and the output node are electrically connected by the plurality of wires BW, it is preferable that the length of each wire BW is shortened. That is, as shown in FIG. 9, it is preferable to increase the area of the convex part PR2. In the example shown in FIG. 9, the areas of the plurality of protrusions PR2 are larger than the areas of the plurality of protrusions PR1 of the metal pattern MPH. For this reason, a space for connecting a plurality of wires BW can be secured.

  Moreover, although the said structure can suppress that the said crack generate | occur | produces in the area | region EX1 shown in FIG. 9, it is preferable to suppress generation | occurrence | production of a crack also in the area | region EX2. Therefore, it is preferable to take measures similar to those of the region EX1 for the region EX2.

  Specifically, the side MUs1 of the metal pattern MPU has a convex part PR3 protruding toward the side MLs2 of the metal pattern MPL and a concave part DT3 formed between the plurality of convex parts PR3 in plan view. Further, the side MVs1 of the metal pattern MPV has a convex part PR3 protruding toward the side MLs2 of the metal pattern MPL and a concave part DT3 formed between the plurality of convex parts PR3 in plan view. Further, the side MWs1 of the metal pattern MPW has a convex part PR3 projecting toward the side MLs2 of the metal pattern MPL and a concave part DT3 formed between the plurality of convex parts PR3 in plan view.

  Further, the side MLs2 of the metal pattern MPL has a convex part PR4 protruding toward the side MUs1 of the metal pattern MPU and a plurality of concave parts DT4 formed on both sides of the convex part PR4 in plan view. Further, the side MLs2 of the metal pattern MPL has a convex part PR4 projecting toward the side MVs1 of the metal pattern MPV and a plurality of concave parts DT4 formed on both sides of the convex part PR4 in plan view. Further, the side MLs2 of the metal pattern MPL has a convex part PR4 protruding toward the side MWs1 of the metal pattern MPW and a plurality of concave parts DT4 formed on both sides of the convex part PR4 in plan view.

  Further, the plurality of convex portions PR4 included in the metal pattern MPL are arranged so as to protrude toward the concave portion DT3 included in each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW in a plan view.

  By providing the above configuration, the region EX2 provided in the ceramic substrate CS1 can extend zigzag along the X direction which is the longitudinal direction of the ceramic substrate CS1.

  Further, from the viewpoint of shortening the width of the region EX2, as shown in FIG. 9, the plurality of convex portions PR4 included in the metal pattern MPL are each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW in plan view. It is preferable to be provided in a region surrounded by the recess DT3 included in the. Thereby, the length of the wire BW for electrically connecting the semiconductor chip CTL which is the low-side switching element shown in FIG. 5 and the metal pattern MPL can be shortened. That is, the impedance component of the transmission path for inputting the low-side potential E2 shown in FIG. 6 can be reduced.

  In the example shown in FIG. 9, the area of the plurality of projections PR4 is larger than the area of the plurality of projections PR3. Therefore, it is possible to secure a space for connecting the plurality of wires BW that electrically connect the semiconductor chip CTL and the metal pattern MPL.

  Incidentally, as described above, it has been found that cracks are likely to occur in the region EX1 and the region EX2 shown in FIG. 14, but the region between the side MHs2 of the metal pattern MPH and the plurality of metal patterns MPT, and the metal pattern MPL. In the region between the side MLs1 and the plurality of metal patterns MPT, the crack is unlikely to occur.

  Therefore, the region where cracks are difficult to occur, that is, the region between the side MHs2 of the metal pattern MPH and the plurality of metal patterns MPT, and the region between the side MLs1 of the metal pattern MPL and the plurality of metal patterns MPT are shown in FIG. As shown, it extends linearly along the X direction. In other words, the side MHs2 of the metal pattern MPH and the side MLs1 of the metal pattern MPL each extend linearly along the X direction. A center line (virtual line VL1 shown in FIGS. 9 and 14) connecting the centers of the short sides (substrate side CSs3 and substrate side CSs4) of the ceramic substrate CS1 is between the side MHs1 of the metal pattern MPH and the side MLs2 of the metal pattern MPL. Since they exist in between, the sides MHs2 and MLs1 are far from the virtual line VL1.

  Thus, when one long side of the metal pattern MPH is formed so as to extend zigzag and the other long side is formed linearly, the area of the metal pattern MPH can be increased. Alternatively, since the semiconductor chip CTH and the semiconductor chip CD shown in FIG. 5 can be easily mounted, the layout of the semiconductor chip CP on the metal pattern MPH is facilitated. On the other hand, when one long side of the metal pattern MPL is formed so as to extend zigzag and the other long side is formed linearly, the area of the metal pattern MPL can be increased.

<Method for Manufacturing Semiconductor Device>
Next, the manufacturing process of the semiconductor device PKG1 described with reference to FIGS. 1 to 10 will be described along the process flow shown in FIG. FIG. 11 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIG.

<Board preparation>
First, in the substrate preparation step shown in FIG. 11, the ceramic substrate shown in FIG. 9 is prepared. A ceramic substrate CS1 prepared in this step is prepared. The ceramic substrate CS1 prepared in this step is a ceramic mainly composed of alumina, for example, and a plurality of metal patterns MP are bonded to the upper surface CSt and the lower surface CSb (see FIG. 4).

  The plurality of metal patterns MP are, for example, a laminated film in which a nickel (Ni) film is laminated on the surface of a copper (Cu) film, and a eutectic reaction is used on the upper surface CSt or the lower surface CSb of the ceramic substrate CS1. Directly joined. Further, a nickel film is laminated on the copper film by electroplating.

  Note that the shapes and layouts of the plurality of metal patterns MP have already been described with reference to FIGS. 9, 10, and 14, and thus redundant description is omitted.

<Die bond>
Next, in the die bonding step shown in FIG. 11, a plurality of semiconductor chips CP are mounted on the metal pattern MP of the ceramic substrate CS1, as shown in FIG. FIG. 12 is a plan view showing a state in which a plurality of semiconductor chips are mounted on a ceramic substrate in the die bonding step shown in FIG.

  In this step, among the plurality of metal patterns MP, the metal pattern MPH to which the high-side potential E1 (see FIG. 6) is supplied includes a plurality (three in this embodiment) of semiconductor chips CTH and a plurality ( In this embodiment, three semiconductor chips CD are mounted. In addition, one semiconductor chip CTL and one semiconductor chip CD are mounted on each of the metal patterns MPU, MPV, and MPW connected to the AC power output terminal among the plurality of metal patterns MP. In addition, the semiconductor chip CP is not mounted on the metal pattern MPL to which the low-side potential E2 (see FIG. 6) is supplied among the plurality of metal patterns MP. Further, among the plurality of metal patterns MP, the semiconductor chip CP is not mounted on the plurality of metal patterns MPT for connecting the input / output terminals LD (see FIG. 5).

  As shown in FIG. 8, in this step, each of the plurality of semiconductor chips CP is mounted by a so-called face-up mounting method with the lower surface CPb of the semiconductor chip CP and the upper surface of the metal pattern MP facing each other. . Further, electrodes PDK and PDC are formed on the lower surface CPb of the semiconductor chip CP, and the semiconductor chip CP is mounted via the solder SD in order to electrically connect the electrodes PDK and PDC to the metal pattern MP. .

  A method of mounting the semiconductor chip CP via solder is performed as follows. First, paste solder is applied to a region where a semiconductor chip is to be mounted. This paste solder contains a solder component and a flux component. Next, a plurality of semiconductor chips CP are prepared (semiconductor chip preparation step shown in FIG. 11) and each is pressed onto the solder. In a state where the plurality of semiconductor chips CP are temporarily bonded onto the metal pattern MP via the paste-like solder, the solder is subjected to a reflow process (heating process). By this reflow process, the solder is melted, one is bonded to the metal pattern MP, and the other is bonded to the electrodes PDK and PDC of the semiconductor chip CP. When the solder is cooled and cured, each of the semiconductor chips CP is fixed on the metal pattern MP.

  In addition to the semiconductor chip CP, when mounting chip components (electronic components, functional elements) other than the semiconductor chip CP, such as a chip capacitor, for example, they can be mounted in a lump in this step.

<Wire bond>
Next, in the wire bonding step shown in FIG. 11, as shown in FIG. 13, the semiconductor chip CP and the metal pattern MP are electrically connected via a wire (conductive member) BW. FIG. 13 is a plan view showing a state in which a plurality of semiconductor chips and a plurality of metal patterns shown in FIG. 12 are electrically connected via wires.

  In this step, each of the emitter electrodes PDE (see FIG. 8) of the plurality of semiconductor chips CTH on the high side and each of the plurality of metal patterns MPU, the metal pattern MPV, and the metal pattern MPW are connected to the plurality of wires BW. Electrical connection through As described above, each of the plurality of wires BW is joined to the convex part PR2 shown in FIG.

  In this step, each of the emitter electrodes PDE (see FIG. 8) of the plurality of semiconductor chips CTL on the low side is electrically connected to the plurality of metal patterns MPL via the plurality of wires BW. As described above, each of the plurality of wires BW is joined to the convex part PR4 shown in FIG.

  In this step, the gate electrodes PDG (see FIG. 8) of the plurality of semiconductor chips CTH on the high side and the gate electrodes PDG of the plurality of semiconductor chips CTL on the low side, and the plurality of metal patterns MPT are formed. Electrical connection is made via the wire BW.

  In this step, the anode electrode PDA of the plurality of semiconductor chips CD on the high side side, the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW, and the plurality of metal patterns MPT via the plurality of wires BW. Are electrically connected to each other via a plurality of wires BW. As shown in FIG. 13, a plurality of locations can be electrically connected by a single wire BW. In the example shown in FIG. 13, first, one end of the wire BW is connected to any one of the plurality of metal patterns MPU, the metal pattern MPV, and the metal pattern MPW. At this time, as described above, the end portion of the wire BW is joined to the convex portion PR2 shown in FIG. Next, the intermediate portion of the wire BW is connected to the anode electrode PDA of the semiconductor chip CD. Next, the other end of the wire BW is bonded to the metal pattern MPT.

  In this step, the anode electrodes PDA of the plurality of low-side semiconductor chips CD and the plurality of metal patterns MPT are electrically connected via the plurality of wires BW via the plurality of wires BW. .

  In the present embodiment, an example is shown in which a wire is used as a member for electrically connecting the semiconductor chip CP and the metal pattern MP. However, as a modification, a metal (for example, an aluminum ribbon) formed in a band shape is shown. Can also be used. Alternatively, a patterned metal plate (copper clip) can be used to connect via solder.

<With terminal>
Next, in the terminal mounting step shown in FIG. 11, the terminals LD are mounted on the plurality of metal patterns MP as shown in FIG. The terminal LD is a lead terminal for electrically connecting a plurality of metal patterns and an external device (not shown), and has one end portion that is elongated and connected to the metal pattern MP. In the example shown in FIG. 4, each of the plurality of terminals LD is mounted on the metal pattern MP via the solder SD.

  In the example shown in FIG. 5, among the plurality of metal patterns MP, the metal pattern MPH to which a high-side potential is supplied and the metal pattern MPL to which a low-side potential is supplied have both ends in the longitudinal direction. Terminals LD are mounted on the substrate side CSs3 side and the substrate side CSs4 side which are short sides. One terminal LD is mounted on each of the plurality of metal patterns MPT. Further, the terminals LD are not mounted on each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW.

<Cover attachment>
Next, in the lid member attaching step shown in FIG. 11, as shown in FIG. 4, the lid member CV is bonded and fixed so as to cover the upper surface CSt of the ceramic substrate CS1. The peripheral edge portion of the upper surface CSt of the ceramic substrate CS1 and the lid material CV are bonded and fixed via an adhesive material BD1.

  At this time, a plurality of through holes THL are formed in the upper surface CVt of the lid member CV, and the plurality of terminals LD are inserted into the plurality of through holes THL, respectively.

  In the example shown in FIG. 4, the cover material CV is integrally formed with a portion where a plurality of through holes THL are formed and a portion that is bonded and fixed to the ceramic substrate CS1. However, as a modification, an independent member that can separate a portion that is bonded and fixed to the ceramic substrate CS1 and a portion in which the plurality of through holes THL are formed may be used. In this case, even when the layout of the terminal LD is changed, only the portion where the plurality of through holes THL are formed needs to be replaced.

<Sealing>
Next, in the sealing step shown in FIG. 11, as shown in FIG. 4, the sealing material MG is supplied into the space surrounded by the ceramic substrate CS <b> 1 and the lid material CV, and a part of each of the plurality of terminals LD, The plurality of semiconductor chips CP and the plurality of wires BW are sealed. The sealing material MG is a gel material, and a supply through hole (not shown) is formed in a part of the lid material CV, and the gel sealing material MG is filled from the through hole.

  Through the above steps, the semiconductor device PKG1 described with reference to FIGS. 1 to 10 is obtained. After that, necessary inspections and tests such as appearance inspection and electrical test are performed and shipped. Moreover, it integrates in the power conversion system shown in FIG.

<Modification>
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. In addition, although some modifications were demonstrated also in the said embodiment, below, the typical modifications other than the modification demonstrated in the said embodiment are demonstrated.

<Modification 1>
For example, in the above embodiment, a power conversion circuit that outputs three-phase AC power using three high-side transistors Q1 and three low-side transistors Q1 as switching elements has been described. There are various variations in the number of elements.

  For example, if a half-bridge circuit is configured using one high-side transistor and one low-side transistor, single-layer AC power can be output. When a single-layer alternating current is output by a full bridge circuit, four transistors Q1 are used.

  In this case, in order to reduce the impedance of the metal pattern MP to which the high-side potential is supplied, a plurality of switching elements are mounted on one metal pattern MP, so the length of one side of the metal pattern MP. Becomes longer. Therefore, as described in the above embodiment, the region facing the long side of the metal pattern MP and not covered by the metal pattern MP is formed to extend zigzag along the extending direction of the long side. Thereby, generation | occurrence | production of the crack in this area | region can be suppressed.

<Modification 2>
Further, for example, in the above embodiment, as the layout of the metal pattern MP on the ceramic substrate CS1, the metal patterns MPU, MPV, and MPW are arranged side by side between the high-side metal pattern MPH and the low-side metal pattern MPL. The embodiment to be described has been described.

  However, as a modification, a metal pattern MPL for low side may be provided between the metal pattern MPH for high side and the metal patterns MPU, MPV, MPW arranged side by side along the X direction. . In this case, among the sides of the low-side metal pattern MPL, the convex portion PR4 (see FIG. 9) and the concave portion DT4 (see FIG. 9) adjacent to the convex portion PR4 are formed on the side MLs2 (see FIG. 9) facing the metal pattern MPH. Preferably). Further, it is preferable that a region provided between the metal pattern MPH and the metal pattern MPL and exposed from the metal pattern MP extends in a zigzag manner along the extending direction of the metal pattern MPH.

  Moreover, it is preferable to provide a recessed part and the convex part adjacent to the said recessed part in the edge | side (illustration omitted) which opposes each of metal pattern MPU, MPV, and MPW among the edges which the metal pattern MPL for low sides has.

<Modification 3>
For example, as described above, various modified examples have been described, but the above-described modified examples can be applied in combination.

  In addition, a part of the contents described in the embodiment will be described below.

(1)
(A) preparing a ceramic substrate having a first surface, a second surface located opposite to the first surface, and a plurality of metal patterns formed on the first surface;
(B) mounting a plurality of first semiconductor chips on a first metal pattern of the plurality of metal patterns;
(C) electrically connecting at least a part of the plurality of first semiconductor chips and a second metal pattern of the plurality of metal patterns;
Have
The plurality of metal patterns are:
A first metal pattern comprising a first side, on which a plurality of first semiconductor chips among the plurality of semiconductor chips are mounted;
A second metal pattern having a second side opposite to the first side of the first metal pattern;
Have
Of the first surface of the ceramic substrate, the first region provided between the first metal pattern and the second metal pattern and exposed from the plurality of metal patterns extends from the first metal pattern. A method for manufacturing a semiconductor device, wherein the method extends in a zigzag along a first direction.

BD1 Adhesive BW wire (conductive member)
CD, CP, CTH, CTL Semiconductor chip CMD Control circuit CNV Converter circuit CPb Lower surface CPt Upper surface CS1, CS2, CSh1 Ceramic substrate CSb Lower surface CSs1, CSs2, CSs3, CSs4 Substrate side CSt Upper surface CV Lid (cap, cover member)
CVb Lower surface CVs1, CVs2, CVs3, CVs4 Side CVt Upper surface D1 Diode DT1, DT2, DT3, DT4 Recessed DTC Distribution circuit E1, E2 Potential EX1, EX2 Region FLG Flange portion INV Inverter circuit LD terminal LT terminal MG1 Sealing material MH , MLs1, MLs2, MUs1, MUs2, MVs1, MVs2, MWs1, MWs2 Side MP, MPB, MPH, MPL, MPT, MPU, MPV, MPW Metal pattern MPm Upper surface PDA, PDC, PDE, PDG, PDK Electrode PKG1 Semiconductor device PKT1 Housing (pocket)
PR1, PR2, PR3, PR4 Convex part Q1 Transistor SCM Solar cell module SD Solder THH, THL Through hole UT, VT, WT Output terminal VL1 Virtual line (center line)
WEX1 width

Claims (9)

A ceramic substrate having a first surface and a second surface located opposite the first surface;
A plurality of metal patterns formed on the first surface of the ceramic substrate;
A plurality of semiconductor chips mounted on a part of the plurality of metal patterns;
Have
The plurality of metal patterns are:
A first metal pattern comprising a first side and mounted with a plurality of first semiconductor chips among the plurality of semiconductor chips;
A second metal pattern having a second side opposite to the first side of the first metal pattern and a third side located on the opposite side of the second side and separated from the first metal pattern When,
A third metal pattern comprising a fourth side opposite to the third side of the second metal pattern and separated from the first metal pattern and the second metal pattern;
Have
The first side of the first metal pattern has a first portion extending in a first direction and a second portion extending in a second direction that is continuous with the first portion and intersects the first direction in plan view. And a third portion that is continuous with the second portion and extends in the first direction,
The second side of the second metal pattern, in plan view, extends in the first direction and is opposed to the first part of the first side, and is connected to the fourth part; and A fifth portion extending in the second direction and facing the second portion of the first side; connected to the fifth portion; and extending in the first direction; and the first side of the first side A sixth portion facing the third portion;
The third side of the second metal pattern has a seventh portion extending in the first direction, an eighth portion extending in the second direction and extending in the second direction in the plan view, and the eighth portion. A ninth portion extending in the first direction and connected to the portion;
The fourth side of the third metal pattern, in plan view, extends in the first direction and is continuous with the tenth portion facing the seventh portion of the third side; and An eleventh portion extending in the second direction and facing the eighth portion of the third side; connected to the eleventh portion; and extending in the first direction; and A twelfth portion facing the ninth portion;
At least some of the plurality of first semiconductor chips are electrically connected to the second metal pattern through a plurality of wires,
Each of the plurality of wires is a semiconductor device bonded to a region of the second metal pattern surrounded by the fourth portion and the fifth portion. In claim 1,
The length of the second part of the first side of the first metal pattern is shorter than the length of the first part of the first side,
The length of the fifth portion of the second side of the second metal pattern is shorter than the length of the fourth portion of the second side. In claim 1,
Each of the plurality of wires extends in a plan view so as to straddle the first portion of the first side and the fourth portion of the second side. In claim 3,
The length of the first portion of the first side of the first metal pattern is longer than the length of the third portion of the first side. In claim 1,
The length of the second part of the first side of the first metal pattern is shorter than the length of the third part of the first side,
The length of the fifth portion of the second side of the second metal pattern is shorter than the length of the sixth portion of the second side. In claim 1,
The first surface of the ceramic substrate includes a first substrate side extending along the first direction, a second substrate side positioned on the opposite side of the first substrate side, and a third substrate extending along the second direction. A fourth substrate side located on the opposite side of the side and the third substrate side,
The lengths of the first substrate side and the second substrate side are longer than the lengths of the third substrate side and the fourth substrate side,
The semiconductor device, wherein each of the first side of the first metal pattern and the second side of the second metal pattern is provided along the first direction. In claim 1,
A first potential is supplied to the first metal pattern,
The semiconductor device, wherein a second potential different from the first potential is supplied to the second metal pattern. A ceramic substrate having a first surface and a second surface located opposite the first surface;
A plurality of metal patterns formed on the first surface of the ceramic substrate;
A plurality of semiconductor chips mounted on a part of the plurality of metal patterns;
Have
The plurality of metal patterns are:
A first metal pattern comprising a first side and mounted with a plurality of first semiconductor chips among the plurality of semiconductor chips;
A second metal pattern having a second side opposite to the first side of the first metal pattern and a third side located on the opposite side of the second side and separated from the first metal pattern When,
A third metal pattern comprising a fourth side opposite to the third side of the second metal pattern and separated from the first metal pattern and the second metal pattern;
Have
The first side of the first metal pattern has a first portion extending in a first direction and a second portion extending in a second direction that is continuous with the first portion and intersects the first direction in plan view. And a third portion that is continuous with the second portion and extends in the first direction,
The second side of the second metal pattern, in plan view, extends in the first direction and is opposed to the first part of the first side, and is connected to the fourth part; and A fifth portion extending in the second direction and facing the second portion of the first side; connected to the fifth portion; and extending in the first direction; and the first side of the first side A sixth portion facing the third portion;
The third side of the second metal pattern has a seventh portion extending in the first direction, an eighth portion extending in the second direction and extending in the second direction in the plan view, and the eighth portion. A ninth portion extending in the first direction and connected to the portion;
The fourth side of the third metal pattern, in plan view, extends in the first direction and is continuous with the tenth portion facing the seventh portion of the third side; and An eleventh portion extending in the second direction and facing the eighth portion of the third side; connected to the eleventh portion; and extending in the first direction; and And a twelfth portion facing the ninth portion. The semiconductor device according to claim 8,
The first surface of the ceramic substrate includes a first substrate side extending along the first direction, a second substrate side positioned on the opposite side of the first substrate side, and a third substrate extending along the second direction. A fourth substrate side located on the opposite side of the side and the third substrate side,
The lengths of the first substrate side and the second substrate side are longer than the lengths of the third substrate side and the fourth substrate side,
The plurality of metal patterns are disposed between the first substrate side of the ceramic substrate and the first metal pattern, and between the third substrate side of the ceramic substrate and the third metal pattern. Having a plurality of fourth metal patterns;
The first metal pattern includes a fifth side that is located on the opposite side of the first side and extends linearly along the first direction so as to face the plurality of fourth metal patterns.
The third metal pattern includes a sixth side that is located on the opposite side of the fourth side and extends linearly along the first direction so as to face the plurality of fourth metal patterns,
The first imaginary line connecting the center of the third substrate side and the center of the fourth substrate side of the ceramic substrate is the first side of the first metal pattern and the fourth side of the third metal pattern. A semiconductor device that exists in between.

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