JP6558008B2 - Transfer device, transfer system, and program - Google Patents

Description

  The present invention relates to a transfer device, a transfer system, and a program.

  Patent Document 1 discloses a technique for monitoring data transfer between a cache and a main memory, determining an address of the accessed main memory, and selecting a data transfer path.

Japanese Patent Laid-Open No. 2008-140078

  An object of the present invention is to achieve both the maintenance of the consistency of the storage contents shared by a plurality of devices and the improvement of the processing speed of these devices.

The transfer device according to claim 1 of the present invention includes a first communication path that communicates with a memory controller that reads and writes to a specified area among a plurality of areas in the shared memory, and one or more operations A second communication path that communicates with an arbitration device that arbitrates a request from a device, designates an area in the shared memory to the memory controller based on the request, and requests read / write; The accepting means for accepting a request for data stored in the shared memory and the request output from the arbitration device to the memory controller are monitored, and the writing process to the area designated by the request is not completed. A registration means for registering the area and the request via the first communication path when the request from the requesting device is not for the area registered by the registration means. Acquiring the data from the controller, and when the request is for the area, acquiring means for acquiring the data from the arbitrating device via the second communication path, and transferring the acquired data to the requesting device possess a transferring means for the said registering means, the request is a request for reading processing, and, when the area specified by the request is not registered, register the region, the When the request is a request for write processing, the number of times of write processing to the area specified by the request is counted, and when the number of times reaches a threshold, it is assumed that the write processing is completed. It is characterized by releasing .

A transfer system according to a second aspect of the present invention includes the above-described transfer device, a memory controller that communicates with the transfer device via the first communication path, and reads / writes from / to a specified area in the shared memory, A device that arbitrates requests between devices, communicates with the transfer device via the second communication path, and allocates an area in the shared memory to the memory controller based on a request from one or more arithmetic devices. An arbitration device that designates a read / write request and a request device that sends a request for data stored in the shared memory to the transfer device.

According to a third aspect of the present invention, a program includes a first communication path that communicates with a memory controller that reads from and writes to a specified area among a plurality of areas in the shared memory, and one or more arithmetic devices A second communication path that communicates with an arbitration device that arbitrates a request from the network and designates an area in the shared memory to the memory controller based on the request and requests read / write, A receiving unit that receives a request for data stored in the shared memory from a requesting device; and a request that is output from the arbitrating device to the memory controller, and a write process to an area specified by the request is performed If not completed, the registration means for registering the area, and the request of the requesting device is not for the area registered by the registration means, Acquiring the data from the memory controller via one communication path, and acquiring the data from the arbitration device via the second communication path when the request is for the area; In addition to functioning as transfer means for transferring data to the requesting device, the registration means, when the request is a request for read processing and the area specified in the request is not registered, When an area is registered and the request is a request for write processing, the number of write processes to the area specified by the request is counted, and when the number reaches the threshold, the write process is completed. As a result, it is a program for causing the computer to function so as to release the area .

According to the first and third aspects of the present invention, it is possible to achieve both maintenance of consistency of stored contents shared by a plurality of devices and improvement in processing speed of these devices.
Further , according to the first to third aspects of the invention, the number of registered areas is suppressed as compared with the case where the number of times of writing is not counted.

The figure which shows the whole structure of the transfer system which concerns on this embodiment. The figure which shows the functional structure of a transfer apparatus. The figure which shows the example of a management table. The figure for demonstrating a shared memory. The sequence diagram which shows operation | movement of a transfer system. The flowchart which shows operation | movement of the registration process in a transfer apparatus. The figure which shows the example of the management table | surface in a modification. The figure for demonstrating the shared memory in a modification. The flowchart which shows operation | movement of the registration process of the transfer apparatus in a modification.

1. Embodiment 1-1. Overall Configuration of Transfer System FIG. 1 is a diagram showing an overall configuration of a transfer system 9 according to the present embodiment. As shown in FIG. 1, the transfer system 9 includes a transfer device 1, a memory controller 3, an arbitration bus 5, and a request device 7. The transfer system 9 includes a shared memory 2, one or more arithmetic devices 4, and an internal bus 6.

  The shared memory 2 is a memory shared between devices constituting the transfer system 9 and is a memory that is read and written by the memory controller 3. The storage capacity of the shared memory 2 is 8 gigabytes, for example. The shared memory 2 is divided into a plurality of areas (areas) in advance for each determined data amount.

  The memory controller 3 is a control device that reads and writes a specified area in the shared memory 2. The memory controller 3 communicates with the transfer device 1 via the first communication path P1. The memory controller 3 receives a read / write request from the arbitration bus 5. This request is monitored by the transfer device 1.

  The arbitration bus 5 is called a cache coherent interconnect (CCI) bus or the like, and functions as a device (arbitration device) that arbitrates requests from the arithmetic device 4. Here, “arbitration” means that when multiple requests are received, the location of the target data is specified for those requests, the processing order is assigned, and the request source of each request is processed. It means to make it wait until it is executed.

  The arbitration bus 5 communicates with the transfer device 1 via the second communication path P2, and designates an area in the shared memory 2 with respect to the memory controller 3 based on a request from one or more arithmetic devices 4, and reads / writes are requested. do. The arbitration bus 5 operates to maintain consistency (coherency) between the data stored in the shared memory 2 and the data read from the shared memory 2 to the cache memory of the arithmetic device 4.

  Since the arbitration bus 5 accepts requests from the transfer device 1 in addition to requests from one or more arithmetic devices 4, the arbitration bus 5 has a temporary storage area for storing a queue for managing the processing of these requests. If the request processing speed cannot keep up with the amount of requests generated, the queue may be congested and it may take some time for the requested processing to be executed.

  The arithmetic device 4 is a device for requesting reading and writing by designating an area in the shared memory 2 to the memory controller 3 via the arbitration bus 5. The number of the arithmetic devices 4 shown in FIG. 1 is two, and each has a cache memory 41 as a temporary storage area used for arithmetic operations. The storage capacity of the cache memory 41 is, for example, 1 megabyte.

The requesting device 7 is a device called direct memory access (DMA) or the like, and is a device that sends a read request for data stored in the shared memory 2 to the transfer device 1.
The transfer device 1 is a device that determines the data request destination according to the content of the request from the requesting device 7, acquires the data, and transfers the acquired data to the requesting device 7.
The internal bus 6 is a bus that relays information transmission between the requesting device 7 and the transfer device 1.

1-2. Configuration of Transfer Device The transfer device 1 includes an arithmetic processing device and a storage device such as a ROM (Read Only Memory) and a RAM (Random Access Memory) as necessary.

  FIG. 2 is a diagram illustrating a functional configuration of the transfer apparatus 1. The transfer device 1 functions as a reception unit 11, a registration unit 12, an acquisition unit 13, a transfer unit 14, a monitoring unit 15, and a storage unit 16.

The monitoring unit 15 monitors the request of the arithmetic device 4 transmitted from the arbitration bus 5 to the memory controller 3.
The registration unit 12 checks whether or not the writing process to the area specified by the request monitored by the monitoring unit 15 is completed. If the registration processing is not completed, the registration unit 12 stores the area in the management table 161 of the storage unit 16. sign up.

  The storage unit 16 includes a storage device such as the above-described ROM or RAM, and stores a management table 161.

  FIG. 3 is a diagram illustrating an example of the management table 161. The management table 161 is a table for registering the area specified by the request when the writing process to the area specified by the request monitored by the monitoring unit 15 is not completed. As shown in FIG. 3A, each area in the shared memory 2 designated by the request for reading is assigned a unique number, and the start position (SP) and the number of times of writing (CT) of the area are indicated. Described in the record that contains it. The number of times of writing indicates the number of times data is written in the area designated by the arithmetic unit 4.

  When the arithmetic unit 4 makes a request to write data from the cache memory 41 to the shared memory 2, it starts the writing process from the start position of the designated area, and then resumes the writing process to that area. On the other hand, a request is made to continue writing at the position where the previous writing process was performed. Therefore, the writing process does not start from the middle of the area, which is not the starting position, and the part where the writing process is completed in the area is not separated and ubiquitous. However, the writing process for another area may be interrupted during the writing process for a certain area. The upper limit of records described in the management table 161 is n.

  Note that the record indicating the area is not always described by the combination of the start position and the number of times of writing. For example, as shown in FIG. 3B, the combination of the start position (SP) and the completion position (EP). May be described. The completion position is indicated by a value obtained by adding the total amount of data written up to when the request is monitored by the monitoring unit 15 to the start position. Therefore, the completion position is an example of a value corresponding to the number of times of writing processing to the area. If the write process is not performed after the read process is performed on the area, for example, a position common to the start position is written in the completion position of the record, or “N / A” indicating an unusable value is indicated. Is entered.

  Further, as indicated by a broken line in FIG. 3, each record may be provided with a field describing the identification information of the communication path associated with the area. This is a field indicating via which communication path data should be acquired when a request for data for the area indicated by the record is sent from the requesting device 7. In this field, the registration unit 12 describes the first communication path P1 if the writing process to the area indicated by the record is completed, and the second communication path P2 otherwise.

  For example, when the number of times of writing to a certain area reaches a predetermined threshold, the transfer apparatus 1 determines that the writing process has been completed, and describes the first communication path P1 in the above field. Therefore, it is determined that the writing process is not completed, and the second communication path P2 is described in the above field.

  The requesting device is used in a period until the record indicating the area is deleted from the management table 161, that is, until the area is released in the management table 161 after the number of times of writing to the area reaches a predetermined threshold. If there is no request from 7, or if the request is queued, this field may not be present.

  FIG. 4 is a diagram for explaining the shared memory 2. The first line in FIG. 4 shows the entire shared memory. As described above, the shared memory 2 is divided into a plurality of areas for each determined data amount. The shared memory 2 shown in FIG. 4 is divided into m areas to which numbers “1” to “m” are assigned.

  The upper limit n of records in the management table 161 is equal to or less than the number m of areas in the shared memory 2 (m ≧ n). When the upper limit of the interrupt in the arbitration bus 5 is determined, the upper limit n of the record in the management table 161 may be determined according to the upper limit of the interrupt.

  The second line in FIG. 4 shows one area. An area includes a fixed number of minimum units. One area may be configured to have a storage capacity corresponding to the cache memory 41 of the arithmetic device 4.

  The area shown in FIG. 4 includes “k” minimum units from “0” to “k−1”. In the area shown in FIG. 4, the hatched portion indicates the range where the writing process is completed. Therefore, in the area with the number “2” shown in FIG. 4, the number of times of writing is 3, and the writing process is completed for the minimum unit of 3 from the start position.

  The third line in FIG. 4 shows one minimum unit. The minimum unit is data written to the shared memory 2 from the cache memory 41 of the arithmetic device 4 in one writing process by the memory controller 3, and the amount of data is, for example, 16 bytes. Therefore, all the data in one minimum unit is either completed or not completed, and the data that has been completed in one minimum unit is completed. There is no coexistence with no data. Note that the position of data in the shared memory 2 is described in units of bytes.

  The accepting unit 11 accepts a request for data stored in the shared memory 2 from the requesting device 7 via the internal bus 6. When receiving the data request, the receiving unit 11 passes the request to the acquiring unit 13.

  The acquiring unit 13 determines whether the request from the requesting device is for the registered area based on the request received by the receiving unit 11 and the registered content of the management table 161. Then, the acquisition unit 13 selects one of the arbitration bus 5 and the memory controller 3 as a data request destination according to the determination result, and acquires data from the selected request destination.

If the determination unit 13 determines that the request from the requesting device 7 is not for the area registered in the management table 161 as a result of the determination, the acquisition unit 13 acquires data from the memory controller 3 via the first communication path P1. On the other hand, when determining that the request from the requesting device 7 is for the area registered in the management table 161, the acquiring unit 13 acquires data from the arbitration bus 5 via the second communication path P2.
The transfer unit 14 transfers the data acquired by the acquisition unit 13 to the requesting device 7 via the internal bus 6.

1-3. Operation of Transfer System FIG. 5 is a sequence diagram showing the operation of the transfer system 9. The transfer device 1 is set to acquire data requested from the requesting device 7 from the memory controller 3 via the first communication path P1 in an initial state immediately after the power is supplied.

  The arbitration bus 5 that has received a request from any of the arithmetic devices 4 makes a read / write request to the memory controller 3 by designating an area in the shared memory 2 based on the request (step S001). The transfer device 1 monitors this request in step S001 (step S002). Then, the transfer device 1 registers this area when the writing process to the area designated by this request is not completed (step S100). This registration process will be described later.

  Next, when the requesting device 7 requests the transfer device 1 to read data by designating any area in the shared memory 2 (step S011), the transfer device 1 that has received this request And the contents registered in step S100 (step S012), and from either the memory controller 3 or the arbitration bus 5 (in the example shown by the solid line in FIG. 5, the memory controller 3). ), The data of the area requested by the requesting device 7 is acquired (step S013). Then, the transfer device 1 transfers the acquired data to the requesting device 7 (step S014).

1-4. Operation of Transfer Device (1) Operation of Registration Process FIG. 6 is a flowchart showing the operation of registration processing of the transfer device 1. The transfer device 1 monitors the request output from the arbitration bus 5 to the memory controller 3, and determines whether or not a request for read processing or write processing from the arithmetic device 4 to the memory controller 3 has been detected (step). S101). When determining that these requests are not detected (step S101; NO), the transfer apparatus 1 continues this determination.

  On the other hand, when determining that a request for a read process or a write process from the arbitration bus 5 to the memory controller 3 has been detected (step S101; YES), the transfer device 1 identifies the area specified by the detected request (step S101: YES). Step S102). Then, the transfer device 1 determines whether or not the request is for reading processing (step S103), and if it is determined that the request is for reading processing (step S103; YES), step If it is determined that the processing is not for reading processing (that is, for writing processing) (step S103; NO), the processing proceeds to step S106.

  In step S104, the transfer apparatus 1 determines whether the area specified in step S102 is not registered in the management table 161, that is, is a new area (referred to as a new area) (step S104). When determining that the identified area is a new area (step S104; YES), the transfer apparatus 1 registers this area in the management table 161. Thereby, this new area is set as an area where data should be acquired from the arbitration bus 5 via the second communication path P2 when requested by the requesting device 7.

  On the other hand, if it is determined that the specified area is not a new area (step S104; NO), the transfer apparatus 1 returns the process to step S101 without performing the registration in step S105.

  In step S106, the transfer apparatus 1 searches the management table 161 for the area specified in step S102, and adds “1” to the number of times of writing the record in which this area is described (step S106). In other words, when the monitoring unit 15 monitors a request for write processing, the transfer device 1 counts the number of times of write processing to the area specified by the request.

  Then, the transfer device 1 determines whether or not the writing process has been completed based on the number of times of writing after “1” is added (step S107). This determination is made based on, for example, whether or not the write count has reached a predetermined threshold value. The determined threshold is, for example, a value obtained by dividing the data amount of the area by the minimum unit, that is, the number of write processes necessary for overwriting one area. Note that this threshold value in FIG. 3 is a numerical value expressed as “0xFFFF” in hexadecimal and “65535” in decimal.

  When determining that the writing process has been completed (step S107; YES), the transfer apparatus 1 releases the above-described area (step S108), and returns the process to step S101. That is, when the write count reaches a predetermined threshold value, the transfer device 1 releases the area on the assumption that the write process has been completed.

  On the other hand, when it is determined that the writing process is not completed (step S107; NO), the transfer apparatus 1 returns the process to step S101 as it is.

  As described above, the transfer device 1 registers the area designated by the calculation device 4 in the request for the read process in the management table 161 of the storage unit 16, and writes based on the number of write processes for the area. It is determined whether or not the processing is completed, and when the writing processing is completed, the registered area is released.

  Then, when there is a data request from the requesting device 7 to the area registered in the management table 161, the transfer device 1 acquires the requested data from the arbitration bus 5 via the second communication path P2. If there is a request for any other area, the requested data is acquired from the memory controller 3 via the first communication path P1 and transferred to the requesting device 7, respectively.

  The area registered in the management table 161 is an area for which the calculation device 4 has requested read processing and the write processing has not been completed. Therefore, the latest data to be written to the area is not yet calculated. There is a high possibility of being on the cache memory 41 of the device 4.

  Therefore, the transfer device 1 acquires and transfers data from the arbitration bus 5 when there is a high possibility that the data requested by the requesting device 7 is in the cache memory 41 of the arithmetic device 4. Is maintained. Further, when there is no possibility that the data requested by the requesting device 7 is in the cache memory 41 of the arithmetic device 4, the data is acquired from the memory controller 3 and transferred, so that the data is acquired from the arbitration bus 5. Thus, the data transfer speed is improved.

2. Modification The above is the description of the embodiment, but the contents of this embodiment can be modified as follows. Further, the following modifications may be combined.

2-1. Modification 1
In the embodiment described above, the transfer device 1 increments the number of writes associated with an area in the management table 161 every time a write process is detected, and whether or not the number of writes reaches a predetermined threshold. Thus, although it has been determined whether or not the writing process for this area has been completed, the transfer apparatus 1 does not have to count the number of times of writing.

  FIG. 7 is a diagram showing an example of the management table 161 in this modification. FIG. 8 is a diagram for explaining the shared memory 2 in this modification. In this modification, the shared memory 2 is divided into a plurality of areas for each determined data amount, and the data amount is a minimum unit data amount. Therefore, each area is composed of a minimum unit.

  In this case, as shown in FIG. 7, the management table 161 does not need to store the number of times of writing shown in FIG. 3 in association with each area where the request for the reading process is detected. This is because the amount of data written by a single writing process is the minimum unit data amount, and there is no “middle” of the process in the writing process to the area configured by the minimum unit. Therefore, when a request for read processing is detected, the area specified by the request is registered in the management table 161, and when a request for write processing is detected, the area specified by the request Are released from the management table 161.

  FIG. 9 is a flowchart showing the operation of the registration process of the transfer apparatus 1 in this modification. In this modification, the transfer device 1 executes the registration process shown in FIG. 9 in step S110 instead of the registration process shown in step S100 in FIGS.

  The transfer device 1 monitors the request output from the arbitration bus 5 to the memory controller 3, and determines whether or not a request for read processing or write processing from the arithmetic device 4 to the memory controller 3 has been detected (step). S111). When determining that these requests are not detected (step S111; NO), the transfer apparatus 1 continues this determination.

  On the other hand, when it is determined that a request for a read process or a write process from the arbitration bus 5 to the memory controller 3 has been detected (step S111; YES), the transfer apparatus 1 identifies the area specified by the detected request (step S111: YES). Step S112). Then, the transfer device 1 determines whether or not the request is for reading processing (step S113), and if it is determined that the request is for reading processing (step S113; YES), step If it is determined that the process is not for reading processing (step S113; NO), the process proceeds to step S118.

  In step S114, the transfer device 1 determines whether or not the area specified in step S112 is a new area (step S114). When determining that the identified area is a new area (step S114; YES), the transfer apparatus 1 registers this area in the management table 161. On the other hand, when determining that the specified area is not a new area (step S114; NO), the transfer apparatus 1 returns the process to step S111 without performing the registration in step S115.

  In step S118, the transfer apparatus 1 determines that the area specified in step S112 is designated by the request for the writing process, and that the writing process is completed by executing the writing process. Release (step S118), and the process returns to step S111.

  Also in this modification, the transfer device 1 acquires and transfers data from the arbitration bus 5 when there is a high possibility that the data requested by the requesting device 7 is in the cache memory 41 of the arithmetic device 4. 2 consistency is maintained. Further, when there is no possibility that the data requested by the requesting device 7 is in the cache memory 41 of the arithmetic device 4, the data is acquired from the memory controller 3 and transferred, so that the data is acquired from the arbitration bus 5. Thus, the data transfer speed is improved.

  In this modified example, since the area is configured by a minimum unit, the number of records and the completion position need not be stored for each area, but instead of the number of records registered in the management table 161 in the embodiment. More than shown. If the number of areas of the shared memory 2 that are accessed in parallel during the period from reading to writing by the arbitration bus 5 increases, the storage capacity for storing the management table 161 needs to be increased.

  On the other hand, as shown in the embodiment, when a plurality of areas constituting the shared memory 2 are each composed of a plurality of minimum units, records registered in the management table 161 compared to the case shown in this modification example. Is suppressed.

2-2. Modification 2
A program for controlling the transfer device 1 is stored in a recording medium readable by a computer device such as a magnetic recording medium such as a magnetic tape or a magnetic disk, an optical recording medium such as an optical disk, a magneto-optical recording medium, or a semiconductor memory. It can be provided in the state. It is also possible to download these programs via the Internet or the like. Note that various devices may be applied as the arithmetic processing device of the transfer device 1, and for example, a dedicated processor or the like is used.

DESCRIPTION OF SYMBOLS 1 ... Transfer apparatus, 11 ... Reception part, 12 ... Registration part, 13 ... Acquisition part, 14 ... Transfer part, 15 ... Monitoring part, 16 ... Memory | storage part, 161 ... Management table, 2 ... Shared memory, 3 ... Memory controller, DESCRIPTION OF SYMBOLS 4 ... Arithmetic unit, 41 ... Cache memory, 5 ... Arbitration bus, 6 ... Internal bus, 7 ... Request device, 9 ... Transfer system, P1 ... 1st communication path, P2 ... 2nd communication path.

Claims (3)

A first communication path that communicates with a memory controller that reads from and writes to a specified area among a plurality of areas in the shared memory;
A second communication path that communicates with an arbitration device that arbitrates a request from one or more arithmetic devices, designates an area in the shared memory to the memory controller based on the request, and requests read / write;
Receiving means for receiving a request for data stored in the shared memory from a requesting device;
A registration unit that monitors a request output from the arbitration device to the memory controller and registers the area when the write process to the area specified by the request is not completed;
When the request of the requesting device is not for the area registered by the registration means, the data is acquired from the memory controller via the first communication path, and when the request is for the area, Obtaining means for obtaining the data from the arbitrating device via the second communication path;
Transfer means for transferring the acquired data to the requesting device;
I have a,
The registration means registers the area when the request is a request for a read process and the area specified in the request is not registered, and the request is a request for a write process. In some cases, the number of times of write processing to the area specified by the request is counted, and when the number of times reaches a threshold, the area is released as the write process is completed. apparatus. A transfer device according to 請 Motomeko 1,
A memory controller that communicates with the transfer device via the first communication path and reads / writes from / to a specified area in a shared memory;
A device that arbitrates requests between devices, communicates with the transfer device via the second communication path, and allocates an area in the shared memory to the memory controller based on a request from one or more arithmetic devices. An arbitration device that specifies and requests reading and writing;
A requesting device for sending a request for data stored in the shared memory to the transfer device;
Having a transfer system. Among the plurality in the region segmented in the shared memory, a first communication path that communicates with a memory controller for reading and writing to the designated area,
A second communication path that communicates with an arbitration device that arbitrates a request from one or more arithmetic devices, designates an area in the shared memory to the memory controller based on the request, and requests read / write;
A computer having
Receiving means for receiving a request for data stored in the shared memory from a requesting device;
A registration unit that monitors a request output from the arbitration device to the memory controller and registers the area when the write process to the area specified by the request is not completed;
When the request of the requesting device is not for the area registered by the registration means, the data is acquired from the memory controller via the first communication path, and when the request is for the area, Obtaining means for obtaining the data from the arbitrating device via the second communication path;
While functioning as transfer means for transferring the acquired data to the requesting device ,
The registration means registers the area when the request is a request for read processing and the area specified by the request is not registered, and the request is a request for write processing. In some cases, the computer counts the number of write operations to the area specified by the request, and when the number of times reaches a threshold, the computer is released so that the write process is completed and the area is released. A program to make it work .

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