JP6554025B2 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit provided with a protection circuit and a method of manufacturing the same.

  The following Patent Document 1 discloses a semiconductor protection device with improved resistance to electrostatic surges. The semiconductor protection device comprises a thyristor and a Zener diode. The thyristor is inserted between the power supply terminal and the ground terminal, and includes a vertical npn bipolar transistor and a horizontal pnp bipolar transistor. Zener diodes are used as trigger elements. The cathode of this Zener diode is connected to the power supply terminal, and the anode is connected to the base region of the vertical npn bipolar transistor.

  In the semiconductor protection device configured as described above, when an electrostatic surge is input to the power supply terminal, breakdown occurs in the zener diode as a trigger element. As a result, an electrostatic surge flows into the base region of the vertical npn bipolar transistor, and the thyristor is turned on. By the operation of the thyristor, the electrostatic surge inputted to the power supply terminal flows to the ground terminal side through the thyristor before being inputted to the internal circuit, so that the internal circuit is protected from the electrostatic surge.

  By the way, in the semiconductor protection device, when an electrostatic surge is input to the power supply terminal, a surge current flows concentrated on the Zener diode. For this reason, since electric field concentration occurs at the pn junction of the Zener diode, there is room for improvement from the viewpoint of preventing the breakdown of the pn junction.

Japanese Patent Laid-Open No. 5-315552

  SUMMARY OF THE INVENTION In view of the above fact, the present invention provides a semiconductor integrated circuit capable of improving the breakdown resistance to a surge of a Zener diode as a trigger element and a method of manufacturing the same.

A semiconductor integrated circuit according to a first embodiment of the present invention is connected between a first power supply terminal and a second power supply terminal to which a power supply voltage different from the power supply voltage applied to the first power supply terminal is applied. A protection circuit for absorbing a surge input to the power supply terminal to the second power supply terminal, a cathode connected to the first power supply terminal, an anode connected to the protection circuit, and a trigger for a surge input to the first power supply terminal And a trigger circuit including a Zener diode for operating the protection circuit and a Zener diode provided between the cathode and the anode, having the same conductivity type as the cathode or the anode, and lower than the impurity density of the cathode or the anode And an electric field relaxation region that has an impurity density and relaxes an electric field caused by a surge at a pn junction between the cathode and the anode. The anode is composed of a second semiconductor region of the second conductivity type opposite to the first conductivity type provided on the main surface of the first semiconductor region of the first conductivity type electrically separated from the other regions. There is. The cathode is provided on the main surface portion of the second semiconductor region, and is constituted by the third semiconductor region of the first conductivity type surrounded by the element isolation insulating region and formed shallower than the element isolation insulating region. There is. The electric field relaxation region is formed along the third semiconductor region on the main surface of the second semiconductor region, and the end of the electric field relaxation region is in contact with the side surface of the element isolation insulating region.

  The semiconductor integrated circuit according to the first embodiment includes a protection circuit and a trigger circuit. The protection circuit is inserted between the first power supply terminal and the second power supply terminal. In the protection circuit, a surge inputted to the first power supply terminal is absorbed by the second power supply terminal. The trigger circuit is configured to include a Zener diode as a trigger element, the cathode of the Zener diode is connected to the first power supply terminal, and the anode is connected to the protection circuit.

  Here, an electric field relaxation region is provided between the cathode and the anode of the Zener diode, and the electric field relaxation region has the same conductivity type as the cathode or the anode and has an impurity density lower than the impurity density of the cathode or the anode. . For this reason, since the extension of the depletion layer at the pn junction between the cathode and the anode becomes large, the electric field concentration due to the surge current at the pn junction is suppressed.

  In a semiconductor integrated circuit according to a third aspect of the present invention, in the semiconductor integrated circuit according to the first aspect or the second aspect, the protection circuit includes a first power electrode terminal and a first main electrode region and a first control electrode region. Is connected, and the second main electrode region is connected to the second main electrode region, the third main electrode region is connected to the second power source terminal, and the fourth main electrode region is connected to the first control electrode region. And a second bipolar transistor having a second main electrode region and a second control electrode region connected to each other, the anode being connected to the second control electrode region.

According to the semiconductor integrated circuit of the second embodiment, the protection circuit is constituted by a thyristor having a first bipolar transistor and a second bipolar transistor, and a Zener diode is connected to the gate of the thyristor. By using the protection circuit as a thyristor, a large surge can flow from the first power supply terminal to the second power supply terminal.

In a semiconductor integrated circuit according to a third aspect of the present invention, in the semiconductor integrated circuit according to any one of the first aspect to the second aspect, a fourth semiconductor region of the first conductivity type and a fourth semiconductor region An insulated gate field effect transistor configured to include a main electrode region having a first conductivity type fifth semiconductor region having an impurity density higher than the impurity density of the fourth semiconductor region. The cathode has the same impurity density as the fifth semiconductor region, and the electric field relaxation region has the same impurity density as the fourth semiconductor region.

According to the semiconductor integrated circuit of the third embodiment, the cathode and the electric field relaxation region have the same structure as the main electrode region of the insulated gate field effect transistor with the same impurity density. Therefore, the Zener diode and the electric field relaxation region can be easily configured.

The method of manufacturing a semiconductor integrated circuit according to the fourth embodiment of the present invention includes a step of forming the fourth semiconductor region and the electric field relaxation region of the semiconductor integrated circuit according to the third embodiment by the same step, a fifth semiconductor region, and a cathode. Forming the same by the same process.

According to the semiconductor integrated circuit manufacturing method of the fourth embodiment, the cathode is formed in the same step as the fifth semiconductor region of the insulated gate field effect transistor, and the field relaxation region is formed in the same step as the fourth semiconductor region. Ru. Therefore, the number of manufacturing steps of the semiconductor integrated circuit can be reduced as compared with the case of forming separately.

  According to the present invention, there is an excellent effect that a semiconductor integrated circuit capable of improving the breakdown resistance to a surge of a Zener diode as a trigger element and a method of manufacturing the same can be obtained.

1 is a main part circuit diagram showing a protection circuit, a trigger circuit, and an internal circuit of a semiconductor integrated circuit according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of main parts of a protection circuit, a trigger circuit, and an internal circuit of the semiconductor integrated circuit shown in FIG. It is an expanded sectional view of the trigger circuit (Zener diode) shown by FIG. FIG. 4A is a first process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to an embodiment, FIG. 3B is a second process cross-sectional view, and FIG. 3C is a third process cross-sectional view. It is an expanded sectional view which shows the electric field concentration location of the trigger circuit shown by FIG.2 and FIG.3. It is an expanded sectional view which shows the electric field concentration location of the trigger circuit which concerns on a comparative example.

  Hereinafter, a semiconductor integrated circuit and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS.

(Circuit configuration of semiconductor integrated circuit)
As shown in FIG. 1, the semiconductor integrated circuit 10 according to the present embodiment includes an internal circuit 14 at the center of the main surface of a semiconductor substrate (semiconductor chip) 12. A first power supply terminal 20, a second power supply terminal 22, and a signal terminal 24 are arranged around the internal circuit 14 and on the main surface of the semiconductor substrate 12. Here, only main external terminals are shown, but a number of external terminals other than those described above are arranged on the semiconductor substrate 12.

  The first power supply terminal 20 is connected to the internal circuit 14 through the power supply wiring 20L. A power supply voltage Vcc required for circuit operation is applied to the first power supply terminal 20 from the outside of the semiconductor integrated circuit 10. The semiconductor integrated circuit 10 according to the present embodiment is mounted on a vehicle such as an automobile, and a power supply voltage (for example, 12 VDC or 24 VDC) from a battery mounted on the vehicle passes through a power supply circuit or the like (not shown). 10 is supplied.

  The second power supply terminal 22 is connected to the internal circuit 14 through the power supply wiring 22L. A power supply voltage Vss required for circuit operation from the outside of the semiconductor integrated circuit 10 and different from the power supply voltage Vcc is applied to the second power supply terminal 22. The power supply voltage Vss is a power supply voltage lower than the power supply voltage Vcc, here 0V (ground voltage).

  The signal terminal 24 is used as an input signal terminal and is connected to the first stage circuit 26 of the internal circuit 14 through the signal wiring 24L. Although the circuit configuration is not limited, in the present embodiment, the first stage circuit 26 is a complementary metal oxide semiconductor (CMOS) circuit. Specifically, the first stage circuit 26 is configured of a p-channel insulated gate field effect transistor (IGFET) Qp and an n-channel IGFET Qn. The gate electrodes of both IGFET Qp and IGFET Qn are connected to the signal terminal 24. A signal IN is input to the signal terminal 24 from the outside of the semiconductor integrated circuit 10, and the operation of the first stage circuit 26 is controlled in accordance with the input signal IN. Note that the drain region as the main electrode region of both the IGFET Qp and the IGFET Qn is connected to a next stage circuit (not shown) via the output terminal 28. The signal OUT is output from the first stage circuit 26 to the next stage circuit. A power supply voltage Vcc is applied to the source region as the main electrode region of the IGFET Qp through the first power supply wiring 20L. The power supply voltage Vss is applied to the source region as the main electrode region of the IGFET Qn through the second power supply wiring 22L.

  In the semiconductor integrated circuit 10, a protection circuit 30 is inserted between the first power supply terminal 20 and the second power supply terminal 22. Further, a trigger circuit 32 is provided between the first power supply terminal 20 and the protection circuit 30.

  In detail, the protection circuit 30 includes a vertical pnp bipolar transistor B1 as a first bipolar transistor, a horizontal npn bipolar transistor B2 as a second bipolar transistor, a resistor R1, and a resistor R2. . In the first bipolar transistor B1, the emitter region as the first main electrode region is connected to the first power supply line 20L between the first power supply terminal 20 and the internal circuit 14, and the base region as the first control electrode region is a resistor. It is connected to the first power supply wiring 20L via R2. The collector region as the second main electrode region of the first bipolar transistor B1 is connected between the second power supply terminal 22 and the internal circuit 14 to the second power supply wiring 22L via the resistor R1. On the other hand, in the second bipolar transistor B2, the emitter region as the third main electrode region is connected to the second power supply wiring 22L between the second power supply terminal 22 and the internal circuit 14, and the collector region as the fourth main electrode region. Are connected to the base region of the first bipolar transistor B1 and to the first power supply line 20L via the resistor R2. The base region as the second control electrode region of the second bipolar transistor B2 is connected to the collector region of the first bipolar transistor B1. That is, the protection circuit 30 is configured by a thyristor having the base region of the second bipolar transistor B2 as a gate (input terminal). The protection circuit 30 is configured such that a surge input to the first power supply terminal 20 is absorbed by the second power supply terminal 22 before being input to the internal circuit 14.

  In the present embodiment, the trigger circuit 32 is configured by a Zener diode ZD. The cathode of the Zener diode ZD is connected to the first power supply terminal 20, and the anode is connected to the gate of the protection circuit 30 (the base region of the second bipolar transistor B2). When a surge exceeding breakdown voltage (breakdown voltage) is input to the first power supply terminal 20, the Zener diode ZD causes breakdown prior to the operation of the protection circuit 30, and the breakdown causes the protection circuit 30 to be broken. It is configured to operate.

(Longitudinal sectional structure of internal circuit of semiconductor integrated circuit)
As shown in FIG. 2, the semiconductor integrated circuit 10 according to the present embodiment includes a semiconductor substrate 12. Here, it is formed of a single crystal silicon substrate set to p-type as the second conductivity type. The power supply voltage Vss is applied to the semiconductor substrate 12. The power supply voltage Vss is supplied to the semiconductor substrate 12 via the p-type well region 40 provided in the main surface portion of the semiconductor substrate 12 and the p-type semiconductor region (substrate contact region) 56 provided in the main surface portion of the p-type well region 40. Applied to the

  The p-type well region 40 is set to an impurity density higher than the impurity density of the semiconductor substrate 12. The p-type semiconductor region 56 is set to an impurity density higher than that of the p-type well region 40. The p-type well region 40 is provided in the formation region of the IGFET Qn in the internal circuit 14 and is applied to the power supply voltage Vss through the p-type semiconductor region 56. Further, an n-type well region as a first semiconductor region electrically isolated from the semiconductor substrate 12 and the p-type well region 40 (electrically isolated from other regions) is provided on the main surface portion of the semiconductor substrate 12. 42 is provided. The n-type well region 42 is provided in the formation region of the IGFET Qp, the formation region of the protection circuit 30, and the formation region of the trigger circuit 32 of the internal circuit 14. An n-type semiconductor region 62 set to have an impurity density higher than the impurity density of n-type well region 42 is provided on the main surface of n-type well region 42, and n-type well region 42 supplies power supply voltage through n-type semiconductor region 62. Applied to Vcc.

  The IGFET Qp of the internal circuit 14 is provided on the main surface portion of the n-type well region 42 in a region surrounded by the element isolation insulating region 46 and the n-type channel stopper region 48 n. In the present embodiment, the element isolation insulating region 46 is formed by a field oxide film (silicon oxide film) formed by a substrate selective oxidation technique. The n-type channel stopper region 48 n is provided on the main surface portion of the n-type well region 42 along the lower surface of the element isolation insulating region 46. The n-type channel stopper region 48 n is set to have an impurity density higher than the impurity density of the n-type well region 42 and lower than the impurity density of the n-type semiconductor region 62.

The IGFET Qp includes a channel formation region, a gate insulating film 50, a gate electrode 52, and a pair of main electrode regions 54 used as a source region and a drain region. The channel formation region is formed using the n-type well region 42. In the present embodiment, main electrode region 54 includes p-type semiconductor region 58 of low impurity density and p-type semiconductor region 56 of high impurity density provided on the main surface of p-type semiconductor region 58. It is considered as a double diffusion structure. p-type semiconductor region 58 is shallower than the junction depth of the n-type well region 42 has a junction depth of 0.38Myuemu～0.52Myuemu, higher than the impurity density of the p-type well region 40, 10 ¹⁸ atoms / The impurity density is set to cm ³ to 10 ¹⁹ atoms / cm ³ . The p-type semiconductor region 56 has a depth of 0.32 μm to 0.36 μm which is shallower than the junction depth of the p-type semiconductor region 58 and is higher than the impurity density of the p-type semiconductor region 58 by 10 ²⁰ atoms / cm. The impurity density of ³ is set. The p-type semiconductor region 56 and the p-type semiconductor region 58 are formed by implanting p-type impurities into the main surface portion of the n-type well region 42 using the element isolation insulating region 46 and the gate electrode 52 as a mask using an ion implantation method. It is done. Therefore, the p-type semiconductor region 56 and the p-type semiconductor region 58 are formed by self-alignment with respect to the element isolation insulating region 46 and the gate electrode 52, respectively.

  The gate insulating film 50 is provided on the main surface of the n-type well region 42 and is formed of, for example, a silicon oxide film. The gate insulating film 50 may be formed of an oxynitride film or a composite film in which a silicon oxide film and a silicon nitride film are stacked. The gate electrode 52 is provided on the gate insulating film 50 and is formed of, for example, a silicon polycrystalline film. For example, phosphorus or boron is introduced into the silicon polycrystalline film, and the resistance value of the silicon polycrystalline film is adjusted and set low. The gate electrode 52 may be formed of a composite film in which a refractory metal film or a refractory metal silicide film is stacked on a silicon polycrystalline film.

  The IGFET Qn is provided on the main surface of the p-type well region 40 in a region surrounded by the element isolation insulating region 46 and the p-type channel stopper region 48p. The p-type channel stopper region 48 p is set to have an impurity density higher than the impurity density of the p-type well region 40 and lower than the impurity density of the p-type semiconductor region 56.

  The IGFET Qn includes a channel forming region, a gate insulating film 50, a gate electrode 52, and a pair of main electrode regions 60 used as a source region and a drain region. The channel formation region is formed using the p-type well region 40. The main electrode region 60 has a double diffusion structure like the main electrode region 54, and an n-type semiconductor region 64 with low impurity density and an n-type high impurity density provided on the main surface of the n-type semiconductor region 64. The semiconductor region 62 is included. The n-type semiconductor region 64 has a junction depth equivalent to the junction depth of the p-type semiconductor region 58, and is set to an impurity density equivalent to the impurity density of the p-type semiconductor region 58. The n-type semiconductor region 62 has a depth equivalent to the depth of the p-type semiconductor region 56, and is set to an impurity density equivalent to the impurity density of the p-type semiconductor region 56. Similar to the p-type semiconductor region 56 and the p-type semiconductor region 58, the n-type semiconductor region 62 and the n-type semiconductor region 64 are formed by self-alignment with respect to the element isolation insulating region 46 and the gate electrode 52, respectively. The gate insulating film 50 and the gate electrode 52 of the IGFET Qn have the same structure as the gate insulating film 50 and the gate electrode 52 of the IGFET Qp.

(Longitudinal structure of protection circuit)
As shown in FIG. 2, the first bipolar transistor B1 of the protection circuit 30 includes a p-type semiconductor region 56 as an emitter region, an n-type well region 42 as a base region, and a p-type semiconductor substrate 12 as a collector region. And is included. The first bipolar transistor B1 is configured as a vertical pnp bipolar transistor that allows current to flow between the p-type semiconductor region 56 and the semiconductor substrate 12 in the thickness direction of the semiconductor substrate 12. On the other hand, the second bipolar transistor B2 includes an n-type semiconductor region 62 as an emitter region, a p-type well region 44 as a base region, and an n-type well region 42 as a collector region. p-type well region 44 is provided on the main surface of the n-type well region 42 is higher than the impurity density of the p-type well region 40, and lower than the impurity density of the p-type semiconductor region 58 of IGFETQp, 10 ¹⁷ atoms The impurity density is set to / cm ³ to 10 ¹⁸ atoms / cm ³ . The n-type semiconductor region 62 is provided on the main surface of the p-type well region 44. The second bipolar transistor B2 is configured as a lateral npn bipolar transistor that allows current to flow between the n-type semiconductor region 62 and the n-type well region 42 in the plane direction of the semiconductor substrate 12.

  The resistor R1 is constituted by a semiconductor substrate 12 as a collector region of the first bipolar transistor B1. The resistor R2 is constituted by an n-type well region 42 as a base region of the first bipolar transistor B1.

(Longitudinal structure of trigger circuit)
As shown in FIGS. 2 and 3, the Zener diode ZD of the trigger circuit 32 includes a p-type well region 44D as an anode and a second semiconductor region, and an n-type semiconductor region 62D as a cathode and a third semiconductor region. It is comprised including. More specifically, the p-type well region 44D is configured by the same structure having the same impurity density and the same junction depth as the p-type well region 44, and further integrally formed with the p-type well region 44. Yes (electrically connected). The n-type semiconductor region 62D is provided in the main surface portion of the p-type well region 44D in a region surrounded by the element isolation insulating region 46 and the p-type channel stopper region 48p. The n-type semiconductor region 62D has the same structure with the same impurity density and the same depth as the high impurity density n-type semiconductor region 62 of the main electrode region 60 of the IGFET Qn.

  The impurity density between the n-type semiconductor region 62D and the p-type well region 44D of the Zener diode ZD is the same as that of the n-type semiconductor region 62D and lower than the impurity density of the n-type semiconductor region 62D. An electric field relaxation region 64D is provided. As shown in FIG. 3, the electric field relaxation region 64D is provided on the main surface portion of the p-type well region 44D along the bottom surface of the n-type semiconductor region 62D on the p-type well region 44D side. The n-type well region 44D and the electric field relaxation region 64D are formed by implanting an n-type impurity by ion implantation using the element isolation / insulation region 46 as a mask. It is formed by self-alignment with the bird's beak 46A. Further, the end portion of the electric field relaxation region 64 </ b> D overlaps with the bird's beak 46 </ b> A and wraps around the end portion of the element isolation insulating region 46. In the present embodiment, the electric field relaxation region 64D has the same structure with the same impurity density and the same depth with respect to the low impurity density n-type semiconductor region 64 of the main electrode region 60 of the IGFET Qn. By providing the electric field relaxation region 64D, the electric field relaxation region 64D functions as an effective cathode. The Zener diode ZD is formed of a low impurity density n-type semiconductor region and a low impurity density p-type well region from a pn junction between the high impurity density n-type semiconductor region 62D and the low impurity density p-type well region 44D. It becomes a pn junction with 44D.

(Method of manufacturing semiconductor integrated circuit)
The method of manufacturing the semiconductor integrated circuit 10 according to the present embodiment is as follows. In the main surface portion of the p-type semiconductor substrate 12, a p-type well region 40 and an n-type well region 42 are formed (see FIG. 2). The p-type well region 40 is formed in the main surface portion of the semiconductor substrate 12 in the formation region of the IGFET Qn in the internal circuit 14. The n-type well region 42 is formed in the main surface portion of the semiconductor substrate 12 in the formation region of the IGFET Qp of the internal circuit 14, the formation region of the protection circuit 30, and the formation region of the trigger circuit 32.

  As shown in FIG. 4A, the p-type well region 44 is formed in the formation region of the protection circuit 30 in the main surface portion of the n-type well region 42. The p-type well region 44D is formed in the formation region of the trigger circuit 32 arranged in the formation region of the protection circuit 30 by the same step as the step of forming the p-type well region 44. Each of the p-type well region 44 and the p-type well region 44D is formed by activating a p-type impurity introduced into the main surface portion of the n-type well region 42. An ion implantation method is used to introduce the p-type impurity, and the p-type impurity is selectively introduced using a mask formed by a photolithography technique. It should be noted that a solid phase diffusion method may be used for introducing the impurity instead of the ion implantation method.

  Next, an element isolation insulating region 46, a p-type channel stopper region 48p, and an n-type channel stopper region 48n are formed (see FIG. 2). The element isolation insulating region 46 is formed on each main surface of the p-type well region 40, the n-type well region 42, the p-type well region 44, and the p-type well region 44D by the substrate selective oxidation technique as described above. The p-type channel stopper region 48p is formed under the element isolation insulating region 46 on the main surface portion of the p-type well region 40, the main surface portion of the p-type well region 44, and the main surface portion of the p-type well region 44D. The n-type channel stopper region 48 n is formed on the main surface portion of the n-type well region 42 under the element isolation insulating region 46.

  Next, in the formation region of the IGFET Qp, the gate insulating film 50 and the gate electrode 52 are sequentially formed on the main surface of the n-type well region 42 (see FIG. 2). By the same step as this step, gate insulating film 50 and gate electrode 52 are sequentially formed on the main surface of p type well region 40 in the formation region of IGFET Qn.

  Next, in the formation region of the IGFET Qp, a low impurity density p-type impurity 58p for forming the p-type semiconductor region 58 is introduced into the main surface portion of the n-type well region 42 (see FIG. 4B). Subsequently, in the formation region of the IGFET Qp, the p-type impurity 56p having a high impurity density for forming the p-type semiconductor region 56 in the main surface portion of the n-type well region 42 is introduced. Both the p-type impurity 58p and the p-type impurity 56p are introduced into the gate electrode 52 and the element isolation insulating region 46 by self-alignment by an ion implantation method. Here, the p-type impurity 56p is introduced into the main surface of the p-type well region 40, the main surface of the n-type well region 42, and the main surface of the p-type well region 44 in the same process.

  As shown in FIG. 4B, in the formation region of the IGFET Qn, the low impurity density n-type impurity 64n for forming the n-type semiconductor region 64 is introduced into the main surface portion of the p-type well region 40. The n-type impurity 64n is introduced in a self-aligned manner with respect to the gate electrode 52 and the element isolation insulating region 46 by ion implantation. Here, the n-type impurity 64n is introduced also into the formation region of the Zener diode ZD by the same process, and is formed as an electric field relaxation region 64D after activation. In the formation region of the Zener diode ZD, the n-type impurity 64n is introduced to the main surface of the p-type well region 44D by self-alignment with the bird's beak 46A at the end of the element isolation insulating region 46.

  As shown in FIG. 4C, in the formation region of the IGFET Qn, a high impurity density n-type impurity 62n for forming the n-type semiconductor region 62 is introduced into the main surface portion of the p-type well region 40. The n-type impurity 62n is introduced by self-alignment with respect to the gate electrode 52 and the element isolation insulating region 46 by ion implantation in the same manner as the n-type impurity 64n. Here, the n-type impurity 62n is also introduced into the formation region of the Zener diode ZD by the same process. In the formation region of the Zener diode ZD, the n-type impurity 62n is introduced in a region slightly shallower than the n-type impurity 64n, and the p-type well region is self-aligned to the bird's beak 46A at the end of the element isolation insulating region 46. It is introduced into the main surface of 44D. Note that the n-type impurity 64n and the n-type impurity 62n are introduced using a mask (not shown) formed by a photolithography technique. The n-type impurity 62n is also introduced into the main surface portion of the n-type well region 42 and the main surface portion of the p-type well region 44 by the same process.

  Next, annealing (activation treatment) is performed, and the p-type impurity 56p, the p-type impurity 58p, the n-type impurity 62n and the n-type impurity 64n are activated by thermal diffusion. In the formation region of the internal circuit 14, the p-type semiconductor region 56 is formed by the p-type impurity 56p, and the p-type semiconductor region 58 is formed by the p-type impurity 58p, thereby completing the IGFET Qp having the main electrode region 54. Further, the n-type semiconductor region 62 is formed by the n-type impurity 62n, and the n-type semiconductor region 64 is formed by the n-type impurity 64n, whereby the IGFET Qn having the main electrode region 60 is completed. On the other hand, when the p-type semiconductor region 56 is formed in the formation region of the protection circuit 30, the first bipolar transistor B1 including the p-type semiconductor region 56, the n-type well region 42, and the semiconductor substrate 12 is completed. . Further, when the n-type semiconductor region 62 is formed, the second bipolar transistor B2 configured to include the n-type semiconductor region 62, the p-type well region 44, and the n-type well region 42 is completed.

  In the region where the trigger circuit 32 is formed, a Zener diode ZD having a p-type well region 44D as an anode and an n-type semiconductor region 62D as a cathode is completed. Then, by introducing and activating the n-type impurity 64D, the electric field relaxation region 64D is formed in the Zener diode ZD.

(Operation and effect of the present embodiment)
The semiconductor integrated circuit 10 according to the present embodiment includes a protection circuit 30 and a trigger circuit 32 as shown in FIG. The protection circuit 30 is inserted between the first power supply terminal 20 and the second power supply terminal 22. In the protection circuit 30, the surge inputted to the first power supply terminal 20 is absorbed by the second power supply terminal 22. The trigger circuit 32 includes a Zener diode ZD as a trigger element. The cathode of the Zener diode ZD is connected to the first power supply terminal 20, and the anode is connected to the protection circuit 30.

  Here, as shown in FIGS. 2 and 3, an electric field relaxation region 64D is provided between the cathode and the anode of the Zener diode ZD, the electric field relaxation region 64D has the same conductivity type as the cathode, and the cathode Have an impurity density lower than that of In the Zener diode ZD, when a surge exceeding the breakdown voltage is input from the first power supply terminal 20 to the cathode (n-type semiconductor region 62D), breakdown occurs, and the surge current I is an anode as shown in FIG. It flows to (p-type well region 44D). The pn junction of the Zener diode ZD is formed by a low impurity density electric field relaxation region 64D and a low impurity density anode. For this reason, the depletion layer extends from the pn junction to the electric field relaxation region 64D side, and the depletion layer extends from the pn junction to the p-type well region 44D side. The spread of the depletion layer suppresses electric field concentration due to the surge current I at the pn junction. As shown in FIGS. 2 and 5, the electric field concentration EC due to the surge current I occurs in the central portion of the Zener diode ZD and slightly on the p-type semiconductor region 56 side. This is because the surge current I flows to the second power supply terminal 22 through the p-type semiconductor region 56.

  On the other hand, as shown in FIG. 6, the Zener diode ZD according to the comparative example does not include the electric field relaxation region 64D. Therefore, the spread of the depletion layer at the pn junction between the cathode (n-type semiconductor region 62D) and the anode (p-type well region 44D) is small, and electric field concentration EC due to the surge current I is easily generated.

  As described above, according to the semiconductor integrated circuit 10 according to the present embodiment, the breakdown resistance to the surge current I of the Zener diode ZD as the trigger element can be improved.

  Further, in the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 3, the anode of the Zener diode ZD is constituted by the p-type well region 44D, and the cathode is surrounded by the element isolation insulating region 46. The n-type semiconductor region 62D. Here, the electric field relaxation region 64D is configured on the main surface portion of the p-type well region 44D along the bottom surface of the n-type semiconductor region 62D, and is configured to wrap around the bird's beak 46A at the end of the element isolation insulating region 46. The Therefore, as shown in FIG. 5, in the pn junction between the cathode and the anode, the extension of the depletion layer at the end of the element isolation / insulation region 46 where the surge current I tends to concentrate becomes large. Electric field concentration EC due to the surge current I at the end of the region 46 is suppressed.

  Further, in the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIGS. 1 and 2, the protection circuit 30 is configured by a thyristor having a first bipolar transistor B1 and a second bipolar transistor B2. The Zener diode ZD of the trigger circuit 32 is connected to the gate of the thyristor. By using the protection circuit 30 as a thyristor, a large surge current I can flow from the first power supply terminal 20 to the second power supply terminal 22.

  Further, in the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 2, the n-type semiconductor region 62D of the cathode of the Zener diode ZD has the same impurity density as the n-type semiconductor region 62 of the main electrode region 60 of IGFET Qn. Of the same structure. In addition, the electric field relaxation region (n-type semiconductor region) 64D has the same structure with the same impurity density as the n-type semiconductor region 64 of the main electrode region 60. For this reason, the Zener diode ZD and the electric field relaxation region 64D can be easily configured.

  Furthermore, in the method for manufacturing the semiconductor integrated circuit 10 according to the present embodiment, the cathode (n-type semiconductor region 62D) of the Zener diode ZD is formed in the same process as the n-type semiconductor region 62 of the IGFET Qn. In addition, an electric field relaxation region (n-type semiconductor region) 64D is formed in the same process as the n-type semiconductor region 64 of the IGFET Qn. For this reason, compared with the case where it forms separately, the number of manufacturing processes of the semiconductor integrated circuit 10 can be reduced.

[Supplementary explanation of the above embodiment]
The present invention is not limited to the above-described embodiment, and can be modified as follows, for example, without departing from the gist thereof. For example, the present invention may include a protection circuit including a vertical npn bipolar transistor and a horizontal pnp bipolar transistor. In addition to the thyristor, the protection circuit may be configured to include a clamp element.
Furthermore, in the trigger circuit according to the present invention, a resistor may be provided between the first power supply terminal and the cathode of the Zener diode. In the present invention, the electric field relaxation region may be formed of a p-type semiconductor region having the same conductivity type as the anode and a lower impurity density than the anode. Furthermore, the present invention adopts a lightly doped drain (LDD) structure in which the impurity density on the channel forming area side of the main electrode area is set low in the IGFET of the internal circuit, and is the same as the semiconductor area with low impurity density in this main electrode area. The electric field relaxation region may be formed by the structure or the same process. In the present invention, the electric field relaxation region may be formed by a single process regardless of the main electrode region of the IGFET.

DESCRIPTION OF SYMBOLS 10 semiconductor integrated circuit 12 semiconductor substrate 14 internal circuit 20 1st power supply terminal 22 2nd power supply terminal 30 protection circuit 32 trigger circuit 40, 44 p type well area 44D p type well area (anode)
42 n-type well region 46 element isolation insulating region 54, 60 main electrode region 56, 58 p-type semiconductor region 62, 64 n-type semiconductor region 62 D n-type semiconductor region (cathode)
64D electric field relaxation region Qn, Qp IGFET
B1, B2 Bipolar transistor R1, R2 resistance

Claims (4)

The second power supply is connected between a first power supply terminal and a second power supply terminal to which a power supply voltage different from the power supply voltage applied to the first power supply terminal is applied, and which is input to the first power supply terminal. A protection circuit to be absorbed by the terminal,
A trigger circuit including a Zener diode having a cathode connected to the first power supply terminal, an anode connected to the protection circuit, and activating the protection circuit using a surge input to the first power supply terminal as a trigger;
The Zener diode is provided between the cathode and the anode, has the same conductivity type as the cathode or the anode, and has an impurity density lower than the impurity density of the cathode or the anode. An electric field relaxation region for relieving an electric field due to a surge at a pn junction between the cathode and the anode;
Bei to give a,
The anode is composed of a second semiconductor region of the second conductivity type opposite to the first conductivity type provided on the main surface of the first semiconductor region of the first conductivity type electrically separated from the other regions. ,
The cathode is provided on a main surface portion of the second semiconductor region, and a periphery thereof is surrounded by an element isolation insulating region, and a third semiconductor region of the first conductivity type formed shallower than the element isolation insulating region Configured by
The electric field relaxation region is formed in a main surface portion of the second semiconductor region along the third semiconductor region, and an end portion of the electric field relaxation region is in contact with a side surface of the element isolation insulating region . The protection circuit is
A first bipolar transistor having a first main electrode region and a first control electrode region connected to the first power supply terminal and a second main electrode region connected to the second power supply terminal;
A second bipolar device in which a third main electrode region is connected to the second power supply terminal, a fourth main electrode region is connected to the first control electrode region, and a second control electrode region is connected to the second main electrode region. Comprising a transistor,
The semiconductor integrated circuit according to claim 1, wherein the anode is connected to the second control electrode region. A fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the first conductivity type provided in a main surface portion of the fourth semiconductor region and having an impurity density higher than the impurity density of the fourth semiconductor region; An insulated gate field effect transistor configured to include a main electrode region having the
The cathode has the same impurity density as the impurity density of the fifth semiconductor region, and
The semiconductor integrated circuit according to claim 1 , wherein the electric field relaxation region has the same impurity density as that of the fourth semiconductor region. Forming the fourth semiconductor region and the electric field relaxation region in the same step;
Forming the fifth semiconductor region and the cathode in the same step;
A method of manufacturing a semiconductor integrated circuit according to claim 3 , comprising:

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