JP6543438B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device provided with an overheat protection circuit.

  FIG. 10 is a plan view showing a first conventional example of a semiconductor device. The semiconductor device 300 according to the first conventional example generates an LDO [a desired output voltage Vo from an input voltage Vi by controlling the conductivity of the power transistor 310 connected between the input terminal PIN11 and the output terminal PIN12]. low drop-out] regulator IC. The input terminal PIN11 and the pad 311 and the output terminal PIN12 and the pad 312 are bonded to each other through the wires W11 and W12, respectively.

  FIG. 11 is a plan view showing a second conventional example of the semiconductor device. The semiconductor device 400 according to the second conventional example has a rectangular wave shape from the switch terminal PIN23 by turning on / off the upper power transistor 410H and the lower power transistor 410L connected in series between the input terminal PIN21 and the ground terminal PIN22. It is a switching regulator IC that outputs a switch voltage Vsw. Note that bonding is performed between the input terminal PIN21 and the pad 411, between the ground terminal PIN22 and the pad 412, and between the switch terminal PIN23 and the pad 413 via wires W21 to W23, respectively.

  The above-described power transistor 310, and the upper power transistor 410H and the lower power transistor 410L become heat sources during operation of the semiconductor devices 300 and 400, respectively. Therefore, overheat protection circuits 320 and 420 are incorporated in the semiconductor devices 300 and 400 for performing a protection operation when the junction temperature exceeds the threshold temperature.

  In addition, patent document 1 can be mentioned as an example of the prior art relevant to the above.

JP 2005-278344 A

  In the conventional semiconductor device, the sensitivity and accuracy of the overheat protection circuit are enhanced by reducing the distance between the heat source and the overheat protection circuit.

  However, as shown in FIG. 10, when the element size of the power transistor 310 serving as a heat source is large, the temperature from the portion HS which is the highest temperature inside the power transistor 310 to the edge of the power transistor 310 Unavoidable temperature gradients occur between them. Therefore, there is a case where heat detection can not be accurately performed even if the distance between the power transistor 310 and the overheat protection circuit 320 is reduced.

  Further, as shown in FIG. 11, when the upper power transistor 410H and the lower power transistor 410L as heat sources are turned on / off, the upper power transistor is prevented in order to prevent malfunction of the overheat protection circuit 420 due to switching noise. It is necessary to increase the distance between the 410H and the lower power transistor 410L and the overheat protection circuit 420, or to place a buffer band 430 between them. Therefore, the sensitivity and accuracy of the overheat protection circuit 420 have been reduced.

  In the prior art of Patent Document 1, the temperature transfer delay or temperature between discrete components (power element (heat source portion) to temperature sensor (heat detection portion)) mounted on a circuit board (printed wiring board) It is intended to reduce the detection value offset and not to improve the sensitivity and accuracy of the overheat protection circuit integrated in the semiconductor device.

  SUMMARY OF THE INVENTION In view of the above problems found by the inventors of the present invention, it is an object of the present invention to provide a semiconductor device with high safety by improving the sensitivity and accuracy of the overheat protection circuit integrated in the semiconductor device.

  In order to achieve the above object, a semiconductor device according to the present invention comprises a heat generation source and a heat detection element formed on a semiconductor substrate, and a heat conductivity and a heat detection element having thermal conductivity higher than that of the semiconductor substrate. And a heat conducting member formed across the both, and integrated (first configuration).

  In the semiconductor device having the first configuration, the heat conduction member is formed by drawing a part of a wiring pattern electrically connected to the heat source to the heat detection element (second Configuration).

  In the semiconductor device having the second configuration, the wiring pattern to be diverted as the heat conducting member is a wiring pattern with the least noise superposition among the plurality of wiring patterns electrically connected to the heat source. It is preferable to use a certain configuration (third configuration).

  Further, in the semiconductor device having the second or third configuration, the wiring pattern used as the heat conduction member may have a configuration (fourth configuration) which is not electrically connected to the heat detection element.

  Further, in the semiconductor device having the first configuration, the heat conduction member is formed using a dummy wiring pattern which is not electrically connected to any of the heat generation source and the heat detection element (fifth embodiment). Configuration).

  Further, in the semiconductor device having the fifth configuration, the heat conduction member may be configured to be connected to a ground end (sixth configuration).

  In the semiconductor device having any one of the first to sixth configurations, the heat conduction member is formed using at least one wiring layer among the plurality of wiring layers formed on the semiconductor substrate. (7th configuration).

  In the semiconductor device having any one of the first to seventh configurations, the heat conducting member is formed by using a wiring layer having the highest thermal conductivity among a plurality of wiring layers formed on the semiconductor substrate. It is good to set it as the structure (8th structure) currently formed.

  In the semiconductor device having any one of the first to eighth configurations, the heat source may be a power transistor (ninth configuration).

  Further, an electronic device according to the present invention is configured to have a semiconductor device having any of the first to ninth configurations (10th configuration).

  According to the present invention, it is possible to improve the sensitivity and accuracy of the overheat protection circuit integrated in the semiconductor device, and in turn, it is possible to improve the safety of the semiconductor device.

A schematic view showing a first embodiment of a semiconductor device A circuit diagram showing a configuration example of the overheat protection circuit 30 Longitudinal sectional view showing a first example (two-layer type) of a wiring pattern Plan view showing a second example (three-layer type) of the wiring pattern A longitudinal sectional view showing a second example (three-layer type) of the wiring pattern A plan view showing a modification of the first embodiment A schematic view showing a second embodiment of the semiconductor device External view of personal computer TV external view A plan view showing a first conventional example of a semiconductor device A plan view showing a second conventional example of a semiconductor device

First Embodiment
FIG. 1 is a schematic view showing a first embodiment (application to an LDO regulator IC) of a semiconductor device. In the drawing, (A) column is a plan view (top view) of the semiconductor device 1 and (B) column is a block diagram of the semiconductor device 1.

  The semiconductor device 1 according to the first embodiment includes a P-channel MOS (metal oxide semiconductor) field effect transistor 10, an operational amplifier 20, an overheat protection circuit 30, resistors 40a and 40b, wiring patterns 50 and 60, and a pad 70. And 80.

  The transistor 10 is a power transistor integrated on a semiconductor substrate, and is connected between the pad 70 (input end of the input voltage Vi) and the pad 80 (output end of the output voltage Vo). Specifically describing the connection relationship, the source of the transistor 10 is connected to the pad 70 via the wiring pattern 50. The drain of the transistor 10 is connected to the pad 80 via the wiring pattern 60. The gate of the transistor 10 is connected to the output end of the operational amplifier 20.

  In the operational amplifier 20, the feedback voltage Vfb (a divided voltage of the output voltage Vo) applied to the non-inverting input terminal (+) matches the reference voltage Vref applied to the inverting input terminal (−) (imaginary short) To generate the gate voltage of the transistor 10. By performing such output feedback control, a desired output voltage Vo can be generated from the input voltage Vi.

  The overheat protection circuit 30 includes the heat detection element 31 integrated on the semiconductor substrate, and monitors whether the junction temperature Tj exceeds a predetermined threshold temperature Tjmax (for example, 150 ° C. or 175 ° C.) to thereby prevent the overheat protection signal. Generate S1. When the overheat protection signal S1 becomes a logic level (for example, low level) at the time of overheat detection, the operational amplifier 20 raises the gate voltage of the transistor 10 regardless of the feedback voltage Vfb to forcibly turn off the transistor 10. Such overheat protection operation can enhance the safety of the semiconductor device 1.

  The resistors 40a and 40b are connected between the pad 80 (the output end of the output voltage Vo) and the ground end, and form a resistive voltage dividing circuit that outputs the feedback voltage Vfb from the connection node of each other.

  The wiring pattern 50 is a conductive member (input line) that electrically connects the source of the transistor 10 and the pad 70. The wiring pattern 60 is a conductive member (output line) that electrically connects the drain of the transistor 10 and the pad 80. Each of the wiring patterns 50 and 60 is formed by patterning a metal (aluminum, copper, silver, or gold) having high conductivity.

  The pad 70 is a metal electrode corresponding to the input end of the input voltage Vi, and is wire-bonded to an input terminal (not shown). The pad 80 is a metal electrode corresponding to the output end of the output voltage Vo, and is wire-bonded to an output terminal (not shown).

  Here, in the semiconductor device 1 of the first embodiment, sensitivity and accuracy of the overheat protection circuit 30 are improved by devising not the circuit configuration of the overheat protection circuit 30 but the wiring layout pattern on the semiconductor substrate. . More specifically, in the semiconductor device 1 according to the first embodiment, heat detection is performed by routing a part of the wiring pattern 60 electrically connected to the drain of the transistor 10 serving as a heat source to the heat detection element 31. A heat conducting member 60 </ b> X overlapping the element 31 is formed. The heat conducting member 60 </ b> X does not necessarily have to be electrically connected to the heat detecting element 31.

  Heretofore, no particular attention has been paid to heat conduction through wiring patterns, and heat is generated mainly through a semiconductor substrate made of silicon (heat conductivity λ = 115 [W / m · K] @ 100 ° C.) It reached the heat detection unit from the source.

  On the other hand, in the semiconductor device 1 of the first embodiment, the wiring pattern 60 formed of aluminum (λ = 232 [W / m · K] @ 100 ° C.) having a thermal conductivity higher than that of silicon and the heat conducting member 60X are transmitted. Since the heat reaches the heat detection element 31 from the transistor 10, the heat is transferred faster than in the prior art. In addition, since the thermal conductivity of metals including aluminum generally has positive temperature dependency, the thermal conductivity of aluminum is the heat of silicon near the threshold temperature Tjmax (150 ° C. or 175 ° C.) of the overheat protection circuit 30. 2 to 4 times the conductivity. Therefore, in the overheat protection circuit 30, the heat generation of the transistor 10 can be detected accurately and quickly, so that the sensitivity and accuracy of the overheat protection circuit 30 can be improved.

  Further, in the semiconductor device 1 of the first embodiment, the heat conduction member 60X is formed by diverting a part of the wiring pattern 60 electrically connected to the transistor 10. With such a configuration, the heat conduction member 60X can be formed without substantially changing the existing design of the wiring patterns 50 and 60.

  In the present specification, for convenience of explanation, a part of the wiring pattern 60 (an extended portion drawn around the heat detection element 31) is referred to as a heat conducting member 60X. The conductive member 60X is one member integrally molded to the last, and the heat generated in the transistor 10 is transmitted to both the wiring pattern 60 and the heat conductive member 60X to reach the heat detection element 31. Therefore, it goes without saying that not only the heat conducting member 60X but also the wiring pattern 60 itself molded integrally with this functions as the heat conducting member.

  Further, in the semiconductor device 1 of the first embodiment, the heat conduction member 60X is formed by partially diverting the wiring pattern 60 having less noise superposition among the wiring patterns 50 and 60 electrically connected to the transistor 10 It is done. With such a configuration, it is possible to reduce the malfunction of the overheat protection circuit 30 due to noise. As long as the noise superposition amount of the wiring patterns 50 and 60 does not change so much, either one may be diverted to form the heat conduction member.

  Further, the material of the heat conducting member 60X (and thus the wiring pattern 60) is not limited to the aluminum (λ = 232 [W / m · K] @ 100 ° C.] exemplified above, and the heat conductivity is further increased. Other metals (eg, copper (λ = 395 [W / m · K] @ 100 ° C.), silver (λ = 422 [W / m · K] @ 100 ° C.), or gold (λ = 313 [W / M · K] @ 100 ° C.) etc. may be used.

<Overheat protection circuit>
FIG. 2 is a circuit diagram showing one configuration example of the overheat protection circuit 30. As shown in FIG. The overheat protection circuit 30 of this configuration example is an npn-type bipolar transistor 31 (which corresponds to the heat detection element 31 described above, and therefore will be described with the same reference numeral hereinafter), a band gap power supply unit 32, and resistors 33 to 33. 35 and inverters 36 and 37.

  The band gap power supply unit 32 generates a constant band gap voltage VBG which does not depend on the power supply voltage Vcc or the ambient temperature. The resistors 33 and 34 are connected in series between the application end of the band gap voltage VBG and the ground end, and form a resistive voltage dividing circuit that outputs a divided voltage Vd from the connection node of each other.

  The base of the transistor 31 is connected to the application end of the divided voltage Vd. The emitter of the transistor 31 is connected to the ground terminal. The collector of the transistor 31 is connected to the first end of the resistor 35 and the input end of the inverter 36. The second end of the resistor 35 is connected to the application end of the power supply voltage Vcc. The output end of the inverter 36 is connected to the input end of the inverter 37. The output terminal of the inverter 37 corresponds to the output terminal of the overheat protection signal S1.

  In the overheat protection circuit 30 of this configuration example, the logic level of the overheat protection signal S1 is utilized by utilizing that the base-emitter voltage Vbe of the transistor 31 (corresponding to the forward drop voltage Vf of the diode) has negative temperature characteristics. Is switched. A more specific operation will be described below.

  As the junction temperature Tj of the semiconductor device 1 is higher, the base-emitter voltage Vbe of the transistor 10 is lower. Therefore, as the junction temperature Tj of the semiconductor device 1 is higher, the collector current flowing to the transistor 10 is increased, the voltage drop amount at the resistor 35 is increased, and the collector voltage of the transistor 10 (voltage at the input end of the inverter 36) is decreased. Do.

  Here, the overheat protection circuit 30 is designed such that the collector voltage of the transistor 31 exceeds the threshold voltage of the inverter 36 when the junction temperature Tj of the semiconductor device 1 is lower than the threshold temperature Tjmax. Therefore, when the overheat is not detected (Tj <Tjmax), the overheat protection signal S1 becomes high level.

  On the other hand, when junction temperature Tj of semiconductor device 1 exceeds threshold temperature Tjmax and the collector voltage of transistor 31 falls below the threshold voltage of inverter 36, the output logic levels of inverters 36 and 37 are switched. Therefore, when the overheat is detected (Tj ハ イ Tjmax), the overheat protection signal S1 is switched from the high level to the low level.

  As described above, when the transistor 31 is used as the heat detection element, the above-described heat conduction member 60X may be formed so as to overlap with the transistor 31.

<Vertical structure>
FIG. 3 is a schematic view showing a first example (two-layer type) of the wiring pattern. In the drawing, (A) column is a plan view (top view) of the semiconductor device 1, and (B) column is an A1-A2 longitudinal sectional view of the semiconductor device 1. In the first example shown in the figure, two wiring layers L1 and L2 are stacked on a semiconductor substrate. The wiring layer L1 of the first layer (lower layer) includes a wiring pattern 101 electrically connected to the transistor 10 (heat generation source) and a wiring pattern 102 electrically connected to the transistor 31 (heat detection element). The second (upper) wiring layer L2 includes a wiring pattern 103 formed across both the transistor 10 (heat generation source) and the transistor 31 (heat detection element). The wiring pattern 101 and the wiring pattern 103 are electrically connected via the vias 104. The wiring pattern 102 and the wiring pattern 103 are not electrically connected.

  Focusing on the wiring pattern 103 of the wiring layer L2, the overlapping portion with the transistor 10 corresponds to the above wiring pattern 60, and the extended portion drawn around from the edge of the transistor 10 toward the transistor 31 is first Corresponds to the heat conduction member 60X. As described above, the heat conducting member 60X may be formed using at least one of the wiring layers L1 and L2 stacked on the semiconductor substrate.

  FIG. 4 is a plan view showing a second example (three-layer type) of the wiring pattern. In the column (A) of this figure, the transistors 10 and 31 formed on the semiconductor substrate are depicted. The transistor 10 is formed by connecting a plurality of unit transistors formed by the source region 10S, the drain region 10D, and the gate oxide film 10G in parallel.

  In the column (B) of the figure, the first (lower) wiring layer L1 formed on the top of the transistors 10 and 31 is depicted. A source wiring pattern L1S in contact with the source region 10S is formed on the source region 10S. A drain wiring pattern L1D in contact with the drain region 10D is formed above the drain region 10D. Further, in the peripheral portion of the transistor 10, a gate wiring pattern L1G in contact with the gate insulating film 10G is annularly formed. Further, a collector wiring pattern L1C, an emitter wiring pattern L1E, and a base wiring pattern L1B are respectively formed on the transistor 31.

  In the column (C) of the figure, a second (middle) wiring layer L2 formed on the upper side of the wiring layer L1 is depicted. A source wiring pattern L2S and a drain wiring pattern L2D are formed in the wiring layer L2. The extending directions of the source wiring pattern L1S and the drain wiring pattern L1D, and the source wiring pattern L2S and the drain wiring pattern L2D are orthogonal to each other. A via V1S is formed between the source wiring pattern L1S and the source wiring pattern L2S to electrically connect the overlapping portions. A via V1D is formed between the drain wiring pattern L1D and the drain wiring pattern L2D to electrically connect the overlapping portions. A heat conducting member L2X is formed on the collector wiring pattern L1C, the emitter wiring pattern L1E, and the base wiring pattern L1B. However, the wiring patterns L1 (C, E, B) and the heat conducting member L2X are not electrically connected.

  In the column (D) of the figure, the third (upper) wiring layer L3 formed on the upper side of the wiring layer L2 is depicted. A source wiring pattern L3S and a drain wiring pattern L3D are formed in the wiring layer L3. The source wiring pattern L3S is formed to cover one half surface of the semiconductor device 10, and is electrically connected to the source wiring pattern L2S via the via V2S. The drain wiring pattern L3D is formed to cover the other half surface of the semiconductor device 10, and is electrically connected to the drain wiring pattern L2D through the via V2D. Further, a part of the drain wiring pattern L3D is drawn as a heat conducting member L3X to a region overlapping with the heat conducting member L2X. A via V2X connecting the heat conducting member L3X and the heat conducting member L2X is formed between the heat conducting member L3X and the heat conducting member L2X.

  FIG. 5 is a longitudinal sectional view showing a second example (three-layer type) of the wiring pattern, and corresponds to the longitudinal sectional view of the wiring pattern shown in FIG. In the second example of this figure, three wiring layers L1 to L3 are stacked on the semiconductor substrate. The wiring layer L1 of the first layer (lower layer) includes a wiring pattern 111 electrically connected to the transistor 10 (heat generation source) and a wiring pattern 112 electrically connected to the transistor 31 (heat detection element). The second (middle) wiring layer L 2 includes a wiring pattern 113 formed on the top of the wiring pattern 111 and a wiring pattern 114 formed on the top of the wiring pattern 112. The third (upper) wiring layer L3 includes a wiring pattern 115 formed across both the transistor 10 (heat generation source) and the transistor 31 (heat detection element). Note that, between the wiring pattern 111 and the wiring pattern 113, between the wiring pattern 113 and the wiring pattern 115, and between the wiring pattern 114 and the wiring pattern 115, respectively, electrically via the vias 116 to 118. It is connected. On the other hand, the wiring pattern 112 and the wiring pattern 114 are not electrically connected.

  Focusing on the wiring pattern 115 of the wiring layer L3, the overlapping portion with the transistor 10 corresponds to the drain wiring pattern L3D, and the extending portion routed from the edge of the transistor 10 to the upper portion of the transistor 31 is It corresponds to the previous heat conducting member L3X (see FIG. 4D). The wiring pattern 114 of the wiring layer L2 corresponds to the above-described heat conduction member L2X (see FIG. 4C). As described above, in the semiconductor device having three (or more) wiring layers, the vertical distance between the uppermost wiring layer and the heat detecting element is increased, so the middle and lower wiring layers are also used in the vertical direction. It is desirable to stack the heat conducting members.

  When the plurality of wiring layers are formed of different materials, it is desirable that the heat conducting member be formed using a wiring layer having the highest thermal conductivity. For example, when the wiring layer L1 is formed of aluminum and the wiring layers L2 and L3 are formed of copper, the heat conductive members L2X and L3X are formed using the wiring layers L2 and L3 having higher thermal conductivity. It is desirable to form. In other words, it is desirable that the wiring layer used as the heat conducting member be formed of a material having a thermal conductivity higher than that of the other wiring layers.

  FIG. 6 is a plan view showing a modification of the first embodiment. The heat conducting member 90 in the column (A) of the figure does not divert the wiring pattern 60 electrically connected to the transistor 10, and is a dummy not electrically connected to any of the transistor 10 and the heat detection element 31. It is formed using a wiring pattern.

  With such a configuration, the wiring pattern 60 and the heat conducting member 90 can be connected to different potential points. For example, as shown in the column (A) of the figure, if the heat conducting member 90 is connected to the ground end, the noise received by the heat conducting member 90 can be quickly dissipated to the ground end. It is possible to reduce the malfunction of the protection circuit 30.

  The heat conducting member 90 may be overlapped with at least a part of the transistor 10 which is a heat source as shown in the column (B) of the figure. With such a configuration, it is possible to form the heat conduction member 90 which is potentially independent of the wiring patterns 50 and 60 without unnecessarily reducing the size of the wiring patterns 50 and 60.

Second Embodiment
FIG. 7 is a schematic view showing a second embodiment (application to a switching regulator IC) of the semiconductor device. In the drawing, (A) column is a plan view (top view) of the semiconductor device 2 and (B) column is a block diagram of the semiconductor device 2.

  The semiconductor device 2 of the second embodiment includes a P-channel MOS field effect transistor 210H and an N-channel MOS field effect transistor 210L, a driver 220, an overheat protection circuit 230, wiring patterns 240 to 260, and pads 270 to 290. And.

  The transistor 210H is an upper power transistor integrated on a semiconductor substrate, and is connected between the pad 270 (input end of the input voltage Vi) and the pad 280 (output end of the switch voltage Vsw). Specifically describing the connection relationship, the source of the transistor 210 H is connected to the pad 270 through the wiring pattern 240. The drain of the transistor 210 H is connected to the pad 280 via the wiring pattern 250. The gate of the transistor 210H is connected to the first output end of the driver 220.

  The transistor 210L is a lower power transistor integrated on a semiconductor substrate, and is connected between the pad 280 and the pad 290 (ground end). Specifically describing the connection relationship, the drain of the transistor 210 L is connected to the pad 280 through the wiring pattern 250. The source of the transistor 210 L is connected to the pad 290 through the wiring pattern 260. The gate of the transistor 210L is connected to the second output end of the driver 220.

  The driver 220 generates gate voltages of the transistors 210H and 210L, respectively, to turn on / off the transistors 210H and 210L complementarily. Here, “complementary” is not only the case where the on / off states of the transistors 210H and 210L are completely reversed, but also the simultaneous off period of the transistors 210H and 210L is provided from the viewpoint of through current prevention. Also includes the case where By performing such on / off control, it is possible to generate a rectangular wave-like switch voltage Vsw which is pulse-driven between the input voltage Vi and the ground voltage GND. A desired output voltage Vo can be generated by smoothing the switch voltage Vsw outside the semiconductor device 2.

  The overheat protection circuit 230 includes the heat detection element 231 integrated on the semiconductor substrate, monitors whether or not the junction temperature Tj exceeds a predetermined threshold temperature Tjmax (eg, 150 ° C. or 175 ° C.), and performs an overheat protection signal. Generate S2. The driver 220 forcibly turns off both the transistors 210H and 210L when the overheat protection signal S2 becomes a logic level (for example, low level) at the time of overheat detection. Such overheat protection operation can enhance the safety of the semiconductor device 2.

  In the semiconductor device 2 according to the second embodiment, switching noise is apt to occur as the transistors 210H and 210L are turned on / off. Therefore, as a means for preventing a malfunction of the overheat protection circuit 230 due to switching noise, it is desirable to provide a buffer band 200 between the transistors 210H and 210L and the overheat protection circuit 420.

  The wiring pattern 240 is a conductive member (input line) that electrically connects the source of the transistor 210H and the pad 270. The wiring pattern 250 is a conductive member (output line) electrically connecting the drains of the transistors 210H and 210L and the pad 280. The wiring pattern 260 is a conductive member (ground line) electrically connecting the source of the transistor 210L and the pad 290. Each of the wiring patterns 240 to 260 is formed by patterning a metal having high conductivity (aluminum, copper, silver, or gold).

  The pad 270 is a metal electrode corresponding to the input end of the input voltage Vi, and is wire-bonded to an input terminal (not shown). The pad 280 is a metal electrode corresponding to the output end of the switch voltage Vsw, and is wire-bonded to a switch terminal (not shown). The pad 290 is a metal electrode corresponding to an application end of the ground voltage GND, and is wire-bonded to a ground terminal (not shown).

  Also in the semiconductor device 2 of the second embodiment, the sensitivity of the overheat protection circuit 230 or the sensitivity of the overheat protection circuit 230 can be obtained by devising the wiring layout pattern on the semiconductor substrate instead of the circuit configuration of the overheat protection circuit 230 as in the first embodiment. Accuracy has been improved. More specifically, in the semiconductor device 2 of the second embodiment, a portion of the wiring pattern 260 electrically connected to the source of the transistor 210L, which is one of the heat sources, is routed to the heat detection element 231. A heat conducting member 260X overlapping the heat detecting element 231 is formed.

  With such a configuration, the overheat protection circuit 230 can detect heat generation of the transistor 10 accurately and quickly, so that the sensitivity and accuracy of the overheat protection circuit 230 can be improved. .

  In the semiconductor device 2 of the second embodiment, among the wiring patterns 240 to 260 electrically connected to the transistors 210H and 210L, the wiring pattern 260 (ground line) with the least noise superposition is diverted in part. A heat conducting member 260X is formed. With such a configuration, it is possible to reduce the malfunction of the overheat protection circuit 230 due to noise. In particular, since switching noise is likely to be superimposed on the wiring pattern 250 to which the rectangular switch voltage Vsw is applied, it is better to avoid using the wiring pattern 250 as a heat conducting member.

<Example of application to electronic devices>
FIG. 8 is an external view of the personal computer X, and FIG. 9 is an external view of the television Y. By using the above-described semiconductor devices 1 and 2 as a power supply IC of such an electronic device, it is possible to improve the safety and reliability of the electronic device.

<Other Modifications>
However, the application of the present invention is not limited to the above, and semiconductor devices in general provided with an overheat protection circuit (for example, a power supply IC, a power supply driver IC, a power management IC, a load switch IC, a motor driver IC, The present invention can be applied to all power devices such as reset ICs.

  Further, various technical features disclosed in the present specification can be modified in various ways without departing from the gist of the technical creation other than the above embodiment. That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is shown by the claims rather than the description of the above embodiment. It is to be understood that the present invention includes all modifications that fall within the meaning and scope equivalent to the claims.

  The present invention can be used to enhance the safety and reliability of a semiconductor device.

1, 2 Semiconductor device 10 P-channel type MOS field effect transistor (heat generation source)
10S source region 10D drain region 10G gate oxide film 20 operational amplifier 30 overheat protection circuit 31 npn bipolar transistor (thermal detection element)
32 band gap power supply section 33 to 35 resistance 36, 37 inverter 40a, 40b resistance 50, 60 wiring pattern 60X heat conducting member (a part of the wiring pattern 60 is diverted)
70, 80 Pad 90 heat conduction member (dummy wiring pattern)
101 to 103, 111 to 115 Wiring pattern 104, 116 to 118 Via 200 Buffer zone 210H P-channel type MOS field effect transistor (heat generation source)
210L N-channel MOS field effect transistor (heat generation source)
220 driver 230 overheat protection circuit 231 heat detecting element 240, 250, 260 wiring pattern 260X heat conducting member (a part of the wiring pattern 260 is diverted)
270, 280, 290 Pad L1 to L3 Wiring layer X Personal computer Y Television

Claims (5)

A heat source and a heat detection element formed on a semiconductor substrate;
A heat conducting member having a thermal conductivity higher than that of the semiconductor substrate and formed over both the heat generating source and the heat detecting element;
Consist of integrating
The heat generation source is a power transistor whose switching is controlled,
The heat conduction member is not electrically connected to the heat detection element among a plurality of wiring patterns electrically connected to the heat generation source, and is a part of a ground line with the least noise superposition. Of the first wiring layer formed on the semiconductor substrate and the second wiring layer laminated on the semiconductor layer and having a higher thermal conductivity. A semiconductor device characterized by using a second wiring layer. The first wiring layer includes a first wiring pattern electrically connected to the heat generation source, and a second wiring pattern electrically connected to the heat detection element.
The second wiring layer includes a third wiring pattern formed across both the heat generation source and the heat detection element.
The first wiring pattern and the third wiring pattern are electrically connected, while the second wiring pattern and the third wiring pattern are not electrically connected.
2. The heat conduction member according to claim 1, wherein an extension portion of the third wiring pattern, which is drawn from the edge of the heat source toward the heat detection element, corresponds to the heat conduction member. Semiconductor device.   A buffer band is provided between the power transistor and the overheat protection circuit including the heat detection element to prevent a malfunction of the overheat protection circuit due to switching noise accompanying on / off of the power transistor. The semiconductor device according to claim 1. The power transistor includes an upper power transistor and a lower power transistor connected in series between the power supply terminal and the ground terminal,
The heat conduction member may be formed by drawing a part of the ground line laid between the lower power transistor and the ground end to the upper part of the heat detection element. The semiconductor device according to any one of claims 1 to 3.   An electronic device comprising the semiconductor device according to any one of claims 1 to 4.