JP6542536B2 - Gaming machine - Google Patents

Description

  The present invention relates to gaming machines such as ball and ball gaming machines and spinning drum gaming machines, and more particularly to light emission control for presentation and presentation in gaming machines.

Patent No. 4613191 gazette

In ball and ball gaming machines (so-called pachinko gaming machines) and rotating drum gaming machines (so-called slot gaming machines), effects accompanied by a game are performed by lighting and blinking operations by light emitting units using LEDs (Light Emitting Diodes) or the like. There are some which perform various situation presentation, error notification, guidance display, etc.
For the operation of the light emitting unit, for example, a microcomputer functioning as an effect control unit supplies drive data to an LED driver circuit or the like. For example, a large number of LEDs are connected to the LED driver, and the LED driver causes each LED to execute a light emission operation by supplying a light emission drive current corresponding to the drive data.

  In the above Patent Document 1, the effect control unit outputs drive data for light emission drive of a plurality of LEDs as serial data to the LED driver, and the LED driver converts the serial data into parallel data and is connected. A technology for supplying current to each LED is disclosed.

In such a game machine, various effects and display operations using the light emitting unit are performed, but the light emitting driver and the periphery are required due to the difference in the light emitting purpose such as the effect and the presentation and the need for the light emitting unit such as a large number of LEDs. The configuration tends to be complicated.
Therefore, the present invention aims to increase the efficiency of the configuration and operation around the light emission driver.

A game machine according to the present invention comprises: a light emitting unit for effect; a light emitting unit for condition presentation; light emission control means for outputting a drive signal for controlling light emission of each of the light emitting units for the effect and the condition presentation; based on the drive signal comprises a light emitting portion for directing, and multiple emission driver that generates a light emission drive current to the light emitting portion for status presentation. Specific emission driver of the plurality of light emitting driver, a plurality of light emitting portions so as to generate a light emission drive current to both the light emitting portion of the light emitting portion and status presentation for presentation are connected, said specific emission driver The light emitting unit for effect connected to is composed of a plurality of LEDs connected in series, and the light emitting unit for situation presentation connected to the specific light emitting driver is composed of one LED, and the specific light emitting unit The light emission driver operates using the first power supply voltage as a power supply voltage, and a second power supply having a voltage higher than the first power supply voltage to flow a light emission drive current to the light emitting unit for effect connected to the specific light emission driver. A voltage is connected, and the first power supply voltage is connected to the light emitting unit for situation presentation connected to the specific light emission driver in order to flow a light emission drive current.
That is, when the light emission driver is driven by the first power supply voltage (for example, 5 V), the light emission unit for effect and the light emission unit for situation presentation are connected to the specific light emission driver to drive light emission. This is because the light emitting unit for effect and the light emitting unit for situation presentation can be shared. In this case, the light emission drive current is supplied using the second power supply voltage (for example, 12 V) for the light emission part for effect, and the light emission drive current is supplied using the first power supply voltage for the light emission part for situation presentation Make it For example, the light emitting unit for status presentation can provide sufficient status presentation by lighting / blinking / lighting off, and can be configured by one LED or the like.
Thus, the peripheral circuit configuration of a specific light emission driver can be simplified.
This also promotes efficient circuit configuration in that it is not necessary to separate the light emission driver for presentation and identification.
In the above-described gaming machine, a plurality of LEDs are connected in series to the light emitting unit for effect connected to the specific light emitting driver, and to the light emitting unit for situation presentation connected to the specific light emitting driver It is conceivable that one LED is connected.
It is preferable that the light emitting unit for effect use a series connection of a plurality of LEDs for the effect of further enhancing the game property and for the light emitting range. In this case, a method using the second power supply voltage is applied to perform sufficient light emission driving.
In the above-described gaming machine, the light emission control unit emits light with two resolutions of lighting and extinguishing, and the light emitting unit for effect presentation emits light with resolution of three gradations or more. It is conceivable to output a drive signal for controlling the light emission of each light emitting unit.
The light emitting unit for effect preferably has a resolution of 3 gradations or more for the effect of further enhancing the game property. On the other hand, since the light emitting unit for status presentation can provide sufficient status presentation by lighting / blinking / lighting out, it may be of two gradations of lighting and off.

  According to the present invention, the processing for light emission control can be made efficient, and the light emission control processing load can be reduced.

It is a perspective view of a pachinko game machine of an embodiment of the invention. It is a front view of the board of a pachinko game machine of an embodiment. It is a block diagram of control composition of a pachinko game machine of an embodiment. It is a block diagram of the connection composition of the driver part of a 1st embodiment. It is a block diagram of an example of an internal configuration of a driver part of a 1st embodiment. It is explanatory drawing of the light emission aspect of the light emission part for the situation presentation of embodiment. It is explanatory drawing of the LED connection structure with respect to the driver part of embodiment. It is a flowchart of main control main processing of an embodiment. It is a flow chart of main control timer interruption processing of an embodiment. It is a flowchart of a special symbol management process of an embodiment. It is a flowchart of the 1st special figure starting opening check processing of an embodiment. It is explanatory drawing of the command of embodiment. It is a flow chart of production control main processing of an embodiment. It is a flowchart of 1 ms timer interruption processing of production control of form of execution. 5 is a flowchart of command analysis processing in effect control of the embodiment. It is a flowchart of the command corresponding | compatible process in presentation control of embodiment. It is a flowchart of the command corresponding | compatible process in presentation control of embodiment. It is a flowchart of the scenario registration process in the effect control of embodiment. It is a flowchart of the scenario deletion process in production control of embodiment. It is a flowchart of a scenario update process in the effect control of the embodiment. It is a flowchart of the sub-scenario update process of embodiment. It is explanatory drawing of scenario registration information of embodiment, lamp data registration information, and motor data registration information. It is an explanatory view of sound data registration information of an embodiment. It is explanatory drawing of the main scenario table of embodiment. It is explanatory drawing of the sub scenario table of embodiment. It is a flowchart of the LED drive data update process of embodiment. It is a flow chart of LED drive data set processing for situation presentation of an embodiment. It is a flow chart of LED output processing of a 1st embodiment. It is an explanatory view of registration information of lamp data of an embodiment. It is explanatory drawing of the address table of lamp data and mask data of embodiment. It is explanatory drawing of the lamp | ramp data table of embodiment, and a mask data table. It is an explanatory view of updating and output of lamp data of an embodiment. It is explanatory drawing of serial data transmitted to the driver of embodiment. It is explanatory drawing of serial data transmission to each channel of embodiment. It is explanatory drawing of serial data transmission operation | movement of the production | presentation control part of embodiment. It is an explanatory view of 8-bit conversion of 4-bit lighting data of an embodiment. It is a flowchart of the LED driver initialization process of embodiment. It is a flowchart of the LED driver initialization process of embodiment. It is a block diagram of the connection composition of the driver part of a 2nd embodiment. It is a block diagram of an example of an internal configuration of a driver part of a 2nd embodiment. It is a flowchart of the LED output process of 2nd Embodiment.

Hereinafter, as an embodiment of a gaming machine according to the present invention, a pachinko gaming machine will be described by way of example in the following order.
<1. Structure of Pachinko Machine>
<2. Control configuration of pachinko gaming machine>
<3. Outline of operation>
<4. Driver Configuration and LED for Presentation of First Embodiment>
<5. Processing of main control section>
<6. Process of production control section>
[6-1: Main processing]
[6-2: 1 ms timer interrupt processing]
[6-3: Command Analysis Processing]
[6-4: Scenario registration / deletion processing]
[6-5: Scenario update process]
[6-6: LED drive data update process]
[6-7: LED Output Processing of First Embodiment]
[6-8: LED driver initialization process]
<7. Second embodiment>
<8. Summary and Modifications>

<1. Structure of Pachinko Machine>

First, the configuration of a pachinko gaming machine 1 as an embodiment of the present invention will be schematically described with reference to FIGS. 1 and 2.
FIG. 1 is a perspective view of the front side showing the appearance of a pachinko gaming machine 1 according to the embodiment, and FIG. 2 is a front view of a game board.
The pachinko gaming machine 1 shown in FIG. 1 and FIG. 2 mainly includes a “frame portion” and a “game board portion”.
The “frame portion” is configured to have a front frame 2, an outer frame 4, a glass door 5, and an operation panel 7 described below. The “play board section” comprises the play board 3 of FIG. In the following description, “frame” or “frame side” is a generic term for the front frame 2, the outer frame 4, the glass door 5, and the operation panel 7. Further, “board part” or “board side” indicates the game board 3.

As shown in FIG. 1, in the pachinko gaming machine 1, a frame-shaped front frame 2 is attached to a front surface of a wooden outer frame 4 so as to be openable and closable. Although not shown, a game board storage frame is formed on the back of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the game area 3a formed on the surface of the game board 3 comes to the front of the game machine shown in FIG. 1 from the opening 2a of the front frame 2.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the front player side through the transparent glass.

The glass door 5 is attached to the front frame 2 so as to be openable and closable by a pivoting mechanism 6. By operating a door lock release key cylinder (not shown) provided at a predetermined position of the glass door 5, the lock state of the glass door 5 with respect to the front frame 2 is released, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can also be released depending on the operation of the door lock release key cylinder.
Further, on the front side of the glass door 5, light emitting units 20w are provided at various places as light emitting means on the frame side. For example, as the light emitting operation by the LED, the light emitting unit 20 w performs a light emitting operation for effect, a light emitting operation for error notification, a light emitting operation according to the operation state, and the like.

An operation panel 7 is provided below the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a support mechanism (not shown).
The operation panel 7 is provided with an upper tray unit 8, a lower tray unit 9, and a firing operation handle 10.

The upper receiving tray unit 8 is formed with an upper receiving tray 8a for storing gaming balls to be provided to the ball. The lower tray unit 9 is formed with a lower tray 9a for storing gaming balls that can not be stored in the upper tray 8a.
Further, the upper tray unit 8 is provided with a ball removing button 16 for removing the gaming balls stored in the upper tray 8a toward the lower tray 9a. The lower receiving tray unit 9 is provided with a ball removing lever 17 for removing the gaming balls stored in the lower receiving tray 9a downward to the gaming machine.
Also, the upper tray unit 8 has a ball lending button 14 for requesting the game ball lending device (not shown) to pay out the game balls, and a card for requesting return of the valuable value medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper tray unit 8 is provided with effect buttons 11 and 12 and a cross key 13. The effect buttons 11 and 12 have a built-in lamp turned on and become operable during a predetermined input acceptance period, and are pressed when the built-in lamp is turned on to be a push button that can bring about a change in the effect. In addition, the cross key 13 is an operation element that allows the player to perform an operation according to the presentation situation, an operation for presentation setting, and the like.

The launch operation handle 10 is provided on the right end side of the operation panel 7 and is an operating element by which a player operates the launch device 32 shown in FIG.
Further, on both sides of the upper portion of the front frame 2 and in the vicinity of the emission control handle 10, speakers 25 for outputting a sound of the effect sound are provided.

  Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or a resin board. A ball guiding rail 31 for guiding the launched game ball is mounted on the gaming board 3 in a ring shape as a board partitioning member, and a substantially circular area surrounded by the ball guiding rail 31 is the gaming area 3a It has become.

A liquid crystal display 32 (LCD: Liquid Crystal Display) is provided substantially in the center of the game area 3a.
In the liquid crystal display device 32, under the control of the effect control unit 51 described later, fluctuation display of, for example, three decorative symbols of left, middle and right is performed on the background image. In addition, display of various effect images such as normal effect, reach effect, and super reach effect is also performed.

In the game area 3a, a center decoration 35C is provided so as to surround the periphery of the display surface of the liquid crystal display device 32.
The center decoration 35C not only exerts a decorative effect by its design, but also has an effect of protecting the display surface of the liquid crystal display device 32 from surrounding game balls. Furthermore, the center decoration 35C also functions as a member that enables right and left hitting of the flow path of the gaming ball according to the strength of the launch of the gaming ball or the stroke length. That is, the flow-down path of the game ball punched out to the upper part of the game area 3a through the ball guiding rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left hitting, the game ball flows down the left gaming area 3b, and in the case of right hitting, the game ball flows down the right gaming area 3c.

A lower left decoration 35L is provided below the left gaming area 3b to exert a decorative effect and to define a range as the left gaming area 3b.
Similarly, a lower right decoration 35R is provided below the right gaming area 3c to exert a decorative effect and to define a range as the left gaming area 3b.
In the game area 3a (the left game area 3b and the right game area 3c), nails 49 and windmills 47 are provided at required places to form various flow paths of the game balls.
Further, a center stage 35S is provided below the liquid crystal display device 32, and exhibits a decorative effect and functions as a play area of the game ball.
Although not shown, the center decoration 35C is provided with a movable object that provides visual effects in a suitable place.

In the vicinity of the upper right edge of the game area 3a, a symbol display unit 33 is provided by a dot display formed by arranging a plurality of LEDs.
In this symbol display portion 33, a first special symbol display portion, a second special symbol display portion, and an ordinary symbol display portion are formed by predetermined dot areas, and the first special symbol, the second special symbol, and the ordinary symbol are formed. The respective variable display operations (a variable display operation in which the fluctuation start and the fluctuation stop are set) are performed.
In addition, the liquid crystal display device 32 varies in time with the variable display of the first and second special symbols by the symbol display unit 33, and variably displays the decorative symbol by the image.

Below the center decoration 35C, there is provided a winning device having an upper starting opening 41 (first special symbol starting opening), and further below the lower starting opening 42a (second special symbol starting opening) A fluctuation winning device 42 is provided.
Inside the upper starting opening 41 and the lower starting opening 42a, detection sensors (upper starting opening sensor 71 and lower starting opening sensor 72 shown in FIG. 3) for detecting passage of gaming balls are formed.

  The upper starting opening 41 is a winning opening relating to the starting condition of the first special symbol variation display operation in the symbol display portion 33, and the fixed winning percentage does not have starting opening opening / closing means (means for opening or enlarging the starting opening). It has become a type winning device.

The normal variation winning device 42 having the lower starting opening 42a is configured as a winning ratio changing type winning device capable of changing the winning percentage of the gaming ball of the starting opening by the starting opening opening / closing means. That is, it is a so-called electric tulip type winning device provided with a pair of left and right movable wing pieces (movable members) 42b that allows the lower starting opening 42a to be opened or enlarged.
The lower start opening 42 a of the normal variation winning device 42 is a winning opening according to the start condition of the variation display operation of the second special symbol in the symbol display section 33. Then, the winning rate of the lower starting opening 42a fluctuates according to the operating state of the movable wing piece 42b. That is, when the movable wing piece 42b is open, winning is easy, and when the movable wing piece 42b is closed, winning is difficult or impossible.

In addition, on the left and right of the normal fluctuation winning device 42, a plurality of general winning openings 43 are provided. Inside each general winning opening 42, a detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting passage of gaming balls is formed.
In addition, on the lower side of the right gaming area 3c, a normal symbol start port 44 formed of a gate (specific passing area) through which the game ball can pass is provided. The normal symbol starting opening 44 is a winning opening related to the variable display operation of the normal symbol in the symbol display portion 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting the passing gaming ball is formed therein. It is done.

A first special variation winning device 45 (special electric winning combination) is provided midway along the flow-down path from the normal symbol start opening 44 to the normal variation winning device 42 in the right gaming area 3c.
The first special variation winning device 45 is configured to close / open the first large winning opening 45a by the open / close type open door 45b. In addition, a sensor (first large winning opening sensor 75 in FIG. 3) for detecting the passage of the gaming ball to the first large winning opening 45a is formed therein.
The lower right decoration 35R bulges from the surface of the game board 3 around the first large winning opening 45a, and the upper side of the bulged portion and the upper surface of the open door 45b are downstream guidance of the right flow down path 3c Form a part. Therefore, by the opening door 45b being drawn into the inside of the board, the gaming ball having reached the downstream guiding portion is easily put into the first large winning opening 45a.

Further, below the normal fluctuation winning device 42, a second special fluctuation winning device 46 (special electric winning combination) is provided. The second special variation winning device 46 is structured such that the second large winning opening 46a inside thereof is closed / opened by an open door 46b which is pivotally supported at its lower part and can be opened and closed. In addition, a sensor (a second large winning opening sensor 76 in FIG. 3) for detecting the passage of the game ball to the second large winning opening 46a is formed therein.
By opening the open door 46b, the second big winning opening 46a is opened. In this state, the gaming balls flowing down the left gaming area 3b or the right gaming area 3c will enter the second big winning opening 50 with high probability.

As described above, the upper start opening 41, the lower start opening 42a, the normal symbol start opening 44, the first large winning opening 45a, the second large winning opening 46a, and the general winning opening 43 are formed as winning openings in the game area of the board. It is done.
In the pachinko gaming machine 1 of the present embodiment, among these winning openings, if there is a winning to a winning opening other than the normal symbol starting opening 44, per winning ball set for each winning opening. The number of winning balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the number of winning balls is set to three for the upper start opening 41 and the lower start opening 42a, 13 for the first large winning opening 45a, 13 for the second large winning opening 46a, 10 for the general winning opening 43, and so on.
In addition, the game ball which did not win a prize in each of these winning openings is discharged from the game area 3 a through the out port 48.
Here, "winning" means that the winning opening takes in the game ball inside thereof, or the game ball passes through the gate. In practice, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated as having a "winning" at the winning opening. The game ball pertaining to this winning is also referred to as a "winning ball".

On the board as described above, the center decoration 35C, the lower left decoration 35L, the lower right decoration 35R, the center stage 35S, the first special fluctuation winning device 45, the second special fluctuation winning device 46, and a movable body character not shown Although not shown in detail, the light emitting units 20b, 20Z, 20H, and 20J, which are, for example, LEDs, are provided as light emitting means on the panel side, though not shown in detail.
The light emitting unit 20 b performs a light emitting operation for effect and a light emitting operation for error notification.
The light emitting units 20Z, 20H, and 20J are light emitting units for presenting various situations.
The light emitting unit 20Z performs a light emitting operation for variable symbol identification. For example, three light emitting units 20Z are provided corresponding to the first special symbol, the second special symbol, and the normal symbol, respectively, and for the corresponding symbols, for example, while the symbol variation is stopped, during the variation, during the hit The light emission operation to identify is performed.
The light emitting unit 20H performs a light emitting operation for displaying the number of holdings. For example, a total of eight light emitting units 20H are provided to display the number of reservations for the first special symbol variation up to four at maximum and the number of reservations for the second special symbol variation up to four at maximum The number of reservations is displayed in the light emission state.
The light emitting unit 20J performs a light emitting operation for notifying a gaming state. A required number of light emitting units 20J are provided (three in this example), and in each light emitting state, they notify of a large hit, a definite change, a time decrease, and the like.
In this example, the light emitting units 20Z, 20H, and 20J are provided on the panel side, but all or part of the light emitting units 20Z, 20H, and 20J may be provided on the frame side.

Hereinafter, for the sake of explanation, the light emitting unit 20 w on the board side and the light emitting unit 20 b on the frame side may be referred to as “effect light emitting unit”.
The light emitting unit 20Z may be described as a "variable symbol identifying light emitting unit", the light emitting unit 20H as a "number-of-holds display light emitting unit", and the light emitting unit 20J as a "game condition notifying light emitting unit".
Furthermore, the light emitting units 20Z, 20H, and 20J may be collectively referred to as "a light emitting unit for situation presentation".

<2. Control configuration of pachinko gaming machine>

Next, a configuration of a control system of the pachinko gaming machine 1 of the present embodiment will be described. FIG. 3 is a schematic block diagram of an internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 according to the present embodiment mainly uses the main control board 50, the effect control board 51, the liquid crystal control board 52, the payout control board 53, the emission control board 54, and the power board 58 as substrates forming the control configuration. Is provided.

A microcomputer or the like is mounted on the main control board 50 and performs overall control related to the entire game operation of the pachinko gaming machine 1. In the following, a component of the main control substrate 50 including a microcomputer mounted on the main control substrate 50 is referred to as a "main control unit 50".
The effect control board 51 has a microcomputer and the like, receives an effect control command from the main control unit 50, and performs control to execute various effect operations using an image display, light emission, sound output, and movable object. I do. In the following, the components of the effect control board 51 including the microcomputer and the like mounted on the effect control board 51 will be referred to as “effect control unit 51”.

The liquid crystal control board 52 is mounted with a microcomputer, a video processor, etc., and receives the display control command from the effect control unit 51 to control the display operation by the liquid crystal display device 32.
The payout control board 53 controls the payout of the winning balls by the gaming ball payout device 55 connected to the pachinko gaming machine 1.
The launch control board 54 controls the launch operation of the gaming balls by the launch device 56 provided in the pachinko gaming machine 1 of the player.
The power supply board 58 performs AC / DC conversion, DC / DC conversion from an external power supply (for example, AC 24 V), and supplies an operating power supply voltage Vcc to each part. The illustration of the power supply path is omitted.

First, the main control unit 50 and its peripheral circuits will be described.
The main control unit 50 includes a microprocessor incorporating a CPU 100 (hereinafter referred to as "main control CPU 100"), a ROM 101 (hereinafter referred to as "main control ROM 101"), and a RAM 102 (hereinafter referred to as "main control RAM 102") It constitutes a microcomputer.
The main control CPU 100 executes various calculations and control processing according to the progress of the game based on the control program.
The main control ROM 101 stores a control program of the game operation by the main control CPU 100 and various data necessary for the game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
Although not shown, the main control unit 50 includes an interface circuit with each part, a random number generation circuit for generating random numbers for drawing concerning a special symbol variation display, CTC (Counter Timer Circuit) for counting various time, main The control CPU 100 is also provided with an interrupt controller circuit that gives an interrupt signal.

The main control unit 50, as described above, each winning means (the upper start opening 41, the lower start opening 42a, the normal symbol start opening 44, the first large winning opening 45a, the second large winning opening 46a, general of the game area of the board It is configured to receive a detection signal of a sensor provided in the winning opening 43).
That is, the main control unit 50 detects detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76. Supplied.
In addition, although these sensors (71-76) are comprised by the detection switch which detects the game ball which entered, specifically, contactless switches, such as non-contact switches, such as a photo switch and a proximity switch, and a micro switch It can be configured by a switch.

  The main control unit 50 receives detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76. Perform processing according to For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, etc. are performed.

The main control unit 50 is also connected to a normal motor combination solenoid 77 that opens and closes the movable wing piece 42b of the lower starting opening 42, and the main control unit 50 transmits a control signal according to the game progress status The driving operation of the accessory solenoid 77 is performed, and the opening and closing operation of the movable wing piece 42b is performed.
Furthermore, the main control unit 50 includes a first large winning opening solenoid 78 for opening and closing the opening door 45b of the first large winning opening 45 and a second large winning opening and closing for the open door 46b of the second large winning opening 46. A mouth solenoid 79 is connected. The main control unit 50 controls the driving of the first large winning opening solenoid 78 or the second large winning opening solenoid 79 according to the so-called jackpot situation, and the opening operation of the first large winning opening 45 or the second large winning opening 46 Run

  A symbol display unit 33 is connected to the main control unit 50, and transmits a control signal to the symbol display unit 33 to execute various symbol display (turning off / lighting / flashing of the LED). Thereby, the display operation in the first special symbol display unit 80, the second special symbol display unit 81, and the normal symbol display unit 82 in the symbol display unit 33 is executed.

  The frame external terminal substrate 57 is connected to the main control unit 50. The main control unit 50 can transmit information on the game progress to a hall computer (not shown) via the frame external terminal board 57. The information related to the game progress is, for example, information such as jackpot winning information, prize ball number information, and symbol variation display execution frequency information. The hall computer is a management computer that centrally manages the pachinko hall gaming machines, and is installed outside the gaming machines.

Further, a payout control board 53 is connected to the main control unit 50. To the payout control substrate 53, a launch control substrate 54 for controlling the launch device 56 and a gaming ball payout device 55 for payout of gaming balls are connected.
The main control unit 50 transmits, to the payout control board 53, a control command related to payout (a payout control command for specifying the number of winning balls). The payout control board 53 controls the gaming ball payout device 55 in accordance with the control command to execute payout of the gaming balls.
Further, the payout control board 53 can transmit information (payout state signal) on the payout operation state to the main control unit 50. On the main control unit 50 side, whether or not the game ball payout device 55 is functioning normally is monitored by the payout state signal. Specifically, at the time of the payout operation of the winning balls, it is monitored whether or not a defect such as a blockage of the balls or insufficient payout of the winning balls has occurred.

  Further, the main control unit 50 transmits, to the effect control unit 51, an effect control command including information on the special symbol variation display. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is performed by one-way communication. This is to prevent an unauthorized signal from an external fraud from being input to the main control unit 50 via the effect control unit 51.

Subsequently, the effect control unit 51 and its peripheral circuits will be described.
The effect control unit 51 has a microprocessor incorporating a CPU 200 (hereinafter referred to as “effect control CPU 200”), a ROM 201 (hereinafter referred to as “effect control ROM 201”), and a RAM 202 (hereinafter referred to as “effect control RAM 202”). It constitutes a microcomputer.
Based on the effect control program and the effect control command received from the main control unit 50, the effect control CPU 200 performs arithmetic processing for various effect operations and controls each effect means. In the case of the pachinko gaming machine 1 according to the present embodiment, the rendering means is the liquid crystal display device 32, the light emitting units 20w and 20b, the speaker 25, and the movable body part whose illustration is omitted.
The effect control CPU 200 also performs control for presenting various situations. Specifically, the light emission control of the light emitting units 20Z, 20H, and 20J is performed.
The effect control ROM 201 stores a control program of effect operation by the effect control CPU 200 and various data necessary for effect operation control.
The effect control RAM 202 is used as a work area used by the effect control CPU 200 for various arithmetic processing, a table data area, and a buffer area for various input / output data and processing data.
Although not shown, the effect control unit 51 gives an interrupt signal to the interface circuit with each part, a random number generation circuit for generating random numbers for lottery for effect, CTC for counting various time, and the effect control CPU 200 It also includes an interrupt controller circuit, a sound source IC for sound effects, and the like.
The main roles of the effect control unit 51 are reception of effect control commands from the main control unit 50, determination of selection of effects based on effect control commands, transmission of liquid crystal control commands to the liquid crystal display device 32, voice of the speaker 45 The output control, the light emission control of the light emitting units 20 w, 20 b, 20 Z, 20 H, and 20 J (LEDs), the operation control of the movable object, and the like are performed.

  The effect control unit 51 transmits the effect control command to the liquid crystal display device 32 side, but the effect control command is sent to the liquid crystal control substrate 52 via the liquid crystal interface substrate 66.

The liquid crystal control substrate 52 performs display control of the liquid crystal display device 32. Although not shown, the liquid crystal control board 52 is provided with a VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, and a liquid crystal control RAM.
The VDP controls overall video output processing such as image expansion processing and image drawing.
The image ROM stores image data (effect image data) on which the VDP performs image expansion processing.
The VRAM is an image memory area for temporarily storing image data expanded by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program describing the display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area or a buffer memory.

  With these configurations, the liquid crystal control board 52 generates various image data based on the liquid crystal control command from the effect control board 51, and outputs the image data to the liquid crystal display device 32. As a result, various effect images are displayed on the liquid crystal display device 32.

Further, a frame driver unit 61 and a board driver unit 62 are connected to the effect control unit 51.
The frame driver unit 61 drives the light emission of the LED of the lamp unit 63 on the frame side. The lamp portion 63 generally indicates the light emitting portion 20w provided on the frame side as shown in FIG.
The panel driver unit 62 drives light emission of the LEDs of the lamp unit 64 on the panel side. The lamp unit 64 generally indicates the light emitting units 20b, 20Z, 20H, and 20J provided on the side of the disc as shown in FIG.

Further, a motor driver unit 70 is connected to the effect control unit 51.
The motor driver 70 drives the movable object combination motor 65 to execute the operation of the movable object provided on the side of the board.
For example, a stepping motor is used as the movable object product motor 65.

In the case of the present embodiment, the frame driver unit 61 is a drive signal output unit of the first system, the panel driver unit 62 is a drive signal output unit of the second system, and the motor driver unit 70 is a drive signal output unit of the third system. .
Although this will be described later in detail with reference to FIG. 4, in the case of the present embodiment, the effect control unit 51 (effect control CPU 200) uses the serial data transmission channels ch1, ch2, and ch3 to emit light drive data and motor drive data. The serial data is output to the frame driver unit 61, the board driver unit 62, and the motor driver unit 70 as serial data.
Note that, for example, a part of the panel driver unit 62 may operate as the motor driver unit 70 to drive the LEDs of the lamp unit 64 and the movable object role motor 65.

Further, the effect control unit 51 controls the sound source IC 59 in order to cause the speaker 25 to output a desired sound. A sound data ROM 69 is connected to the sound source IC 59, and the sound source IC 59 acquires necessary sound data (sound data of a phrase to be reproduced) from the sound data ROM 69 and performs audio signal output.
The sound source IC 59 mixes phrases of a plurality of channels to obtain a predetermined number (channel number) of audio signals. As shown in FIG. 1, in the case of this example, since a plurality of speakers 25 are provided, the number of output channels of the sound source IC 59 can be, for example, two channels of Lch and Rch (stereo output). By the above mixing, phrases of a plurality of channels instructed to be reproduced by the effect control unit 51 can be reproduced simultaneously.

An output sound signal from the sound source IC 59 is amplified by the amplifier unit 67 and then given to the speaker 25.
Although the number of output channels of the sound source IC 59 is one in FIG. 3 for convenience of illustration, in actuality, output channels corresponding to, for example, Lch and Rch are provided as the amplifier unit 67 and the speaker 25, respectively. It is possible to play sound by
Further, although the sound source IC 59 is provided separately from the effect control unit 51 in this example, the sound source IC 59 may be provided in the effect control unit 51.

Further, the effect control unit 51 is connected to the operation unit 60 operable by the player, and can receive an operation detection signal from the operation unit 60. The operation unit 60 is the effect buttons 11 and 12 and the cross key 13 described with reference to FIG. 1 and their operation detection mechanism.
The effect control unit 51 can perform various effect control in accordance with the operation detection signal from the operation unit 60.

  Based on the effect control command sent from the main control unit 50, the effect control unit 51 determines the effect pattern by lottery or uniquely from among a plurality of effect patterns prepared in advance, and performs various effects at necessary timings. Control the means. Thereby, the display of the effect image by the liquid crystal display device 32 corresponding to the effect pattern, the reproduction of the sound from the speaker 25, the lighting and blinking drive of the LED in the lamp units 63 and 64 (light emitting units 20w, 20b, 20Z, 20H, 20J) The movement of the movable body part by the movable body part product motor 65 is realized, and various effect patterns are developed in time series. As a result, a "reproduction scenario" is realized.

The effect control command defines a function according to a 2-byte configuration including a 1-byte long mode (MODE) and a 1-byte long event (EVENT).
In order to distinguish between MODE and EVENT, Bit7 of MODE is ON and Bit7 of EVENT is OFF.
When these pieces of information are transmitted as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, main control CPU 100 sets and outputs mode (MODE) information for transmitting the command to effect control unit 51, and the first strobe signal after a predetermined time has elapsed since this setting. Send Furthermore, event (EVENT) information is set and output after a predetermined time has elapsed since transmission of this strobe signal, and a second strobe signal is transmitted after a predetermined time has elapsed since this setting.
The strobe signal is controlled by the main control CPU 100 to an active state for a predetermined period in which the effect control CPU 200 can reliably receive a command.
The effect control unit 51 (effect control CPU 200) generates an interrupt based on the input of the strobe signal to execute a control program for command reception interrupt processing, and the effect control command is acquired in the interrupt processing. .

<3. Outline of operation>

An outline of the operation of the pachinko gaming machine 1 will be described.
[Symbol variation display game]
In the pachinko gaming machine 1, the main control unit 50 performs a big hit lottery by random number lottery on the condition that a predetermined starting condition, specifically, the game ball has won the upper starting opening 41 or the lower starting opening 42. Based on the lottery result, the special symbol (identification symbol for notifying the big hit lottery result) is variably displayed on the first special symbol display unit 80 or the second special symbol display unit 81, and the special symbol variation display game is started, After a predetermined time has passed, the result is displayed on the special symbol display section (80 or 81).

In the present embodiment, the jackpot lottery based on the winning of the upper starting opening 41 and the jackpot lottery based on the winning of the lower starting opening 42 are performed independently. Therefore, the jackpot lottery result for the upper starting opening 41 is derived and displayed on the first special symbol display unit 80 side, and the jackpot lottery result for the lower starting opening 42 is derived and displayed on the second special symbol display unit 81 side.
In addition, for the sake of explanation, the special symbol variation display game on the first special symbol display unit 80 side is "the first special symbol variation display game", and the special symbol variation display game on the second special symbol display unit 81 side is "the second special symbol variation It is called "display game". However, the first and second special symbols are collectively referred to as "special symbol", and the first and second special symbol variation display games are collectively referred to as "special symbol variation display games".

  When the special symbol variation display game is started, the decorative symbol variation display game in which the decorative symbol (game symbol) is variably displayed on the liquid crystal display device 32 is started along with this, and various effects appear accompanying it Be done. Then, when the lottery result is displayed on the first and second special symbol display portions (80, 81), the result is also displayed on the liquid crystal display device 32 by the decorative symbol. That is, in this decorative symbol variation display game, an effect display reflecting the lottery result in the special symbol variation display game, that is, an effect reflecting the big hit lottery result appears.

  For example, when the result of the special symbol variation display game is "big hit", the result of the decorative symbol variation display game is also an effect reflecting the "big hit". In the special symbol display section (80, 81), a special symbol indicating a big hit is stopped and displayed in a predetermined display mode, and the liquid crystal display device 32 displays each display area of "left", "middle" and "right". In the display area where the decorative symbol reflects the big hit lottery result on the hit effective line (for example, in each display area of "left", "middle" and "right", three decorative symbols are "7" "7" " It is stopped and displayed in the display state of 7 ".

When this "big hit", for example, the first large winning opening solenoid 78 or the second large winning opening solenoid 79 is driven, the opening operation of the first large winning opening 45 or the second large winning opening 46 in a predetermined pattern A special gaming state (big hit game) occurs which is executed and which is more advantageous to the player than the normal gaming state. In this big hit game, the opening of the big winning opening is open until a predetermined time elapses, or a predetermined number of gaming balls are winning in the large winning opening, and the large winning opening is predetermined on the condition that one of them is satisfied. A round game such as being closed for a time is repeated a predetermined number of times.
When the big hit game is started, an opening effect for notifying that the big hit is started is performed first, and after the opening effect is finished, the above-mentioned round game is performed for the specified number of rounds. In addition, during the round game, a round effect corresponding to each round is performed. Then, after the defined number of rounds, an ending effect notifying that the big hit is finished is performed, whereby the big hit game is finished.

  As described above, the special symbol variation display game and the decorative symbol variation display game are substantially the same as the symbol game time (the timing from the start timing of the variation display to the stop display timing), and the result of the special symbol variation display game is reflected. Since what is expressed in the decorative symbol variation display game, the two symbol variation display games can be regarded as equivalent symbol games. For the sake of explanation, the above-mentioned two symbol variation display games may be simply referred to as a "symbol variation display game".

  Further, based on the fact that the game ball has passed through the gate 44 (normal symbol starting opening), the main control unit 50 performs a lottery for assistance per random number lottery. According to the lottery result, the normal symbol represented by the LED of the normal symbol display unit 82 is variably displayed, and the normal symbol variation display game is started, and after a predetermined time has passed, the result is specified as lighting and non-lighting of the LED Stop display in combination.

  Then, in the case of "assist hit", the normal electric combination solenoid 77 operates, the movable wing piece 42b is opened, the lower starting opening 42 is opened or enlarged, and the gaming ball tends to flow in (the starting opening is opened In this case, an auxiliary gaming state (hereinafter referred to as a "general power release game") occurs which is more advantageous to the player than the normal gaming state. In this common power release game, the movable wing pieces 42b are opened for a predetermined time (for example, 0.2 seconds) or a predetermined number (for example, four) of game balls are released, and then for a predetermined time (for example, An operation of closing the movable wing piece 42b for 0.5 seconds) is repeated a predetermined number of times. In addition, also when the game ball wins in the lower starting opening 42 during the normal power release game, the above-mentioned special symbol variation display game is similarly performed, and the decoration symbol variation display game is performed accordingly.

Here, during the special symbol variation display game, during the normal symbol variation display game, during the big hit game, or during the public opening game, etc., further from the upper starting opening sensor 71 or the lower starting opening sensor 72 or the gate sensor 73 When there is an input of the detection signal and the start condition is satisfied, the game information to be used for the lottery is acquired based on the detection signal, and the data relating to the right to start each variable display game to be played As the (pending data), except for those involved during the variable display, pending storage can be performed up to the maximum pending storage number (for example, a maximum of 4) which is a predetermined upper limit value. In order to make this hold number clear to the player, a hold display provided as an icon image is lit and displayed on the screen by the hold number display unit 20H and the liquid crystal display device 32.
Normally, the variable display game is executed for each holding ball in the order of occurrence of the holding balls. In the present embodiment, four pieces of the same number as the maximum number of pending storages are treated as the predetermined number of the upper limit, and the pending data regarding the first special symbol and the second special symbol are stored up to four each, and the variation of the special symbol or the ordinary symbol Hold as fixed number of times.

[Playing state]
The pachinko gaming machine 1 of the present embodiment is configured to be capable of generating a plurality of types of gaming states.
First, the pachinko gaming machine 1 of the present embodiment is provided with a “probability fluctuation (hereinafter, referred to as“ probability variation ”) function” in which the main control unit 50 (CPU 100) takes charge of its function unit. There are two types of this: a probability variation function (hereinafter referred to as "special symbol probability variation function") according to a special symbol and a probability variation function according to a regular symbol (hereinafter referred to as "normal symbol probability variation function").

The special symbol probability change function is advantageous over the normal gaming state by changing the lottery probability of the big hit from the low probability (for example, 1/399) of the predetermined probability (ordinary probability) to the high probability (for example, 1/3/9) It is a function to generate a "high probability state". Under this high probability state, the big hit is likely to occur because the big hit lottery probability is high.
The normal symbol probability variation function is advantageous over the normal gaming state by changing from low probability (e.g. 1/256) to high probability (e.g. 255/256) where the lottery probability per assist is a predetermined probability (normal probability). It is a function to generate the “perhaps auxiliary collision probability state”. Under this auxiliary hit probability change state, the auxiliary hit is more likely to be generated since the auxiliary hit lottery probability is in a high probability state, and the common power release game occurs frequently, and the movable wing per unit time than the normal game state It will be in the operating rate improvement state which the operating rate of piece 42b improves.

  In addition, the pachinko gaming machine 1 of the present embodiment is provided with a “variation time shortening (hereinafter referred to as“ time reduction ”) function” in which the main control unit 50 takes on its functional unit. There are two types of time-saving functions (hereinafter referred to as "special-design time-shorting functions") related to special symbols and time-shorting functions (hereinafter referred to as "normal-pattern time-shorting functions") related to ordinary designs.

The special symbol time-shortening function is the "special symbol," which has reduced the average time required for one special symbol variation display game (the time for a certain symbol to be displayed after the special symbol starts to change, that is, the variation time for the special symbol). It is a function to generate a time saving state. Under the special symbol time short state, the average fluctuation time of the special symbol in one special symbol fluctuation display game is shortened, and the lottery number improving state in which the jackpot number per unit time is improved more than the normal gaming state.
In pachinko gaming machine 1, the variation display time of the special symbol may be shortened due to the difference in the number of reservations, but in this case, the special symbol time reduction state is not generated, but it is by other control processing It is a thing.

  The normal symbol time-shortening function is the “normal symbol, with the average time required for one normal symbol variation display game (the time from when the normal symbol starts to change until the final display is made, that is, the normal symbol variation time). It is a function to generate a time saving state. Under normal symbol time short state, average fluctuation time of normal symbol in one normal symbol fluctuation display game is shortened, and the lottery number is improved, in which the number of lottery per auxiliary time is improved more than the normal gaming state. .

In addition, the pachinko gaming machine 1 of the present embodiment is provided with an “open extension function” in which the main control unit 50 takes on its functional unit.
The open extension function is a function to generate an “open extension state” in which the movable wing piece 42b is opened and the open frequency thereof is extended. This open extension state is referred to as a so-called "electric chew support state". Under the open extension state, the open operation period (start opening opening state time) of the movable wing piece 42b is extended, for example, from 0.2 seconds to 1.7 seconds, and the number of times of opening and closing thereof is, for example, 1 to 2 times. The operation rate is improved, in which the operation rate of the movable wing piece 42b per unit time is improved compared to the normal gaming state.

By activating one or more types of each function as described above, it is possible to change the internal gaming state of the gaming machine.
Here, in this embodiment, the operation start conditions of the normal symbol probability variation function, the normal symbol time short function, and the open extension function are the same as the operation start conditions of the special symbol time short function, and each function operates with the same trigger It will be done.

[About hit]
In the pachinko gaming machine 1 of the present embodiment, “15R low base non-probability variation big hit”, “15R low base probability variation α” as a hit type to be drawn in the special symbol variation display game, that is, a hit type to be a big hit lottery target. There are several types of hits such as "big hit", "15R low base probability variation β big hit", "15R high base probability variation big hit", "2R low base probability variation big hit", and "small hit".

<4. Driver Configuration and LED for Presentation of First Embodiment>

Subsequently, a driver configuration according to the first embodiment will be described. Frame driver unit 61 (first system) to which light emission drive data and motor drive data are supplied as serial data by serial data transmission channels ch1, ch2 and ch3 of effect control unit 51 described above, board driver unit 62 (second system) , And a configuration of a motor driver 70 (third system).

The frame driver unit 61, the board driver unit 62 and the motor driver unit 70 connected to the effect control unit 51 are shown in FIG.
In the frame driver unit 61, which is the drive signal output unit of the first system, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the effect control CPU 200.
As a signal line of the serial data output channel ch1, a reset signal line for supplying a reset signal RESET, a clock line for supplying a clock signal CLK, and serial data DATA as light emission drive data (also referred to as "LED drive data") A data line and an enable signal line for supplying an enable signal ENABLE are provided. Each of these signal lines is connected so as to supply each signal in parallel to n LED drivers 90 that constitute the frame driver unit 61.
In each LED driver 90 of the frame driver unit 61, a device ID used as a slave address by the effect control CPU 200 is set. That is, it is an identifier of each LED driver 90. For convenience of explanation, the device ID (slave address) of each LED driver 90 is represented as w1 to w (n) as illustrated.

Further, in the panel driver unit 62, which is the drive signal output unit of the second system, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the effect control CPU 200.
The signal line of the serial data output channel ch2 is also the reset signal line for supplying the reset signal RESET, the clock line for supplying the clock signal CLK, the data line for supplying serial data DATA as light emission drive data, and the enable signal ENABLE And an enable signal line for supplying. Each of these signal lines is connected to supply m signals to the m LED drivers 90 constituting the panel driver 62 in parallel.
In each LED driver 90 of the board driver unit 62, a device ID (an identifier of each LED driver 90) used by the effect control CPU 200 as a slave address is set. For convenience of explanation, the device ID (slave address) of each LED driver 90 is denoted as b1 to b (m) as shown in the figure.

Further, in the motor driver unit 70 which is a drive signal output unit of the third system, p motor drivers 90M are connected in parallel to the serial data output channel ch3 of the effect control CPU 200.
Similarly, the signal line of the serial data output channel ch3 similarly supplies a reset signal line for supplying a reset signal RESET, a clock line for supplying a clock signal CLK, a data line for supplying serial data DATA as motor drive data, and an enable signal ENABLE. An enable signal line is provided. Each of these signal lines is connected so as to supply respective signals in parallel to p motor drivers 90M constituting the motor driver 70.
In each motor driver 90M of the motor driver unit 70, a device ID (identifier of each motor driver 90M) used by the effect control CPU 200 as a slave address is set. For convenience of explanation, the device ID (slave address) of each motor driver 90M will be described as mt1 to mt (p) as shown in the figure.

As each LED driver 90 in the frame driver unit 61 and the board driver unit 62, for example, “LV5236V (manufactured by Sanyo Semiconductor Co., Ltd.)” which is a 24-channel LED driver can be used, and has 24 current terminals. Therefore, one LED driver 90 can supply LED drive current for up to 24 series. Specifically, for example, eight series of R (red) LED drive current supply, eight series of G (green) LED drive current supply, eight series of B (blue) LED drive current supply, and light emission of eight full color LEDs It is possible to drive. Here, one “series” refers to one LED connected to one current terminal or a group of a plurality of LEDs connected in series or in parallel to one current terminal. There is.
The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of light emitting units 20 w). Therefore, n may be 1 or 2 or more. The frame driver unit 61 has one or more LED drivers 90.
The number m of the LED drivers 90 in the board driver unit 62 is determined by the number of LED series (number of series of light emitting units 20b, 20Z, 20H, and 20J) arranged on the board side. Therefore, m may be 1 or 2 or more. The board driver unit 62 has one or more LED drivers 90.

The schematic structural example of the principal part of the LED driver 90 is shown to FIG. 5A.
The LED driver 90 includes a serial bus interface 91, an address setting unit 92, a data buffer / PWM controller 93, a D / A converter 94, and drive current source circuits 95-1 to 95-24.
The drive current source circuits 95-1 to 95-24 are current sources that perform the 24 series of drive current outputs from the current terminals 96-1 to 96-24, respectively.

The enable signal ENABLE, the clock signal CLK, and the serial data DATA from the effect control CPU 200 are input to the LED driver 90 to the serial bus interface 91. The serial bus interface 91 takes in the serial data DATA at the timing of the clock signal CLK in a period defined by the enable signal ENABLE. The serial bus interface 91 converts the acquired serial data into parallel data and transfers the parallel data to the data buffer / PWM controller 93.
Although the format of the serial data will be described later with reference to FIG. 33, the effect control CPU 200 transmits the LED drive data by designating the slave address.
The data buffer / PWM controller 93 performs slave address confirmation for parallel data transferred from the serial bus interface 91. When it is confirmed that the slave address included in the parallel data matches the slave address (one of w1 to w (n) and b1 to b (m)) of its own set in the address setting unit 92. The LED drive data included in the parallel data is stored as valid data in a designated register.

When the data buffer / PWM controller 93 takes in the LED drive data of each series, the value corresponding to the luminance information (gradation value) indicated by the LED drive data is D / A as each drive control value of 24 series. It outputs to the converter 94.
The D / A converter 94 converts a value corresponding to the luminance information into an analog signal, and sets it as a control signal to each of the current source circuits 95-1 to 95-24.

The 24 series of LEDs 120 are connected to all (or part) of the current terminals 96-1 to 96-24. Although the figure shows a state in which one LED 120 is connected to one series of current terminals 96 in a simplified manner, a configuration in which a plurality of LEDs are connected to one series of current terminals 96 (for example, series connection) It is natural.
In each series (current terminals 96-1 to 96-24), the power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. The current source circuits 95-1 to 95-24 cause a current to flow to the LEDs 120 of each series to emit light.
That is, each of the current source circuits 95-1 to 95-24 operates so as to flow a drive current of an amount of current corresponding to the signal supplied from the D / A converter 94 to the LED 120 of the corresponding series.

Specifically speaking of such LED drive control for one series, the data buffer / PWM controller 93 converts a digital data series corresponding to a pulse duty according to the gradation value of the series into a D / A converter 94. The D / A converter 94 converts the digital data train into a pulse signal as an analog signal and supplies the pulse signal to the current source circuit 95 of the series. The current source circuit 95 is output controlled by the H / L of the pulse signal, and performs, for example, current output of 0 mA and 5 mA. For example, in such an operation, a drive current that results in an average current value corresponding to the gradation value flows to the LED 120.
In the present embodiment, although the current values are set to, for example, 0 mA and 5 mA by the PWM driving method and gradation control is performed (integrally) in the time axis direction, it goes without saying that gradation control is It is needless to say that the current value may actually be changed in accordance with the gradation, without limitation. Whether it is duty control or level control, the average current value per unit time is made to be a level according to the gray level, so that appropriate gray level expression becomes possible.

The motor driver 90M in the motor driver 70 may have the same configuration as the LED driver 90. For example, "LV5236V (manufactured by Sanyo Semiconductor Co., Ltd.)" can also be used.
The number p of motor drivers 90M in the motor driver 70 is determined by the number of motors of the movable object. Therefore, p may be 1 or 2 or more. The motor driver 70 has one or more motor drivers 90M.

The motor driver 90 </ b> M is connected to a movable body-effect product motor 65 that drives the movable body-effect object.
FIG. 5B shows an example in which, for example, a stepping motor 121 as a movable object function motor 65 is connected to all (or a part) of current terminals 96-1 to 96-24 of a certain motor driver 90M. Although FIG. 5B shows only the portions of the current terminals 96-1 to 96-24, the internal configuration of the motor driver 90M is the same as that of FIG. 5A.
Here, drive current is supplied to the four-phase stepping motor 121 by current terminals 96-1 to 96-4, current terminals 96-5 to 96-8,..., Current terminals 96-21 to 96-24. Shows an exemplary configuration.
The driver of the configuration shown in FIG. 5A is a circuit that outputs a current instructed by a given command (serial data) from current terminals 96-1 to 96-24. It can also be used as a motor driver 90M for a physical movable body drive device such as a solenoid.
The operation of the movable body part is finely set according to the rendering scenario, and accordingly the presentation control unit 51 controls the driving direction, the driving amount, etc. However, the movable body using the motor driver 90M in the motor driver unit 70 By driving the goods, the movable body part control by serial data becomes possible together with each light emitting part (LED 20b) of the lamp part 64, and the control processing and configuration can be made efficient.

  In one LED driver 90, a part of current terminals may be used for LED driving, and another part of current terminals may be used for driving a stepping motor, a solenoid, or the like.

As described above, according to the serial data DATA received from the effect control CPU 200, the LED driver 90 drives each of the LEDs 120 to emit light at the designated luminance. The motor driver 90M drives the stepping motor 121 according to the serial data DATA.
Then, drive signals are outputted to one or a plurality of effect means, respectively, to drive signal output means (frame driver unit 61, board driver unit 62, motor driver unit 70) of the first system, second system and third system. A plurality of LED drivers 90 or motor drivers 90M are included, and serial data from the effect control unit 51 is transmitted in parallel to each of the LED drivers 90 and the motor driver 90M in one system. Then, each LED driver 90 or motor driver 90M acquires drive data (serial data) including its own ID (slave address).
As will be described later, in the present embodiment, the effect control unit 51 (effect control CPU 200) controls the serial data of one transmission unit in the first system and the second system as drive signal output means (frame driver unit 61). The serial data of the next transmission unit after the transmission to the frame driver unit 61 and the panel driver unit 62 of the serial data of the transmission unit is output substantially simultaneously. Transmission processing for substantially simultaneously outputting to the driver unit 61 and the board driver unit 62 is performed.

In the present embodiment, the board driver unit 62 is configured to perform LED light emission drive for the light emission units 20Z, 20H, and 20J for situation presentation in addition to LED light emission drive for the light emission unit 20b for effect.
FIG. 6 shows an example of the light emitting operation of the light emitting units 20Z, 20H and 20J for situation presentation.

FIG. 6A shows an example of the light emission operation of the variable symbol identification light emission unit 20Z. Three light emitting units 20Z-1, 20Z-2, and 20Z-3 are provided as the variable symbol identification light emitting unit 20Z. Each of the light emitting units 20Z-1, 20Z-2, and 20Z-3 performs a light emitting operation representing a variation state corresponding to each of the first special symbol, the second special symbol, and the normal symbol.
For example, while "flashing" is fluctuating, "lighting" is stopping (hit) and "lighting off" is a light emission mode for identifying stopping (off).
Therefore, when the first special symbol, the second special symbol, and the normal symbol are not varied at all, the light emitting units 20Z-1, 20Z-2, and 20Z-3 are all turned off.
When the variation of the first special symbol is started, the flashing of the light emitting unit 20Z-1 is started, and when the result of the variation is the winning, the light emitting unit 20Z-1 is turned on.
Further, when the variation of the second special symbol is started, the flashing of the light emitting unit 20Z-2 is started, and when the result of the variation is the winning, the light emitting unit 20Z-2 is turned on.
In addition, when fluctuation of the normal symbol is started, blinking of the light emitting unit 20Z-3 is started, and when the result of the fluctuation becomes a hit, the light emitting unit 20Z-3 is turned on.

FIG. 6B shows an example of the light emission operation of the hold number display separate light emitting unit 20H. Eight light emitting units 20H-1 to 20H-8 are provided as the holding number display light emitting units 20H.
The number of reservations (maximum four) for the first special symbol variation display game is displayed with four of the light emitting units 20H-1 to 20H-4. That is, among the light emitting units 20H-1 to 20H-4, the light emitting units 20H of the number according to the number of holdings are lighted.
The number of reservations (maximum four) for the second special symbol variation display game is displayed with four of the light emitting units 20H-5 to 20H-8. That is, of the light emitting units 20H-5 to 20H-8, the light emitting units 20H of the number according to the number of holdings are turned on.

FIG. 6C is another example of the hold number display separate light emitting unit 20H. In this example, four light emitting units 20H-11 to 20H-14 are provided, and two light emitting units 20H-11 and 20H-12 display the number of reservations for the first special symbol variation display game, and the light emitting units The number of reservations for the second special symbol variation display game is displayed by 20H-13 and 20H-14.
For example, the number of reservations of “0” to “4” by the two light emitting units 20H is displayed as follows.
· 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · blink

FIG. 6D shows an example of the light emitting operation of the gaming state notification light emitting unit 20J. As the gaming state notification light emitting unit 20J, for example, three light emitting units 20J-1, 20J-2, and 20J-3 are provided according to the gaming state of "big hit", "certain change", and "time reduction".
During the jackpot, the light emitting unit 20J-1 lights up.
The light emitting unit 20J-2 lights up during a definite change.
During the short time, the light emitting unit 20J-2 lights up.
This is an example, and in the case of providing another gaming state to be notified, the number of gaming state notification light emitting units 20J may be changed as appropriate.
When there are a plurality of types of hits, a plurality of game state notification light emitting units 20J may be provided to correspond to the types of hits.

The light emitting units 20Z, 20H, and 20J for situation presentation are driven to emit light, for example, by the LED driver 90 in the board driver unit 62.
FIG. 7 shows an example in which the symbol identification light emitting unit 20Z and the number-of-holds display light emitting unit 20H are connected to the LED driver 90 whose slave address is "b2". The LED driver 90 is also connected to the effect light emitting unit 20b.

Connected to the current terminals 96-1 to 96-8 of the LED driver 90 are eight LEDs 120 corresponding to the above-described light emitting units 20H-1 to 20H-8 as the light emitting units 20H for holding number display one by one. It is done.
For example, an LED 120 functioning as a light emitting unit 20H-1 and a resistor R are connected in series to the current terminal 96-1, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, an LED 120 functioning as a light emitting unit 20H-2 and a resistor R are connected in series to the current terminal 96-2, and the other end of the resistor R is connected to the first power supply voltage VCC1.
Similarly, one LED 120 functioning as the light emitting unit 20H-3 to 20H-8 and the resistor R are connected in series to each of the current terminals 96-3 to 93-8 in the same manner, and are connected to the first power supply voltage VCC1.

In addition, in the current terminals 96-9 to 96-11 of the LED driver 90, three LEDs 120 corresponding to the light emitting units 20Z-1 to 20Z-3 as the symbol identifying light emitting unit 20Z are provided one by one. It is connected.
For example, the LED 120 functioning as the light emitting unit 20Z-1 is connected in series to the current terminal 96-9, and the resistor R is connected in series, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, an LED 120 functioning as a light emitting unit 20Z-2 and a resistor R are connected in series to the current terminal 96-10, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20Z-3 and the resistor R are connected in series to the current terminal 96-11, and the other end of the resistor R is connected to the first power supply voltage VCC1.

Further, to the current terminals 96-12 to 96-20 of the LED driver 90, the LED 120 functioning as the effect light emitting unit 20b is connected.
For example, three LEDs 120 and a resistor R are connected in series to the current terminals 96-12 to 96-17, respectively, and the other end of the resistor R is connected to the second power supply voltage VCC2.
Two LEDs 120 and a resistor R are connected in series to the current terminals 96-18 to 96-20, respectively, and the other end of the resistor R is connected to the second power supply voltage VCC2.
In this example, the current terminals 96-21 to 96-24 are not used.

As the operating power supply voltage of the LED driver 90, the first power supply voltage VCC1 (for example, 5 V) is used.
As described above, the situation presentation light emitting unit (20Z, 20H) and the effect light emitting unit 20b are mixedly connected to the LED driver 90 of the slave address "b2".
The serial data DATA transmitted from the effect control unit 51 to the LED driver 90 includes, in addition to light emission drive data for light emission effect, light emission drive data for symbol identification, and display of the number of reservations. The light emission drive data is included. Thus, the LED driver 90 drives the light emission of the LED 120 connected to the current terminals 96-12 to 96-20 based on the light emission drive data for light emission effect, and based on the light emission drive data for symbol identification. The LED 120 connected to the current terminals 96-9 to 96-11 is driven to emit light, and the LED 120 connected to the current terminals 96-1 to 96-8 is driven to emit light based on the light emission drive data for displaying the number of reservations. .

Here, since the LED driver 90 is driven at a relatively low voltage (for example, 5 V), the first power supply voltage VCC1 is prepared. On the other hand, although the light emission drive current is made to flow using the second power supply voltage (12 V) for the effect light emitting unit 20b, this is because the effect light emitting unit 20b has many series connection of a plurality of LEDs according to the request for decoration. Therefore, a relatively high voltage (for example, 12 V) is required as a power supply of the drive current.
For this reason, power supply lines of first and second power supply voltages VCC1 and VCC2 are prepared as peripheral circuits of the LED driver 90 for driving the effect light emitting unit 20b.

Considering the symbol identification light emitting unit 20Z and the number-of-holds display light emitting unit 20H, light emission for one presentation can be realized by one LED 120. As described above, when one LED is connected to each of the current terminals 96-1 to 96-11, each of the light emitting units 20H-1 to 20H-8 as the light emitting unit 20H for holding number display and for symbol identification The light emitting units 20Z-1 to 20Z-3 can sufficiently function as the light emitting units 20Z.
Then, 12V is not necessary as a power source for light emission drive of symbol identification light emitting unit 20Z and light emitting unit 20H for holding number display, but if it is driven with 12V, a large resistance value is required as resistance R, and heat is generated. It will
Although it is conceivable to prepare another power supply (third power supply voltage) as a measure for this heat, this would complicate the peripheral circuit of the LED driver 90.

Therefore, in the present embodiment, the first power supply voltage VCC1 used by the LED driver 90 as a power supply is used as a power supply for light emission drive of the symbol identification light emitting unit 20Z and the number-of-holds display light emitting unit 20H. .
By doing this, it is not necessary to arrange a large resistance value as the resistor R connected to the LED for symbol identification light emitting unit 20Z and the number-of-holds display light emitting unit 20H, and it becomes appropriate as a heat countermeasure.
Furthermore, since the third power supply voltage is not introduced, the peripheral circuits of the LED driver 90 are not complicated.

The LED driver 90 with the slave address "b2" drives the symbol identification light emitting unit 20Z and the number-of-holds display light emitting unit 20H in addition to the effect light emitting unit 20b, for example, the slave address "b3" The LED driver 90 drives the game state notification light emitting unit 20J in addition to the effect light emitting unit 20b.
Although illustration is omitted, the three LED drivers 90 correspond to the current terminals 96-1 to 96-3 and the light emitting units 20J-1 to 20J-3 as the game state notifying light emitting unit 20J. The LEDs 120 are connected one by one.
That is, the LED 120 functioning as the light emitting unit 20J-1 and the resistor R are connected in series to the current terminal 96-1, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, an LED 120 functioning as a light emitting unit 20J-2 and a resistor R are connected in series to the current terminal 96-2, and the other end of the resistor R is connected to the first power supply voltage VCC1.
For example, the LED 120 functioning as the light emitting unit 20J-3 and the resistor R are connected in series to the current terminal 96-31, and the other end of the resistor R is connected to the first power supply voltage VCC1.
Further, all or a part of the current terminal 96-4～96-24 the LED driver 90 in the slave address "b3", a plurality of LED120 and the resistor R which functions as their respective Starring exits light emitting portion 20b in series It is connected and driven by the second power supply voltage VCC2.
By doing this, the heat countermeasure and the complication prevention of the peripheral circuit are achieved also for the LED driver 90 of the slave address “b3”.

In the serial data DATA transmitted from the effect control unit 51 to the LED driver 90 with the slave address “b3”, light emission drive data for notifying the gaming state is added to the light emission drive data for light emission effect. It is intended to be included. Thus, the LED driver 90 drives the light emission of the LEDs 120 connected to the current terminals 96-4 and later based on the light emission drive data for light emission effect, and the current terminals based on the light emission drive data for notifying the gaming state. The LEDs 120 connected to the 96-1 to 96-3 are driven to emit light.

<5. Processing of main control section>

The control process of the present embodiment will be described below. First, main processing by the main control unit (main control board) 50 will be described here.
FIG. 8 is a flowchart showing main processing of the main control unit 50. The main process starts when the power is turned on without operating the initialization switch (not shown) as when recovering from a power failure state, or when the initialization switch is turned on. May be turned on. In any case, when the pachinko gaming machine 1 is powered on, the power supply board 58 supplies a voltage to each control board. In this case, the main control unit 50 (main control CPU 100) starts main processing shown in FIG.

In the main control side main processing, in step S11, the main control CPU 100 first executes necessary initialization processing before the start of the game operation. For example, first, oneself is set to the interrupt disabled state, and is set to a predetermined interrupt mode (interrupt mode 2), and the register values in the CPU including the respective units of the microcomputer are initialized.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of the RAM clear signal which is the output signal of the RAM clear switch input through the input port (not shown). The RAM clear signal is a signal for determining whether to initialize the entire area of the RAM. The RAM clear signal usually has a value corresponding to the ON / OFF state of the initialization switch operated by the clerk of the pachinko parlor.

If the RAM clear signal is in the ON state, the main control CPU 100 advances the process from step S12 to step S16 to perform zero clear of the entire area of the RAM. Therefore, the value of the backup flag set at the time of power-off becomes zero along with other checksum values and the like.
Subsequently, at step S17, the main control CPU 100 transmits a "RAM clear display command" for notifying that the RAM area is zero cleared to each control board as an initialization command. Then, in step S18, for example, 30 seconds is stored in the RAM clear notification timer as a time for notifying that the RAM is cleared.

Next, in step S19, the main control CPU 100 initializes CTC, which outputs an interrupt signal for activating a timer interrupt operation, and sets the CPU to an interrupt enabled state.
Thereafter, in the processes of steps S20, S21, and S22, the interrupt disabled state and the interrupt enabled state are repeated until an interrupt occurs, while various random number updating processes are executed. In the random number updating process of step S21, random numbers used to change initial values (start values) of various random numbers used for special symbol variation display and normal symbol variation display, and variations used for selecting a variation pattern Update pattern random numbers.
The various random numbers used for the special symbol variation display and the normal symbol variation display are, for example, random numbers related to a big hit lottery circulating a predetermined numerical range by increment processing (random symbol judgment random numbers used for symbol lottery) Or, it is a random number (an auxiliary hit judgment random number used for a winning lottery of an auxiliary hit) or the like pertaining to the auxiliary hit lottery. The random numbers used for changing the initial value are an initial value random number for special symbol determination, an initial value random number for supplementary hit determination, and the like.

The main control RAM 102 is a random number counter for special symbol determination random number counter used as a random number counter used for symbol lottery, auxiliary hit lottery, fluctuation pattern lottery, etc. There are provided a counter for generation of an initial value of an auxiliary collision judgment random number counter, a random number counter for auxiliary collision judgment, a fluctuation pattern random number 1 counter, a fluctuation pattern random number 2 counter, and the like. These counters function as random number generation means for generating random numbers in software.
In the various random number update processing of step S21, two initial value generation counters for generating initial values of the above-mentioned special symbol determination random number counter and the auxiliary hit determination random number counter, variation pattern random number 1 counter, variation pattern random number 2 The counters and the like are updated to generate the various soft random numbers. For example, assuming that the numerical value range that can be taken as the fluctuation pattern random number 1 counter is 0 to 238, the value is acquired from the count value storage area for generating the value of the fluctuation pattern random number 1 of the main control RAM 102, and the acquired value is 1 Are stored in the original count value storage area. At this time, if the result of adding 1 to the obtained value is 239, 0 is stored in the original random number counter storage area. The other initial value generation random number counters are similarly updated. The main control CPU 100 is configured to repeatedly execute various random number update processes except during the timer interrupt process which is intermittently executed.

The above has described the case where it is determined in step S12 that the RAM clear switch is ON. The case of the RAM clear switch OFF will be described subsequently. For example, at the time of recovery from a power failure state, the initialization switch (RAM clear signal) is in the OFF state. In such a case, the main control CPU 100 proceeds from step S12 to step S13 to determine a backup flag value. The backup flag is set to the ON state when the power is shut off, and is reset to the OFF state in the first timer interrupt process after the power is restored.
Therefore, when the power is turned on or the power is restored, the backup flag should normally be in the ON state. However, the backup flag is reset (OFF) when the predetermined processing is not completed before power-off for some reason. Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from step S13 to S16, and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from step S13 to step S14, and executes the checksum operation for calculating the checksum value. Here, the checksum operation is an 8-bit addition operation that targets the work area of the main control RAM 102.
Then, when the checksum value is calculated, the calculation result is compared with the stored value of the SUM address of the main control RAM 102. At the SUM address, a checksum value obtained by the same checksum operation is stored when the power is shut off. Then, the stored calculation results are maintained by the backup power source, along with other data of the main control RAM 102. Therefore, originally, both should match each other by the determination of step S14.
However, if the checksum operation can not be executed when the power is shut off, or if it can be executed, the data of the work area may be damaged until the execution of the checksum operation of the main process. In such a case, the determination result of step S14 does not match.
If data corruption is detected due to the non-coincidence of the determination result, the main control CPU 100 proceeds from step S14 to step S16 to execute the RAM clear process, and returns the operating state of the gaming machine to the initial state.

If the checksum value by the checksum operation in step S14 matches the storage value of the SUM address, the main control CPU 100 proceeds to step S15 and restores the stack pointer before the power is cut off based on the backup data, The game recovery processing necessary to start the game from the processing state at the time of power shutoff is executed.
When the game recovery process in step S15 is completed, the process proceeds to step S19, in which CTC is initialized to set the CPU to the interrupt enabled state, and thereafter, the interrupt disabled state and the interrupt enabled state until the interrupt occurs. While repeating the various random number updating processes described above (steps S20 to S22).

  Next, timer interrupt processing of the main control CPU 100 will be described. FIG. 9 shows timer interrupt processing of the main control CPU 100. The main control timer interrupt process is activated by an interrupt from CTC at predetermined time intervals (about 4 ms), and is executed while the main process described above is being executed.

  When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and then performs a power supply abnormality check process of monitoring the supply state of the power from the power supply substrate 58 in step S51 of FIG. In this power supply abnormality check process, it is mainly monitored whether the power supply is normally supplied. Here, for example, when an abnormality such as a power failure occurs, a backup process of storing predetermined game information at the time of power failure in the RAM is performed so that the game can be restored without any trouble at the time of power recovery.

  Next, in step S52, the main control CPU 100 performs timer management processing for managing a timer used for game operation control. The timer values of various timers (for example, special symbol role thing operation timer etc.) used for the game operation control of the pachinko gaming machine 1 are managed (updated) by this process.

In step S53, the main control CPU 100 performs an input management process. In this input management process, detection information by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. Information detected by the various sensors here is, for example, the upper starting opening sensor 71, the lower starting opening sensor 72, the gate sensor (normal symbol starting opening sensor) 73, the first large winning opening sensor 75, the second large winning opening sensor They are ON / OFF information (winning detection information) of a switch signal output from a winning detection switch such as the general winning opening sensor 74 or the like.
Through the process of step S53, whether or not a winning is detected (a winning is generated) at each winning opening is monitored at every interruption. The "winning counter" is a counter provided corresponding to each winning opening and counting the number of winning game balls (number of winning balls). In the present embodiment, the upper start opening winning counter for the upper starting opening 41, the lower starting opening winning counter for the lower starting opening 42a, the normal symbol starting opening winning counter for the gate 44, The first large winning opening winning counter for 1 large winning opening 45a, the second large winning opening winning counter for second large winning opening 46a, the winning counter for general winning opening for general winning opening 43, etc. are provided .
Further, in this input management process, it is also monitored whether or not there is an unfair prize based on whether or not the detection information from the prize detection switch has won during a period in which the prize should be permitted. For example, when the first and second big winning opening sensors 75 and 76 detect a game ball despite not being a big hit game, this is regarded as an incorrect winning and the winning detection information is invalidated and invalidated. In order to notify the effect to the outside, predetermined error processing is performed in the error management processing of step S55 described later.

  In step S54, the main control CPU 100 performs a timer interruption random number management process of periodically updating the random number related to each variable display. In this regular random number update process, the special symbol determination random number and the auxiliary hit determination random number are updated (+1 is added for each interrupt), and the process of changing the start value of the random number counter is performed each time the random number counter makes one revolution. For example, the value of the special symbol determination random number counter is updated (+1 added) within a predetermined range, and the value of the generation counter for the special symbol determination random number counter initial value is read out each time the special symbol determination random number counter makes one revolution. The value of the generation counter is stored in the special symbol determination random number counter. Since the start value of the special symbol determination random number counter is changed according to the value of the generation counter, the count value of the special symbol determination random number counter becomes random although the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process to monitor the presence or absence of an abnormality in the gaming operation state. In this error management process, these abnormal operations (errors) occurred, for example, by monitoring whether there was a break between the boards or monitoring whether there was an incorrect prize, as an abnormality in the gaming operation state. In this case, predetermined error processing corresponding to the error is performed.
As the error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation, a game ball launch operation, etc.) is stopped, or an error notification command is transmitted to the effect control unit 51, Or a notification that a problem has occurred.

In step S56, the main control CPU 100 performs a winning ball management process. In this prize ball management process, the data stored in the input management process in step S53 is grasped, and the above-mentioned winning counter is confirmed. Transmit to substrate 53.
The payout control board 53 that has received this payout control command controls the gaming ball payout device 55 to cause the designated balls to be paid out. Thereby, the number of winning balls corresponding to each winning opening is paid out. The number of winning balls corresponding to the winning opening is the predetermined number of winning balls per winning ball set for each winning opening × number of winning balls corresponding to the value of the winning counter.

  At step S57, the main control CPU 100 performs normal symbol management processing. In this normal symbol management process, a lottery for assistance in normal symbol variation display is performed, and based on the result of the lottery, the variation pattern of the normal symbol or the stop display mode of the normal symbol is determined, or the blinking is repeated every predetermined time Create data of symbol (data for LED blinking display during normal symbol fluctuation) or data for stop display (data for LED blinking display during normal symbol stop display) unless normal symbol is changing To

In step S58, the main control CPU 100 performs ordinary electric role management processing. In this ordinary electric role management process, generation of an excitation signal for solenoid control for the ordinary electric role solenoid 77 and its data (solenoid control data) based on the drawing result of the drawing per drawing of the regular symbol management process of step S57. Make settings. Based on the data set here, an excitation signal is output to the normal motorized combination solenoid 77 in a solenoid management process of step S64 described later, whereby the operation of the movable wing piece 42b is controlled.
In step S59, the main control CPU 100 performs special symbol management processing. In this special symbol management process, a big hit lottery in the special symbol variation display is mainly performed, and based on the lottery result, the variation pattern of the special symbol (look-ahead variation pattern, variation pattern at the start of variation) or the special stop symbol etc. decide.
In step S60, the main control CPU 100 performs a special electric role management process. In this special electric role management process, when the big hit lottery result is "big hit" or "small hit", the setting process necessary to control execution of the hit game corresponding to that hit is performed.

In step S61, the main control CPU 100 performs right-handed notification information management processing. In this right-handed notification information management process, for example, a right-handed instruction in a situation where right-handed driving is advantageous, such as an opportunity for opening the first and second big winning openings 45a and 46a and an electric support state where the movable wing piece 42b is driven. A process is performed to cause "launch position guidance effect (right-handed notification effect)" to be notified. The right-handed instruction is, specifically, an effect operation for instructing a technician to aim at the right gaming area 3c, and for example, the liquid crystal display device 32 displays an image prompting the player to "right-handed" , Speaker 25 generates a right-handed message sound.
When the right-handed notification effect is performed, in the right-handed notification information management process, a “right-handed command” instructing execution of the right-handed notification effect is transmitted to the effect control unit 51 as an effect control command, and this command is received Then, the effect control unit 51 performs execution control of right-handed notification by image and sound.
In step S62, the main control CPU 100 performs LED management processing. The LED management process is a process of outputting display data for normal symbol display and first and second special symbol displays to the symbol display section 33. By this processing, variable display and stop display of a normal symbol and a special symbol are performed. In addition, the display data of the normal symbol created in the normal symbol management process of step S57, and the display data of the special symbol created in the special symbol display data update process during the special symbol management process of step S59 are the LED management process Output.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operating state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. The operation status information indicates that a big hit game has occurred (the condition device has been activated), a small hit game has occurred, and a symbol variation display has been executed (a special symbol variation display game has been started or ended) , And information such as winning information (indicating that a starting opening or a large winning opening has been won or winning ball number information) is included.
In step S64, the main control CPU 100 performs a solenoid management process. In this solenoid management processing, output processing of the excitation signal to the common motorized combination solenoid 77 based on the solenoid control data generated in the common motorized combination management processing in step S58, and in the special motorized combination management processing in step S60 The output processing of the excitation signal to the first and second big winning opening solenoids 78 and 79 is performed based on the solenoid control data. As a result, the movable wing piece 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start opening 42a and the special winning opening 45a and 46b are opened and closed.

  After completing the above-described processes of steps S51 to S64, the main control CPU 100 restores the contents of the saved register and sets the interrupt enabled state in step S65. As a result, the timer interrupt process is terminated, and the process returns to the main control side main process of FIG. 6 before the interrupt, and the main control main process is performed until the next timer interrupt occurs.

Next, the special symbol management process of step S59 of FIG. 9 will be described. FIG. 10 is a flow chart showing the details of the special symbol management process of step S59.
In FIG. 10, the main control CPU 100 first performs first special view starting opening check processing on the first special symbol side (upper starting opening 41 side) in step S71, and then the second special symbol side (lower starting opening) in step S72. The second special view start opening check process is performed on the side 42a).

  Next, in step S73, the main control CPU 100 determines the state of the small hit middle flag. The small hit flag is a flag for specifying whether or not the small hit game is in progress. When the flag is in the ON state, it indicates that the small hit game is in progress, and the flag is in the OFF state. If it is, it indicates that the small hit game is not in progress.

  If the small hit middle flag is in the OFF state, the main control CPU 100 determines the state of the condition device activation flag in step S74. The condition device operation flag is a flag for designating whether or not a big hit game is in progress, and when the flag is in the ON state, it indicates that a big hit game is in progress, and when the flag is in the off state, Indicates that the jackpot is not in progress.

If the condition device operation flag is in the OFF state, the main control CPU 100 branches the process to perform the process according to the process state indicating the behavior of the special symbol in step S75.
That is, when the processing proceeds to step S75 because it is neither in the small hit game nor in the big hit game, the special symbol is put under the variable state, whereby the special symbol operation status is "standby", "during", "confirming" Depending on which state of, the process regarding the variable display operation of the special symbol corresponding to each is performed.
On the other hand, when a small hit game or a big hit game is being played, the special symbol is not placed under the variable state, and therefore the process proceeds to step S79 without performing processing relating to the variable display operation of the special symbol.
Here, the above-mentioned "standby" indicates that the behavior of the special symbol is in the standby state for the next change, and "under the change" indicates that the behavior of the special symbol is changing (variation display). Indicates that “under confirmation” indicates that the variation of the special symbol has ended and the display is stopped (fixed) (during the special symbol confirmation time).

  Specifically, when the special symbol operation status is "standby", the process proceeds from step S75 to S76, and when the special symbol variation start process is "changing", the process proceeds from step S75 to S77. If the special symbol variation processing is "under confirmation", the process proceeds from step S75 to S78 to perform processing during the special symbol confirmation time. By these processes, as a special symbol variation display game, a variation display operation in which the variation start and the variation stop of the special symbol are set is realized.

  In step S79, the main control CPU 100 performs special symbol display data update processing. In this special symbol display data update process, it is determined whether or not the special symbol is in change, and if it is in change, data of the special symbol that repeats blinking every predetermined time (for example, 0.5 seconds) is created If the special symbol is not changing, create data for stop display. The display data of the special symbol created here is output in the LED management process (step S62) of FIG.

Subsequently, the first special drawing start port check process of step S71 described above will be described.
FIG. 11 is a flow chart showing the details of the first special view starting opening check process of step S71. The first special view starting opening check processing plays a role as a winning processing performed based on the establishment of a predetermined starting condition, and the winning check processing for the upper starting opening 41 according to the first special symbol variation display game is To be done.

The main control CPU 100 first determines at step S71 whether or not a winning (a winning ball) has been detected at the upper starting opening 41. When the winning of the upper starting opening 41 is detected, it is determined in step S82 whether or not the number of holding balls of the first special symbol is four or more. That is, it is determined whether the number of holding balls of the first special symbol (hereinafter referred to as "first special view holding ball") is less than the maximum number of holding memories (here, the upper limit is four).
When the winning of the upper starting opening 41 is not detected in step S81, nothing is done and the first special view starting opening checking process is exited.

If the number of first special image holding balls is four or more, the process proceeds to step S95. On the other hand, when the number of holding balls is less than 4, the number of holding balls is incremented by one (+1) in step S83.
Next, in step S84, various random numbers used for the first special symbol variation display game based on the first special figure reservation ball (random number for big hit determination, random number for special symbol determination, random number 1 for variation pattern, and variation pattern The current value of the random number counter of the random number 2) is acquired and stored in the pending storage area of the main control RAM 102, respectively. In the reserve storage area, the above-mentioned various random number values (predetermined game information relating to symbol game) are retained as reserve data, and a predetermined number of memories are set as an upper limit until being subjected to the variable display operation of the first special symbol. It is reserved and stored in the order of establishment of starting conditions (in order of winning, in this embodiment, the number of first special figure reserved balls, which is the maximum number of reserved storages, is less than 4).
In the holding storage area of the main control RAM 102, a holding storage area corresponding to the first special symbol and the second special symbol is provided, and it is possible to store holding data for the number of holding balls.

The special symbol determination random number, the variation pattern random number 1 and the variation pattern random number 2 are extracted from the corresponding random number counters. These random number values are updated in a random manner in the main processing executed between the interrupt processing that occurs intermittently and the interrupt processing in the count value storage areas corresponding to the respective ones provided in the main control RAM 102. The value is obtained as it is. On the other hand, the jackpot determination random number value is extracted from a random number generation circuit (a jackpot determination random number counter: not shown) that generates a random number in hardware. The random number generation circuit is a counter that counts a jackpot determination random number value. The random number generation circuit latches the count value at this timing when the detection signal of the gaming ball is input from the upper start opening sensor 71 or the lower start opening sensor 72, and the latched value is stored in the register incorporated in the random number generation circuit. It is stored and the count value is input to the microcomputer. The main control CPU 100 stores the count value as a jackpot determination random number value in a predetermined storage area (a special motorized product operation determination random number latch buffer) provided separately from the storage storage area of the main control RAM 102 The big hit judgment random number value stored from the random number latch buffer for the special motorized product activation determination is read out and used at a proper timing.
In the present embodiment, the random number value for big hit determination at the time of winning is stored in the special electric combination product operation determination random number latch buffer and the corresponding storage area, but the special electric combination product operation determination random number latch When a buffer is not provided, it may be stored as it is in the pending storage area, and the jackpot determination random number value for the relevant pending storage area may be read out at the necessary timing.

  Next, in step S86, as the prize command data for creating the hold addition command, the prefetch prohibition data for prohibiting the prefetch judgment is acquired, and the first special symbol forgery discrimination is prohibited. It is determined whether or not The first special view pre-reading prohibition condition is a condition which prohibits the pre-reading advance notice on the first special symbol, that is, the pre-reading advance notice for the first special view holding ball. In the present embodiment, it is a condition that the game state is either a short time state or a definite change state A to C is a prohibition condition, and if any of these game states, the advance notice regarding the first special symbol is prohibited (preread Make advance notice lottery itself).

If the first special view prefetch prohibition condition is satisfied, the process proceeds to step S95.
If the first special view prefetch prohibition condition is not satisfied, the process proceeds to step S87, the first special drawing hit random number determination table is acquired, and in step S88 the main control RAM 102 The random number value for big hit determination stored in (1) is acquired, and the random number determination process of step S89 is performed.
In the random number determination process, a "lottery lottery" relating to the special symbol variation display game (here, the first special symbol variation display game) is performed using the random number value for big hit determination.

Next, at step S90, the main control CPU 100 acquires a first special drawing symbol table selection table, and at step S91 acquires a special symbol determination random number value stored in the main control RAM 102, and at step S92 a special stop symbol. Perform data creation processing.
In the special stop symbol data creation process, the symbol lottery relating to the special symbol variation display game (here, the first special symbol variation display game) is performed using the winning lottery result of the random number determination processing and the random value for the special symbol determination. Do.

In step S93, the main control CPU 100 performs random number determination processing at start opening winning. In this starting opening winning combination random number determination process, based on the data (the special symbol determination data and the variation pattern selection offset) obtained in the stop symbol data creation process of step S92, winning command data used to create the hold addition command (2nd byte (EVENT): lower byte) is acquired. In step S94, winning command data (lower byte (EVENT)) is created, and in step S95, pending addition command based on the number of balls for holding (upper byte (MODE)) Are generated and transmitted to the effect control unit 51 in step S96.
As a result, the first special view start opening check processing is exited, and the second special symbol start opening check processing in step S72 of FIG. 10 is performed. The second special symbol starting opening check process is substantially the same as that of FIG. 11 with respect to the second special symbol, so detailed description will be omitted.

So far, the main process, timer interrupt process, and special symbol management process of the main control unit 50 (main control CPU 100) have been described, but the main control unit 50 sequentially transmits necessary commands to the effect control unit 51.
As an example of the command, FIG. 12A shows a part of the fluctuation pattern command and the command at the time of winning according to the winning lot of the special symbol fluctuation display game, and FIG. 12B shows a part of the symbol designation command.
In the variation pattern command and the winning command, the type of variation pattern is defined by the upper byte and the lower byte, and the upper byte is configured to be different according to the deviation / hit.
In the symbol designation command, the first and second special symbols are shown in the upper byte, and the type of the hit is specified in the lower byte.

<6. Process of production control section>
[6-1: Main processing]

Subsequently, the process of the effect control unit 51 will be described. The processing of the effect control unit 51 mainly includes processing performed every 16 ms on the main loop (hereinafter also referred to as "16 ms processing") and interrupt processing performed every 1 ms (hereinafter referred to as "1 ms timer interrupt processing") Say).
First, the main process including the 16 ms process will be described here.
FIG. 13 shows the main processing of the effect control unit 51. The effect control unit 51 (effect control CPU 200) starts the main processing of FIG. 13 when the game machine body is powered on.
In this main processing, the effect control CPU 200 first performs necessary initialization processing before the start of the game operation in step S101. For example, as initial setting processing, command reception interrupt setting, movable body role start point return processing, CTC initial setting, timer interrupt permission, initial setting of a register value in the CPU including each part of the microcomputer, and the like are performed.

When the initial setting process of step S101 is completed, the processes of steps S102 to S119 are repeatedly performed as the process at the time of normal operation.
That is, in this example, the effect control CPU 200 performs the ID check in step S102 and the random number update in step S119 every loop, and performs the processing of steps S105 to S118 (16 ms processing) every 16 ms.

In the ID check in step S102, the effect control CPU 200 confirms the ID of its own or connected parts set in the system. If an ID abnormality is detected due to any cause, system stop processing is performed as step S103.
At normal times when there is no problem with the ID, the effect control CPU 200 performs the processing of step S104 and thereafter. That is, the effect control CPU 200 determines whether the value of the interrupt counter for determining execution of the 16 ms process is larger than “15”. This interrupt counter is a counter that is incremented in step S207 of the 1 ms timer interrupt process of FIG. 14 described later. Therefore, when the value of the interrupt counter is larger than "15", it means that the timing of 16 ms processing is reached.

When the value of the interruption counter is “15” or less, the effect control CPU 200 proceeds from step S104 to step S119, performs the updating process of the effect soft random number, finishes one main process, and performs the process from step S102 again I do.
On the other hand, when the value of the interruption counter is "16" or more, the effect control CPU 200 executes the processing of steps S105 to S118, and then performs the processing for updating the effect soft random number in step S119 and performs one main processing The process from step S102 is performed again.

As described above, the effect control CPU 200 performs the 16 ms process from step S105 every 16 ms counted by the interrupt counter.
In that case, first, in step S105, the interrupt counter is reset to zero. After that, it is to count up to the next 16 ms processing again.
Next, at step S106, the effect control CPU 200 performs an error process. The error processing includes processing of an error processing timer during RAM clear error, during a character error, during right turn error, scenario registration processing for error notification when various errors occur, error scenario after error notification Will be performed.
Next, in step S107, the effect control CPU 200 performs a demonstration process. In this demonstration process, processes such as playback sound control, demonstration movie execution, and feature origin correction scenario registration, and a command set thereof are performed. In the customer waiting state, a demonstration movie is displayed by executing the scenario set in the demonstration process.

In step S108, the effect control CPU 200 performs command analysis processing. In this command analysis process, the effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and reads this command if the effect control command is stored. . Then, effect control processing corresponding to the read effect control command is performed. Details will be described later with reference to FIGS.
In step S109, the effect control CPU 200 performs an input detection process. In this input detection processing, detection of input by operation of the operation elements (effect buttons 11, 12 and cross key 13) of the operation unit 60 is performed, and when input is detected, processing corresponding to the operation is performed.
In step S110, the effect control CPU 200 performs a scenario update process. In this process, updating of the main scenario and updating of the sub scenario are performed. At that time, registration of lighting patterns of the lamp portions 64 and 65, registration of sound to be reproduced, registration of motor operation for driving the movable object, and the like are also performed. Details will be described later with reference to FIGS. 20 and 21.
In step S111, the effect control CPU 200 performs sound reproduction processing. The effect control CPU 200 outputs data such as a phrase number and a volume to the sound source IC based on sound data registered as a sound channel in a work based on scenario data. As a result, reproduction and output of sound effects, music and voice from the speaker 25 are performed.
In step S112, the effect control CPU 200 performs a character feature error process. Here, position error determination such as that the movable body role is not returned to the origin is performed.

At step S113, the effect control CPU 200 initializes the LED driver 90. The initialization of the LED driver 90 is a process of outputting a default value to a register not used in the LED driver 90. For example, each LED driver 90 of the frame driver unit 61 and each LED driver 90 of the board driver unit 62 are initialized.
At step S113, the effect control CPU 200 updates the LED drive data. Here, processing for creating LED drive data is performed based on lamp data registered as a lamp channel in a work based on scenario data. Details will be described later with reference to FIG.
At step S114, the effect control CPU 200 performs LED output processing. That is, the effect control CPU 200 controls the light emission drive data (LED drive data) for the LED driver 90 from the serial data output channels ch1 and ch2 for each LED driver 90 of the frame driver unit 61 and each LED driver 90 for the board driver unit 62. Output). The details will be described later with reference to FIG.

In step S116, the effect control CPU 200 calculates and saves checksums for the work area of the effect control RAM 202, and in step S117, saves backup data.
Further, in step S118, the scenario update counter is reset to zero. The scenario update counter is a counter that is incremented by 1 ms timer interrupt processing described later.
The above 16 ms processing is performed every 16 ms in the main loop processing of FIG.

[6-2: 1 ms timer interrupt processing]

Next, 1 ms timer interrupt processing will be described with reference to FIG. The effect control CPU 200 executes the 1 ms timer interrupt process of FIG. 14 in response to the interrupt request generated every 1 ms by the time count.
In the 1 ms timer interrupt process, first, in step S201, it is determined whether a checksum is being calculated according to a test command from the main control CPU 100. If the checksum is not being calculated, the effect control CPU 200 proceeds to the input process of step S202.

The input process of step S202 is a process for each 1 ms for performing the input detection by the operation of the operation together with the input detection process of step S109 of FIG. 13 described above. For example, in this input processing, processing is performed to reset the input counter when an edge is detected in the signal waveform of the operation detection signal of the operation element, and then to count up the input counter while no edge is generated. In the 1 ms timer interrupt process, input information (H or L of the input signal waveform) is detected, and reset or increment of the input counter is performed depending on the presence or absence of an edge. Then, in step S109 in the main loop process (16 ms process), when the value of the input counter is 16 or more and the input information has changed from the previous time, the input change is recognized.
By such input processing (S202) and input detection processing (S109), it is possible to prevent erroneous input recognition due to noise chattering. Further, since the input counter is used, and in the present embodiment, for example, it is possible to count up to 65535 ms (about 65 seconds) using a 16-bit counter, so-called long press detection becomes possible.

In step S203, the effect control CPU 200 performs motor operation update processing. In this case, the effect control CPU 200 performs processing of creating motor drive data based on motor data registered as a motor channel in a work (motor data registration information described in FIG. 22C) based on scenario data. This is motor drive data to be output to the motor driver 90M of the motor driver unit 70 to drive and control the movable object product motor 65. In the present embodiment, the LED drive data update is performed every 16 ms in step S114, while the motor drive data update is performed every 1 ms.
In step S204, the effect control CPU 200 outputs motor drive data. In this step S204, serial data as drive data for the stepping motor 121 as the movable object product motor 65 is output to the motor driver 90M of the motor driver unit 70.

In step S205, the effect control CPU 200 executes each process according to the value of the interrupt counter. The interrupt counter is reset to zero in step S105 of the 16 ms process described above, and is incremented in step S207 of the 1 ms timer interrupt process. Therefore, when step S205 is executed in the 1 ms timer interrupt process, the value of the interrupt counter is any one of 0-15.
The process of step S205 is defined as case 0 to case 15 in accordance with the value 0 to 15 of the interrupt counter. For example, in the present embodiment, in case 0, a WDT (watchdog timer) clear signal ON is performed. In Cases 1 to 3, the motor driver 90M is initialized. In case 8, the WDT clear signal is turned off.

In step S206, the effect control CPU 200 outputs an effect control command to the liquid crystal control board 52. For example, one command (two bytes) is transmitted in one 1 ms timer interrupt process. That is, a 2-byte effect control command as a mode and an event is transmitted.
Thereafter, the effect control CPU 200 increments the interrupt counter in step S207, and increments the scenario update counter in step S208. If the value of the scenario update counter is less than 100, the 1 ms timer interrupt process is ended.
Since the scenario update counter is reset to zero in step S118 of the 16 ms process as described above, normally, the value of the scenario update counter does not become 100 or more. The case of 100 or more is the case where the 16 ms process is not executed due to an operation error, process response error or the like, or the progress of a certain process in the 16 ms process is stopped. In such a case, an infinite loop is entered to wait for the WDT to perform time-up processing.

When it is determined that the checksum is being calculated in step S201 when the 1 ms timer interrupt process is started, the effect control CPU 200 advances the process to step S210 and clears the WDT. Then, in step S211, transmission control of the effect control command to the liquid crystal control board 52 is performed. Then, in step S212, the interrupt counter is incremented to complete the 1 ms timer interrupt process.

[6-3: Command Analysis Processing]

Next, the command analysis process performed in step S108 of FIG. 8 as the 16 ms process will be described with reference to FIGS. The effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer as the command analysis process of step S108, and if the effect control command is stored, this command Read out. As this specific process, the processes of steps S301 to F308 of FIG. 15 are performed.

In the effect control unit 51, for example, a effect reception buffer for taking in the effect control command transmitted from the main control unit 50 is prepared in the effect control RAM 202. At step S301 in FIG. 15, the effect control CPU 200 first confirms the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The write pointer is updated in response to the reception of the command, and the received effect control command is stored at the address indicated by the write pointer. The read pointer is updated (step S302) when reading from the command reception buffer. Therefore, if the read pointer is not the write pointer, it means that the effect control command which has not been read out is stored in the command reception buffer. Therefore, if the read pointer is not the write pointer, the process proceeds to step S302, and the effect control CPU 200 loads 1 byte of command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next read (load).

As described above, one effect control command is formed by two bytes of one byte as a mode and one byte as an event. In step S303, the effect control CPU 200 confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit 7 out of 8 bits (Bit 0 to Bit 7).
If the mode is the mode, the process proceeds to step S304 as processing for receiving upper data of the command, and the read command data is saved in the register "command HI byte". Also clear the "command LO byte" register. Then, the process returns to step S301.
Subsequently, if the read pointer is not the write pointer, the effect control command that has not been read out is stored in the command reception buffer, so the process proceeds to step S302 and the effect control CPU 200 uses the read pointer in the command reception buffer. Load 1 byte of command data from the indicated address. Also, the read pointer is incremented.
Then, if the read command is an event, the process proceeds from step S303 to S305 as processing of lower data reception of the command, and the read command data is saved in the register "command LO byte".

By the command data of the mode and the event being saved in the register "command HI byte" and "command LO byte", the effect control CPU 200 takes in one command.
Therefore, in step S306, the effect control CPU 200 performs processing in accordance with the fetched command. A specific example will be described later with reference to FIGS.

  The read pointer equals the write pointer when there is no effect control command which has not yet been fetched by the effect control CPU 200 in the command reception buffer. Therefore, the process proceeds to step S307 because a new acquisition is not necessary. In this case, it is checked whether 100 ms has elapsed while waiting for the symbol command. If such a situation does not occur, the command analysis process of FIG. 15 is ended. On the other hand, if 100 ms has elapsed in the symbol command waiting state, processing of symbol variation in the command omission is performed in step S308.

An example of the command corresponding process in step S306 described above will be described with reference to FIGS.
FIG. 16A shows basic processing as command corresponding processing. In response to the reception of the 2-byte effect control command, the effect control CPU 200 first checks in step S321 in FIG. 16A whether or not the test mode is currently in progress. If in the test mode, clearing of all the rendering scenarios, stopping of the sound output, and turning off the LEDs in the lamp portions 63 and 64 are performed in step S322. Then, the test mode is ended in step S323.
These processes are not performed unless in the test mode.
Then, at step S330, the effect control CPU 200 performs processing for the taken effect control command.

  As the effect control command, for example, a special symbol variation pattern designation command, a special symbol designation command, a hold ball subtraction command, a hold ball addition command, an error display designation command, a jackpot start designation command, etc. are variously set. In step S330, the effect control CPU 200 performs the process defined by the program in response to the received command. Here, seven rendering control commands are listed in FIGS. 16B to 16E and FIGS. 17A to 17C to illustrate specific processing.

FIG. 16B shows, as command processing in step S330, processing S330a in the case of capturing a variation pattern command.
In this case, the effect control CPU 200 performs a process of setting a symbol command waiting state in step S331. This is because the effect control CPU 200 controls the fluctuation display of the symbol by sequentially receiving the fluctuation pattern command and the symbol command.

FIG. 16C shows, as command processing in step S330, processing S330b in the case where a symbol designation command is fetched.
In this case, the effect control CPU 200 first checks in step S332 whether or not the fluctuation pattern command has been received. If not received, the process ends.
If the variation pattern command has already been received when the symbol designation command is received, the process proceeds to step S333, and first, scenario registration for the operation of the feature origin correction is performed. Then, in step S334, the symbol variation flag is set. The symbol variation flag is provided corresponding to each of the first special symbol, the second special symbol, and the normal symbol, and each flag represents a variation state. For example, the first special symbol variation flag FZ1, the second special symbol variation flag FZ2 and the normal symbol variation flag FZ3 of 2 bits are prepared, and during variation, stop (hit) and stop (disengagement) are shown. Here, along with the start of fluctuation, the corresponding symbol fluctuation flag (one of FZ1, FZ2 and FZ3) is set to a value indicating "during fluctuation".
In the case of a hit, the symbol change flag is set to a value indicating "during stop (hit)" for a predetermined time at the end of symbol change, and thereafter, a value indicating "during stop (disengagement) until symbol change is started" Set to
At step S335, the effect control CPU 200 performs fluctuation start processing. After that, the variation pattern command is deleted in step S336 according to the start of variation.

FIG. 16D shows, as command processing in step S330, processing S330c in the case of capturing a power on command.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S337. For example, the contents of the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the storage area of the checksum are cleared.
Then, in step S338, an error cancellation command is transmitted, in step S339 clearing of product error information, in step S340 stopping of the product operation, in step S341 registration of power on scenario, in step S342 transmitting power to liquid crystal control board 52 Do a set of commands sequentially.

FIG. 16E shows a process S330d in the case where a RAM clear command is fetched as the command process in step S330.
In this case, the effect control CPU 200 performs a process of clearing the effect control RAM 202 in step S343. For example, the contents of the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the storage area of the checksum are cleared.
Then, in step S344, an error release command is transmitted, and in step S345, the RAM clear error is set and the error notification timer is set. Further, in step S346, the information on the lottery process in the effect control RAM 202 is cleared, and in step S347, the information on the scenario is cleared. Then, in step S348, a power initial on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

FIG. 17A shows, as command processing in step S330, processing S330e in the case where a hold addition command is fetched.
In this case, in step S350, the effect control CPU 200 holds the number of corresponding hold number register of the first special symbol variation display game or the second special symbol variation display game (the first hold number set in the presentation control RAM 202 or The value of the hold number in the register area as the second hold number is read out and added. Then, in step S351, a command for displaying the number of holdings is set on the liquid crystal control board 52, and in step S352, the updated value is set as the first number of holdings or the second number of holdings.

FIG. 17B shows, as command processing in step S330, processing S330f in the case where the hold addition command is fetched.
In this case, in step S360, the effect control CPU 200 controls the number of holdings corresponding to either the first special symbol variation display game or the second special symbol variation display game (the first hold number set in the presentation control RAM 202 or the corresponding number) The value of the hold number in the register area as the second hold number is read out and subtracted. Then, in step S361, a command for displaying the number of holdings is set on the liquid crystal control board 52, and in step S362, the updated value is set as the first number of holdings or the second number of holdings.

FIG. 17C illustrates a process S330g in the case where a status notification command is fetched as the command process in step S330.
In this case, the effect control CPU 200 sets a game state notification flag in step S371. As the gaming state notification flags, for example, flags FJ1, FJ2, and FJ3 indicating "big hit", "incorrect", and "in time" are prepared. In step S371, the effect control CPU 200 sets one of the corresponding game state notification flags in accordance with the game state instructed by the state notification command.

[6-4: Scenario registration / deletion processing]

Next, scenario registration / deletion processing will be described. The scenario is data that defines various operations to be performed such as presentation control, error processing, and the like. The scenario data to be executed is registered in the work area of the effect control RAM 202 as scenario registration information. Although the structure of the scenario registration information shown in FIG. 22A will be described later, 64 scenario channels from 0 to 63 are prepared as scenario registration information. Scenarios registered in the 64 scenario channels can be simultaneously executed. Hereinafter, the scenario channel is indicated by "sCH".
The scenario registration process is a process of registering a scenario of a scenario number requested to be registered in an arbitrary scenario channel in the scenario registration information. In principle, any of sCH0 to sCH63 scenario channels may be used.

  The scenario registration described below is called and executed as necessary, for example, in the process of the error process of step S106 of FIG. 13, the demonstration process of step S107, and the command analysis process of step S108. For example, step S333 in FIG. 16C and step S341 in FIG. 16D described above are an example of scenario registration.

As the process of FIG. 18, the effect control CPU 200 performs a process of registering the value of the scenario number and the waiting time (delay) corresponding to the scenario specified on the command or program in the work (scenario registration information).
In step S401, the effect control CPU 200 first confirms whether the scenario number to be registered this time is normal. If the scenario number can not be found, the process ends without doing anything.

  If the scenario number is appropriate, the effect control CPU 200 sets the variable B to zero in step S402. The variable B is a variable used to sequentially search for free channels among the scenario channels sCH0 to sCH63. Furthermore, the variable B doubles as a variable for determining whether or not there remains a scenario channel which has not yet been searched (confirmation of whether or not it is an empty channel).

At step S403, the effect control CPU 200 confirms whether the scenario channel of the “addition pointer” + B is empty. The additional pointer is a pointer set in step S407 described later when scenario registration is performed. When the process of FIG. 18 is started, the value of the addition pointer is a value indicating a scenario channel next to the scenario channel registered previously. The initial value of the additional pointer (the value when the process of FIG. 18 is performed for the first time from the initial state) is zero.
If the scenario channel of “additional pointer” + B is not empty, the effect control CPU 200 increments the variable B in step S404.
If B <64 in the step S405, the process of FIG. 18 ends. This is a case where searching is performed for all scenario channels, but there is no empty channel and scenario registration becomes impossible.
When all scenario channels have not been searched (confirmation of whether they are empty channels), B <64 in step S405. In that case, the confirmation process of step S406 is performed, and if the value of "addition pointer" + B is not more than the value "64" exceeding the maximum value of the scenario channel sCH, the process returns to step S403.
If the value of “additional pointer” + B is “64” or more, the value of the additional pointer is corrected in step S407. Specifically, when the value of "addition pointer" + B becomes "64", the value of the addition pointer is subtracted by "64". Then, the process returns to step S403.

According to the processing of steps S403 to S407, it is checked in order from the scenario channel next to the scenario channel registered previously that whether or not the scenario channel is free.
That is, by incrementing the variable B in step S404, the scenario channels sCH confirmed each time step S403 is performed are sequentially advanced one by one.
Since variable B is reset to zero in step S402 and then incremented in step S404, if B <64 is not satisfied in step S405 (that is, if variable B reaches 64), step S403 is already performed. Processing is performed 64 times. This is a case where all scenario channels sCH0 to sCH63 were examined, but it was judged that there was no space. Therefore, the process of FIG. 18 is ended on the assumption that registration is impossible.

In addition, since the value of “additional pointer” is a value indicating the scenario channel next to the scenario channel registered previously, “additional pointer” + B is also performed at B <64 when no empty channel is checked for all scenario channels. The value of (that is, the number of the scenario channel sCH to be checked next) may be "64" or more. Specifically, the value of “addition pointer” + B is 63 at the time of step S403 just before, and after confirming about the scenario channel sCH 63, the variable B is incremented in step S404. In this state, a scenario channel sCH 64 which does not exist next will be designated.
Therefore, if this point is confirmed in step S406 and the value of "addition pointer" + B is "64", in step S407, the correction of the addition pointer is corrected in order to return the scenario channel to be confirmed next to "sCH0". Do. That is, by setting the value of the additional pointer to -64, the value of "additional pointer" + B is made "0". Thus, in the next step S403, it is checked whether the scenario channel sCH0 is free.

If a vacant scenario channel is found in the process of step S403 at a certain point in time, the effect control CPU 200 proceeds to step S408 and sets the scenario number and the waiting time (delay) in the vacant scenario channel. Also clear the data necessary for other scenario management to zero.
Then, in step S409, the addition pointer is updated to the value of the scenario channel +1 that has been registered. That is, the value of the scenario channel next to the scenario channel registered this time is stored as an additional pointer, and can be used for the next registration process. In the present embodiment, since the scenario channel is 64 channels of sCH0 to sCH63, the maximum value of the additional pointer is 63.

  According to the process of FIG. 18, when registering a scenario, a vacant channel is searched from the scenario channel next to the scenario channel registered previously. The initial value of the additional pointer is “0” and is then updated in step S407 according to registration. According to this process, scenario registration is performed using scenario channel sCH0 in order in many cases. . Then, at the time of scenario registration, confirmation of availability is performed from the scenario channel next to the previous registration channel. Therefore, in most cases, a vacant channel can be found quickly, and the scenario registration process can be performed efficiently. Thereby, the processing load on the effect control CPU 200 is reduced.

  As a modification of the process, the value of the additional pointer updated in step S407 may be stored as the number of the scenario channel that has been registered, and 1 may be substituted for the variable B in step S402. However, in this case, it is determined in step S405 whether B ≦ 65.

Next, scenario deletion processing will be described. This is a process of deleting a scenario registered in a certain scenario channel of a work.
FIG. 19A shows the process of the effect control CPU 200 when a certain scenario is deleted from the scenario registration information.
The effect control CPU 200 starts the process of FIG. 19A based on the value of the scenario number (main scenario number (mcNo) described later) to be deleted, which is designated on the command or program program. First, at step S421, the effect control CPU 200 confirms whether or not the scenario number relating to the deletion request is normal. If the scenario number can not be found, the process ends without deleting it.

  If the scenario number is appropriate, the effect control CPU 200 sets the variable B to zero in step S422. The variable B in this case is a variable used to search for a channel in which the scenario to be deleted is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B doubles as a variable for determining whether or not there remains a scenario channel which has not yet been searched (confirmation of whether a scenario to be deleted is registered).

In step S423, the effect control CPU 200 confirms whether the scenario registered in the B area, that is, the scenario channel sCH (B) is that of the scenario number to be deleted. If the scenario registered in the scenario channel sCH (B) is not the deletion target scenario number, the variable B is incremented in step S424, and it is confirmed that B <64 in step S425, and the process of step S423 is performed. Do.
According to the processing of steps S423 and F424, the scenario to be deleted is searched in order from the scenario channel sCH0 toward the scenario channel sCH63.
If the scenario registered in the scenario channel sCH (B) at step S 423 is the scenario number to be deleted, the process proceeds to step S 426 and the scenario registered in the B area, that is, the scenario channel sCH (B) is deleted Do the process.
As described above, processing for deleting a scenario of a requested scenario number from a work (scenario registration information) is performed.
If it is determined in step S425 that B is not less than 64, that is, if the variable B has reached 64, all scenario channels sCH0 to sCH63 have been searched, but the deletion target scenario is not registered. Finish the process because it will be a problem.

FIG. 19B shows the process of deleting a range of scenarios. This process is performed when a deletion scenario is specified as a range.
When the effect control CPU 200 is designated for deletion within a certain scenario number range on the command or program, the variable B is first set to zero in step S431. The variable B in this case is a variable used to search for a channel in which a scenario corresponding to the deletion target range is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B doubles as a variable for determining whether there is a scenario channel which has not been searched (confirmation of whether a scenario corresponding to the deletion target range is registered).

In step S432, the effect control CPU 200 confirms whether the scenario registered in the B area, that is, the scenario channel sCH (B) is a scenario number within the range to be deleted. Then, if the scenario registered in the scenario channel sCH (B) is a scenario number within the range to be deleted, the scenario registered in the scenario channel sCH (B) is deleted in step S433. Then, the process proceeds to step S434.
If the scenario registered in the scenario channel sCH (B) is not a scenario number within the range targeted for deletion, the process proceeds to step S434 without performing step S433.
In step S434, the effect control CPU 200 increments the variable B, confirms that B <64 in step S435, and returns to step S432. If the variable B has reached 64, the processing has been completed for all scenario channels sCH0 to sCH63, so this scenario range deletion processing is ended.
As described above, deletion from the work (scenario registration information) is performed for one or more scenarios in the scenario number range.

FIG. 19C shows a process of deleting all registered scenarios. For example, it is a process called upon deleting a scenario as a matter of system convenience. Note that the scenario targeted for protection is not deleted.
When the scenario control deletion is requested, the effect control CPU 200 first sets the variable B to zero in step S441. The variable B in this case is a variable used to confirm, among the scenario channels sCH0 to sCH63, the scenario channel in which the scenario to be protected is registered. Furthermore, the variable B doubles as a variable for determining whether or not there remains a scenario channel that has not been confirmed (confirmed as to whether or not a scenario to be protected is registered).

In step S 442, the effect control CPU 200 confirms whether the scenario registered in the B area, that is, the scenario channel sCH (B) is a protection target scenario. If it is a protected scenario, it is not deleted. If it is not a protected scenario, the scenario registered in the scenario channel sCH (B) is deleted in step S443.
Then, the variable B is incremented in step S444, and if B <64 in step S445, the process returns to step S442. If the variable B has reached 64, this means that the process has been completed for all scenario channels sCH0 to sCH63, so this scenario all deletion process is ended.
As described above, for the scenarios registered as scenario registration information in the work, deletion of all the scenarios excluding the scenario to be protected is performed.

[6-5: Scenario update process]

Subsequently, a scenario update process performed in step S110 of the 16 ms process of the main process will be described. In the scenario updating process, the main scenario and the sub-scenario are updated as described with reference to FIGS. 20 and 21.

First, the structure of the scenario registration information will be described with reference to FIGS. FIG. 22A shows the structure of scenario registration information as a main scenario and a sub-scenario. The scenario registration information is set using the work area of the effect control RAM 202.
In the present embodiment, as described above, the scenario registration information includes 64 channels of scenario channels sCH0 to sCH63. Scenarios registered in each scenario channel sCH can be simultaneously executed.

  As shown in the figure, as information that can be registered in each scenario channel sCH, a sub-scenario execution line (an execution line of the sub-scenario timer (scTm) and previous time (scPrevTm) used in sub-scenario update processing and sound / motor sub-scenario table ( scIx), sub scenario execution line lmp (lmpIx) indicating execution line of ramp sub scenario table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating execution line of main scenario table, main There are a scenario number (mcNo), a main scenario option (mcOpt) which is optional data that can be added to the main scenario, a user option (userFn), a waiting time (delay), and a checksum (checkSum).

When sound output by the speaker unit 59, light emission by the lamp units 63 and 64, and presentation by driving the movable object by the movable object role motor 65 are started, the standby time (delay) and the main scenario number ( mcNo ) are scenarios It registers to a vacant scenario channel among the channels sCH0 to sCH63.
The waiting time (delay) indicates the time from registration to the scenario channel sCH to the start of the scenario. The waiting time (delay) is decremented by 1 every 16 ms processing. When the waiting time (delay) is 0, processing corresponding to the registered data is performed.

FIG. 24 shows an example of scenario numbers 1, 2 and 3 as a part of the main scenario table. As the scenario of each scenario number, while the value of the main scenario timer (msTm) is described as time data in each line (line) of the scenario, the sub scenario number (scNo) and the option (OPT) can be described . That is, in the main scenario table, a sub-scenario (and possibly an option) to be executed is specified as a time by the main scenario timer (msTm). In the last line of the scenario, a scenario data end code D_SEEND or a scenario data loop code D_SELOP is described.
In addition, since the value of the main scenario timer (msTm) is incremented by 1 in the process of updating the scenario performed in the 16 ms process from the start of the main scenario, “1” indicates 16 ms. The scenario table of each scenario number will advance to the next row when the time of the main scenario timer (msTm) in a certain row elapses. The time data of each row indicates the timing at which the row ends.
For example, in the case of scenario No. 2, the operation of sub scenario No. 2 is designated as the time of 1500 × 16 ms, the action of sub scenario No. 20 is designated as the time of the next 500 × 16 ms, and the sub of 2000 × 16 ms as the time of the next The action of scenario number 21 is specified. The next line is scenario data end code D_SEEND. In the case of the scenario data end code D_SEEND, this scenario is deleted from the scenario registration information (work) (see step S617 in FIG. 20 described later).

Next, the structure of lamp data registration information will be described with reference to FIG. 22B. As the lamp data registration information, information indicating a scenario selected from the lamp sub-scenario table, that is, information indicating a rendering operation (lighting pattern) by the lamp units 63 and 64 is registered. The lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the ramp data registration information includes 16 channels of ramp channels dwCH0 to dwCH15. Priority is set to each ramp channel dwCH0 to dwCH15, and the priority becomes higher in order from the ramp channel dwCH0 to dwCH15. Therefore, the scenario registered in the ramp channel dwCH 15 (ramp sub-scenario) is executed with the highest priority. Further, for example, if a scenario is registered in the ramp channel dwCH3 or dwCH10, the scenario registered in the ramp channel dwCH10 is preferentially executed.
The lamp channel dwCH0 is mainly used for lamp effects accompanying BGM (Back Ground Music), and the lamp channel dwCH15 is used for lamp effects relating to errors, and the lamp channels dwCH1 to dwCH14 are used for normal effects.

  As information that can be registered in each lamp channel dwCH, as shown, a registered lighting number (lmpNew) indicating the number of the registered lighting pattern, an execution lighting number (lmpNo) indicating the number of the lighting pattern to be executed, and There is an offset (offset) indicating an execution line, an execution time (time), and a checksum (checkSum).

  FIG. 25A shows an example of lamp sub-scenario numbers 1, 2 and 3 as a part of the lamp sub-scenario table. As a lamp sub-scenario of each number, the value of time data (time) is described in each line (line) of the scenario, and a lamp channel and a lamp number indicating various lighting patterns are described. In the last line, a lamp scenario data end code D_LSEND is described.

In the ramp sub-scenario table, time data (time) of each line indicates a time when the line is started since the sub-scenario is started.
The main scenario timer (msTm) is compared with the time data of the table every 16 ms, and when they match, the lamp number of the line is registered in the lamp data registration information of FIG. 22B. The ramp channel dwCH to be registered is the channel indicated in the line.
For example, in the above-mentioned certain scenario channel sCH, scenario number 2 shown in FIG. 24 is registered, and sub-scenario number 2 is referred to. In the lamp sub-scenario No. 2 shown in FIG. 25A, the lamp channel 5 (dwCH5) and the lamp number 5 are described as time data (time) = 0 in the first line. In this case, when the main scenario timer (msTm) = 0, the information of the first line is registered as the registered lighting number (lmpNew) = 5 in the lamp channel dwCH5 of the lamp data registration information of FIG. 22B. The value of the sub scenario execution line lmp (lmpIx) of the scenario registration information is updated to the value of the next line (the second line). This is a registration for performing the lighting pattern operation of lighting number 5 with a relatively low priority of the lamp channel dwCH5.
The same process is performed for the second line when 500 × 16 ms is reached. That is, registered lighting number (lmpNew) = 6 (that is, an instruction of the lighting pattern of lighting number 6) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) has the same value in two consecutive lines, processing for each line will be started simultaneously.
In the LED drive data update process described later, LED drive data is created based on the lamp data registration information updated in this manner.

Next, the structure of motor data registration information will be described with reference to FIG. 22C. As motor data registration information, information indicating a scenario selected from the sound / motor sub-scenario table is registered. The motor data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, motor data registration information includes eight channels of motor channels mCH0 to mCH7.
As information which can be registered in each motor channel mCH, as shown, an execution operation number (no), a registration operation number (noNew), an operation count (lcnt), an excitation counter (tcnt), an execution step (step), an operation line (Offset), parent (migration source) / child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) , Current input information (currentSw), switch information on software (softSw), and count on software (softCnt).

FIG. 23 shows sound data registration information. As the sound data registration information, information indicating a scenario selected from the sound / motor sub-scenario table is registered. The sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information includes 16 channels of sound channels aCH0 to aCH15.
As information that can be registered in each sound channel aCH, as shown in the figure, volume transition amount (frzVq), volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), stereo (frzSt) , Loop (frz Lp), phrase number hi (frz Hi), phrase number low (frz Lo).

FIG. 25B shows an example of the sound / motor sub scenario numbers 1 and 2 as a part of the sound / motor sub scenario table. As the sound / motor sub-scenario of each number, the value (ms) of time data (time) is described in each line (line) of the scenario, and BGM, warning sound, error sound, sound control, motor, solenoid / Information on user options is described. In the last line, a scenario data end code D_SEEND is described.
Regarding this sound / motor sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (still initially 0), the value of time data (time) of this sound / motor sub-scenario table Set to scTm). The time data (time) of each line indicates the timing at which the line ends. The sub-scenario timer (scTm) describes an absolute time, therefore, the time data value to be set is the value of (time data of the relevant line)-(time data of the previous line).
The BGM data of the line is composed of information registered in sound data registration information such as BGM phrase number and volume value, and is set to sound channel aCH0 (in addition in the case of stereo, aCH1) in sound data registration information .
The data of the warning sound of the line is composed of information registered in sound data registration information such as the phrase number of the warning sound and the volume value, and is set in a vacant place of the sound channels aCH2 to aCH14.
The error sound data of the line is composed of information registered in sound data registration information such as a phrase number of error sound and volume value, and is set to the sound channel aCH15.
The sound control data is channel information in the lower 6 bytes and control information in the upper 2 bytes.
The data of the motor is configured to indicate the operation pattern number of the motor with one byte per motor. The operation pattern number is set to the motor channel corresponding to the motor number.

In the motor operation update process described as step S203 in FIG. 14, motor drive data is created based on the motor data registration information updated in the scenario update process in FIGS.
Further, in the sound reproduction processing of step S111 of FIG. 13, reproduction output is performed based on the sound data registration information updated in the scenario update processing of FIGS.

Scenario update processing using the above pieces of information will be described with reference to FIGS.
In the scenario update process of FIG. 20 executed as step S110 of the 16 ms process of FIG. 13, the effect control CPU 200 performs the processes of steps S601 to S616 for each of scenario channels sCH0 to sCH63 as loop process LP1. The scenario channel to be processed each time of the loop processing is described as “sCHn”.

  At step S601, the effect control CPU 200 confirms the standby time (delay) of the scenario channel sCHn. If the waiting time (delay) is not 0, the value of the waiting time (delay) is decremented by one in step S602. Then, in step S615, the checksum of the data related to the scenario channel sCHn is calculated and stored. Also, in step S616, data related to the scenario channel sCHn is backed up and saved. This completes one process for the scenario channel sCHn.

On the other hand, when it is confirmed in step S601 that the waiting time (delay) = 0, the effect control CPU 200 proceeds to step S603 to execute the main scenario number (mcNo) registered in the scenario channel sCHn and the main scenario execution. Identify the address of the main scenario table corresponding to the line (mcIx).
In step S604, it is checked whether the execution line of a certain main scenario number in the main scenario table indicated by the specified address is the last line in which the end code D_SEEND (see FIG. 24) is described.
If it is the last line in which the end code is described, the processing to be executed in the scenario registered in the scenario channel sCHn is completed, so the scenario registered in the scenario channel sCHn in step S617. Delete from scenario registration information (work).
The deletion of the scenario registration in this case is a normal deletion corresponding to the end of the scenario. It should be added that the scenario deletion described above with reference to FIG. 19 is a process for deleting, for example, an unfinished scenario other than the normal deletion from scenario registration information (work).

If the line in the main scenario table is not the end code in step S604, the effect control CPU 200 proceeds to step S605 and first sets the option (OPT) of the line in the main scenario option (mcOpt) of the scenario channel sCHn. Do. In step S606, it is checked whether the scenario number is 0. If it is not 0, 0 is substituted for the user option (userFn) in step S607.
Then, in step S608, the sub-scenario specified by the scenario channel sCHn is updated. The update of the sub-scenario will be described later with reference to FIG.

In step S609, the effect control CPU 200 increments (increments) the main scenario timer (msTm) by one. Then, in step S610, the value of the main scenario timer (msTm) is compared with the time data of the corresponding line of the main scenario table (see FIG. 24: described by msTm). As mentioned above, the time data of each line of the main scenario table defines the end timing of that line. Therefore, if the value of the main scenario timer (msTm) is equal to or greater than the time data described in the line of the main scenario table, the processing of that line ends and the next line is targeted. In this case, the process proceeds from step S610 to S611, where the main scenario execution line (mcIx) of the scenario channel sCHn is incremented by one. In other words, the next line will be targeted next time.
In that case, it is checked in step S612 whether or not the next line is a loop designation. In scenario number 1 in the main scenario table in FIG. 24, an example is shown in which the final line is the scenario data loop code D_SELOP. However, when the loop is designated in this way, the main scenario execution line ( Set loop line to mcIx).

In step S614, the effect control CPU 200 performs a clear process in accordance with the end of one line. In other words, main scenario timer (msTm), sub scenario timer (scTm), previous time (scPrevTm), sub scenario execution line (scIx), sub scenario execution line lmp (lmpIx), main scenario option (mcOpt), user option (userFn) , Clear the waiting time (delay).
Then, the checksum processing in step S615 and the backup processing in step S616 are performed to complete one process for the scenario channel sCHn.
As the scenario update process, the above process is executed for each of the scenario channels sCH0 to sCH63 as the loop process LP1.

The sub-scenario updating process performed in step S608 is shown in detail in FIG. 21A.
The update processing of the sub-scenario of FIG. 21A is performed based on the main scenario timer (msTm), the scenario channel sCHn, and the sub-scenario number (scNo) described in the main scenario table.

First, at step S621, the effect control CPU 200 checks whether the scenario channel sCHn indicates any of 0 to 63, that is, whether or not it is an appropriate value. If the scenario channel sCHn is 64 or more, the update processing can not be performed, and the processing in FIG. 21A ends.
If the scenario channel sCHn is an appropriate value, the effect control CPU 200 specifies the address of the lamp sub-scenario table (see FIG. 25A) corresponding to the sub-scenario number (scNo) and the sub-scenario execution line lmp (lmpIx) in step S622. .

In step S623, the effect control CPU 200 first sets 0 to the lamp channel dwCH in order to update the lamp data registration information. That is, first, the lamp channel dwCH0 is designated.
Then, in step S624, the main scenario timer (msTm) and the time data (time) of the lamp sub-scenario table are compared. The time data (time) of the ramp sub-scenario table indicates the time (ms) at which the relevant line (line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, when the time of the main scenario timer (actually, the time of msTm × 16 ms) is equal to or more than the time data (time), the processing for the line is performed. In that case, it is checked in step S625 whether the value of the ramp channel dwCH is normal (within the range of dwCH0 to dwCH15). If the value is abnormal, the process is ended. If it is a normal value, it is checked in step S626 whether the current line is a line in which the lamp scenario data end code D_LSEND is described.

If the lamp scenario data end code D_LSEND is not described in the line, the effect control CPU 200 acquires the lamp channel dwCH and the lamp number described in the line in step S627, and in step S628 the acquired lamp channel dwCH. Register the lighting pattern number.
The registration process of the lighting pattern number is shown in FIG. 21B. In this case, first, at step S651, the effect control CPU 200 determines whether the value of the lamp channel dwCH described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If it is a normal value, it is determined in step S652 whether or not the lamp number described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If both the lamp channel dwCH and the lamp number are normal values, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH in the lamp data registration information of the work in step S653. Do. That is, the lamp number acquired from the relevant line of the lamp sub-scenario table is set to the registered lighting number (lmpNew), and "0" is set to the execution lighting number (lmpNo).
When the process of FIG. 21B is performed in step S628, the effect control CPU 200 increments the value of the sub-scenario execution line lmp (lmpIx) in step S629, increments the value of the lamp channel dwCH in step S630, and returns to step S624. .

In step S624, the time of the main scenario timer does not reach the time data (time) of the line indicated by the sub-scenario execution line lmp (lmpIx), and the lamp scenario data end code D_LSEND is confirmed in step S626. The processing of the effect control CPU 200 proceeds to step S631.
In step S631, it is checked whether the sub-scenario timer (scTm) is zero. If it is not 0, the process proceeds to step S639 without registering the sound and the motor. In this case, the value of the sub-scenario timer (scTm) is decremented in step S640, and the process of FIG. 21A ends.

If the sub-scenario timer (scTm) = 0 at the time of step S631, the effect control CPU 200 advances the process to step S632 to register the sub-scenario number described in the main scenario table and the scenario channel sCHn currently being processed. The address of the sound / motor sub-scenario table corresponding to the sub-scenario execution line (scIx) being specified is specified.
In step S633, the effect control CPU 200 determines whether the line indicated by the sub scenario execution line (scIx) in the corresponding sound / motor sub scenario number table is a line in which the scenario data end code D_SEEND is described. The process is ended if it is a line in which the scenario data end code D_SEEND is described.
If the scenario data end code D_SEEND is not described in the row, the effect control CPU 200 substitutes a value obtained by subtracting the previous time (scPrevTm) from the time data (time) of the line in the sub scenario timer (scTm) in step S634. Do. Further, time data (time) of the line is substituted for the previous time (scPrevTm).

Then, the effect control CPU 200 registers the sound in step S635, and registers the motor in step S636. Although detailed description is avoided, the information of the corresponding line of the corresponding sub-scenario number of the sound / motor sub-scenario table illustrated in FIG. 25B, the optional motor channel of the motor data registration information of FIG. 22C, and the sound data registration information of FIG. Perform processing to register in any sound channel. Also, in step S637, the information of the solenoid / user option described in the line is also registered in the scenario registration information or the like.
Then, in step S638, the value of the next line is set as the value of the sub scenario execution line (scIx). If the sub-scenario timer (scTm) is not 0 in step S639, the sub-scenario timer (scTm) is decremented in step S640, and the process is ended.

In step S110 of FIG. 13, the processes of FIGS. 20 and 21 are performed as described above, and scenario registration information, lamp data registration information, motor data registration information, and sound data registration information on the work are sequentially updated. By performing the effect control in accordance with this, the effect operation along the scenario is executed.

[6-6: LED drive data update process]

The LED drive data update process of step S114 of FIG. 13 will be described.
This process is a process of creating LED drive data with reference to the lamp data table corresponding to the lighting number (registered lighting number (lmpNew), effective lighting number (lmpNo)) registered in the lamp data registration information. . As described above, the lamp number indicating the lighting pattern originally described in the lamp sub-scenario table is set as the lighting number of the lamp data registration information. Although the lamp number is described as the number indicating the lighting pattern, specifically, it indicates the number of lamp data of the lamp data table described in FIG. 31A.

FIG. 26 shows the LED drive data update process.
At step S701, the effect control CPU 200 clears the LED drive data which has been used as the output data.
Then, as loop processing LP2, processing of steps S702 to S720 is performed for each of the lamp channels dwCH0 to dwCH15 of the lamp data registration information. Hereinafter, the lamp channel to be processed will be described as “dwCHn”.

In step S702, the effect control CPU 200 checks whether the actual lighting number (lmpNo) and the registered lighting number (lmpNew) in the target lamp channel dwCHn match. Since the registration of the lighting pattern number is performed as in step S653 of FIG. If the values do not match, the value of the registered lighting number (lmpNew) is substituted for the execution lighting number (lmpNo) in step S703 as the lighting start. In step S704, the execution line (ofset) is set to 0, and the execution time (time) is set to 0.
If the actual lighting number (lmpNo) and the registered lighting number (lmpNew) match, the processing in steps S703 and S704 has already been performed in the past, and these processings are unnecessary.

About information registered in a certain lamp channel dwCH, after registration, the LED drive data to be output to each LED driver 90 is created with the information reflected on each occasion of the LED drive data update processing.
FIG. 29A shows a state where registration is performed in the lamp channels dwCH 0, dwCH 5, dwCH 8 in the lamp data registration information of the work shown in FIG. 22B. The state of this figure is an example of the state of the time point t0 of FIG. 29B.
That is, the information on the lamp channels dwCH0 and dwCH5 is reflected in the LED drive data before time t0. For the lamp channel dwCH0, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to the third (third line). Also for the lamp channel dwCH5, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) already match, and the execution line (ofset) has advanced to 2 (the second line). At time t0, the lamp channel dwCH 8 is just after registration, and the execution lighting number (lmpNo) and the registration lighting number (lmpNew) are not yet matched. After this, the processes of steps S703 and S704 are performed.

As described above, in the present embodiment, priority is set to the ramp channels dwCH0 to dwCH15, and the priorities become higher in order from the ramp channels dwCH0 to dwCH15. As shown in FIG. 29A, the high priority ramp channel dwCH 15 is used for error notification. The lamp channels having high priority, such as the lamp channels dwCH12, dwCH13 and dwCH14, are used for rendering with relatively high reliability such as continuous notice and final notice. In addition, a lamp channel with medium priority is used for moving object effects, and a lamp channel with relatively low priority is used for effects with relatively low reliability such as conversation notices and step-up notices, and lamps with even lower priorities The channel is usually used for lamp effects synchronized with fluctuation, reach and the like.
When the operations of a plurality of lamp channels dwCH overlap as shown in FIG. 29B due to the setting of such priorities, the lighting operation of the lamp channels with high priorities is executed. For example, from time t0, the lighting operation based on the lamp channels dwCH0 and dwCH5 is limited, and LED driving data is generated so that lighting based on dwCH8 is performed. In order not to reflect the information of the low priority lamp channel, mask data to be described later is used.

Subsequently, in step S705 in FIG. 26, the effect control CPU 200 confirms whether the value of the on lighting number (lmpNo) is within the normal range. The normal range is a range in which numbers exist as lamp data of the lamp data table shown in FIG. 31A.
If the execution lighting number (lmpNo) is abnormal, the process proceeds to step S719. Also in the case of a vacant channel in which the ramp channel dwCHn is not registered, the process proceeds to step S719 as an abnormality here.

If the execution lighting number (lmpNo) is normal, the process proceeds to step S706. In step S706, the effect control CPU 200 specifies an address of the lamp data table corresponding to the execution lighting number (lmpNo) registered in the lamp channel dwCHn and the execution line (ofset).
In step S707, the execution lighting number (lmpNo) registered in the lamp channel dwCHn and the address of the mask data table are specified.
In order to specify the address, the effect control CPU 200 refers to a lamp data address table as shown in FIG. In the lamp data address table, addresses of lamp data numbers for realizing each lighting pattern, for example, total blink, right blink, left blink, special item lighting and the like are shown. The numbers on the left end of FIG. 30 are the lamp numbers shown in the lamp sub-scenario table of FIG. 25A. The stored address is described.
Further, in the column of the address of mask data, an address at which mask data required to execute the lighting pattern of the lamp data number is stored. For example, when the lighting pattern of the right side blinking of the lighting number 5 is performed, a center case mask is required, but the address of mask data for performing the center case mask is described.

FIG. 31A shows lamp data 1 and 2 as a part of the lamp data table.
In each line of the lamp data of each number, time data and lighting data as a timer (frame) are described. A timer (frame) defines a time for generating LED drive data based on lighting data of each line.
The lighting data is described corresponding to each LED driver 90. In FIG. 4, it is assumed that n LED drivers 90 are present in the frame driver unit 61 and m LED drivers 90 are present in the board driver unit 62. In that case, each line of lamp data is as shown in FIG. 31A. Lighting data is described corresponding to each of the (n + m) LED drivers 90. In the figure, the correspondence with each LED driver 90 is indicated by w1 to w (n) and b1 to b (m) by slave addresses of the LED driver 90.
As lighting data, 4 bits (0h to Fh) are allocated to one current terminal 96 (one series of LED driving current generation) of the LED driver 90 described in FIG. 4 and FIG. 5 (“h” is Hexadecimal notation is shown), and 16 levels of luminance are designated. As described in FIG. 5, the LED driver 90 has 24 current terminals 96-1 to 96-24. For this reason, one lighting data is information of (4 × 24) bits as in “FFFF000055550000AAAAAAAA (h)”. If the lighting data for the LED driver 90 (w1) is "FFFF000000000000555550,000 (h)" as in the first line of the lamp data 1 shown, the current terminals 96-1 to 96 of the LED driver 90 (w1) -4 outputs a drive current for emitting the maximum luminance "F", and the current terminals 96-5 to 96-16 and 96-21 to 96-24 do not emit light (minimum luminance), the current terminal 96-17 .About.96-20 is information for designating output of the drive current as the luminance "5".
Such lighting data is set in the lamp data for each of the LED drivers 90 (w1 to w (n), b1 to b (m)), and they are set for each line. A predetermined light emission pattern which changes in time series is shown. (In the figure, the lighting data is illustrated only in part. The blank part is not shown and the lighting data is actually described.)

In the example of FIG. 31A, a part (areas Azh and Aj) of areas corresponding to the LED drivers 90 having slave addresses “b2” and “b3” are hatched. In the shaded areas Azh and Aj, dummy data (for example, all “0”) is described.
The areas Azh and Aj are data areas corresponding to the current terminals to which the LED 120 as the light source for situation presentation is connected in the LED drivers 90 with slave addresses “b2” and “b3”.

As described in FIG. 7, the LED driver 90 with the slave address “b2” corresponds to the current terminals 96-1 to 96-8 and the light emitting units 20H-1 to 20H-8 as the light emitting unit 20H for number-of-holds display. The LED 120 is connected. Moreover, LED120 corresponded to the light emission parts 20Z-1-20Z-3 as light emission part 20Z for symbol identification is connected to the current terminals 96-9-96-11.
In the ramp data table of FIG. 31A, the area of (4 × 11) bits corresponding to the current terminals 96-1 to 96-11 of the slave address “b2” is the area Azh shown by the hatched portion. Dummy data is arranged.

Further, as described above, the LED driver 90 of the slave address "b3" corresponds to the current terminals 96-1 to 96-3 and the LED 120 corresponding to the light emitting units 20J-1 to 20J-3 as the game state notifying light emitting unit 20J. Is connected.
In the ramp data table of FIG. 31A, the area of (4 × 3) bits corresponding to the current terminals 96-1 to 96-3 of the slave address “b3” is an area Aj indicated by a hatched portion. Dummy data is arranged.

  The dummy data of these areas Azh and Aj will be replaced with light emission drive data for status presentation (for gaming status notification, for holding number display, for gaming status notification) in the processing of step S721 described later.

FIG. 31B shows mask data 1 to 5 as an example of the mask data table. Each mask data is a mask for driving the light emitting unit 20 w on the frame side, a mask for driving the light emitting unit 20 b on the panel side, a mask for the entire case, a mask for the center case, and a mask for a part The necessary mask patterns are stored, for example, for
For each of the mask data 1 to 5, “0 h” for no light, no mask for each current terminal 96-1 to 96-24 of each LED driver 90 (w1 to w (n), b1 to b (m)) It is considered as the data shown by "Fh".
For example, with regard to the mask data 1, regarding the LED driver 90 (w1 to w (n)) in the frame driver unit 61, “0000... 00 (h)” and each current terminal 96-1 to 96- 24 is set to be unlit, and for the LED driver 90 (b1 to b (m)) of the board driver unit 62, "FFFF ..... FF (h)" and each current terminal 96-1 to 96-24 About no mask is set. That is, it is data specifying that only the light emitting unit 20w on the frame side is to be masked. (In the mask data 4 and 5, illustration of data values is omitted.)

  In each mask data, areas Mzh and Mj corresponding to areas Azh and Aj in which dummy data is arranged in the ramp data are all “Fh” indicating no mask. That is, of the mask data, an area of (4 × 11) bits corresponding to current terminals 96-1 to 96-11 of slave address "b2" and current terminals 96-1 to 96-3 of slave address "b3". The mask setting is not performed for the (4 × 3) bit area corresponding to.

In steps S706 and S707 in FIG. 26, an address corresponding to the lamp channel dwCHn being processed is specified in such a lamp data table and mask data table.
Subsequently, at step S 708, the effect control CPU 200 acquires a timer (frame) of the corresponding line (line indicated by the execution line (offset) of the lamp channel dwCHn currently targeted) in the lamp data table and substitutes this into the variable Dtime. .

  In step S709, the effect control CPU 200 develops the corresponding lighting data and mask data specified in the above steps S706 and S707, and generates LED driving data. Although this process will be described later, the process is to reflect the lighting data and mask data for the lamp channel dwCHn currently being processed on the LED drive data to be output.

In step S710, the execution time (time) which is information of the ramp channel dwCHn is incremented by one.
In step S711, the variable Dtime is compared with the execution time (time). The timer (frame) of the line currently being executed is assigned to the variable Dtime. The execution time (time) is incremented by one in step S710 in the LED drive data update process (every 16 ms). Therefore, when Dtime ≦ time, it becomes the end timing of the current line. If it is not Dtime ≦ time, the process proceeds from step S711 to S719 as it does not reach the end of the current line. If Dtime ≦ time, the process proceeds from step S711 to step S712 as the end of the current line.
At step S 712, the effect control CPU 200 resets the execution time (time) to zero. In step S713, the value of the execution line (offset) is incremented by one. In other words, the next line is targeted.
In step S714, the effect control CPU 200 specifies the address of the lamp data table corresponding line corresponding to the execution line (offset). Then, in steps S715 and S717, it is checked whether the end code (D_DTEND) is described in the line or whether the loop code (LMP_LP) is described.
If the end code (D_DTEND) is described, the registered lighting number of the lamp channel dwCHn is updated to 0 in step S716. In other words, it indicates that the processing according to the registration of the lamp channel dwCH is completed on the work.
If the loop code (LMP_LP) is described, the value of the execution line (offset) is updated to the address of the loop destination in step S718.

At step S719, the effect control CPU 200 calculates a checksum of LED drive data at the time of the lamp channel dwCHn. In step S720, backup data is saved.
This completes the LED data update for one lamp channel dwCHn. As the loop processing LP2, the above processing is sequentially performed to the ramp channels dwCH0 to dwCH15.

The update of the LED drive data in each lamp channel dwCHn is performed in step S709, which is the following process.
FIG. 32A schematically shows an output data buffer (light emission drive data storage unit) which stores LED drive data generated by expanding the lighting data and the mask data.
The output data buffer is prepared corresponding to each of the LED drivers 90 (w1 to w (n), b1 to b (m)) as well as the lamp data table and the mask data table. One mass shown indicates a buffer area of (4 × 24) bits of information corresponding to one LED driver 90.

For such an output data buffer, in step S709, processing is performed to expand mask data by AND (logical product) and expand lighting data by OR (logical sum). This is sequentially performed in step S709 for each ramp channel dwCH0 to dwCH15 by loop processing (LP2).
For example, at time t0 shown in FIG. 29, in the output data buffer, mask data (see FIG. 30: no mask) of lamp data 2 is AND-expanded, and lighting data of the third line of lamp data 2 is OR-expanded After the state, the mask data (see FIG. 30: center case mask) of the lamp data 5 is AND-expanded, and the lighting data of the second line of the lamp data 5 is OR-expanded.
As described above, in the mask data, 0h (= 0000) is turned off and Fh (= 1111) is not masked. Therefore, expanding the mask data by AND means that the bit to be turned off (masked) is set to "0" and the bit not to be masked is not changed for the value of the output data buffer up to that point.
Further, expanding the lighting data by OR means that the lighting data of the lamp channel dwCH being processed is reflected in the masked output data buffer.
By sequentially performing this processing for the lamp channels dwCH0 to dwCH15, LED drive data with higher priority given to lamp channels with higher numbers is formed on the output data buffer.

  Thus, in the lamp data registration information (see FIG. 22B), when a plurality of types of lamp data corresponding to a plurality of light emission effects are set in a plurality of hierarchies to which a priority is set, the priority order is low. By reflecting the lamp data and creating the LED drive data for the light emission effect, it becomes possible to generate the LED drive data for the light emission effect reflecting the priority with a simple process.

When LED drive data based on lamp data specified by the lamp channels dwCH0 to dwCH15 are generated in the loop processing LP2 of FIG. 26, the effect light emitting units 20w and 20b are generated based on a plurality of types of lamp data as the LED drive data. It can be said that the light emission drive information for rendering for is generated.
However, at this time, the LED drive data on the output data buffer of FIG. 32A is (4 × 11) bit area DBzh corresponding to current terminals 96-1 to 96-11 of slave address “b2” and slave address “b3”. The dummy data of the areas Azh and Aj of the ramp data table is expanded for the (4 × 3) bit area DBj corresponding to the current terminals 96-1 to 96-3 of The light emission drive information for status presentation (for variable symbol identification, for display of number of reservations, for notification of gaming state) for the light emitting units 20Z, 20H, 20J is not reflected.

  Therefore, in step S 721 of FIG. 26, the effect control CPU 200 generates light emission drive information for situation presentation (for variable symbol identification, for holding number display, for playing state notification), develops this in an output data buffer, and outputs On the data buffer, LED drive data for one timing in which the light emission drive information for presentation and the light emission drive information for situation presentation are combined is created.

A processing example of step S721 will be described with reference to FIG.
At step S731, the effect control CPU 200 checks the symbol fluctuation flag. As described in FIG. 16C, the effect control CPU 200 sequentially performs the first special symbol variation flag FZ1, the second special symbol variation flag FZ2, and the normal symbol variation flag FZ3 according to the symbol designation command from the main control unit CPU 100. Is set. In step S731, these symbol variation flags (FZ1, FZ2, FZ3) are confirmed, and in accordance with each symbol variation flag, step S732 corresponds to the current terminals 96-9 to 96-11 of the slave address "b2" (4 × 3) Set the light emission drive data of bit. Then, in step S733, this is expanded into the corresponding area on the output data buffer (ie, the second half 4 × 3 bits of the area DBzh).

In this case, although not to set the tone value of the light-emitting portion 20 Z -1,20 Z -2,20 Z -3 for variation pattern discrimination, if for each to turn "Fh: (= 1111 In the case of the light off, "0h (= 0000)". In the case of blinking, "Fh" and "0h" are set alternately at predetermined timings. Therefore, if it is a state where the symbol variation flag instructs to blink, is it the timing when this time is "Fh"? , It separately manages whether it is the timing to set to "0h".
And each "0h" or "Fh" and has been tone values for the three light-emitting portion 20 Z -1,20 Z -2,20 Z -3 to (4 × 3 bits), on the output data buffer, area Expand to 4 × 3 bits in the second half of DBzh. At this time, in the case of lighting ("Fh"), OR expansion is performed, and in the case of light extinction ("0h"), AND expansion is performed. Since the dummy data is all zero data, whereby each tone value of the light-emitting portion 20 Z -1,20 Z -2,20 Z -3 is reflected in the LED driving data on the output data buffer.
In the case the dummy data as in this example is "0h", in either case the gradation values of the light-emitting portion 20 Z -1,20 Z -2,20 Z -3 is the "0h" and "Fh" However, OR expansion may be performed on the area DBzh.
However, in the case of OR expansion, when dummy data (“0h”) is rewritten to some value due to noise or the like, the undefined data is output. On the other hand, as described above, in the case of light off ("0h"), if AND expansion is performed, "0h" is obtained in the case of light off ("0h") regardless of the value of the dummy data. it can. In other words, by performing OR expansion in the case of lighting (“Fh”) and AND expanding in the case of light extinction (“0h”), light emitting units 20 Z −1, 20 Z − are realized regardless of changes in dummy data due to noise or the like. LED drive data each gradation value is correctly reflected on 2,20 Z -3 can be generated on the output data buffer.

Subsequently, in step S734, the effect control CPU 200 checks the number of reservations. This FIG. 17A, as described with reference to FIG. 17B, the effect control CPU200 is sequentially updated pending addition command from Omosei your C PU 100, a first number of holding in accordance with the pending subtraction command, a second number of pending doing. Step S734 first number of holding of the second check the number of holding, in step S735 in accordance with these values, corresponding to the current terminal 96-1～96-8 slave address "b2" (4 × 8 ) Set the light emission drive data of the bit. Then, in step S736, this is expanded into the corresponding area on the output data buffer (ie, the first half 4 × 8 bits of the area DBzh).

  In this case, the tone values for the light emitting units 20H-1 to 20H-8 for displaying the number of reservations are set, but for each case, "Fh" for lighting and "0h" for lighting off. . Then, each gray scale value (4 × 8 bits) for eight light emitting units 20H-1 to 20H-8, which are set to “0h” or “Fh”, respectively, 4 × 8 in the first half of the area DBzh on the output data buffer OR expand (with “Fh”) or AND (with “0h”) to a bit. Since the dummy data is all 0 data, the gradation values of the light emitting units 20H-1 to 20H-8 are reflected on the LED drive data on the output data buffer by this development.

  Subsequently, the effect control CPU 200 checks the game state notification flag in step S737. As described in the description of FIG. 17C, the effect control CPU 200 sequentially sets, for example, flags FJ1 and FJ2 indicating “big hit”, “probable change”, and “time in the middle” in response to the status notification command from the main control unit CPU 100. I have set FJ3. Step S7317 confirms these gaming state notification flags (FJ1, FJ2, FJ3), and corresponds to the current terminals 96-1 to 96-3 of the slave address "b3" according to the respective gaming state notification flags in step S738. Light emission drive data of (4 × 3) bits are set. Then, in step S739, this is expanded into the corresponding area (ie, 4 × 3 bits of area DBj) on the output data buffer.

In this case, the tone values for the light emitting units 20J-1, 20J-2 and 20J-3 for notifying the gaming state are set, but "Fh" for turning on each and "off" for turning off It is assumed that 0h.
Then, each gray scale value (4 × 3 bits) for the three light emitting units 20J-1, 20J-2 and 20J-3, which are set to “0h” or “Fh”, respectively, in the output data buffer OR expansion (in the case of “Fh”) or AND expansion (in the case of “0h”) to × 3 bits. Since the dummy data is all 0 data, the gradation values of the light emitting units 20J-1, 20J-2, and 20J-3 are reflected on the LED drive data on the output data buffer by this expansion.

At step S740, the effect control CPU 200 calculates a checksum of the developed LED drive data. In step S741, backup data is saved.
The process of FIG. 27 described above is performed as step S721 of FIG. In this state, on the output data buffer of FIG. 32, for effect presentation light emission information for effect presentation light emission units 20 w and 20 b and for light emission units 20 Z, 20 H and 20 J for situation presentation (for fluctuation symbol identification, The LED drive data for one timing in which the light emission drive information of the number-of-holds display and the game state notification is synthesized is generated and stored.

[6-7: LED Output Processing of First Embodiment]

The LED drive data generated by the LED data update process as described above is actually output to each LED driver 90 in step S115 of FIG.
In the present embodiment, the effect control CPU 200 substantially transmits serial data of one transmission unit of LED drive data to the drive signal output means (frame driver unit 61 and board driver unit 62) of the first system and the second system. Output simultaneously.
For example, as shown in FIG. 32B, the LED drive data is transmitted to the LED driver 90 (w1 to w (n)) of the frame driver unit 61 by the serial data transmission channel ch1, and the panel driver unit 62 is transmitted by the serial data transmission channel ch2. The LED drive data is transmitted to the LED driver 90 (b1 to b (m)).
In the present embodiment, transmission of LED drive data by the serial data transmission channels ch1 and ch2 is performed in parallel and simultaneously, but may not necessarily be simultaneous.

FIG. 33 shows a serial data structure of LED drive data transmitted to one LED driver 90.
For example, to each of the LED drivers 90 (w1 to w (n) and b1 to b (m)) shown in FIG. 32B, LED drive data is transmitted as serial data of the structure of FIG. Note that FIG. 33 shows the serial data DATA and the enable signal ENABLE described in FIG. 4 and FIG.
The serial data is sequentially transmitted byte by byte in a period in which the enable signal ENABLE is turned ON. That is, each byte of serial data of the structure is one transmission unit.

The serial data DATA includes 1-byte slave address, 1-byte data setting start register address (SX), 1-byte write data to address (SX), write data to address (SX + 1),. • It consists of a total of 26 bytes of write data to the address (SX + 23).
Such serial data DATA is taken into the LED driver 90 during a period defined by the enable signal ENABLE.

“Slave address” is a device ID of each LED driver 90, and is a 1-byte code identifying w1 to w (n) or b1 to b (m).
The “data setting start register address (SX)” is information for specifying the head of a register for capturing data in the LED driver 90. For example, it is designation information of the internal register of the data buffer / PWM controller 93 of FIG. The LED driver 90 employed in the present embodiment is provided with, for example, registers (8 bits each) of register addresses 00h to 2Ch for capturing serial data. Among them, 24 registers (8 bits each) of register addresses 15h to 2Ch are registers (tones for inputting lighting data (PWM tone instruction data) corresponding to 24 current terminals 96-1 to 96-24. Value setting unit). Therefore, the register address 15h is designated as the "data setting start register address (SX)".
As "write data to address (SX)", write data to the register of the register address ("15h" in this embodiment) designated by "data setting start register address (SX)", that is, the current terminal LED drive data corresponding to 96-1 is set.
As "write data to address (SX + 1)", write data to the register of register address +1 ("16h" in this embodiment) designated by "data setting start register address (SX)", that is, current The LED drive data corresponding to the terminal 96-2 is set.
The same applies to “the write data to address (SX + 23)”, the register address +23 (“2 Ch” in the present embodiment) designated by “data setting start register address (SX)”. Write data, that is, LED drive data corresponding to the current terminals 96-24 are set.

Although the write data has an 8-bit structure, one lighting data has a 4-bit structure of “0 h (= 0000)” to “Fh (= 1111)” as described above. The 4 bits represent the brightness of 16 gradations. On the other hand, each register (each 8 bits) of the register addresses 15h to 2Ch to which the PWM gradation instruction data is input can correspond to 256 gradations by 8 bits.
In the case of the present embodiment, since the lighting data is data of 16 gradations, the lighting data is set in the upper 4 bits as the 8-bit write data to each register of the register addresses 15h to 2Ch. There is. This point will be described later.
Further, although it has been stated in step S113 in FIG. 13 that the LED driver 90 is to be initialized, specifically, this is transmission processing in which default values are set in the registers of register addresses 00h to 14h which are not used. This point will also be described later.

The LED drive data output process performed in step S115 of the 16 ms process will be described with reference to FIG.
At step S801 in FIG. 28, the effect control CPU 200 specifies the top address of the LED drive data (output data buffer in FIG. 32A) of the serial data output channels ch1 and ch2 corresponding to the start value.
The start value is the value of the LED driver 90 to be transmitted first. In this embodiment, transmission is first performed from the serial data output channels ch1 and ch2 to the LED driver 90 (w1) and the LED driver 90 (b1), respectively. The head address storing the LED drive data and the head address storing the LED drive data for b1 are specified.

  Next, in step S802, the effect control CPU 200 specifies slave addresses of the serial data output channels ch1 and ch2 corresponding to the start value. That is, it is an address code indicating "w1" and "b1".

Then, as the loop processing LP3, the processing of steps S803 to S815 is looped and executed for the number of driver numbers.
The serial data output channel ch1 transmits to the n LED drivers 90 of the frame driver unit 61, and the serial data output channel ch2 transmits to the m LED drivers 90 of the panel driver unit 62. The number of times of loop processing is n times or m times (n or the larger value of m). If n <m, then m times.

In step S803, the effect control CPU 200 turns on the enable signal ENABLE in the serial data output channels ch1 and ch2.
Then, in step S804, the effect control CPU 200 transmits data of the first transmission unit (1 byte) as the output of the serial data DATA of the serial data output channels ch1 and ch2, that is, in this case, the serial data structure shown in FIG. Sends out and outputs the first 1 byte slave address. Data transmission is simultaneously and simultaneously performed on the serial data output channels ch1 and ch2.
When transmission of one transmission unit is performed, in steps S 805 and S 806, completion of transmission output for each of the serial data output channels ch 1 and ch 2 is awaited.

When transmission output completion for the serial data output channels ch1 and ch2 is confirmed, the effect control CPU 200 causes the data setting start register address (SX) as data transmission of the next transmission unit (1 byte) in step S807. In the case of 15h) send out. Also in this case, data transmission is simultaneously and simultaneously performed on the serial data output channels ch1 and ch2.
When transmission of one transmission unit is performed, in steps S 808 and S 809, transmission output completion for each of the serial data output channels ch 1 and ch 2 is awaited.

When completion of transmission output for serial data output channels ch1 and ch2 is confirmed in steps S808 and S809, in step S810, the effect control CPU 200 transmits data of one transmission unit (1 byte) as the register address (SX = 15h) to Sends and outputs write data (= LED drive data) to (SX + 23 = 2Ch).
First, 1-byte LED drive data transmission to the register address (15h) is simultaneously performed in parallel on the serial data output channels ch1 and ch2. Then, in steps S811 and S812, the transmission output completion for each serial data output channel ch1 and ch2 is waited.
When the transmission completion is confirmed, transmission of step S810 is executed byte by byte until transmission of LED drive data of a total of 24 bytes, that is, register addresses 15h to 2Ch is confirmed in step S813. Therefore, next, 1-byte LED drive data transmission to the register address (16 h) is performed for the serial data output channels ch1 and ch2. Further, after the transmission confirmation, LED drive data transmission to the register address (17 h) is performed. Thereafter, the transmission completion standby → LED drive data transmission to the register address (18 h) → transmission completion standby → LED drive data transmission to the register address (19 h) → transmission completion standby ... → LED to the register address (2 Ch) A process of drive data transmission → transmission completion standby is performed.

When transmission output of 24 bytes is completed for LED drive data, serial data output to one LED driver 90 of the structure of FIG. 33 is completed. Therefore, in step S814, the enable signal ENABLE is turned off, and the target slave address is incremented by one. And I finish one loop process.
FIG. 34 shows data transmitted in the above-mentioned one loop process. Slave addresses, data setting start register addresses, LED drive data LPDT1, LPDT2,..., LPDT24 are sequentially transmitted in parallel on the serial data output channels ch1 and ch2 as shown.
Such transmission is performed, and the LED drive data is set in the LED driver 90. On the LED driver 90 side, each current terminal 96-1 is based on the light emission luminance (16 gradations of 0h to Fh) indicated by the LED drive data LPDT1, LPDT2. The amount of current of -96-24 is controlled, and light emission of the LEDs 120 of each series connected to the current terminals 96-1 to 96-24 is performed.

Subsequently, as the second loop process, the processes of steps S803 to S815 are similarly performed for the LED driver 90 (w2) and the LED driver 90 (b2). Thereafter, as the third loop processing, the processing of steps S803 to S815 is similarly performed for the LED driver 90 (w3) and the LED driver 90 (b3).
Thereafter, the loop processing LP3 is repeated until transmission to all of the LED driver 90 (w (n)) and the LED driver 90 (b (m)). In the case of n <m, after serial data transmission to all of the n LED drivers 90 of the frame driver unit 61 is completed, steps S803 to S815 are performed only for the remaining LED drivers 90 of the panel driver unit 62. Processing will be performed.
Serial data output to the (n + m) LED drivers 90 as shown in FIG. 32B is executed by m loop processes LP3 and LED drive data output (processing of step S115 in FIG. 13) is completed. If the number of the mounted LED drivers 90 is different, the number of times of loop naturally changes.
Although the above example is described using two serial data output channels ch1 and ch2, serial data transmission is simultaneously performed in parallel even when three or more serial data output channels are used. You should do it.

As in the process of FIG. 28 described above, in the present embodiment, the effect control CPU 200 is a drive signal output unit (frame driver) for the first system (serial data output channel ch1) and the second system (serial data output channel ch2) Serial data of one transmission unit is simultaneously transmitted to the unit 61 and the board driver unit 62). After completion of the transmission, serial data of the next transmission unit is transmitted substantially simultaneously to the drive signal output means of the first system and the second system. By such processing, LED drive data is transmitted to each LED driver 90.
As a result, the time required for the entire serial data transmission operation can be shortened, and the processing load on the effect control CPU 200 can be reduced.

The reason is explained.
FIG. 35 shows the write timing of the clock signal CLK used for serial data transmission by the effect control CPU 200, transmission data, TDRE (transmission data empty flag), and transmission data to the transmission data register.
The transmission data corresponds to the above-described slave address, data setting start register address, LED drive data LPDT1, LPDT2,..., LPDT24. Here, eight bits as one transmission unit are shown as data d0 to d7.

In the case of transmitting 8-bit data of one transmission unit in steps S804, S807, and S810 of FIG. The transmission data written to the transmission data register is transmitted and output by one bit at each timing of the clock signal CLK.
Here, TDRE is “0” when transmission data is written to the transmission data register, and indicates that valid data exists in the transmission data register. When the data of the transmission data register is actually transmitted and output (loaded to the transmission shift register) and transmission is started, it becomes "1", indicating that valid data is not present in the transmission data register.
Therefore, as transmission processing of the effect control CPU 200, it is confirmed that TDRE has become "1", the 8-bit transmission data is written to the transmission data register, and the next 8-bit transmission data is written next Wait until TDRE becomes "1". That is, the processing of the next transmission data can not be performed in the period shown as the waiting time TW in FIG.

With regard to serial data transmission, conventionally, serial data of one transmission unit (8 bits) is transmitted from one serial data output channel to, for example, drive signal output means of the first system, and after the transmission is completed, from the next transmission channel The transmission operation is performed such that serial data of one transmission unit (8 bits) is transmitted to the drive signal output means of the second system. For example, the processes corresponding to steps S804 to S806 in FIG.
(ST1) Slave address output from ch1 (write to transmission data register)
(ST2) Transmission output completion wait (ST3) Data setting start register address output from ch1 (writing to transmission data register)
(ST4) Wait for transmission output completion (ST5) Output LED drive data LPDT1 from ch1 (write to transmission data register)
(ST6) Transmission output completion standby (ST7) ch1 LED drive data LPDT2 output (ST8) transmission output completion standby ··············
(ST51) ch1 LED drive data LPDT 24 output (ST52) transmission output completion standby (ST53) ch2 slave address output (ST54) ch2 transmission output completion standby (ST55) ch2 data setting start register address output (ST56) transmission output completion Standby (ST57) ch2 LED drive data LPDT1 output (ST58) transmission output completion standby (ST59) ch2 LED drive data LPDT2 output (ST60) transmission output completion standby ...
(ST103) Output of LED drive data LPDT 24 from ch2 (ST104) transmission output completion standby is performed.
In this case, a waiting time occurs for each transmission of one transmission unit in each of the serial data output channels ch1 and ch2, and transmission processing efficiency is poor.
On the other hand, in the present embodiment,
(S804) Slave address output from ch1 and ch2 (writing to transmission data register)
(S805, S806) The processing can be streamlined by simultaneously performing transmission processing on both serial data output channels ch1 and ch2 such as ch1 and ch2 transmission output standby.
The same applies to the processes of steps S807 to S809 and the processes of steps S810 to S812.

Then, transmission to one LED driver 90 is equivalent to 26 bytes (one write to the transmission data register 26 times) for each transmission channel in one loop processing. If simultaneous processing is not performed for each of the serial data output channels ch1 and ch2, the total standby time is approximately (52 × TW) in one loop processing period. In the case of this embodiment, this can be significantly shortened to approximately (26 × TW) in one loop processing period.
In the LED drive data output process of step S115 of FIG. 13, the efficiency of the serial data output process can be improved as described above, so that the processing load on the effect control CPU 200 is greatly reduced.

Further, in the present embodiment, the LED drive data transmitted as serial data is data indicating light emission luminance (tone), and as described above, the light emission drive of 16 tones is realized by 4 bits, for example. By enabling such gradation control, more various effects can be realized.
In the present embodiment, an example of 16 gradations has been described, but of course more gradations may be used.

The pachinko gaming machine 1 of the present embodiment is provided with a frame (front frame 2, outer frame 4 and glass door 5) and a game board (game board 3) attached to the frame. The drive signal output unit (frame driver unit 61) of the first system is provided with a plurality of driver circuits (LED drivers) for outputting LED drive signals to the lamp unit 63 (light emitting unit 20w) which is rendering unit provided in the front frame 2. 90), and the drive signal output means (the board driver unit 62) of the second system is LED driven to the lamp unit 64 (the light emitting units 20b, 20Z, 20H, 20J) which is the presentation means provided on the game board 3 It is comprised by the several driver circuit (LED driver 90) which outputs a signal.
With such a configuration, all the LED drivers 90 of the frame driver unit 61 correspond to the light emitting units 20 w on the frame side, and all the LED drivers 90 of the panel driver unit 62 correspond to the light emitting units 20 b on the panel side. As a result, it is possible to realize the simplification of wiring, the improvement of efficiency, the ease of setting of presentation control, and the like.

By the way, in the present embodiment, in step S810, the lighting data having the 4-bit structure as described above is converted into 8-bit data and output as serial data of one transmission unit.
This bit conversion will be described with reference to FIG. FIG. 36A shows an example of 4 × 24 bits of lighting data transmitted to one LED driver 90. That is, it is an example of data corresponding to one square of the output data buffer of FIG. 32A. The head "F8h"("h" is omitted in the figure) is lighting data to be transmitted to the register addresses 15h and 16h of the LED driver 90, that is, "Fh" writes to the register address 15h of the LED driver 90. "8h" is lighting data as a gradation value for the current terminal 96-2 to be written to the register address 16h as the gradation value for the terminal 96-1. The next “0 Fh” similarly corresponds to the register addresses 17 h and 18 h. Likewise, the last "00h" corresponds to the register addresses 2Bh and 2Ch.

Here, in the case of dividing into 8-bit units as internal processing units of the effect control CPU 200 as in “F8h” “0Fh” to “00h” in FIG. 36A, the upper 4 bits (for example, “F8h” Among them, "Fh" is lighting data for odd register address (for example, register address 15h), and lower 4 bits (for example, "8h" of "F8h") is lighting data for even register address (for example, register address 16h) It becomes.
Here, “odd register address” and “even register address” are examples corresponding to the register design of the LED driver 90. The destination is merely described for convenience as the case where the register addresses 15h to 2Ch are used.
In this case, the effect control CPU 200 masks the lower 4 bits of 8-bit data and transmits it to the LED driver 90 for lighting data to the odd register addresses (15 h, 17 h,... 2 Bh). On the other hand, for lighting data to the even register addresses (16h, 18h,... 2Ch), the effect control CPU 200 masks the upper 4 bits of the 8-bit data and shifts it by 4 bits to the LED driver 90. Send. That is, as a result, 4 bits of lighting data are converted into 8 bits and transmitted.

As this bit conversion, the case of "F8h" is shown to FIG. 36B and FIG. 36C.
FIG. 36B shows a process of transmitting lighting data “Fh” to the register address 15 h. The lighting data extracted from the output data buffer of FIG. 32A is “F8h” = “11111000” which is two lighting data of 4 bits each. The lower 4 bits are masked for this data. For example, an AND operation is performed using mask data “F0h” = “11110000”. As a result, as shown, serial data "11110000" = "F0h" to be transmitted to the register address 15h is obtained. In this case, the drive current output of the maximum gradation value (F0h) is performed from the current terminal 96-1.
On the other hand, FIG. 36C shows a process for transmitting the lighting data "8h" to the register address 16h. As described above, the lighting data extracted from the output data buffer of FIG. 32A is “F8h” = “11111000”. The upper 4 bits are masked for this data. For example, an AND operation is performed using mask data “0Fh” = “00001111”. As a result, data "00001000" is obtained as illustrated. Further, in this case, serial data "10000000" = "80h" to be transmitted to the register address 16h can be obtained by shifting the data by 4 bits. In this case, an intermediate gradation value (80 h) drive current is output from the current terminal 96-1.

As described above, in the present embodiment, the effect control unit 51 causes the effect brightness information of the second bit number (for example, 4 bits) to be smaller than the first bit number (for example, 8 bits) in the effect control ROM 201, for example. (Lighting data) is stored in the form of a lamp data table or the like. Then, the effect control CPU 200 converts the light emission luminance information of the second bit number into the first bit number to generate LED drive data, and the LED drive data is serialized to the LED driver 90 which is a light emission drive signal output unit. Send.
The fact that the register addresses 15h to 2Ch of the LED driver 90 can input 8-bit PWM data means that if 8-bit lighting data is used, LED light emission control of 256 gradations is possible. However, 256 gradations are not necessary for controlling the light emitting units 20w and 20b used for the light emission effect of the gaming machine of the present embodiment. Specifically, 16 gradations of "00h", "10h", "20h" ... "F0h" are sufficient.
Therefore, in the present embodiment, the lighting data has a 4-bit structure, and 16 gradations are represented. At the time of output to the LED driver 90, 4 bits are converted to 8 bits and transmitted.

By doing this, the effect control unit 51 can greatly reduce the data capacity of the lighting data stored in the internal ROM (effect control ROM 201), and can suppress the memory capacity consumption.
In addition, in recent years, a general-purpose LED driver of a high performance type such as 256 gradation has a large production amount and is often advantageous in price. Therefore, for example, when 16 gradations are required, cost merit can be obtained by adopting an LED driver with 256 gradations rather than adopting an LED driver with 16 gradation control capability, and it is stable. Availability is also good. This provides manufacturing and cost advantages.
Further, as described above, the effect control CPU 200 arranges 4-bit lighting data in the upper 4 bits in 8 bits, and generates 8-bit LED drive data (serial data to be transmitted).
As described above, with the upper 4 bits arranged, it is possible to generate LED driving data of 16 gradations, and the processing is a very simple processing as in the example of FIG. 36B and FIG. 36C, for example. For this reason, the processing burden of bit number conversion hardly poses a problem.

In the above example, the lighting data converted into 8 bits is "00h", "10h", "20h" ... "F0h", but the following example can be considered.
In this case, when the 4-bit lighting data is "Fh", the 8-bit serial data "F0h" has the maximum luminance in control, but the LED driver 90 can cope with "FFh". Therefore, the lower 4 bits of “F0h” of 8-bit serial data may be converted to “1111” to transmit “FFh” (= 11111111). That is, the serial data to be transmitted is "00h", "10h", "20h", ... "E0h""FFh". In this way, it is possible to execute light emission with maximum brightness on the light emission drive capability of the LED driver 90.
Also, for "10h""20h" ... "F0h" other than "00h", the lower 4 bits may be converted to "1111" and transmitted as "1Fh""2Fh" ... "FFh" . As a result, it is possible to increase the light emission luminance at each gradation and to improve the rendering effect.
Moreover, although the example which makes the lighting data of 4 bits 8 bits until now so far has been described, this is an example. The first bit number (for example, 8 bits) is determined according to the design of the LED driver. The second bit number (for example, 4 bits) may be set according to the gradation to be expressed. For example, it may be 1 bit for 2 gradations, 2 bits for 4 gradations, 3 bits for 8 gradations, and so on.
Further, in the present embodiment, LED drive data transmission is performed as serial data output, but the process of converting the lighting data of the second number of bits into the first number of bits and transmitting it to the light emission driving driver is parallel The present invention can also be applied to data output or wireless transmission output, and in this case, when there is a difference between the gradation capability of the transmission destination and the gradation expression to be obtained, the reduction effect of the data storage capacity of the transmission source can be obtained.

[6-8: LED driver initialization process]

Although it has been described in step S1113 in FIG. 13 that the LED driver 90 is to be initialized, this is transmission processing in which default values are set in the registers of the register addresses 00h to 14h which are not used.
As described above, the register addresses 15h to 2Ch of the LED driver 90 are registers to which lighting data (gradation values) corresponding to the current terminals 96-1 to 96-24 are written, respectively. Data is written to each of the registers as follows.

00h: PWM cycle setting data is set by 3 bits among 8 bits, and master / slave setting data is set by 1 bit.
01h: Each setting data of fade-in speed per gradation is set by three bits among eight bits, and fade-out speed is set by three bits.
02h: Red LED current value data is set at 5 bits out of 8 bits.
03h: Current value data of the green LED is set by 5 bits out of 8 bits.
04h: The current value data of the blue LED is set at 5 bits out of 8 bits.
05h: The on / off setting data of the current terminals 96-1 to 96-6 are set at six bits in eight bits.
06h: On / off setting data of current terminals 96-7 to 96-12 are set at six bits in eight bits.
07h: On / off setting data of the current terminals 96-13 to 96-18 are set at six bits in eight bits.
08h: On / off setting data of current terminals 96-19 to 96-24 are set at six bits in eight bits. The registers of the above register addresses 05h to 08h serve as on / off setting units for each of the current terminals 96-1 to 96-24.
09h to 0Eh: One of “PWM output priority”, “fade output priority”, and “forced on / off output priority” is selected and set in each register (8 bits) for each of 2 output terminals. The six resistors 09h to 0Eh correspond to the 24 current terminals 96-1 to 96-24.
0Fh to 11h: 3 registers (24 bits in total) set enable / disable of the fade function of 24 current terminals 96-1 to 96-24.
12h to 14h: Force on / off setting of 24 current terminals 96-1 to 96-24 is performed by three registers (24 bits in total).

In the initialization process of the LED driver 90, default values are set to these registers (00h to 14h). The default value is as follows. "0x" indicates hexadecimal notation as in "h". “0x” and “h” are used properly to distinguish between the value of the register address and the data value (default value).
00h: 0x00 ... Initial setting of PWM cycle 01h: 0x00 ... No slope of fade in / fade out 02h: 0x 1 F ... Initial setting of red LED current value 03h: 0x 1 F ... Initial setting of green LED current value 04h: 0x1F: Initial setting of blue LED current value 05h: 0x77: On setting of current terminals 96-1 to 96-6 06h: 0x77: On setting of current terminals 96-7 to 96-12 07h : 0x77 ... ON setting of current terminals 96-13 to 96-18 08h: 0x77 ... ON setting of current terminals 96-19 to 96-24 09h: 0x00 ... PWM output priority 0Ah: 0x00 ... PWM output priority 0Bh: 0x00 ... PWM output priority 0Ch: 0x00 ... PWM output priority 0Dh: 0x00 ... PWM Output priority 0Eh: 0x00: PWM output priority 0Fh: 0x00: fade function invalid 10h: 0x00: fade function invalid 11h: 0x00: fade function invalid 12h: 0x00: forced on / off setting All off 13h: 0x00 ... Forced on / off setting is all off 14h: 0x00 ... Forced on / off setting is all off

The setting of the default value as described above is performed on each of the LED drivers 90 (w1 to w (n) and b1 to b (m)) in step S113 of the 16 ms process of FIG.
FIG. 37 shows an example of the LED driver initialization process. FIG. 37 shows the initialization process for one LED driver 90. In step S113, the process of FIG. 37 is sequentially performed on each of the LED drivers 90 (w1 to w (n) and b1 to b (m)).

In step S901, the effect control CPU 200 turns on an enable signal (ENABLE) corresponding to the LED driver 90 that performs initialization. For example, the first slave address (for example, w1) is targeted at the beginning. Then, in step S902, the slave address of the target LED driver 90 is output.
Further, in step S903, the effect control CPU 200 outputs the data setting start register address. In this case, since data is written to the register addresses "00h" to "14h", the data setting start register address is set to 00h.
Then, in step S904, the effect control CPU 200 sequentially transmits data of default values corresponding to the respective register addresses "00h" to "14h". In this process, the above-described default value is written to each of the register addresses “00h” to “14h” of the LED driver 90 that is the target. That is, the LED driver 90 is initialized.
When the above is completed, the enable signal (ENABLE) is turned off in step S905, and the slave address is incremented by 1 in step S906. That is, the next LED driver 90 can be specified. Then, the initialization process for one LED driver 90 is completed.

Here, in the case of the present embodiment, as described above, serial data output of two systems as the serial data output channels ch1 and ch2 is performed.
FIG. 37 shows an initialization process for one LED driver 90, but according to the process of FIG. 37, for example, (n + m) pieces of LED drivers 90 (w1 to w (n), b1 to b (m)) The initialization may be performed one by one sequentially.

  However, by performing substantially simultaneous transmission using the serial data output channels ch1 and ch2, each LED driver 90 (w1 to w (n), b1 to b (m) of the frame driver unit 61 and the panel driver unit 62 can be transmitted. The initialization process for) can be streamlined. That is, the same method as the LED drive data transmission described above can be adopted. For example, as shown in the example of the output of LED drive data in FIG. 32B, transmission is performed simultaneously and in parallel using the serial data output channels ch1 and ch2. An example of processing in that case is shown in FIG.

As the process of FIG. 38, the effect control CPU 200 specifies slave addresses of the serial data output channels ch1 and ch2 in step S951. According to an example similar to FIG. 32B, the address code indicating “w1, b1” is specified.
Then, as the loop processing LP5, the processing of steps S952 to S964 is looped and executed for the number of driver numbers. If n <m, loop processing LP5 is performed m times.

At step S952, the effect control CPU 200 turns on the enable signal ENABLE in the serial data output channels ch1 and ch2.
Then, at step S 953, the effect control CPU 200 transmits data of the first transmission unit (1 byte) as the output of the serial data DATA of the serial data output channels ch 1 and ch 2, that is, in this case, shown in the serial data structure of FIG. Sends out and outputs the first 1 byte slave address. Data transmission is simultaneously and simultaneously performed on the serial data output channels ch1 and ch2.
When the transmission of one transmission unit is performed, in steps S954 and S955, the transmission output completion for each of the serial data output channels ch1 and ch2 is waited.

When transmission output completion for serial data output channels ch1 and ch2 is confirmed, the effect control CPU 200 transmits data setting start register address (SX) as data transmission of the next transmission unit (1 byte) in step S956. Do. Since writing to the register addresses 00h to 14h, SX = 00h. Also in this case, data transmission is simultaneously and simultaneously performed on the serial data output channels ch1 and ch2.
When the transmission of one transmission unit is performed, in steps S957 and S958, transmission output completion for each serial data output channel ch1 and ch2 is awaited.

When completion of transmission output for serial data output channels ch1 and ch2 is confirmed in steps S957 and S958, in step S959, effect control CPU 200 transmits data of one transmission unit (1 byte) as register addresses (00h) to (14h). Send out the default data to).
First, 1-byte default data transmission to the register address (00h) is simultaneously and concurrently performed on the serial data output channels ch1 and ch2. Then, in steps S960 and S961, the completion of transmission output for each serial data output channel ch1 and ch2 is awaited.
After confirming the completion of transmission, the transmission of step S959 is executed byte by byte until completion of transmission of the default data to the register addresses 00h to 14h is confirmed in step S962. Therefore, next, 1-byte default data transmission to the register address (01h) is performed for the serial data output channels ch1 and ch2. Further, after the transmission confirmation, default data transmission to the register address (02h) is performed. Also thereafter, transmission completion standby → default data transmission to register address (03h) → transmission completion standby → default data transmission to register address (04h) → transmission completion standby ... → default data transmission to register address (14h) → Processing of waiting for transmission completion is performed.

  When transmission output of default data to the register addresses 00h to 14h is completed, the enable signal ENABLE is turned off in step S963, and the slave address to be processed next is incremented by one. And I finish one loop process.

Subsequently, as the second loop process, the processes of steps S952 to S964 are similarly performed for the LED driver 90 (w2) and the LED driver 90 (b2). Thereafter, as the third loop process, the processes of steps S952 to S964 are similarly performed for the LED driver 90 (w3) and the LED driver 90 (b3).
The process of steps S 952 to S 964 is performed m times, whereby the LED driver initialization process of FIG. 38 is completed. That is, the initialization by the output of the default data to the (n + m) LED drivers 90 is completed. If the number of LED drivers 90 mounted is different, the number of loops may naturally be different.
In the above example, two serial data output channels ch1 and ch2 are used, but even when three or more serial data output channels are used, serial data (default data) can be simultaneously and concurrently It is sufficient if transmission is performed.

  As in the process of FIG. 38 described above, drive signal output means (frame driver unit) of the first system (serial data output channel ch1) and the second system (serial data output channel ch2) also regarding the initialization process of the LED driver 90 Serial data of one transmission unit is simultaneously transmitted with respect to 61 and the board driver unit 62). After completion of the transmission, serial data of the next transmission unit is transmitted substantially simultaneously to the drive signal output means of the first system and the second system. By performing the initialization process of the LED driver 90 in this process, the time required for the entire initialization process can be shortened, and the processing load on the effect control CPU 200 can be reduced.

In the present embodiment, as described above, initialization of each LED driver 90 is performed by serial data transmission of default data as initial setting data, whereby each LED driver 90 generates a gradation value indicated by LED drive data. Accordingly, the light emission drive signal for realizing the light emission luminance at the time of turning off, lighting, and lighting of the LEDs 120 connected to the current terminals 96-1 to 96-24 is output.
That is, the above-described default value (= on data) is always set by the initialization process for register addresses 05h to 08h which are on / off setting units for current terminals 96-1 to 96-24. All 1 to 96-24 are turned on, and further, by setting default values of the register addresses 09 h to 14 h, priority is given to PWM, and the fade function and the forced on / off function are invalidated. Therefore, each LED driver 90 performs PWM control based on the gradation value (the value of lighting data) written in the register addresses 15h to 2Ch, which are the gradation value setting units, and the current terminals 96-1 to 96-24. The light emission drive current of the amount corresponding to the gradation from the point of time is supplied.

That is, in the LED drive data output process of FIG. 28 performed in step S115 of FIG. 13, 16 of “00h”, “10h”, “20h”... “F0h” as LED drive data written to the register addresses 15h to 2Ch. Gradation data transmission is performed, but at the time of this LED drive data transmission, data of 16 gradations of “00h”, “10h”, “20h”. The controlled lighting (10h to F0h) is performed.
When this is viewed from the effect control CPU 200 side, all of the light emission luminance control at the time of lighting off, lighting, and lighting can be executed by the lighting data of 0h to Fh.
Thereby, in the effect control CPU 200, LED light emission control can be realized by simple setting of lighting data, the processing load is small, and the data capacity necessary for control can be reduced to only lighting data, and the capacity of the effect control ROM 201 etc. Reduced consumption is also realized.

In summary, the effect control unit 51 performs processing in which the register addresses 05h to 08h, which are on / off setting units, are always on, and generates LED drive data including a gradation value according to the game state. By transmitting to the LED driver 90 and setting the gradation value to the register addresses 15h to 2Ch as the gradation value setting unit, 16 gradations of "00h" ... "F0h" at the time of LED drive data transmission It is possible to execute control from turning off to turning on with gradation control only by transmitting data of (1).
In the present embodiment, initialization processing is performed every 16 ms as processing for setting the register addresses 05h to 08h, which are on / off setting units, to be always on, but it is turned off only by transmitting data of 16 gradations. In order to control from gradation control to lighting with gradation control, the register addresses 05h to 08h may be set to be always on. Therefore, for example, the effect control CPU 200 may perform initialization processing at the beginning of power-on, for example, and set the register addresses 05h to 08h to ON. This is also an example of processing in which the on / off setting unit is always on.

  In the above embodiment, the LED driver 90 defines the operation of the LED driver 90 and the first register (register address 15h to 2Ch) to which the LED drive data that changes according to the game state is set, the gaming state And a second register (register address 00h to 14h) in which fixed data (initialization data) which does not change according to the second register (register data 00h to 14h) is set. Then, the effect control unit 51 sets the LED drive data of the first register every predetermined period (every 16 ms processing), and sets the fixed data of the second register every predetermined period (every 16 ms processing). When viewed from the individual LED drivers 90, initialization data is set in the second register every 16 ms, and LED drive data (gradation value) is set in the first register every 16 ms.

In the case of the present embodiment, the set values of the register addresses 00h to 14h are always the above-mentioned default values during the game. Therefore, the process of setting the above-described default value in the second register as the initialization process may be performed once at startup or the like. However, the set values of the register addresses 00h to 14h may be destroyed or lost due to noise or the like, and the operation of the LED driver 90 may not be the operation intended by the LED drive data. On the other hand, in the present embodiment, by periodically performing the initialization process, even if the set values of the register addresses 00h to 14h are destroyed, it is possible to immediately restore the original initialization state. Thus, an accurate LED light emission operation based on the LED drive data is always performed. Thus, the output operation of the light emission drive signal based on the LED drive data can be stably maintained in the normal state.

<7. Second embodiment>

Subsequently, a driver configuration according to the second embodiment will be described. The configurations and processes similar to those of the first embodiment will be omitted, and only different points will be described.
FIG. 39 shows the connection configuration of the effect control unit 51 (effect control CPU 200) and the LED driver 130 in the same format as FIG. 4 in the first embodiment.
Also in this example, the effect control CPU 200 uses three serial data output channels ch1, ch2, and ch3. Two systems (frame driver unit 61 and board driver unit 62) are provided as the LED driver 130, and one system as the motor driver 130M. (Motor driver unit 70) is provided.
Serial data transmission to a plurality of LED drivers 130 as the frame driver unit 61 is performed by the serial data output channel ch1.
Serial data transmission to a plurality of LED drivers 130 as the board driver unit 62 is performed by the serial data output channel ch2.
Serial data transmission to a plurality of motor drivers 130M as the motor driver 70 is performed by the serial data output channel ch3.

As signal lines for the serial data output channels ch1, ch2, ch3, a latch signal line for supplying a latch signal LATCH, a clock line for supplying a clock signal CLK, an enable signal line for supplying an enable signal ENABLE, light emission drive data or a motor A data line for supplying serial data DATA as drive data is provided.
The latch signal LATCH, the clock signal CLK, and the enable signal ENABLE are supplied in parallel to a plurality of LED drivers 130 (or motor driver 130M) constituting the frame driver 61 (or the panel driver 62, motor driver 70). Be done. On the other hand, the serial data DATA is sent from the top LED driver 130 (or motor driver 130M) among the plurality of LED drivers 130 (or motor driver 130M) that make up the frame driver 61 (or board driver 62, motor driver 70). ) And sequentially transfer them to the LED driver 130 (or motor driver 130M) in the subsequent stage.
That is, each LED driver 130 (or motor driver 130M) in one system is sequentially connected in series with the input and output of serial data DATA, and the serial data DATA from the effect control CPU 200 is the first LED in one system The data is sequentially transferred from the driver 130 (or the motor driver 130M) to the LED driver 130 (or the motor driver 130M) at the end, and each LED driver 130 (or the motor driver 130M) serial data based on the latch signal from the effect control CPU 200 It is configured to capture DATA.

As each LED driver 130 and motor driver 130M, "BD7851FP (made by ROHM Co., Ltd.)" which is a 16-bit constant current LED driver can be used, for example, and it has, for example, 16 constant current terminals.
Therefore, one LED driver 130 can output up to 16 series of LED drive current. One "series" refers to a group of one or more LEDs connected in series or in parallel to one current output terminal.
The number of LED drivers 130 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of light emitting units 20 w).
The number of LED drivers 130 in the board driver unit 62 is determined by the number of LED series (number of series of light emitting units 20b, 20Z, 20H, 20J) arranged on the board side.
The number of motor drivers 130M in the motor driver 70 is determined by the number of motors of the movable object.

FIG. 40 shows a schematic configuration example of the main part of the LED driver 130. As shown in FIG. Although the description of the configuration of the motor driver 130M is omitted below, it is the same as the LED driver 130.
The LED driver 130 includes a 16-bit shift register 131, a latch unit 132, an output gate unit 133, and constant current terminals 139-1 to 139-16.
16 series LED120 is connected to all (or one part) of constant current terminal 139-1-139-16. Although the figure shows a simplified state in which one LED 120 is connected to one series of constant current terminals 139, a configuration in which a plurality of LEDs are connected to one series of constant current terminals 139 (for example, series connection Of course).

The serial data DATA is supplied to the terminal 134 of the shift register 131, and the clock signal CLK is input to the terminal 135 of the LED driver 130.
The serial data DATA from the effect control CPU 200 is supplied to the terminal 134 of the LED driver 130 at the top of each system. The terminal 136 of the previous LED driver 130 is connected to the terminals 134 of the second and subsequent LED drivers 130 of each system.
The shift register 131 comprises, for example, 16 stages of D flip flop circuits, and takes in serial data DATA from the terminal 134 at the timing of the clock signal CLK and shifts the data held in each D flip flop circuit to the subsequent stage Go. The output of the sixteenth stage D flip-flop circuit is supplied from the terminal 136 to the shift register 131 from the terminal 134 of the next LED driver 130.

Further, the latch signal LATCH from the effect control CPU 200 is supplied from the terminal 137 to the latch unit 132 to each LED driver 130. The latch unit 132 latches the values of the 16 D flip-flop circuits in the shift register 131 at the timing when the latch signal LATCH is input. Sixteen bits of data will be latched.
The 16-bit data latched by the latch unit 132 is supplied to the output gate unit 133.
The LED driver 130 of each system has a configuration in which serial data DATA is sequentially transferred. The effect control CPU 200 controls the LED drive data (16 bits) for the LED driver 130 at the end, the LED drive data (16 bits) for the LED driver 130 before that, and the LED drive data (16 bits) for the LED driver 130 at the top. Output sequentially one after another. Each LED driver 130 is supplied to itself by outputting the latch signal LATCH in parallel to all the LED drivers 130 in the system at the timing when the 16-bit LED drive data for the first LED driver 130 is transferred. The 16-bit LED drive data can be fetched into the latch unit 132.

When the enable signal ENABLE from the terminal 138 is ON, the output gate unit emits light of the LED 120 connected to the constant current terminal 139-1 to 139-16 based on the 16-bit data latched by the latch unit 132. Supply current for Each of the latched 16 bits becomes a current control value for each of 16 constant current terminals 139-1 to 139-16.
With such a configuration, each LED driver 130 drives up to 16 connected LEDs 120.

In addition to the LED light emission drive for the light emission unit 20b for effect, the LED driver 130 of a part of the board driver unit 62 also performs LED light emission drive for the light emission units 20Z, 20H, and 20J for situation presentation. That is, in some of the LED drivers 130, any one of the light emitting units 20Z, 20H, and 20J is connected to any of the constant current terminals 139-1 to 139-16.
Although the detailed description is omitted because it is similar to the outline, actually, in some LED drivers 130, the symbol identification light emitting unit 20Z, the number-of-holds display light emitting unit 20H, and the light emitting unit 20b as described in FIG. One of the game state notification light emitting units 20J is connected.
In that case, as in FIG. 7, when a plurality of LEDs 120 as light emitting units 20b for effect are connected in series, the second power supply voltage (for example, 12 V) is connected as a power supply for light emission driving, while symbol identification A single LED 120 is used as the light emitting unit 20Z, the light emitting unit for holding number display 20H, and the game state notifying light unit 20J, and the first power supply voltage VCC1 (for example 5 V) used as a power supply by the LED driver 130 is used. It may be connected to be used as a power source for light emission drive.

In the second embodiment, the effect control CPU 200 substantially simultaneously transmits serial data of one transmission unit to drive signal output means (frame driver unit 61 and board driver unit 62) of the first system and the second system. Output.
The LED output process according to the second embodiment will be described with reference to FIG.
Similar to the case described in the first embodiment, LED drive data generated in the LED data update process of step S114 of FIG. 13 is output to each LED driver 130 in the process of step S115.
In the LED drive data generated by the LED data update process, dummy data is arranged in the area corresponding to the constant current terminal to which the light emitting units 20Z, 20H, and 20J for presentation are connected in the lamp data as the source. The dummy data is updated by the process as shown in FIG. 27 so that the light emission drive information for effect and the light emission drive information for status indication (for symbol identification, for holding number display, for notification of gaming state) are combined. It has been done.

In step S 851, the effect control CPU 200 specifies the top address of the LED drive data (for example, the output data buffer corresponding to the output data buffer in FIG. 32A of the first embodiment) in each serial data output channel ch 1, ch 2. In the first embodiment, LED drive data for one LED driver 90 is 4 × 24 bits, but in the second embodiment, LED drive data for one LED driver 130 is, for example, 16 bits. Become.
Next, in step S852, the effect control CPU 200 turns off the latch signal LATCH of each of the serial data output channels ch1 and ch2. Further, in step S853, the enable signal ENABLE of each of the serial data output channels ch1 and ch2 is turned on.

Then, the processing of steps S854 to S857 is repeated as necessary as loop processing LP4.
For the sake of explanation, it is assumed that the number of LED drivers 130 is five for the frame driver units 61 and six for the panel driver units 62. That is, the serial data output channel ch1 transmits to the five LED drivers 130, and the serial data output channel ch2 transmits to the six LED drivers.
Note that while writing to the transmission data register is performed in 8-bit units, 16-bit data is transmitted to one LED driver 130. Therefore, two transmissions are required for one LED driver 130. Accordingly, writing to the transmission data register is performed ten times on the serial data output channel ch1 and twelve times on the serial data output channel ch2.
The loop processing LP4 is looped by the number of transmissions of the serial data output channel ch2 (= 12 times), which has the largest number of LED drivers 130 (6).

As the loop processing LP4, in step S854, the effect control CPU 200 performs output of the serial data DATA (writing of 8 bits in the transmission data register) as transmission of one transmission unit of the serial data output channel ch1.
Also, substantially simultaneously, in step S855, the serial data DATA of the serial data output channel ch2 is output (8-bit writing to the transmission data register).
As described above, transmission of serial data DATA (16 bits × the number of LED drivers) of the respective systems is simultaneously performed on the serial data output channels ch1 and ch2.
Then, in steps S 856 and S 857, the effect control CPU 200 waits for the completion of transmission of the serial data DATA in each of the serial data output channels ch 1 and ch 2.
When the transmission is completed, the processes of steps S854 and S855 are performed again.

Note that due to the difference in the number of LED drivers 130, a serial data output channel is generated that completes all data output earlier than others. In the case of the above example, the serial data output channel ch1 is completed by performing step S854 ten times, and the serial data output channel ch2 is completed by performing step S855 twelve times.
Therefore, in this example, the serial data output of step S854 may not be performed for the serial data output channel ch1 at the loop number after completion.
As a matter of course, control (for example, masking or the like) of the clock signal CLK is performed so that data shift in the shift register 131 is not performed except during actual serial data transmission.

When transmission is completed (in the above example, loop processing LP4 is completed 12 times as loop processing), the latch signal LATCH of the serial data output channels ch1 and ch2 is turned on in step S860. Thus, serial data DATA (16-bit LED drive data) is taken in all the LED drivers 130. After the latch, the latch signal LATCH of the serial data output channels ch1 and ch2 is turned off in step S861.
At this point, the enable signal ENABLE is on. For example, when the enable signal ENABLE from the terminal 138 is off, the output gate unit 133 of each LED driver 130 drives the constant current terminals 139-1 to 139-16 with the LED drive data latched by the latch unit 132. It is assumed. Therefore, the effect control CPU 200 turns off the enable signal ENABLE in step S862. As a result, each LED driver 130 drives the light emission of the connected LED 120 based on the LED drive data written this time.

Also in this second embodiment, the effect control CPU 200 is a drive signal output means (frame driver unit 61, board driver unit 62) of the first system (serial data output channel ch1) and the second system (serial data output channel ch2). Simultaneously transmit serial data.
Then, after the transmission is completed, each LED driver 130 performs a latch.
As a result, the time required for the entire serial data transmission operation can be shortened, and the processing load on the effect control CPU 200 can be reduced.

For example, conventionally, the processing corresponding to steps S854 to S860 in FIG.
(ST1) Serial data transmission of ch1 (writing to transmission data register)
(ST2) ch1 transmission output completion standby ... above is repeated the required number of times (STx) ch1 latch signal LATCH on

Serial data transmission of (STx + 1) ch 2 (writing to transmission data register)
(STx + 2) ch2 transmission output completion waiting ... or the required number of loops (STy) ch2 had done so on the latch signal LATCH ON.
In this case, waiting time occurs in each of the serial data output channels ch1 and ch2, and transmission processing efficiency is poor.
On the other hand, in the present embodiment,
(S 854, S 855) Serial data transmission start from ch 1, ch 2 (S 856, S 857) Wait for transmission output completion of ch 1, ch 2 (S 860) Latch signal LATCH on ch 1, ch 2 simultaneously Both serial data output channels ch 1 , Ch2 can be processed efficiently.

In the case of the second embodiment, in particular, serial data for drive signal output means (frame driver unit 61 and panel driver units 62A and 62B) of one system is the number of LED drivers 130 included in the system × 16. It is a unit of bits.
Therefore, the entire standby time is the time until the serial data transfer to the drive signal output means with the largest number of LED drivers 130 is completed. That is, in the above example, data transmission to all the serial data output channels ch1 and ch2 can be completed within the time required for the serial data output channel ch2 having the largest number of LED drivers 130.
As a result, the entire time required for serial data transmission can be significantly reduced compared to performing output to and waiting for individual drive signal output means.

Preferably, the number of LED drivers 130 in the drive signal output means of each system may be the same. Alternatively, dummy drivers may be provided to make the same number. Then, the effect control CPU 200 can simultaneously start serial data transmission from the two serial data output channels ch1 and ch2 simultaneously, can complete transmission simultaneously, can latch at the timing immediately after that, and processing becomes easy.
In FIG. 41, after confirming the completion of transmission on the serial data output channels ch1 and ch2 in steps S856 and S857, the latch of all the systems is executed in step S860. However, serial data output is actually completed. It is also possible to latch on from the serial data output channel.
When three or more LED driver 130 systems are used, for example, the frame driver unit, the first panel driver unit, and the second panel driver unit 62 are connected to the serial data output channels ch1, ch2, and ch3, respectively. In this case, the process of FIG. 41 may be performed on the three serial data output channels ch1, ch2, and ch3. The same applies to four or more systems.

In the second embodiment, the drive signal output unit (frame driver unit 61) of the first system transmits the LED drive signal to the lamp unit 63 (light emitting unit 20w) which is the rendering unit provided on the front frame 2. It comprises a plurality of driver circuits (LED driver 130) for outputting. Drive signal output means of the second system (a plurality of driver circuits (LED driver 130) for outputting an LED drive signal to the lamp part 64 (light emitting part 20b) which is the rendering means provided on the game board 3 It consists of
With such a configuration, all the LED drivers 130 of the frame driver unit 61 correspond to the light emitting units 20w on the frame side, and all the LED drivers 130 of the panel driver unit 62 are on the panel side light emitting units 20b, 20Z, 20H, and 20J. Accordingly, the wiring can be simplified, the efficiency can be improved, and the effect control setting can be realized.

<8. Summary and Modifications>

According to the pachinko gaming machine 1 of the above embodiment, the processing for light emission control can be made efficient, and the light emission control processing load can be reduced.
In the pachinko gaming machine 1 of the embodiment, light emitting units 20w and 20b for effect, light emitting units for condition presentation (pattern identification light emitting unit 20Z, number-of-holds display light emitting unit 20H, gaming state notification light emitting unit 20J And a light emission control unit (effect control unit 51) for controlling the light emission of each of the light emission units for effect and situation presentation. The effect control unit 51 as the light emission control means performs a determination process (scenario update process S110) for determining the light emission effect at appropriate timing, and generates the light emission drive information and outputs the light emission drive information to the light emission drive data storage unit (output Data processing (generation processing (LED drive data update processing S114) stored in the data buffer) and output processing (LED output processing S115) for outputting a drive signal based on the light emission drive information stored in the light emission drive data storage unit A light emission effect is realized by performing (every 16 m process). Then, in the creation process, in the state of executing the determined light emission effect, the light emission drive information for effect (LED drive data for effect) for the light emitting units 20w and 20b for effect based on the lamp data corresponding to the effect to be executed Create (steps S701 to S720 in FIG. 26). Furthermore, according to the game situation, light emission drive information for situation presentation (for each variable symbol identification, for display of the number of reservations, for display of the game state notification) for the situation presentation light sources 20Z, 20H, 20J is created (S721 The light emission drive information (LED drive data) for one timing in the predetermined cycle is obtained by combining the light emission drive information for presentation and the light emission drive information for situation presentation.
Since the light emission drive control of each of the light emitting unit for effect and the light emitting unit for condition presentation (for variable symbol identification, for holding number display, for game status notification) is executed in common output processing, the effect control is performed. The processing of the unit 51 can be streamlined, the processing load can be reduced, and the speed of processing can be realized. It is not necessary to output each of the LED drive data for variable symbol identification, for holding number display, and game status notification at a different timing from the LED drive data for effect, and separate output processing for these situation presentation It is because it is not necessary to carry out.
In addition, the common light emitting part (LED 120) and the light emitting part (LED 120) for displaying the situation (for variable symbol identification, for displaying the number of reservations, for notifying the gaming state) are common LED drivers by using common output processing. It is easy to control when connecting to 90 (130). This is because there is no need to separately transfer LED drive data for status presentation to a specific LED driver 90 (130).

Further, the pachinko gaming machine 1 of the embodiment includes the main control unit 50 that outputs a control command related to a game operation, and the effect control unit 51 creates light emission drive information and stores the light emission drive information in the light emission drive data storage. In the creation processing stored in the unit, in a state in which the light emission effect determined in the determination process is executed based on the control command, the light emission drive information for effect for the light emitting unit for effect based on lamp data corresponding to the effect to be executed create. Further, light emission driving information for situation presentation to the light emitting unit for situation presentation is created according to the game situation notified by the control command. A combination of effect light emission drive information and situation presentation light emission drive information is used as light emission drive information (LED drive data) for one timing in the predetermined cycle.
As a result, efficient processing is realized for effect light emission by the main control unit 50 and light emission for presentation of the status (pattern change state, number of reservations, game state) notified from the main control unit 50. Ru. That is, when the light emission effect is sequentially instructed from the main control unit 50 and the game situation is sequentially instructed from the main control unit 50, the effect control unit 51 can streamline the light emission control processing for effect and situation presentation .

In the embodiment, in the state of executing the plurality of light emission effects determined in the determination process, the effect light emission drive information for the effect light emitting unit is created based on the plurality of types of lamp data corresponding to the effects to be performed. . That is, on the basis of the lamp data registration information (see FIG. 22B) of the lamp channels dwCH0 to dwCH15, effect light emission drive information reflecting light emission effects of a plurality of layers is generated. In addition, light emission drive information for situation presentation for the light emitting units 20Z, 20H, 20J (for variable symbol identification, for holding number display, for each game state notification LED drive according to the game situation (symbol change state, number of holds, game situation) Data) is created, and a combination of effect light emission drive information and situation presentation light emission drive information is used as light emission drive information (LED drive data) for one timing in the predetermined cycle.
As a result, it is possible to efficiently execute the light emission drive based on a plurality of designated various light emission effects and the light emission drive for variable symbol identification, for displaying the number of holdings, and for notifying the gaming state.

In the embodiment, the effect control unit 51 is a creation process, lamp data is selected based on timer management defined by the light emission effect determined in the determination process, and light emission for effect based on the selected lamp data Create effect light emission drive information for the part. That is, in the processing of FIG. 20 and FIG. 21, lamp data is selected based on timer management based on the designated main scenario and sub scenario, and light emission drive information for effect is performed to execute the light emission effect indicated by the lamp data. Create In addition to this, the situation presentation light emission drive information for the situation presentation light emitting part is created according to the game situation, and the one combining the presentation light emission drive information and the situation presentation light emission drive information for one timing in the predetermined cycle Light emission drive information (LED drive data).
As a result, while the light emission effect specified in the scenario is appropriately realized, the light emission drive control of the light emitting unit for situation presentation can be efficiently executed.

In the creation process, light emission drive information for presentation of a predetermined size for one timing is generated, and then light emission drive information for situation presentation (for variable symbol identification, for holding number display, for game status notification) is created, By rewriting the specific data area (DBzh, DBj in FIG. 32) in the light emission drive information for presentation to the light emission drive information for situation presentation, the light emission drive information of a predetermined size for one timing is generated (FIG. 26, See Figure 27).
That is, only by preparing a specific data area and updating a part of the light emission drive information for presentation to the light emission drive information for variation symbol identification, it is possible to generate the light emission drive information combining the presentation and the situation presentation. It is possible to generate light emission drive data for performing light emission drive both for presentation and for situation presentation by an easy process.

Further, lamp data is set such that dummy data is to be arranged in the specific data area (DBzh, DBj in FIG. 32) of the effect light emission drive information. That is, the areas Azh and Aj in FIG. In the creation processing, the dummy data of the specific data area is rewritten to the fluctuation symbol identification light emission drive information.
By arranging dummy data as data of the lamp data areas Azh and Aj arranged in the specific data areas DBzh and DBj, the light emission drive information for situation presentation is synthesized without affecting the light emission control for presentation. it can. For this reason, it is easy to combine the light emission drive data for presentation and situation presentation, and an increase in processing load can be avoided.

In the pachinko gaming machine 1, the light emitting unit 20b for effect and the light emitting units 20Z, 20H, and 20J for situation presentation are emitted based on the drive signal (LED drive data) output by the output process of the effect control unit 51. One or more LED drivers 90 (130) for supplying a driving current are provided. For example, it is the LED driver 90 of slave address "b2""b3."
These specific LED drivers 90 (b 2) (b 3) are configured to supply the light emission drive current to both the light emitting part 20 b for effect and the light emitting parts 20 Z and 20 H (or 20 J) for situation presentation. Is connected. In the creation process of the effect control unit 51 corresponding to this, the light emission drive information as the basis of the drive signal outputted to the specific LED driver 90 (b2) (b3) and the light emission drive information for effect and the situation presentation Light emission drive information is included. For example, in the output data buffer, a part of the area corresponding to the LED driver 90 (b2) (b3) is set as the specific data areas DBzh, DBj, and the situation presentation light emission drive information is arranged.
As a result, there is no need to separate the LED driver 90 for effect presentation and for situation presentation (for variable symbol identification, for holding number display, for gaming state notification), and an efficient circuit configuration is possible.

Further, in the creation process of the effect control unit 51, a plurality of types of lamp data corresponding to a plurality of light emission effects determined in the determination process based on the control command are set in a plurality of hierarchies to which priority is set (see FIG. In the lamp channel dwCH0 to dwCH15 of the lamp data registration information of 22B), the light emission drive information for effect for the light emitting portion for effect is sequentially sent from the lamp data designated in the hierarchy (lamp channel) with lower priority, and the lamp data By updating the value to the value corresponding to, the effect light emission drive information reflecting the priority is created (loop processing LP2 in FIG. 26).
That is, when a plurality of types of lamp data corresponding to a plurality of light emission effects are set in a plurality of layers to which priority is set, the light emission drive information for effect reflecting lamp data in descending order of priority is overwritten. By creating as described above, it is possible to realize effect control reflecting priority by simple processing, and by combining the effect light emission drive information with the condition presentation light emission drive signal, the effect light emitting unit and the condition presentation The control of the light emitting unit for common use can be easily made common.

Further, in the creation process of the effect control unit 51, in the state of executing the light emission effect determined in the determination process based on the control command, three gradations for the light emitting unit for effect based on lamp data corresponding to the effect to be executed. The light emission drive information for presentation which expresses the above gradation value is created, and the light emission for situation presentation which expresses two gradations of lighting and extinguishing to the light emission part for situation presentation according to the game situation notified by the control command The drive information is created, and light emission drive information is generated by combining these.
In particular, the light emission drive information for effect is generated as data of three gradations or more (for example, 16 gradations), and the effect of enhancing the game property can be realized by the large number of gradation expressions. On the other hand, since two gradations are sufficient for the purpose of the situation presentation, the light emission drive signal for situation presentation is generated as information of two gradations of light emission / extinguishing, so that generation of light emission drive information for situation presentation is facilitated. Do. For example, the light emission drive information for situation presentation can be easily generated as it may be "0" or "F".

  Further, in this case, specific data areas (DBzh and DBj in FIG. 32) are prepared, and a part for light emission drive information for presentation is updated to light emission drive information for situation presentation, for presentation and situation presentation The combined light emission drive information is generated. In particular, it is possible to generate light emission drive information combining the effect and the identification only by simply updating to a binary (for example, “0” or “F”) for situation presentation about the specific data area. Further, for example, by being a binary value of “0” or “F”, it is possible to easily incorporate the situation presentation light emission drive information in a specific area of the number of bits that can express three gradations or more.

The pachinko gaming machine 1 of the embodiment is stored in the light emission drive data storage unit for the plurality of LED drivers 90 including the specific LED drivers 90 (b2) and (b3) in the output process of the effect control unit 51. A drive signal based on the light emission drive information for one timing is output from a predetermined serial port (ch2).
Thus, a plurality of light emitting units are connected to the specific LED driver 90 so as to generate light emission drive current for both the light emitting unit 20b for effect and the light emitting units 20Z and 20H (or 20J) for situation presentation. Correspondingly, the light emission drive control of each of the light emission part for effect and the light emission part for situation presentation is executed by common output processing. In addition, it is possible to realize the light emission drive including one for presentation and one for situation presentation by one port output.
In other words, even when the specific LED driver 90 (b2) (b3) has a circuit configuration in which the light emitting unit for effect and the light emitting unit for situation presentation are driven to emit light, the specific LED driver 90 ( b2) It is possible not to complicate the light emission control for (b3).

  Also, by creating light emission drive information for one timing so that the light emission drive information for presentation and the light emission drive information for situation presentation are included in the light emission drive information that is the basis of the drive signal output to the specific light emission driver. Generates light emission drive information combining the light emission drive information for presentation and the light emission drive information for situation presentation at each timing, and appropriately executes effect light emission and situation presentation fixed time issuance by a specific LED driver 90 (b2) (b3) be able to.

In the pachinko gaming machine 1 according to the embodiment, the specific LED driver 90 (b2) (b3) operates with the first power supply voltage VCC1 as the power supply voltage, and is connected to the specific LED driver 90 (b2) (b3) The second power supply voltage VCC2 higher than the first power supply voltage VCC1 is connected to the light emission unit 20b for effecting to emit light emission drive current, and light emission is performed to the light emission units 20Z and 20H (or 20J) for situation presentation The first power supply voltage VCC1 is connected to flow the drive current.
The effect light emitting unit requires a large number of series connections of a plurality of LEDs 120 due to a request for decoration, and a power supply of a drive current requires a voltage (for example, 12 V) that is somewhat high. The LED driver 90 is also driven at a relatively low voltage (for example, 5 V). Here, considering the light emitting parts 20Z, 20H, and 20J for situation presentation, it can usually be realized by one LED, and the power supply does not require 12V, while driving with 12V on the contrary requires a large resistance and has heat I will. Also, preparing another power supply complicates the circuit. Therefore, by using the first power supply voltage VCC1 for light emission driving of the situation presentation light emitting units 20Z, 20H, and 20J, it is possible to prevent heat countermeasures and complication of the circuit.

In addition, a plurality of LEDs 120 are connected in series to a light emitting unit 20b for effect connected to a specific LED driver 90 (b2) (b3), and the light emitting units 20Z and 20H (or 20J) for situation presentation , One LED 120 is connected.
It is preferable that the light emitting unit 20b for effect use a series connection of a plurality of LEDs for the effect of further enhancing the game property and for the light emitting range. In this case, it is preferable to apply a method using the second power supply voltage VCC2 to perform sufficient light emission driving.
Further, the effect control unit 51 is configured such that the light emitting unit 20b for effecting light emission with resolution of three or more gradations, and the light emitting units 20Z and 20H (or 20J) for situation presentation are emitted with two gradations of lighting and extinguishing Outputs LED driving data for controlling the light emission of each light emitting unit.
The light emitting unit 20b for effect preferably has a resolution of three gradations or more for the effect of further enhancing the game property. On the other hand, the light emitting unit 20Z, 20H (or 20J) for situation presentation can provide sufficient situation presentation by lighting / blinking / lighting off, and thus only two gradations of lighting and extinguishing can be used, thereby emitting light for situation presentation The drive information can be easily generated.

Although the embodiment has been described above, the present invention is not limited to the examples described in the embodiment, and various modifications and applications may be considered.
Although examples of one system (one serial data output channel) on the frame side and one system on the panel side have been exemplified as the lamp parts 63 and 64 by LEDs etc., it is of course not limited thereto. A plurality of systems may be provided for the lamp portion 63 on the frame side, or a plurality of systems may be provided for the lamp portion 64 on the panel side.
Further, the light emitting unit 20b on the panel side and the light emitting unit 20w on the frame side may be mixed in one system.
Moreover, the LED driver 90 which drives the light emission part 20w by the side of a frame, and the light emission parts 20Z, 20H, and 20J for presentation may be provided.
Further, the light emitting unit for situation presentation also includes a light emitting unit for error notification (for example, an LED for error notification). That is, the same light emission control as the above-described light emission unit for variable symbol identification, the light emission unit for holding number display 20H, and the light emission unit for game condition notification 20J can be performed on the error notification light emission unit.

In addition, serial data transmission of LED drive data according to the embodiment is serial data transmission for other drive control, for example, serial to motor driver unit 70M (130M) for driving movable body part product motor 65 such as stepping motor or solenoid. It can also be applied to data transmission.
Although the present invention is applied to a ball and ball game machine such as a pachinko game machine 1, the present invention is also applicable to a roll-to-roll type game machine (so-called slot machine).
For example, it is conceivable that serial data transmission of LED drive data is performed as the first system and the second system, respectively, for the decoration LED on the front side of the slot machine housing and the backlight LED for the reel. Alternatively, the upper and lower portions on the front side of the case may be divided into serial data transmission systems. In addition, on the system of one or more serial data transmissions, the light emission driving of the light emitting unit for situation presentation can be performed similarly to the embodiment.

1 pachinko gaming machine 20w, 20b light emitting unit 20H pending number display unit 20J gaming state notification unit 20Z fluctuation symbol identification unit 32 liquid crystal display device 33 symbol display unit 41 upper starting opening 42 normal fluctuation winning device 42a lower starting opening 43 general winning opening 44 gate 45 the first special variation winning device 46 second special variation winning device 50 main control board 51 the performance control board 52 liquid crystal control board 61 frame driver unit 62 Release driver portions 63 and 64 the lamp unit 90,130 LED driver 120 LED
200 production control CPU
201 Effect control ROM
202 Production control RAM

Claims (2)

A light emitting unit for effect,
A light emitting unit for situation presentation,
Light emission control means for outputting a drive signal for controlling light emission of each of the light emission units for the effect and the situation presentation;
On the basis of the drive signal, and a light emitting portion for directing the multiple light emitting driver that generates a light emission drive current to the light emitting portion for status presentation,
Equipped with
Among the plurality of light emission drivers , a plurality of light emission units are connected to generate a light emission drive current for both the light emission unit for effect and the light emission unit for situation presentation ,
The light emitting unit for effect connected to the specific light emitting driver comprises a plurality of LEDs connected in series;
The light emitting unit for situation presentation connected to the specific light emitting driver consists of one LED,
The specific light emission driver operates with the first power supply voltage as the power supply voltage.
A second power supply voltage higher than the first power supply voltage is connected to the light emitting unit for effect connected to the specific light emitting driver in order to flow a light emitting drive current,
The first power supply voltage is connected to the light emitting unit for situation presentation connected to the specific light emitting driver in order to supply a light emitting drive current. The light emission control means emits light of each light emitting portion such that the light emitting portion for effect is emitted with resolution of 3 gradations or more and the light emitting portion for status presentation is emitted with 2 gradations of lighting and extinguishing Output a drive signal to control
The gaming machine according to claim 1 .

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