JP6541260B2 - Transformation processing apparatus, inverse transformation processing apparatus, encoding apparatus, decoding apparatus, and computer program - Google Patents

Description

  The present invention relates to a technology for converting a signal such as a video signal.

  The moving picture experts group (MPEG) video coding method is an efficient information compression method by converting a video signal to spatial frequency using orthogonal transform represented by discrete cosine transform (DCT). To achieve. As conventional techniques of DCT and Discrete Sine Transform (DST), for example, Non-Patent Document 1, Patent Documents 1, 2, and 3 are known.

  The latest MPEG-H HEVC / H. In the video coding method of H.265, two-dimensional orthogonal transform can be performed with a pixel block size of "4 × 4" to "32 × 32". As a result, orthogonal transform can be applied with a pixel block size suitable for a video signal, and therefore, finer encoding control can be performed. In addition, UHD (Ultra High Definition) video called 4K (3840 × 2160) or 8K (7680 × 4320) enables high-definition video representation with a large amount of information, but increases the area that does not require a sense of definition. From this, it becomes a video with a wide dynamic range with a sense of definition. For such video signals, coding efficiency is improved by selecting the size of the coding block suitable for the video area. For example, in MPEG-H HEVC / H.2 that performs encoding control in units of pixel blocks of a plurality of sizes. According to the H.265 video coding method, the previous generation MPEG-4 AVC / H. Compared with the H.264 video coding method, the coding performance is approximately doubled, and the effect is particularly high for UHD video.

  However, MPEG-H HEVC / H. In the video coding method of H.265, the size of the coding block called CU (Coding Unit) is the maximum pixel block size of “64 × 64”, while the size of the orthogonal transformation block called TU (Transform Unit) Is small with a pixel block size of up to “32 × 32”. This is considered to be one of the reasons why the improvement of the coding efficiency has not been sufficiently achieved particularly for high resolution 8K video and CG (Computer Graphics) video where the signal change is extreme. It is known that coding efficiency is further improved by performing coding with a pixel block size of “128 × 128” exceeding “64 × 64” for such 8K video and CG video. .

JP 2012-147205 A Unexamined-Japanese-Patent No. 2-116969 Japanese Patent Publication No. 2014-509108 gazette

W. Chen, C. H. Smith, and S. C. Fralick, "A fast computational algorithm for the discrete cosine transform," IEEE Trans. Commun., Vol. COMM-25, pp. 1004-1009, Sept. 1977.

  However, in the above-described conventional techniques of DCT and DST, there is a problem that it is difficult to make the size of the orthogonal transformation block larger than the “32 × 32” pixel block size. This is because, in the prior art, when the orthogonal transformation of a larger size is performed using a high-speed algorithm having a recursive process represented by a butterfly operation, a required amount of memory increases, so that CPU (Central Processing Unit) This is because the internal cache memory runs short of memory and there is a possibility that sufficient processing speed can not be obtained.

  Further, orthogonal transformation such as DCT and DST is a process of transforming a time domain signal into a frequency domain signal using a cosine function and a sine function which are trigonometric functions as transformation kernels. In this orthogonal transformation process, a high-speed algorithm called butterfly operation utilizing periodicity of trigonometric functions is generally used. FIG. 9 shows a signal diagram of an 8-point DCT whose orthogonal transformation block size is “8 × 8” as a configuration example of butterfly operation. The signal diagram of the 8-point DCT in FIG. It is adopted by H.265 video coding method.

As shown in FIG. 9, a typical butterfly operation, the input value x _{n (where,} n is an integer from 0 to "N-1") input value and the input value x _n of x _N-1-n Is performed as the operation of the first stage. When N-point DCT of the video signal is performed by this butterfly operation, for example, in order to start addition processing of the first stage of the N-point DCT in the processing of the video signal in the vertical direction, If so, even if the actual circuit configuration is elaborated, it is necessary to read the video signal of at least W × N / 2 pixels as an input value. For this reason, a delay time proportional to the value of N of the orthogonal transformation block size occurs as the processing time of the N-point DCT. For example, when applying 64-point DCT to the video format “7680 × 4320 / 60P” of 8K video, since the scanning time of one line is approximately 4 microseconds, approximately “4 × 64/2 = 128” micro A delay time of seconds will occur. Similar problems occur with relatively small size DCTs such as 32-point DCT and 4-point DCT, but the larger size DCT is more affected by delay time. In particular, when encoding high-resolution video signals, it is preferable to apply orthogonal transform of a wide size from the viewpoint of encoding efficiency, but despite the fact that the number of data per unit time to be processed is larger in real time processing. Since the delay time becomes longer as the size of the orthogonal transform increases, there is a possibility that large size orthogonal transform can not be applied.

  The present invention has been made in consideration of such circumstances, and a conversion processing device, an inverse conversion processing device, and an encoding device capable of shortening the delay time in the conversion processing of a signal such as a video signal. It is an object of the present invention to provide a decoding device and a computer program.

(1) One aspect of the present invention is a conversion processing apparatus that performs conversion of N points whose conversion block size is “N × N, where N is an integer of 4 or more”. N / 2 two-point Hadamard transform units performing two-point Hadamard transform with a transform block size of “2 × 2” for each pair of input values, and two inputs among the results of the two-point Hadamard transform N / 2 point DCT operation unit for performing discrete cosine transform operation with orthogonal transform block size “N / 2 × N / 2” for sum of values, and two of the results of the two-point Hadamard transform And an N / 2-point DST operation unit for performing an operation of discrete sine conversion in which an orthogonal conversion block size is “N / 2 × N / 2” with respect to the difference between the input values of
(2) One aspect of the present invention is the conversion processing device which performs conversion of a plurality of conversion block sizes (N points) in the conversion processing device of the above (1), wherein the plurality of conversion block sizes (N points) The N / 2 point DCT operation unit and the N / 2 point DST operation unit respectively corresponding to the plurality of N / 2 point DCT operation units respectively corresponding to the plurality of transform block sizes (N points); A two-point DST operation unit shares the two-point Hadamard transformation unit.

(3) One aspect of the present invention is an inverse transform processing device that performs inverse transform of N points whose inverse transform block size is “N × N, where N is an integer of 4 or more”. Among them, the inverse transform block size is “N / 2 × N / 2” for N / 2 input values that are the result of discrete cosine transform whose orthogonal transform block size is “N / 2 × N / 2”. The N / 2-point IDCT operation unit that performs the inverse discrete cosine transform operation, and the result of the discrete sine transform whose orthogonal transformation block size is “N / 2 × N / 2” among N input values An N / 2 point IDST operation unit for performing an inverse discrete sine conversion operation in which the inverse orthogonal transformation block size is “N / 2 × N / 2” for N / 2 input values, and the N / 2 point Inverse transformation using the output value from the IDCT operation unit and the output value from the N / 2 point IDST operation unit And an inverse transform signal generation unit configured to generate a signal after conversion.

(4) One aspect of the present invention is an encoding apparatus that generates an encoded signal from a signal converted by a predetermined conversion method, comprising: the conversion processing apparatus according to any one of the above (1) or (2) It is.
(5) One aspect of the present invention is a decoding device that decodes a coded signal generated from a signal converted by a predetermined conversion method, and is a decoding device including the inverse conversion processing device of (3).

(6) One embodiment of the present invention is a computer program for performing conversion of N points whose conversion block size is “N × N, where N is an integer of 4 or more”, and in N input values. N / 2 two-point Hadamard transform function for performing two-point Hadamard transform with a transform block size of “2 × 2” for each pair of continuous input values, and two of the results of the two-point Hadamard transform N / 2-point DCT operation function of performing discrete cosine transform operation with orthogonal transform block size “N / 2 × N / 2” for the sum of the input values, and the result of the two-point Hadamard transform In order to make a computer realize an N / 2 point DST operation function that performs an operation of discrete sine conversion whose orthogonal transformation block size is “N / 2 × N / 2” with respect to the difference of two input values among them. Is a computer program of
(7) One embodiment of the present invention is a computer program for performing inverse conversion of N points whose inverse conversion block size is “N × N, where N is an integer of 4 or more”, and includes N inputs Among the values, the inverse transform block size is “N / 2 × N /” for N / 2 input values that are the result of discrete cosine transform whose orthogonal transform block size is “N / 2 × N / 2”. N / 2 point IDCT operation function which performs inverse discrete cosine transform operation which is 2 ", and the result of discrete sine conversion whose orthogonal transformation block size is" N / 2 × N / 2 "among N input values N / 2 point IDST operation function for performing inverse discrete sign conversion operation whose inverse orthogonal transformation block size is “N / 2 × N / 2” with respect to N / 2 input values that are The output value from the 2-point IDCT operation function and the N / 2-point IDST operation function A computer program for causing a computer to realize an inverse conversion signal generation function of generating a signal after inverse conversion using an output value.

  According to the present invention, it is possible to shorten the delay time in the conversion process of a signal such as a video signal.

It is a block diagram which shows the Example of the conversion processing apparatus 1 which concerns on one Embodiment of this invention. It is a block diagram which shows the Example of the inverse transformation processing apparatus 2 which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the conversion processing apparatus 3 which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the inverse transformation processing apparatus 4 which concerns on one Embodiment of this invention. It is a block diagram which shows the example of the encoding apparatus 100 which concerns on one Embodiment of this invention. It is a block diagram which shows the example of the decoding apparatus 200 which concerns on one Embodiment of this invention. It is a block diagram for demonstrating the orthogonal transformation in the conventional video coding system. It is a block diagram for demonstrating the conversion in one Embodiment of this invention. It is a figure which shows the structural example of the conventional butterfly operation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Basic principle]
First, the basic principle according to the present embodiment will be described. In the present embodiment, a 2-point Walsh type Hadamard transform is used for conversion processing of a signal such as a video signal. The two-point Walsh type Hadamard transform is called a two-point Hadamard transform. The two-point Hadamard transformation is represented by a 2-row 2-by-two transformation matrix H shown in the following equation (1). In the two-point Hadamard transform, a transform block size which is a size of a transform block is “2 × 2”. Note that the two-point Hadamard transform matches the two-point Haar transform.

As can be seen from equation (1) above, the two-point Hadamard transform consists of calculating the sum and the difference for two input value pairs. When this two-point Hadamard transformation is used to convert a signal such as a video signal, the sum calculation is performed for the input value x _2n and the input value x _{2n + 1} , which are pairs of input values included in the input signal. It is sufficient to calculate the difference. Here, n is an integer from 0 to “N−1”, and N is a conversion block size of the signal conversion processing and is an even number.

  When two-point Hadamard transform is used for video signal conversion processing, the minimum delay time in the conversion processing is W, which is the number of horizontal pixels for one line of the video signal, regardless of the conversion block size of the video signal conversion processing. It takes time to read the number of pixels. For example, in the case of the video format “7680 × 4320 / 60P” of 8K video, the minimum delay time is about 4 microseconds which is the scanning time of one line regardless of the conversion block size, and 64 points by the conventional butterfly computation. The delay time of DCT is shortened as compared with "about 128 microseconds". As described above, according to the two-point Hadamard transform, it is possible to shorten the delay time in the transform processing of the video signal, as compared with the orthogonal transform by the conventional butterfly operation.

  When the two-point Hadamard transform is used for the conversion process of the video signal, the conversion process is performed by averaging the adjacent pixels of the input video signal and reducing the resolution to half, and the adjacent image to be input The difference between pixels has an effect of generating an edge image which is an image having a half resolution. That is, to apply the two-point Hadamard transform in the horizontal direction and the vertical direction of the video signal, an average image whose resolution is “N / 2 × N / 2” is obtained for the video signal of the “N × N” pixel block size. And mean to separate into edge images.

  From this, in the present embodiment, the conversion processing for the signal resulting from the 2-point Hadamard conversion of the video signal of the “N × N” pixel block size is selected by (1) and (2) shown below.

(1) Conversion to Average Image The average image has the same signal property as a general image with half the resolution. For this reason, N / 2-point DCT is used as transformation processing for the average image. This is because the coding efficiency by DCT is high for a video signal having a high correlation between adjacent pixels like a general video signal. Specifically, of the results of matrix multiplication of the transformation matrix H of the above equation (1) and the two input values, the sum of two input values corresponds to the average image. Therefore, an N / 2 point DCT is performed on the sum of the two input values.

(2) Conversion Process to Edge Image The edge image is an image containing a large amount of high frequency components. For this reason, N / 2 points DST are used as conversion processing for edge images. This is because the coding efficiency by DST is high for a video signal with low correlation between adjacent pixels. Specifically, among the results of matrix multiplication of the transformation matrix H of the equation (1) and the two input values, the difference between the two input values corresponds to the edge image. Therefore, N / 2 points DST are performed on the difference between the two input values.

[Example of Conversion Processing Device]
Next, examples of the conversion processing apparatus and the inverse conversion processing apparatus according to the present embodiment will be described.

FIG. 1 is a block diagram showing an example of the conversion processing apparatus 1 according to the present embodiment. The N input values x _{0 to} x _N−1 are input to the conversion processing device 1. However, N is an integer of 4 or more. Conversion processing device 1 shown in FIG. 1 includes N / 2 adders 11-0 to N / 2-1, N / 2 subtractors 12-0 to N / 2-1, and N / 2 points. A DCT operation unit 13 and an N / 2 point DST operation unit 14 are provided.

The addition units 11-0 to N / 2-1 respectively calculate the sum of the input value x _{2 n} and the input value x _{2 n + 1} , which are a pair of input values in which the arrangement is continuous in the input values x _{0 to} x _N−1 . However, n is an integer from 0 to "(N / 2) -1". The adder 11-n adds the input value x _{2 n} and the input value x _{2 n + 1} . For example, the addition unit 11-0 adds an input value _{x 1} and the input value _{x 0.} Addition unit 11-1 adds an input value _{x 2} and the input value _{x 3.} The addition unit 11 -N / 2-1 adds the input value x _N-2 to the input value x _{N -1} . The sum, which is the addition result of each addition unit 11-0 to N / 2-1, is output to the N / 2-point DCT operation unit 13.

Subtraction unit 12-0~N / 2-1 are respectively calculates the difference between the input value _x 0 _{~x N-1} Odor is a pair of input values lined successive input values _{x 2n} and the input value _{x 2n + 1.} However, n is an integer from 0 to "(N / 2) -1". Subtraction unit 12-n subtracts the input value _{x 2n + 1} from the input value _{x 2n.} For example, the subtraction unit 12-0 subtracts the input value _{x 1} from the input value _{x 0.} Subtraction unit 12-1 subtracts the input value _{x 3} from the input value _{x 2.} The subtractor unit 12-N / 2-1 subtracts the input value xN _-1 from the input value xN _-2 . The difference, which is the subtraction result of each of the subtraction units 12-0 to N / 2-1, is output to the N / 2-point DST calculation unit 14.

  The adders 11-0 to N / 2-1 and the subtractors 12-0 to N / 2-1 shown in FIG. 1 correspond to N / 2 two-point Hadamard transform units. A pair of the adding unit 11-n and the subtracting unit 12-n corresponds to one two-point Hadamard transform unit.

The N / 2-point DCT operation unit 13 performs an N / 2-point DCT operation using the addition result output from the addition units 11-0 to N / 2-1 as an input value. The N / 2-point DCT operation unit 13 is configured using a high-speed algorithm such as a known butterfly operation. The N / 2 point DCT operation unit 13 outputs values X _{0 to} X _{N / 2-1} , which are the operation results of the N / 2 point DCT.

The N / 2-point DST operation unit 14 performs an N / 2-point DST operation using the subtraction result output from the subtraction units 12-0 to N / 2-1 as an input value. The N / 2-point DST operation unit 14 is configured using a known high-speed algorithm such as butterfly operation. The N / 2-point DST operation unit 14 outputs values X _{N / 2 to} X _N-1 which are the operation results of the N / 2-point DST.

FIG. 2 is a block diagram showing an example of the inverse conversion processing device 2 according to the present embodiment. N inverse input values X _{0 to} X _N−1 are input to the inverse transformation processing device 2. However, N is an integer of 4 or more. N input values _X 0 _{to X} N / 2 input values _X of the _N-1 0 _{to X N / 2-1,} the conversion processing device 1 of the N / 2-point DCT operation unit shown in Figure 1 of the It corresponds to the output value of 13. The N / 2 input values X _{N / 2 to} X _N-1 of the _N input values X _{0 to} X _N-1 are the N / 2 point DST operation unit of the conversion processing apparatus 1 shown in FIG. 1 described above. It corresponds to the output value of 14.

  The inverse conversion processing device 2 shown in FIG. 2 performs inverse conversion of the conversion processing device 1 shown in FIG. The inverse transform processing device 2 shown in FIG. 2 includes an N / 2 point inverse discrete cosine transform (IDCT) operation unit 21 and an N / 2 point inverse discrete sine transform (IDST) operation unit. 22, N / 2 addition units 23-0 to N / 2-1, N / 2 subtraction units 24-0 to N / 2-1, N 1 / 2-fold units 27-0 To N / 2-a, 27-0 to N / 2-b.

The N / 2-point IDCT operation unit 21 performs an N / 2-point IDCT operation using the N / 2 input values X _{0 to} X _{N / 2−1} . The N / 2-point IDCT operation unit 21 is configured using a high-speed algorithm such as a known butterfly operation. The N / 2-point IDCT operation unit 21 outputs a value y (n) which is the operation result of the N / 2-point IDCT. However, n is an integer from 0 to "(N / 2) -1".

The N / 2-point IDST operation unit 22 performs an N / 2-point IDST operation using N / 2 input values X _{N / 2 to} X _N−1 . The N / 2-point IDST operation unit 22 is configured using a high-speed algorithm such as a known butterfly operation. The N / 2 point IDST calculation unit 22 outputs a value z (n) which is the calculation result of the N / 2 point IDST. However, n is an integer from 0 to "(N / 2) -1". The value y (n) and the value z (n) of each n are input to the adder 23-n and the subtractor 24-n corresponding to each n.

The adder 23-n adds the value y (n) and the value z (n). The half multiplication unit 27-n-a halves the sum which is the addition result of the addition unit 23-n. A value obtained as a result of being halved by the halving unit 27-n-a is output from the inverse transformation processing device 2 as an output value x '(2n). However, n is an integer from 0 to "(N / 2) -1". As a result, the output values x ′ ₀ , x ′ ₂ , x ′ ₄ ,..., X ′ _{N− 2} are output from the inverse transformation processing device 2.

The subtraction unit 24-n subtracts the value z (n) from the value y (n). The half multiplication unit 27-n-b halves the difference which is the subtraction result of the subtraction unit 24-n. The value obtained as a result of being halved by the halving unit 27-n-b is output from the inverse transformation processing device 2 as an output value x '(2n + 1). However, n is an integer from 0 to "(N / 2) -1". As a result, the output values x ′ ₁ , x ′ ₃ , x ′ ₅ ,..., X ′ _N−1 are output from the inverse transformation processing device 2.

  The adders 23-0 to N / 2-1, the subtractors 24-0 to N / 2-1, and the half parts 27-0 to N / 2-a, 27-0 to N / 2-b. Corresponds to the inverse conversion signal generation unit.

  When the conversion processing apparatus 1 is configured using a CPU, a CPU having a cache memory with a memory capacity sufficient for the required memory capacity of the N / 2 point DCT operation unit 13 and the N / 2 point DST operation unit 14 is used. Is preferred. As a result, the calculation processing of the N / 2-point DCT calculation unit 13 and the N / 2-point DST calculation unit 14 can be executed in parallel at high speed. The same applies to the inverse conversion processing device 2.

According to the conversion processing apparatus 1 shown in FIG. 1 described above, the first stage operation is addition and subtraction of the input value x _2n and the input value x _{2n + 1} which are operations of two-point Hadamard transformation. Therefore, in the first stage operation, the sum calculation and the difference calculation may be performed on the input value x _{2 n} and the input value x _{2 n + 1} , which are pairs of continuous input values included in the input signal. This makes it possible to shorten the delay time until the conversion process is started, as compared with the conventional orthogonal conversion by butterfly operation. Further, since the two-point Hadamard transform is formed by addition and subtraction, the calculation can be performed very lightly.

  Further, according to the conversion processing apparatus 1 shown in FIG. 1 described above, it is possible to select and perform conversion processing according to the characteristics of the signal resulting from the two-point Hadamard conversion. Specifically, among the results of the two-point Hadamard transform, N / 2-point DCT is performed on the sum of two input values, and N / 2-point DST is performed on the difference between the two input values. Thereby, the video signal of the pixel block size of "NxN" can be encoded efficiently. Also, the N / 2 point DCT and the N / 2 point DST can be processed in parallel. As a result, the processing can be reduced in weight as compared to the conversion processing by the N-point DCT or the N-point DST.

[Modification of Conversion Processing Device]
Next, modified examples of the conversion processing apparatus and the inverse conversion processing apparatus according to the above-described embodiment will be described.

  FIG. 3 is a diagram showing a configuration example of the conversion processing device 3 according to an embodiment of the present invention. In this FIG. 3, the same code | symbol is attached to the part corresponding to said each part of FIG. 1, and the description is abbreviate | omitted. In the transform processing device 3 shown in FIG. 3, the N / 2-point DST operation unit 14 in the transform processing device 1 shown in FIG. 1 is configured by an N / 2-point DCT operation unit 32. The N / 2 point DCT operation unit 13 shown in FIG. 3 is the same as the transform processing device 1 shown in FIG. Similarly, the adding units 11-0 to N / 2-1 shown in FIG. 3 are the same as the conversion processing device 1 shown in FIG. Hereinafter, in FIG. 3, points different from the configuration of FIG. 1 will be mainly described.

  For example, Patent Document 1 describes a technique in which the DST operation unit is configured by a DCT operation unit. The N / 2-point DST operation unit 14 in the conversion processing device 1 is configured by the N / 2-point DCT operation unit 32 by applying the technique described in Patent Document 1 to the conversion processing device 1 shown in FIG. can do.

  The N / 2 point DCT operation unit 32 shown in FIG. 3 is provided to realize the N / 2 point DST operation unit 14 in the transform processing device 1 shown in FIG. The subtraction units 12-0 to N / 2-1 shown in FIG. 3 are the same as the conversion processing device 1 shown in FIG. Of the subtraction results of the subtraction units 12-0 to N / 2-1, the subtraction results of the subtraction unit 12-2m (m is an integer from 0 to "(N / 4) -1") are N / 2 as they are. It is input to the DCT operation unit 32. Of the subtraction results of the subtraction units 12-0 to N / 2-1, the subtraction result of the subtraction unit 12-2m + 1 (m is an integer from 0 to "(N / 4) -1") is the sign inversion unit 31-. The sign is inverted by 2m + 1 and then input to the N / 2-point DCT operation unit 32. The sign inverting unit 31-2m + 1 inverts the sign of the input value. However, m is an integer from 0 to "(N / 4) -1".

  According to this modification, in the conversion processing apparatus according to the present embodiment, the N / 2-point DST operation unit can be configured by an N / 2-point DCT operation unit. Thus, the configuration of the conversion processing apparatus can be simplified, and the utilization efficiency of the operation unit can be improved.

  FIG. 4 is a diagram showing an example of the configuration of the inverse transform processing device 4 according to an embodiment of the present invention. In this FIG. 4, the same code | symbol is attached to the part corresponding to said each part of FIG. 2, and the description is abbreviate | omitted. In the inverse transform processing device 4 shown in FIG. 4, the N / 2 point IDST operation unit 22 in the inverse transform processing device 2 shown in FIG. 2 is configured by an N / 2 point IDCT operation unit 41. The N / 2 point IDCT operation unit 21 shown in FIG. 4 is the same as the inverse transform processing device 2 shown in FIG. Hereinafter, in FIG. 4, points different from the configuration of FIG. 2 will be mainly described.

  For example, Patent Document 1 describes a technique in which an IDST operation unit is configured by an IDCT operation unit. For example, by applying the technique described in Patent Document 1 to the inverse transform processing device 2 shown in FIG. 2 described above, the N / 2 point IDST operation unit 22 in the inverse transform processing device 2 is an N / 2 point IDCT operation unit 41. Can be configured by

  The N / 2 point IDCT operation unit 41 shown in FIG. 4 is provided to realize the N / 2 point IDST operation unit 22 in the inverse conversion processing device 2 shown in FIG. N / 2 adders 23-0 to N / 2-1 shown in FIG. 4 and N / 2 subtractors 24-0 to N / 2-1 shown in FIG. Same as 2.

Among the addition units 23-0 to N / 2-1, the addition unit 23-2m adds the value y (2m) and the value z (2m) as it is. On the other hand, of the adders 23-0 to N / 2-1, the adder 23-2m + 1 adds the value y (2m + 1) and the value of the value z (2m + 1) inverted by the sign inverting unit 42-2m + 1. Do. However, m is an integer from 0 to "(N / 4) -1". The half multiplication unit 27-n-a halves the sum which is the addition result of the addition unit 23-n. However, n is an integer from 0 to "(N / 2) -1". As a result, the output values x ′ ₀ , x ′ ₂ , x ′ ₄ ,..., X ′ _{N− 2} are output from the inverse transformation processing device 4.

Among the subtracting units 24-0 to N / 2-1, the subtracting units 24-0 to 2m subtracts the value z (2m) from the value y (2m) as it is. On the other hand, among the subtracting units 24-0 to N / 2-1, the subtracting unit 24-2m + 1 subtracts the value whose sign z (2m + 1) is sign-inverted by the sign inverting unit 42-2m + 1 from the value y (2m + 1) . However, m is an integer from 0 to "(N / 4) -1". The half multiplication unit 27-n-b halves the difference which is the subtraction result of the subtraction unit 24-n. However, n is an integer from 0 to "(N / 2) -1". As a result, output values x ′ ₁ , x ′ ₃ , x ′ ₅ ,..., X ′ _N−1 are output from the inverse transform processing device 4.

  According to this modification, in the inverse conversion processing device according to the present embodiment, the N / 2 point IDST calculation unit can be configured by the N / 2 point IDCT calculation unit. Thus, the configuration of the inverse transform processing device can be simplified, and the utilization efficiency of the operation unit can be improved.

[Embodiments of Encoding Device and Decoding Device]
Next, examples of the encoding device and the decoding device according to the present embodiment will be described. As an example of the encoding device and the decoding device, a video signal encoding device and a decoding device will be described as an example.

  FIG. 5 is a block diagram showing an example of the coding apparatus 100 according to the present embodiment. Encoding apparatus 100 shown in FIG. 5 includes a screen division unit 101, a subtraction unit 102, a conversion unit 103, a quantization unit 104, an entropy coding unit 105, an inverse quantization unit 106, and an inverse conversion unit 107. And an adding unit 108, a loop filter 109, an intra prediction unit 110, a motion compensation prediction unit 111, and a switching unit 112.

  The screen division unit 101 inputs a video signal to be encoded, and divides the input signal into blocks of processing units of encoding processing. The screen division unit 101 outputs the signal of the divided block to the subtraction unit 102. The subtraction unit 102 subtracts the signal input from the switching unit 112 from the signal input from the screen division unit 101. The subtraction unit 102 outputs the signal of the subtraction result to the conversion unit 103.

  The transform unit 103 transforms the signal input from the subtractor unit 102, and outputs the signal of the transform result to the quantization unit 104. In the present embodiment, the conversion unit 103 is configured by the conversion processing device 1 shown in FIG. 1 or the conversion processing device 3 shown in FIG.

  The quantization unit 104 quantizes the signal input from the transform unit 103, and outputs the quantized signal to the entropy coding unit 105 and the dequantization unit 106. The entropy coding unit 105 performs entropy coding on the signal input from the quantization unit 104, and outputs a coded signal. As entropy coding, for example, CABAC (Context-based adaptive binary coding), CAVLC (Context-adaptive variable-length coding) or PIPE (Probability interval partitioning entropy) can be used.

  The inverse quantization unit 106 inversely quantizes the signal input from the quantization unit 104, and outputs the inversely quantized signal to the inverse transform unit 107. The inverse transform unit 107 performs inverse transform on the signal input from the inverse quantization unit 106, and outputs a signal of the result of the inverse transform to the addition unit 108. The inverse conversion performed by the inverse conversion unit 107 is the inverse conversion of the conversion performed by the conversion unit 103. In the present embodiment, the inverse conversion unit 107 is configured by the inverse conversion processing device 2 shown in FIG. 2 or the inverse conversion processing device 4 shown in FIG. The addition unit 108 adds the signal input from the inverse conversion unit 107 and the signal input from the switching unit 112, and outputs a signal of the addition result to the loop filter 109.

  The loop filter 109 performs filtering such as smoothing on the signal input from the adding unit 108, and outputs the signal of the filtering result to the intra prediction unit 110 and the motion compensation prediction unit 111. The intra prediction unit 110 performs intra prediction on the signal input from the loop filter 109, and outputs a signal of the intra prediction result to the switching unit 112. The motion compensation prediction unit 111 performs motion compensation prediction on the signal input from the loop filter 109, and outputs a signal of the motion compensation prediction result to the switching unit 112. The switching unit 112 switches which of the signal input from the intra prediction unit 110 or the signal input from the motion compensation prediction unit 111 is to be output. The signal output from the switching unit 112 is input to the subtracting unit 102 and the adding unit 108.

  In the encoding device 100 shown in FIG. 5, the conversion unit 103 includes the conversion processing device of the present embodiment. Thereby, since the delay time in the transform unit 103 is shortened, the delay time in the encoding process can also be shortened. From this, it is possible to obtain an effect that it is easy to apply large size conversion to the video signal. This is preferable from the viewpoint of coding efficiency particularly in coding of high resolution video signals.

  FIG. 6 is a block diagram showing an example of the decoding apparatus 200 according to the present embodiment. The decoding device 200 shown in FIG. 6 performs decoding corresponding to the coding of the coding device 100 of FIG. 5 described above. The decoding apparatus 200 illustrated in FIG. 6 includes an entropy decoding unit 201, an inverse quantization unit 202, an inverse conversion unit 203, an addition unit 204, a screen combining unit 205, a loop filter 206, and an intra prediction unit 207. A motion prediction unit 208 and a switching unit 209 are provided.

  The entropy decoding unit 201 receives an encoded signal to be decoded, and performs entropy decoding on the input encoded signal. The entropy decoding unit 201 outputs the signal of the entropy decoding result to the inverse quantization unit 202. The inverse quantization unit 202 inversely quantizes the signal input from the entropy decoding unit 201, and outputs the inversely quantized signal to the inverse transform unit 203.

  The inverse transform unit 203 performs inverse transform on the signal input from the inverse quantization unit 202, and outputs a signal as a result of the inverse transform to the addition unit 204. The inverse conversion performed by the inverse conversion unit 107 is the inverse conversion of the conversion performed by the conversion unit 103 shown in FIG. 5 described above. In the present embodiment, the inverse conversion unit 203 is configured by the inverse conversion processing device 2 shown in FIG. 2 or the inverse conversion processing device 4 shown in FIG.

  The addition unit 204 adds the signal input from the inverse conversion unit 203 and the signal input from the switching unit 209, and outputs a signal of the addition result to the screen combining unit 205 and the loop filter 206. The screen combining unit 205 combines blocks of processing units of decoding processing configured from the signal input from the adding unit 204 to generate a video signal. The screen combining unit 205 outputs the generated video signal as a decoded signal.

  The loop filter 206 performs super-resolution processing on the signal input from the addition unit 204, and outputs the signal of the super-resolution processing result to the intra prediction unit 207 and the motion prediction unit 208. The intra prediction unit 207 performs intra prediction on the signal input from the loop filter 206, and outputs the signal of the intra prediction result to the switching unit 209. The motion prediction unit 208 performs motion prediction on the signal input from the loop filter 206, and outputs a signal of the motion prediction result to the switching unit 209. The switching unit 209 switches which of the signal input from the intra prediction unit 207 or the signal input from the motion prediction unit 208 is to be output. The switching control of the switching unit 209 is performed based on the addition result of the adding unit 204. The signal output from the switching unit 209 is input to the adding unit 204.

  Next, one of the effects of the encoding device 100 according to the present embodiment will be described. In the coding of the video signal, it is preferable to apply the conversion with a pixel block size suitable for the video signal, since finer coding control can be performed. For example, MPEG-H HEVC / H. In the video coding method of H.265, two-dimensional orthogonal transform can be performed with a pixel block size of "4 × 4" to "32 × 32". From this, in the encoding device 100, conversion of a plurality of pixel block sizes may be performed. For example, the conversion unit 103 shown in FIG. 5 described above is configured to convert a plurality of pixel block sizes. Further, the inverse conversion unit 107 shown in FIG. 5 and the inverse conversion unit 203 shown in FIG. 6 are configured to perform inverse conversion of a plurality of pixel block sizes. At this time, according to the conversion processing apparatus of the present embodiment, the following effects can be obtained.

  FIG. 7 is a configuration diagram for explaining orthogonal transform in the conventional video coding system. As a conventional video coding method, for example, MPEG-H HEVC / H. No. 265 is a video encoding method. FIG. 7 (a) shows the configuration of the first stage of the butterfly operation in 8-point DCT in which the orthogonal transformation block size is “8 × 8”, and FIG. 7 (b) shows the orthogonal transformation block size “4”. The configuration of the first stage of the butterfly operation in the four-point DCT which is × 4 ”is shown. As apparent from comparison between FIG. 7A and FIG. 7B, the output value of the first stage of the butterfly operation in the 8-point DCT shown in FIG. This is different from the output value of the first stage of the butterfly operation in two minutes of the 4-point DCT. For this reason, there is no part that can be made common in the configuration of the butterfly operation in the 8-point DCT shown in FIG. 7A and the configuration of the butterfly operation in the 4-point DCT shown in FIG. 7B. Therefore, in the prior art, when performing orthogonal transformation of a plurality of pixel block sizes, it is necessary to perform butterfly computation of all pixel block sizes.

  FIG. 8 is a configuration diagram for explaining conversion in the present embodiment. FIG. 8A shows the configuration of four two-point Hadamard transformations in 8-point transformation in which the transformation block size is “8 × 8”. FIG. 8B shows two configurations of two two-point Hadamard transformations for two of the two-point transformation whose transformation block size is “4 × 4”. As apparent from comparison between FIG. 8 (a) and FIG. 8 (b), output values of the configuration of four two-point Hadamard transformations shown in FIG. 8 (a) and two shown in FIG. 8 (b) The output values of the two sets of two-point Hadamard transform of are the same. Therefore, the configuration of the two-point Hadamard transformation in the eight-point conversion shown in FIG. 8A and the configuration of the two-point Hadamard transformation in the four-point conversion shown in FIG. 8B can be made common.

  Therefore, according to the present embodiment, in the case of performing conversion of a plurality of pixel block sizes, at least a configuration of N / 2 two-point Hadamard conversion in N-point conversion of the maximum pixel block size may be provided. For example, in the present embodiment, as shown in FIG. 8, when performing 8-point conversion of pixel block size of “8 × 8” and 4-point conversion of pixel block size of “4 × 4”, 8-point conversion The configuration of the four two-point Hadamard transforms in is shared with the two two-point Hadamard transforms in the four-point transform. Thus, according to the present embodiment, when performing conversion of a plurality of pixel block sizes, it is not necessary to separately calculate the configuration of two-point Hadamard transformation for all pixel block sizes.

  As described above with reference to FIGS. 7 and 8, according to the present embodiment, the apparatus configuration can be simplified when the encoding apparatus 100 performs conversion of a plurality of pixel block sizes. An effect is obtained.

  Note that the conversion processing device according to the present embodiment may be realized by dedicated hardware, or may be configured by a memory and a CPU, and a computer program for realizing the function of the conversion processing device is a CPU The function may be realized by executing the. The same applies to the inverse conversion processing device according to the present embodiment.

  Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and design changes and the like within the scope of the present invention are also included.

  The embodiments described above can be applied to various video block coding schemes based on pixel blocks. For example, MPEG-2, MPEG-4 AVC / H. H.264, MPEG-H HEVC / H. The present invention can be applied to a video coding method such as H.265. In addition, the present invention is also applicable to a video coding method in which predictive coding is not performed.

  Further, in the above-described embodiment, the present invention is applied to the coding device for coding the video signal and the decoding device corresponding to the coding device, but the present invention is not limited to this. The above-described embodiment is applied to a coding device that generates a coded signal from a signal converted by a predetermined conversion method, and a decoding device that decodes a coded signal generated from a signal converted by a predetermined conversion method. It is possible.

Further, a computer program for realizing the functions of the conversion processing apparatus or the inverse conversion processing apparatus described above is recorded in a computer readable recording medium, and the program recorded in the recording medium is read into a computer system and executed. You may do so. Note that the “computer system” referred to here may include an OS and hardware such as peripheral devices.
The “computer readable recording medium” is a writable non-volatile memory such as a flexible disk, a magneto-optical disk, a ROM, a flash memory, etc., a portable medium such as a DVD (Digital Versatile Disk), and a computer system. Storage devices such as hard disks.

Furthermore, the “computer-readable recording medium” is a volatile memory (for example, DRAM (Dynamic Memory) inside a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line). As Random Access Memory), it is assumed that the program which holds the program for a fixed time is included.
The program may be transmitted from a computer system in which the program is stored in a storage device or the like to another computer system via a transmission medium or by transmission waves in the transmission medium. Here, the “transmission medium” for transmitting the program is a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line.
Further, the program may be for realizing a part of the functions described above. Furthermore, it may be a so-called difference file (difference program) that can realize the above-described functions in combination with a program already recorded in the computer system.

1, 3 ... conversion processing device, 2, 4 ... reverse conversion processing device, 11-0 to N / 2 -1, 2 3 0 to N / 2 1, 108, 204 ... addition unit, 12-0 to N / 2-1, 24-0 to N / 2-1, 102 ... subtraction unit, 13, 32 ... N / 2 point DCT operation unit, 14 ... N / 2 point DST operation unit, 21, 41 ... N / 2 point IDCT Arithmetic unit, 22... N / 2-point IDST arithmetic unit, 27-0 to N / 2-a, 27-0 to N / 2-b... 1/2 times portion, 31-1 to N / 2-1, 42 -1 to N / 2-1: sign inversion unit, 100: encoding device, 101: screen division unit, 103: transformation unit, 104: quantization unit, 105: entropy encoding unit, 106, 202: inverse quantization , 107, 203 ... inverse transform unit, 109, 206 ... loop filter, 110, 207 ... intra prediction unit, 111 ... motion compensation prediction unit, 112 209 ... switching unit, 200 ... decoding unit, 201 ... entropy decoding unit, 205 ... screen combining unit, 208 ... motion prediction unit

Claims (7)

In a conversion processing apparatus that performs conversion of N points whose conversion block size is “N × N, where N is an integer of 4 or more”,
N / 2 two-point Hadamard transformation units that perform two-point Hadamard transformation with a transformation block size of “2 × 2” for each pair of input values whose arrangement is continuous in N input values;
N / 2-point DCT operation unit that performs discrete cosine transform operation with orthogonal transform block size “N / 2 × N / 2” on the sum of two input values among the results of the two-point Hadamard transform When,
N / 2-point DST operation unit that performs discrete sine transform operation with orthogonal transform block size “N / 2 × N / 2” on the difference between two input values among the results of the two-point Hadamard transform When,
Conversion processing device comprising: The conversion processing apparatus that converts a plurality of conversion block sizes (N points),
The N / 2-point DCT operation unit and the N / 2-point DST operation unit respectively corresponding to the plurality of transform block sizes (N points);
The two-point Hadamard transform unit is shared by the N / 2-point DCT operation unit and the N / 2-point DST operation unit respectively corresponding to the plurality of transform block sizes (N points).
The conversion processing device according to claim 1. In an inverse transform processing apparatus that performs inverse transform of N points whose inverse transform block size is “N × N, where N is an integer of 4 or more”,
The inverse transform block size is N / N for N / 2 input values that are the result of discrete cosine transform whose orthogonal transform block size is “N / 2 × N / 2” among N input values. An N / 2-point IDCT operation unit that performs an inverse discrete cosine transform operation that is 2 × N / 2 ′ ′;
Of the N input values, the inverse orthogonal transform block size is “N” for N / 2 input values that are the result of discrete sine transform whose orthogonal transform block size is “N / 2 × N / 2”. An N / 2 point IDST operation unit that performs an inverse discrete sine conversion operation that is 2 / 2N / 2 ";
An inverse transform signal generation unit that generates a signal after inverse transform using the output value from the N / 2 point IDCT operation unit and the output value from the N / 2 point IDST operation unit;
Inverse conversion processing device comprising: In an encoding device that generates an encoded signal from a signal converted by a predetermined conversion method,
The encoding apparatus provided with the conversion processing apparatus of any one of Claim 1 or 2. In a decoding device for decoding a coded signal generated from a signal converted by a predetermined conversion method,
A decoding apparatus comprising the inverse transform processing apparatus according to claim 3. A computer program for performing conversion of N points whose conversion block size is “N × N, where N is an integer of 4 or more”,
N / 2 two-point Hadamard transform functions that perform two-point Hadamard transforms whose transform block size is “2 × 2” for each pair of input values whose sequence is continuous in N input values;
N / 2 point DCT operation function that performs discrete cosine transform operation with orthogonal transform block size “N / 2 × N / 2” on the sum of two input values among the results of the two-point Hadamard transform When,
N / 2-point DST operation function that performs discrete sine transformation operation with orthogonal transformation block size “N / 2 × N / 2” on the difference between two input values among the results of the two-point Hadamard transformation When,
A computer program for realizing a computer. A computer program for performing inverse conversion of N points whose inverse conversion block size is “N × N, where N is an integer of 4 or more”,
The inverse transform block size is N / N for N / 2 input values that are the result of discrete cosine transform whose orthogonal transform block size is “N / 2 × N / 2” among N input values. N / 2-point IDCT operation function which performs inverse discrete cosine transform operation which is 2 × N / 2 ′ ′;
Of the N input values, the inverse orthogonal transform block size is “N” for N / 2 input values that are the result of discrete sine transform whose orthogonal transform block size is “N / 2 × N / 2”. N / 2 point IDST operation function that performs inverse discrete sine conversion operation which is 2 / 2N / 2 ";
An inverse transform signal generation function of generating a signal after inverse transform using an output value from the N / 2 point IDCT operation function and an output value from the N / 2 point IDST operation function;
A computer program for realizing a computer.

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