JP2012147205A - Discrete sine transform circuit, inverse discrete sine transform circuit, combination-use circuit, encoding device, decoding device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress cost and power consumption by realizing DST or IDST using a widespread existing DCT circuit or IDCT circuit respectively.SOLUTION: Inversion elements 10-1 and 10-2 of a DST circuit 1-1 input a signal g(x) corresponding to odd-numbered x among signals g(x), and invert its sign. A DCT circuit 11 inputs the first signal g(0) and the third signal g(2) among the signals g(x) parallelized in a unit of four points, and inputs the second signal g(1) and the fourth signal g(3) whose signs are inverted from the inversion elements 10-1 and 10-2. Then, the DCT circuit 11 performs DCT in a unit of four input points using an operational expression of DCT. Thereby, DST can be realized using the DCT circuit 11.

Description

  The present invention relates to a discrete sine transform circuit, an inverse discrete sine transform circuit, a combinational circuit, an encoding device, a decoding device, and a program, and in particular, performs discrete sine transform using discrete cosine transform and uses inverse discrete cosine transform. The present invention relates to a technique for performing inverse discrete sine transform.

  Conventionally, in the field of video or audio coding, processing by discrete cosine transform (hereinafter referred to as DCT) has been widely used. For example, a high-speed DCT algorithm based on butterfly computation using the periodicity of trigonometric functions is used in many fields such as low power consumption circuit implementation technology (see Non-Patent Document 1). Discrete sine transform (hereinafter referred to as DST) also has the same properties as DCT, and similarly, high-speed computation is possible using the periodicity of trigonometric functions.

  Since DST has very few fields of use, development of high-speed processing apparatuses that perform DST has not been carried out much. However, with the recent advancement of coding technology, the field of use has expanded, and the demand for DST is increasing. On the other hand, the DCT application range is currently wider than the DST application range. Therefore, in order to use DCT and DST together, it is assumed that a DST circuit is newly added to the DCT circuit. However, this combined device is not preferable because it is necessary to provide a DCT circuit and a DST circuit, respectively, which increases the cost and power consumption.

  FIG. 9 is a block diagram showing a configuration of a conventional encoding apparatus using both DCT and DST. The encoding apparatus 100 includes a preprocessing unit 101, a subtraction unit 102, a DCT unit 103, a DST unit 104, a switching unit 105, a quantization unit 106, an entropy encoding unit 107, an inverse quantization unit 108, a switching unit 109, an IDCT. Unit 110, IDST unit 111, addition unit 112, frame memory 113, and signal prediction unit 114. α1 and β1 will be described later.

  The preprocessing unit 101 inputs a signal to be encoded, and performs predetermined preprocessing necessary for encoding on the input signal. Since the preprocessing is known, the description thereof is omitted here. The subtraction unit 102 receives the preprocessed signal from the preprocessing unit 101 and also receives the prediction signal from the signal prediction unit 114 described later, and subtracts the prediction signal from the preprocessed signal.

  The DCT unit 103 receives the subtraction result signal from the subtraction unit 102 and performs DCT. In addition, the DST unit 104 inputs a signal of the subtraction result from the subtraction unit 102 and performs DST. The switching unit 105 inputs the signal DCT (DCT signal) DCT unit 103 or the DST signal DST (DST signal) DST unit 104, and switches one of the signals.

  The quantization unit 106 receives the DCT signal or DST signal from the switching unit 105 and performs quantization. The entropy encoding unit 107 receives the quantized signal from the quantization unit 106, performs entropy encoding, and outputs the encoded signal. The inverse quantization unit 108 receives the quantized signal from the quantization unit 106, performs inverse quantization, and outputs the inversely quantized signal to the switching unit 109. Since the processes of entropy coding, quantization, and inverse quantization are known, the description thereof is omitted here.

  The switching unit 109 receives the inversely quantized signal from the inverse quantizing unit 108 and performs switching for outputting this signal to either the IDCT unit 110 or the IDST unit 111. In this case, the switching unit 109 performs the same switching as the switching unit 105. That is, when the switching unit 105 performs switching for outputting a signal from the DCT unit 103, the switching unit 109 performs switching for outputting the input signal to the IDCT unit 110. On the other hand, when the switching unit 105 performs switching for outputting a signal from the DST unit 104, the switching unit 109 performs switching for outputting the input signal to the IDST unit 111.

  IDCT section 110 receives a signal from switching section 109, performs IDCT, and outputs an IDCT signal to addition section 112. In addition, IDST section 111 receives a signal from switching section 109, performs IDST, and outputs an IDST signal to addition section 112. The adder 112 receives the IDCT signal from the IDCT unit 110 or the IDST signal from the IDST unit 111, and also inputs the prediction signal from the signal prediction unit 114 described later, and adds both signals.

  The frame memory 113 receives the addition result signal from the adder 112 and stores it as a decoded signal. The decoded signal stored in the frame memory 113 is read out as a reference signal when generating a prediction signal by the signal prediction unit 114 described later.

  The signal prediction unit 114 reads the reference signal from the frame memory 113, generates a prediction signal by a predetermined prediction method based on the reference signal, and outputs the prediction signal to the subtraction unit 102 and the addition unit 112. Since the method for generating the prediction signal is known, the description thereof is omitted here. Note that the prediction method used for the processing of the signal prediction unit 114 is, for example, H.264. Intra prediction, motion compensation prediction, and the like used in H.264 may be used.

  As described above, the coding apparatus 100 shown in FIG. 9 includes the DCT unit 103 and the DST unit 104 having substantially the same scale as the DCT unit 103. Further, the coding apparatus 100 substantially includes the IDCT unit 110 and the IDCT unit 110. An IDST unit 111 of the same scale is provided. Therefore, two similar circuits of the same scale exist, so that the circuit scale increases as a whole, resulting in an increase in cost and power consumption.

  FIG. 10 is a block diagram showing a configuration of a conventional decoding apparatus using an inverse discrete cosine transform (hereinafter referred to as IDCT) and an inverse discrete sine transform (hereinafter referred to as IDST) together. FIG. The decoding apparatus 200 includes an entropy decoding unit 201, an inverse quantization unit 202, a switching unit 203, an IDCT unit 204, an IDST unit 205, an addition unit 206, a post-processing unit 207, a frame memory 208, and a signal prediction unit 209. . γ1 will be described later.

  The entropy decoding unit 201 receives the encoded signal output from the encoding device 100 illustrated in FIG. 9 and performs entropy decoding corresponding to the entropy encoding of the entropy encoding unit 107 illustrated in FIG. 9. Since the entropy decoding process is known, the description thereof is omitted here. The inverse quantization unit 202 inputs the signal entropy-decoded by the entropy decoding unit 201, performs inverse quantization, and switches the inverse-quantized signal to the switching unit 203 in the same manner as the inverse quantization unit 108 illustrated in FIG. Output to.

  The switching unit 203 receives the inverse-quantized signal from the inverse-quantizing unit 202 and performs switching for outputting this signal to either the IDCT unit 204 or the IDST unit 205.

  The IDCT unit 204 receives a signal from the switching unit 203, performs IDCT, and outputs an IDCT signal to the adding unit 206. IDST section 205 receives a signal from switching section 203, performs IDST, and outputs an IDST signal to addition section 206. The adder 206 receives the IDCT signal from the IDCT unit 204 or the IDST signal from the IDST unit 205, and also receives the prediction signal from the signal prediction unit 209 described later, and adds both signals.

  The post-processing unit 207 inputs a decoded signal that is a signal resulting from the addition from the adding unit 206, and performs predetermined post-processing corresponding to the pre-processing of the pre-processing unit 101 illustrated in FIG. Output as an output signal. Since post-processing is already known, description thereof is omitted here.

  The frame memory 208 receives the addition result signal from the addition unit 206 and stores it as a decoded signal. The decoded signal stored in the frame memory 208 is read out as a reference signal when generating a prediction signal by a signal prediction unit 209 described later.

  The signal prediction unit 209 reads the reference signal from the frame memory 208, generates a prediction signal by a predetermined prediction method based on the reference signal, and outputs the prediction signal to the addition unit 206.

  As described above, the decoding device 200 illustrated in FIG. 10 includes an IDCT unit 204 and an IDST unit 205 having substantially the same scale as the IDCT unit 204. Therefore, since there are two similar circuits of the same scale, the circuit scale increases as a whole, resulting in an increase in cost and power consumption.

W.Chen, C.H.Smith, and S.C.Fralick, “A fast computational algorithm for the discrete cosine transform,” IEEE Trans. Commun., Vol.COMM-25, pp.1004-1009, Sept. 1977.

  As described above, a device using both DCT and DST and a device using IDCT and IDST both need to be provided with independent conversion circuits, so that there is a problem that the cost increases and the power consumption increases. Therefore, it is desirable to realize DST by sharing a part of existing DCT circuits that are widely spread and adding a few functions and circuits. The same applies to the implementation of IDST.

  Accordingly, the present invention has been made to solve the above-mentioned problems, and the object thereof is to realize DST or IDST by using a widely used existing DCT circuit or IDCT circuit, respectively, thereby reducing cost and consumption. An object is to provide a DST circuit, an IDST circuit, a combined circuit, an encoding device, a decoding device, and a program capable of suppressing power.

  To achieve the above object, the discrete sine transform circuit according to claim 1 of the present invention is a discrete sine transform circuit that performs discrete sine transform on an input signal, and includes an inverting element that inverts the sign of part of the signal, A preprocessing unit that outputs a signal whose sign is inverted by an inverting element and another signal whose sign is not inverted, and a discrete cosine transform circuit that performs discrete cosine transform, and the preprocessing unit A part of the sign is inverted, the signal with the sign inverted and the other input signal with the sign not inverted are output as a signal for discrete sine, and the discrete cosine transform circuit is output by the preprocessing unit A discrete cosine transform is performed on the signal for discrete sine.

  According to a second aspect of the present invention, there is provided a combinational circuit including the discrete sine transformation circuit according to the first aspect, wherein the combinational circuit performs discrete cosine transformation or discrete sine transformation by switching signals, In addition to the preprocessing unit and the discrete cosine transform circuit, a switching circuit is provided, and the switching circuit inputs the discrete sine signal output by the preprocessing unit and inputs the input signal as a discrete cosine signal. Then, one of the two input signals is switched and output, and the discrete cosine transform circuit performs discrete cosine transform on the signal output by the switching circuit.

  The inverse discrete sine transform circuit according to claim 3 of the present invention is an inverse discrete sine transform circuit for performing an inverse discrete sine transform on an input signal, and an inverse discrete cosine transform circuit for performing an inverse discrete cosine transform on the input signal; A post-processing unit that has an inverting element that inverts the sign of a part of the signal converted by the cosine conversion circuit, and that outputs a signal whose sign is inverted by the inverting element and another signal whose sign is not inverted, It is characterized by having.

  According to a fourth aspect of the present invention, there is provided a combinational circuit including the inverse discrete sine transform circuit according to the third aspect and performing an inverse discrete cosine transform or an inverse discrete sine transform by switching signals. In addition to the inverse discrete cosine transform circuit and the post-processing unit, a switching circuit is provided, and the switching circuit switches the signal transformed by the inverse discrete cosine transform circuit, as a signal after inverse discrete cosine transform, or inversely Output as a signal for discrete sine, and the post-processing unit inverts a part of the sign of the signal for inverse discrete sine output by the switching circuit, and the signal with the inverted sign and the sign is not inverted Another inverse discrete sine signal is output as a signal after inverse discrete sine transform.

  An encoding apparatus according to claim 5 of the present invention comprises the combinational circuit according to claim 2 and the combinational circuit according to claim 4, wherein the encoding apparatus encodes an input signal and outputs an encoded signal. 3. The combinational circuit according to claim 2, wherein a signal to be encoded generated based on an input signal and a prediction signal is input, and a signal after discrete sine transform or a signal after discrete cosine transform is output; A quantization unit that quantizes a signal or a signal after discrete cosine transform, an inverse quantization unit that inversely quantizes the quantized signal, and an input of the inverse quantized signal, and after inverse discrete sine transform And a signal predicting unit that generates the prediction signal based on the signal after the inverse discrete sine transform or the signal after the inverse discrete cosine transform; Comprising the above Based on the signal after coca, and generates and outputs an encoded signal, characterized in that.

  According to a sixth aspect of the present invention, there is provided a decoding apparatus comprising the combinational circuit according to the fourth aspect, wherein the decoding apparatus decodes an input encoded signal and outputs a decoded signal, wherein the encoded signal is inversely quantized. And a combinational circuit according to claim 4 that inputs the signal after inverse quantization and outputs a signal after inverse discrete sine transform or a signal after inverse discrete cosine transform, and after the inverse discrete sine transform A signal prediction unit that generates a prediction signal based on the signal or the signal after the inverse discrete cosine transform, and based on the signal after the inverse discrete sine transform or the signal after the inverse discrete cosine transform and the prediction signal, A decoded signal is generated and output.

  According to a seventh aspect of the present invention, there is provided a computer program comprising: a computer; a discrete sine transform circuit according to the first aspect; an inverse discrete sine transform circuit according to the third aspect; a combined circuit according to the second or fourth aspect; The coding apparatus according to Item 5 or the decoding apparatus according to Claim 6 is made to function.

  As described above, according to the present invention, DST is realized using a DCT circuit, and IDST is realized using an IDCT circuit. As a result, the same circuit can be shared and the number of circuits can be reduced, so that the cost and power consumption can be suppressed as a whole.

(1) is a block diagram showing a configuration of a 4-point DST circuit according to an embodiment of the present invention. (2) is a block diagram showing a configuration of an 8-point DST circuit. (1) is a block diagram showing a configuration of a 4-point IDST circuit according to an embodiment of the present invention. (2) is a block diagram showing a configuration of an 8-point IDST circuit. It is a block diagram which shows the structure of the DCT / DST combined circuit by embodiment of this invention. It is a block diagram which shows the structure of the IDCT / IDST combined circuit by embodiment of this invention. It is a block diagram which shows the structure of the DCT / DST combined circuit which switches by a control signal. It is a block diagram which shows the structure of the IDCT / IDST combined circuit which switches by a control signal. It is a block diagram which shows the structure of the encoding apparatus by embodiment of this invention. It is a block diagram which shows the structure of the decoding apparatus by embodiment of this invention. It is a block diagram which shows the structure of the conventional encoding apparatus. It is a block diagram which shows the structure of the conventional decoding apparatus.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
[DCT and DST equations]
First, the relationship between the DCT arithmetic expression and the DST arithmetic expression, which is the basic principle of the embodiment of the present invention, will be described. DCT and DST are one of the methods derived from Fourier transform using trigonometric functions as transform kernels. A sine function and a cosine function are periodic functions that are orthogonal to each other, and by using this property, a DST arithmetic expression can be derived from a DCT arithmetic expression as shown below.

但し、Ｃ（ｕ）は以下のとおりである。

The u-order DST coefficient G (u) expressed by the one-dimensional N-point DST equation is expressed by the following equation.

However, C (u) is as follows.

Here, in order to change the order range from 0 to N-1, when u is replaced with N-u, the following equation is obtained.

From the above equation (3), it is understood that the u-th order DST coefficient G (N−u) includes a component of a DCT arithmetic expression when a signal whose sign is inverted every step is used as an input signal. This is because the u-order DCT coefficient G (N−u) represented by the one-dimensional N-point DCT equation is represented by the following equation.

前記式（５）から、ｕ次のＩＤＳＴ係数ｇ（ｘ）は、ＩＤＣＴの演算式の成分が含まれており、ＩＤＣＴ式による演算結果に対し１ステップ毎に符号反転して得られることがわかる。 Similarly, the u-th order IDST coefficient g (x) expressed by the one-dimensional N-point IDST formula is also expressed by the following formula.

From the above equation (5), it can be seen that the u-th order IDST coefficient g (x) includes the component of the IDCT arithmetic expression and is obtained by inverting the sign for each step of the calculation result by the IDCT expression. .

  In this manner, the DST arithmetic expression can be derived from the DCT arithmetic expression, and similarly, the IDST arithmetic expression can be derived from the IDCT arithmetic expression. In the present invention, DST using a DCT circuit is realized based on the relationship between the above-described DCT arithmetic expression and the DST arithmetic expression and the relation between the IDCT arithmetic expression and the IDST arithmetic expression. IDST using an IDCT circuit is realized.

[DST circuit]
First, a DST circuit using a DCT circuit will be described. FIG. 1A is a block diagram showing a configuration of a 4-point DST circuit according to an embodiment of the present invention. The DST circuit 1-1 includes inverting elements 10-1 and 10-2, a DCT circuit 11, and a replacement circuit 12. The DST circuit 1-1 parallelizes and inputs a signal to be converted every four steps (points), uses the DCT circuit 11 to realize DST, and outputs it as a DST coefficient. Referring to the equations (1) to (3), the input signal of the DST circuit 1-1 is g (x), x = 0, 1, 2, 3 and the DST coefficient which is the output signal is G (u). , U = 0, 1, 2, 3.

  The inverting element 10-1 receives g (1) of the input signal g (x) and inverts the sign. The inverting element 10-2 receives g (3) of the input signal g (x) and inverts the sign.

  The DCT circuit 11 receives the first input signal g (0) of the input signals g (x) and the second input signal g (1) whose sign is inverted from the inverting element 10-1. The DCT circuit 11 receives the third input signal g (2) and also receives the fourth input signal g (3) whose sign is inverted from the inverting element 10-2. Then, the DCT circuit 11 performs DCT for every four input points according to the DCT arithmetic expression shown in the equation (4). The DCT circuit 11 outputs DST coefficients G (3), G (2), G (1), and G (0).

  The exchange circuit 12 inputs the DST coefficient G (u) every 4 points from the DCT circuit 11 and exchanges the order every 4 points. The replacement circuit 12 replaces the DST coefficient G (0) as the first output signal, the DST coefficient G (1) as the second output signal, and the DST coefficient G (2) as the third output signal. The DST number G (3) is output as the fourth output signal.

  Thereby, the DST circuit 1-1 outputs DST coefficients G (0) to G (3) as output signals for the input signals g (0) to g (3).

  In FIG. 1 (1), the order of the DST coefficients G (u) every 4 points is switched by the switching circuit 12, and the DST circuit 1-1 changes the DST coefficients G (u) from the lower order to the higher order by 4 points. Although output is performed in ascending order every time, high-order to low-order DST coefficients G (u) output by the DCT circuit 11 are output as they are in descending order every 4 points without being replaced by the replacement circuit 12. You may make it do. That is, the replacement circuit 12 may be omitted from the DST circuit 1-1 shown in FIG.

  FIG. 1B is a block diagram showing a configuration of an 8-point DST circuit according to the embodiment of the present invention. The DST circuit 1-2 includes inverting elements 13-1 to 13-4, a DCT circuit 14, and a replacement circuit 15. The DST circuit 1-2 parallelizes and inputs a signal to be converted every 8 steps (points), uses the DCT circuit 14 to realize DST and outputs it as a DST coefficient. The DST circuit 1-2 is an extension of the 4-point DST circuit 1-1 shown in FIG.

  In FIG. 1 (2), the order of the DST coefficients G (u) every 8 points is switched by the switching circuit 15, and the DST circuit 1-2 sets the DST coefficients G (u) from the lower order to the higher order 8 points. Although the output is performed in ascending order every time, the replacement by the replacement circuit 15 may not be performed. That is, the replacement circuit 15 may be omitted in the DST circuit 1-2 shown in FIG.

  Thus, according to the 4-point DST circuit 1-1 shown in FIG. 1A and the 8-point DST circuit 1-2 shown in FIG. 1B, the 4-point DCT circuit 11 is used. In addition, DST processing is performed using the DCT circuit 14 for 8 points. As a result, DST can be realized without using a DST circuit that executes an arithmetic expression of DST.

  1 (1) shows an example of a 4-point DST circuit 1-1, and FIG. 1 (2) shows an example of an 8-point DST circuit 1-2. The DST circuit for use can be realized by the same extension.

[IDST circuit]
Next, an IDST circuit using an IDCT circuit will be described. FIG. 2A is a block diagram showing a configuration of a 4-point IDST circuit according to the embodiment of the present invention. The IDST circuit 2-1 includes a replacement circuit 21, an IDCT circuit 22, and inverting elements 23-1 and 23-2. The IDST circuit 2-1 inputs the signal to be converted in parallel every four steps (points), and implements IDST by using the IDCT circuit 22, and outputs it as an IDST coefficient. Referring to the equation (5), the input signal of the IDST circuit 2-1 is G (u), u = 0, 1, 2, 3, and the IDST coefficient as an output signal is g (x), x = 0. , 1, 2, 3.

  The replacement circuit 21 inputs the input signal G (u) in parallel every four points, and switches the order of every four points. The replacement circuit 21 outputs the signal G (3) as the first output signal for the first input signal G (0) by the replacement, and the second input signal G (1) for the second input signal G (1). A signal G (2) is output as an output signal, a signal G (1) is output as a third output signal for the third input signal G (2), and a fourth input signal G (3) is output. The signal G (0) is output as the fourth output signal.

  The IDCT circuit 22 receives the signal G (u) every 4 points from the switching circuit 21 and performs IDCT by the IDCT arithmetic expression every 4 points. The IDCT circuit 22 outputs a signal obtained by inverting the IDST coefficient g (0), the IDST coefficient g (1), and a signal obtained by inverting the IDST coefficient g (2) and the IDST coefficient g (3).

  The inverting element 23-1 receives a signal obtained by inverting the IDST coefficient g (1) from the IDCT circuit 22, and inverts the sign. The inverting element 23-2 receives a signal obtained by inverting the IDST coefficient g (3) from the IDCT circuit 22, and inverts the sign.

  As a result, the IDST circuit 2-1 outputs IDST coefficients g (0) to g (3) as output signals for the input signals G (0) to G (3).

  In FIG. 2A, the order of the signals G (u) every 4 points is switched by the switching circuit 21, and the IDST circuit 2-1 changes the IDST coefficient g (x) from the lower order to the higher order every 4 points. Are output in ascending order, but the IDST coefficient g (x) from higher order to lower order may be output in descending order every 4 points without being replaced by the replacement circuit 21. That is, the replacement circuit 21 may be omitted from the IDST circuit 2-1 shown in FIG.

  FIG. 2B is a block diagram showing a configuration of an 8-point IDST circuit according to the embodiment of the present invention. The IDST circuit 2-2 includes a replacement circuit 24, an IDCT circuit 25, and inverting elements 26-1 to 26-4. The IDST circuit 2-2 inputs the signal to be converted in parallel every 8 steps (points), and implements the IDST by using the IDCT circuit 25, and outputs it as an IDST coefficient. The IDST circuit 2-2 is an extension of the 4-point IDST circuit 2-1 shown in FIG.

  In FIG. 2 (2), the order of the signal G (u) every 8 points is switched by the switching circuit 24, and the IDST circuit 2-2 changes the IDST coefficient g (x) from the lower order to the higher order every 8 points. Are output in ascending order, but the replacement by the replacement circuit 24 may not be performed. That is, the replacement circuit 24 may be omitted from the IDST circuit 2-2 shown in FIG.

  In this way, according to the 4-point IDST circuit 2-1 shown in FIG. 2A and the 8-point IDST circuit 2-2 shown in FIG. 2B, the 4-point IDCT circuit 22 is used. IDST processing is performed using the IDCT circuit 25 for 8 points. Thus, IDST can be realized without using an IDST circuit that executes an IDST arithmetic expression.

  2A shows an example of a 4-point IDST circuit 2-1, and FIG. 2B shows an example of an 8-point IDST circuit 2-2. The IDST circuit for use can be realized by the same extension.

[DCT / DST combination circuit]
Next, a circuit using both a DCT circuit and a DST circuit will be described. FIG. 3 is a block diagram showing a configuration of the DCT / DST combined circuit according to the embodiment of the present invention. The DCT / DST combination circuit 3-1 includes delay elements 31-1, 31-2,..., Inverting elements 32-1, 32-2,. The DCT / DST combined circuit 3-1 inputs one system signal to be converted in parallel every N points, and shares the DCT function and the DST function by time division. In addition to realizing DCT, DST is realized using this DCT circuit 33, and a DCT coefficient or a DST coefficient is output in a time division manner every N points.

  The delay elements 31-1, 31-2,... Input signals g (0), g (2),. In order to match the output timing, delay processing for the same processing time as the inverting elements 32-1, 32-2,.

  The inverting elements 32-1, 32-2,... Receive the signals g (1), g (3),. As a result, the timing of the signals output from the delay elements 31-1, 31-2,... And the inverting elements 32-1, 32-2,.

The DCT circuit 33 outputs the signal g (x) parallelized every N points, or N points from the delay elements 31-1, 31-2,... And the inverting elements 32-1, 32-2,. Signals (-1) ^x g (x) parallelized every time are input, and DCT is performed by the DCT arithmetic expression shown in the above equation (4) every N points. When DCT is performed on the signal g (x), the DCT circuit 33 outputs a DCT coefficient G (u), and delay elements 31-1, 31-2,... And inverting elements 32-1, 32. When DCT is performed on the signals (−1) ^x g (x) from −2,..., The DST coefficient G (u) is output.

Here, the signal g (x) input by the DCT circuit 33 or the signal (−1) ^x from the delay elements 31-1, 31-2,... And the inverting elements 32-1, 32-2,. For g (x), one of the signals is input by time division, and for either the DCT coefficient G (u) or the DST coefficient G (u) output from the DCT circuit 33, either signal is also obtained by time division. Is output.

  Further, since the DCT / DST combined circuit 3-1 shown in FIG. 3 outputs either the DCT coefficient G (u) or the DST coefficient G (u) in time division, the order of the signals is changed. The replacement circuit (for example, the replacement circuits 12 and 15 shown in FIGS. 1 (1) and (2)) is not provided. In this case, when the DCT / DST combined circuit 3-1 outputs the DCT coefficient G (u), the low-order to high-order signals are output in ascending order every N points, and the DST coefficient G (u) is output. In this case, high-order to low-order signals are output in descending order every N points.

As described above, according to the DCT / DST combination circuit 3-1 shown in FIG. 3, the DCT circuit 33 performs the signal g (x) or the delay elements 31-1, 31-2, ... and signals from the inverting elements 32-1, 32-2, ... (-1) ^x g (x) are switched and input in a time-sharing manner, and DCT processing is performed. The DCT coefficient G (u) is output for the former signal, and the DST coefficient G (u) is output for the latter signal. That is, the DCT circuit 33 is used to realize not only DCT but also DST. As a result, the same DCT circuit 33 can be shared in order to realize DCT and DST, and the number of circuits can be reduced, so that the cost and power consumption can be suppressed as a whole.

  The DCT / DST combined circuit 3-1 shown in FIG. 3 does not include the replacement circuits 12 and 15 shown in FIGS. 1 (1) and (2), but the order of the output signals is changed as necessary. A replacement circuit for replacement may be provided.

[IDCT / IDST combination circuit]
Next, a circuit using both an IDCT circuit and an IDST circuit will be described. FIG. 4 is a block diagram showing the configuration of the combined IDCT / IDST circuit according to the embodiment of the present invention. The IDCT / IDST combination circuit 4-1 includes an IDCT circuit 41, delay elements 42-1, 42-2,... And inverting elements 43-1, 43-2,. The IDCT / IDST combined circuit 4-1 inputs one system signal to be converted in parallel every N points, and shares the IDCT function and the IDST function by time division. In addition to realizing IDCT, IDST is realized by using this IDCT circuit 41, and IDCT coefficients or IDST coefficients are output in a time division manner every N points.

  The IDCT circuit 41 inputs a signal G (u) that is parallelized every N points, and performs IDCT using an IDCT arithmetic expression. The signal g (x) IDCTed by the IDCT circuit 41 is output as an IDCT coefficient g (x), or delay elements 42-1, 42-2,... And inverting elements 43-1, 43-. Output to 2, ...

  The delay elements 42-1, 42-2,... Receive the signals g (0), g (2),... From the IDCT circuit 41, and the inverting elements 43-1, 43-2,. In order to match the output timing between the inverting elements 43-1, 43-2,...

  The inverting elements 43-1, 43-2,... Receive the signals g (1), g (3),. As a result, the timings of the signals output by the delay elements 42-1, 42-2,... And the inverting elements 43-1, 43-2,. Output as a coefficient g (x).

  Here, the signal output from the IDCT circuit 41 as the IDCT coefficient g (x), or the IDCT circuit 41 includes delay elements 42-1, 42-2,... And inverting elements 43-1, 43-2,. As for the signal to be output to the signal, either one of the signals is output by time division.

  Further, since the IDCT / IDST combination circuit 4-1 shown in FIG. 4 outputs either the IDCT coefficient g (x) or the IDST coefficient g (x) in a time division manner, the order of the signals is changed. The replacement circuit (for example, the replacement circuits 21 and 24 shown in FIGS. 2 (1) and 2) is not provided. In this case, when the IDCT / IDST combination circuit 4-1 inputs the low-order to high-order signal G (u) in ascending order every N points, the IDCT / IDST combination circuit 4-1 starts from the low-order when outputting the IDCT coefficient g (x). When outputting higher order signals in ascending order every N points and outputting IDST coefficient g (x), higher order to lower order signals are outputted in descending order every N points.

  As described above, according to the IDCT / IDST combination circuit 4-1 shown in FIG. 4, the IDCT circuit 41 inputs the signal G (u) of one system, performs IDCT, and uses the IDCT coefficient g (x) as the IDCT coefficient g (x). The signal or any one of the signals to the delay elements 42-1, 42-2,... And the inverting elements 43-1, 43-2,. I made it. The delay elements 42-1, 42-2, ... and the inverting elements 43-1, 43-2, ... output a signal as an IDST coefficient g (x). That is, the IDCT circuit 41 is used to realize not only IDCT but also IDST. As a result, the same IDCT circuit 41 can be shared for realizing IDCT and IDST, and the number of circuits can be reduced, so that the cost and power consumption can be suppressed as a whole.

  Note that the IDCT / IDST combination circuit 4-1 shown in FIG. 4 does not include the replacement circuits 21 and 24 shown in FIGS. 2 (1) and 2 (2), but the order of each input signal is changed as necessary. A replacement circuit for replacement may be provided.

[DCT / DST combination circuit that switches by control signal]
Next, a DCT / DST combination circuit that switches according to a control signal will be described. FIG. 5 is a block diagram showing a configuration of a DCT / DST combination circuit that performs switching according to a control signal. The DCT / DST combination circuit 3-2 includes delay elements 34-1, 34-2,..., Inverting elements 35-1, 35-2,..., A switching circuit 36, and a DCT circuit 37. . The DCT / DST combined circuit 3-2 inputs the two signals A and B to be converted in parallel at every N points, and inputs the DCT signal A and the DST signal (delay elements 34-1, 34). ,... And output signals of the inverting elements 35-1, 35-2,...) Are switched by the switching circuit 36, thereby sharing the DCT function and the DST function. In addition to realizing DCT, the DCT circuit 37 is used to realize DST, and the DCT coefficient or DST coefficient is switched and output every N points.

  The delay elements 34-1 34-2,... And the inverting elements 35-1, 35-2,... Are the delay elements 31-1, 31-2,. Since it is the same as 32-1, 32-2,.

  The switching circuit 36 receives a control signal, and delays and inverts the signal B from the signal A and the delay elements 34-1 and 34-2,... And the inverting elements 35-1, 35-2,. Each of the received signals (referred to as signal C) is input and switched to either signal A or signal C according to the control signal and output. Here, the control signal is a signal for switching to the signal A or the signal C, and in the preprocessing for the input signals A and B, the nature of the signal is evaluated by obtaining the inter-pixel correlation so that it matches the nature of the signal. Generated to switch to.

  The DCT circuit 37 inputs the signal A or the signal C parallelized every N points from the switching circuit 36, and performs DCT by the DCT arithmetic expression of the above equation (4) at every N points. The DCT circuit 37 outputs a DCT coefficient G (u) when DCT is performed on the signal A, and outputs a DST coefficient G (u) when DCT is performed on the signal C.

  In this case, when outputting the DCT coefficient G (u), the DCT circuit 37 outputs a low-order to high-order signal in ascending order every N points, and outputs the DST coefficient G (u) from the high-order. A low-order signal is output in descending order every N points.

  As described above, according to the DCT / DST combined circuit 3-2 shown in FIG. 5, the switching circuit 36 includes the signal A, the delay elements 34-1, 34-2,. 35-2,... Are switched by the control signal with the signal C obtained by delaying and inverting the signal B. The DCT circuit 37 performs DCT, outputs a DCT coefficient G (u) for the signal A from the switching circuit 36, and outputs a DST coefficient G (u) for the signal C. That is, the DCT circuit 37 is used to realize not only DCT but also DST. As a result, the same DCT circuit 37 can be shared in order to realize DCT and DST, and the number of circuits can be reduced, so that the cost and power consumption can be suppressed as a whole.

  Note that the DCT / DST combination circuit 3-2 shown in FIG. 5 does not include the replacement circuits 12 and 15 shown in FIGS. 1 (1) and (2), but the order of the output signals can be changed as necessary. A replacement circuit for outputting in the order of replacement ascending order or descending order may be provided in the subsequent stage of the DCT circuit 37.

[IDCT / IDST combined circuit for switching by control signal]
Next, an IDCT / IDST combination circuit that performs switching by a control signal will be described. FIG. 6 is a block diagram showing a configuration of an IDCT / IDST combination circuit that performs switching according to a control signal. The IDCT / IDST combination circuit 4-2 includes an IDCT circuit 44, a switching circuit 45, delay elements 46-1, 46-2,... And inverting elements 47-1, 47-2,. . The IDCT / IDST combined circuit 4-2 inputs the signal to be converted in parallel every N points, and the switching circuit 45 inputs the IDCT signal A and the IDST signal (delay elements 46-1, 46-2). ,... And the input signals of the inverting elements 47-1, 47-2,..., And the IDCT function and the IDST function are shared, and the IDCT circuit 44 realizes the IDCT. IDST is realized using the IDCT circuit 44, and a signal A that is an IDCT coefficient or a signal B that is an IDST coefficient is output every N points.

  The IDCT circuit 44 inputs a signal G (u) that is parallelized every N points, and performs IDCT using an IDCT arithmetic expression. The signal subjected to IDCT by the IDCT circuit 44 is output to the switching circuit 45.

  The switching circuit 45 inputs a control signal, inputs a signal from the IDCT circuit 44, and outputs the signal input from the IDCT circuit 44 as the signal A of the IDCT coefficient g (x) according to the control signal, or Are output as a signal C to the delay elements 46-1, 46-2,... And the inverting elements 47-1, 47-2,. Here, the control signal is used to switch to the signal A or the signal C, and is the same as the control signal in FIG.

  The delay elements 46-1, 46-2, ... and the inverting elements 47-1, 47-2, ... are the delay elements 42-1, 42-2, ... and the inverting elements shown in FIG. 43-1, 43-2,... Are the same and will not be described here. As a result, the timings of the signals output from the delay elements 46-1, 46-2,... And the inverting elements 47-1, 47-2,. It is output as a signal B having a coefficient g (x).

  Here, the IDCT / IDST combination circuit 4-2 inputs the DCT coefficient G (u) in the ascending order from low order to high order, and the ascending order from low order to high order by the IDCT circuit 44 from the switching circuit 45. A signal A that is an IDCT coefficient g (x) is output. In addition, the IDCT / IDST combination circuit 4-2 causes the IDCT circuit 44 to change the delay elements 46-1, 46-2,... And the inverting elements 47-1, 47-2,. The signal B which is the next descending IDST coefficient g (x) is output. That is, the IDCT / IDST combination circuit 4-2 has a signal A that is an IDCT coefficient g (x) in ascending order from low order to high order, or a signal B that is an IDST coefficient g (x) in descending order from high order to low order. Can be output as aligned signals.

  As described above, according to the IDCT / IDST combination circuit 4-2 shown in FIG. 6, the IDCT circuit 44 inputs the signal G (u) to perform IDCT, and the switching circuit 45 performs the IDCT circuit 44 according to the control signal. .., And the delay elements 46-1, 46-2,... And the inverting elements 47-1, 47-2,. ··· Changed to output as signal C to ···. The delay elements 46-1, 46-2, ... and the inverting elements 47-1, 47-2, ... output a signal B having an IDST coefficient g (x). That is, the IDCT circuit 44 is used to realize not only IDCT but also IDST. As a result, the same IDCT circuit 44 can be shared for realizing IDCT and IDST, and the number of circuits can be reduced, so that the cost and power consumption can be suppressed as a whole.

  The IDCT / IDST combination circuit 4-2 shown in FIG. 6 does not include the replacement circuits 21 and 24 shown in FIGS. 2 (1) and 2 (2). Alternatively, a replacement circuit for outputting in descending order or the like may be provided in the preceding stage of the IDCT circuit 44.

[Encoder]
Next, an encoding device provided with a DCT / DST combined circuit and an IDCT / IDST combined circuit will be described. FIG. 7 is a block diagram showing a configuration of the encoding apparatus according to the embodiment of the present invention. The encoding device 5 includes a preprocessing unit 101, a subtraction unit 102, a DST preprocessing unit 51, a switching circuit 52, a DCT unit 103, a quantization unit 106, an entropy encoding unit 107, an inverse quantization unit 108, and an IDCT unit 110. , A switching circuit 54, an IDST post-processing unit 55, an addition unit 112, a frame memory 113, and a signal prediction unit 114. The encoding device 5 inputs a signal and switches between a DCT signal and a DST signal (an output signal of the DST preprocessing unit 51) by a switching circuit 52, thereby switching between a DCT function and a DST function. The DCT is realized by the DCT unit 103 and the DST is realized by using the DCT unit 103, and the switching circuit 54 switches between the IDCT decoded signal and the IDST decoded signal. The IDCT function and the IDST function are shared, and IDCT is realized by the IDCT unit 110, and IDST is realized by using the IDCT unit 110.

  Comparing the conventional coding apparatus 100 shown in FIG. 9 with the coding apparatus 5 in FIG. 7, both coding apparatuses 100 and 5 include a preprocessing unit 101, a subtraction unit 102, a DCT unit 103, and a quantization unit 106. The entropy encoding unit 107, the inverse quantization unit 108, the IDCT unit 110, the addition unit 112, the frame memory 113, and the signal prediction unit 114 are the same. In FIG. 7, the same reference numerals as those in FIG. 9 are given to portions common to those in FIG. 9, and detailed description thereof is omitted.

  On the other hand, the encoding device 5 uses a DST preprocessing unit 51 and a switching circuit 52 instead of the DCT / DST combined circuit α1 including the DCT unit 103, the DST unit 104, and the switching unit 105 in the encoding device 100 shown in FIG. And a DCT / DST combination circuit α composed of the DCT unit 103. Also, the encoding device 5 uses an IDCT unit 110, a switching circuit 54, and an IDST instead of the IDCT / IDST combined circuit β1 including the switching unit 109, the IDCT unit 110, and the IDST unit 111 in the encoding device 100 shown in FIG. The difference is that an IDCT / IDST combination circuit β comprising a post-processing unit 55 is provided.

  The DCT / DST combined circuit α of the encoding device 5 corresponds to the DCT / DST combined circuit 3-1 shown in FIG. 3 and the DCT / DST combined circuit 3-2 shown in FIG. In addition, the DST is realized using the DCT unit 103. Specifically, the DST pre-processing unit 51 of the DCT / DST combined circuit α is connected to the delay elements 31-1, 31-2,... And the inverting elements 32-1, 32-2,. 5 corresponds to the delay elements 34-1, 34-2,... And the inverting elements 35-1, 35-2,..., And the switching circuit 52 corresponds to the switching circuit 36 in FIG. The DCT unit 103 corresponds to the DCT circuit 33 in FIG. 3 and the DCT circuit 37 in FIG.

  The IDCT / IDST combination circuit β corresponds to the IDCT / IDST combination circuit 4-1 shown in FIG. 4 and the IDCT / IDST combination circuit 4-2 shown in FIG. 6, and implements IDCT by the IDCT unit 110. IDST is realized using the IDCT unit 110. Specifically, the IDCT unit 110 of the IDCT / IDST combined circuit β corresponds to the IDCT circuit 41 of FIG. 4 and the IDCT circuit 44 of FIG. 6, the switching circuit 54 corresponds to the switching circuit 45 of FIG. The post-processing unit 55 corresponds to the delay elements 42-1, 42-2,... And the inverting elements 43-1, 43-2,. .., And inverting elements 47-1, 47-2,.

  Note that the preprocessing unit 101 performs predetermined preprocessing necessary for encoding on the input signal, evaluates the characteristics of the signal by obtaining the inter-pixel correlation of the input signal, and determines the signal characteristics. The control signal for switching to either the DCT signal or the DST signal is generated and output to the switching circuit 52 so as to meet the above. In response to this control signal, a control signal for switching to either the IDCT signal or the IDST signal is also generated and output to the switching circuit 54. This control signal is updated for each partial image constituting the frame of the moving image, for example. This control signal indicates the type of DCT or DST, and is output by the encoding device 5 as a part of the encoded signal.

  As described above, according to the encoding device 5 shown in FIG. 7, the DCT / DST combined circuit α including the DST preprocessing unit 51, the switching circuit 52, and the DCT unit 103, the IDCT unit 110, the switching circuit 54, and the IDST. An IDCT / IDST combination circuit β comprising a post-processing unit 55 is provided. The DCT / DST combination circuit α realizes DCT by the DCT unit 103 and also realizes DST by the DST preprocessing unit 51 and the DCT unit 103, and the IDCT / IDST combination circuit β realizes IDCT by the IDCT unit 110. The IDST is realized by the IDCT unit 110 and the IDST post-processing unit 55. Accordingly, the same DCT unit 103 can be shared for realizing DCT and DST, and the same IDCT unit 110 can be shared for realizing IDCT and IDST. Therefore, since the number of circuits can be reduced, the cost and power consumption can be suppressed as a whole. In addition, the DCT / DST combination circuit α can realize DST with extremely low complexity compared to the DCT / DST combination circuit α1 shown in FIG. 9. In the IDCT / IDST combination circuit β, FIG. Compared with the IDCT / IDST combination circuit β1 shown in FIG. 1, IDST can be realized by processing with extremely low complexity.

[Decoding device]
Next, a decoding device provided with the IDCT / IDST combination circuit will be described. FIG. 8 is a block diagram illustrating a configuration of a decoding device according to an embodiment of the present invention. The decoding device 6 includes an entropy decoding unit 201, an inverse quantization unit 202, an IDCT unit 204, a switching circuit 61, an IDST post-processing unit 62, an addition unit 206, a post-processing unit 207, a frame memory 208, and a signal prediction unit 209. ing. The decoding device 6 receives the encoded signal, and switches the IDCT decoded signal and the IDST decoded signal by the switching circuit 61 to share the IDCT function and the IDST function. At the same time, IDST is realized using the IDCT unit 204.

  Comparing the conventional decoding device 200 shown in FIG. 10 with the decoding device 6 shown in FIG. 8, both decoding devices 200 and 6 include an entropy decoding unit 201, an inverse quantization unit 202, an IDCT unit 204, an addition unit 206, This is the same in that a processing unit 207, a frame memory 208, and a signal prediction unit 209 are provided. In FIG. 8, the same reference numerals as those in FIG.

  On the other hand, the decoding device 6 uses an IDCT unit 204, a switching circuit 61, and an IDST post-process instead of the IDCT / IDST combined circuit γ1 including the switching unit 203, the IDCT unit 204, and the IDST unit 205 in the decoding device 200 shown in FIG. The difference is that an IDCT / IDST combined circuit γ comprising a unit 62 is provided.

  The IDCT / IDST combination circuit γ of the decoding device 6 corresponds to the IDCT / IDST combination circuit 4-1 shown in FIG. 4 and the IDCT / IDST combination circuit 4-2 shown in FIG. 6, and the IDCT unit 204 realizes IDCT. In addition, IDST is realized using the IDCT unit 204. Specifically, the IDCT unit 204 of the combined IDCT / IDST circuit γ corresponds to the IDCT circuit 41 in FIG. 4 and the IDCT circuit 44 in FIG. 6, the switching circuit 61 corresponds to the switching circuit 45 in FIG. The post-processing unit 62 corresponds to the delay elements 42-1, 42-2,... And the inverting elements 43-1, 43-2,. .., And inverting elements 47-1, 47-2,.

  The switching circuit 61 receives a control signal indicating the type of DCT or DST included in the encoded signal from the entropy decoding unit 201, and performs switching according to the control signal. That is, the switching circuit 61 performs the same switching according to the same control signal as the control signal input by the switching circuit 54 of the encoding device 5 shown in FIG.

  As described above, the decoding apparatus 6 shown in FIG. 8 includes the IDCT / IDST combined circuit γ including the IDCT unit 204, the switching circuit 61, and the IDST post-processing unit 62. The IDCT / IDST combined circuit γ realizes IDCT by the IDCT unit 204 and IDST by the IDCT unit 204 and the IDST post-processing unit 62. Thereby, the same IDCT unit 204 can be shared in order to realize IDCT and IDST. Therefore, since the number of circuits can be reduced, the cost and power consumption can be suppressed as a whole. In addition, the IDCT / IDST combination circuit γ can realize IDST with a process with extremely low complexity compared to the IDCT / IDST combination circuit γ1 shown in FIG.

  The DST circuits 1-1 and 1-2, the IDST circuits 2-1 and 2-2, the DCT / DST combination circuits 3-1 and 3-2, and the IDCT / IDST combination circuit 4-1 according to the embodiment of the present invention. As a hardware configuration of the 4-2, the encoding device 5 and the decoding device 6, a normal computer can be used. These are respectively configured by a computer having a volatile storage medium such as a CPU and a RAM, a non-volatile storage medium such as a ROM, and an interface. DST circuits 1-1 and 1-2, IDST circuits 2-1 and 2-2, DCT / DST combined circuits 3-1 and 3-2, IDCT / IDST combined circuits 4-1 and 4-2, and encoding device 5 Each function of each component provided in the decoding device 6 is realized by causing the CPU to execute a program describing these functions. These programs can also be stored and distributed in a storage medium such as a magnetic disk (floppy (registered trademark) disk, hard disk, etc.), optical disk (CD-ROM, DVD, etc.), semiconductor memory, or the like.

1 DST (Discrete Sine Transform) Circuit 2 IDST (Inverse Discrete Sine Transform) Circuit 3 DCT / DST (Discrete Cosine / Sine Transform) Combined Circuit 4 IDCT / IDST (Inverse Discrete Cosine / Sine Transform) Combined Circuit 5,100 Encoding Device 6,200 Decoding device 10, 13, 23, 26, 32, 35, 43, 47 Inversion element 11, 14, 33, 37 DCT (discrete cosine transform) circuit 12, 15, 21, 24 Replacement circuit 22, 25, 41 44 IDCT (Inverse Discrete Cosine Transform) Circuits 31, 34, 42, 46 Delay Elements 36, 45, 52, 54, 61 Switching Circuit 51 DST (Discrete Sine Transform) Pre-Processor 55, 62 IDST (Inverse Discrete Sine Transform) Post-processing unit 101 Pre-processing unit 102 Subtraction unit 103 DCT (Discrete cosine transform) unit 104 DST (Discrete sine transform) unit 1 5, 109, 203 switching unit 106 quantization unit 107 entropy encoding unit 108, 202 inverse quantization unit 110, 204 IDCT (inverse discrete cosine transform) unit 111, 205 IDST (inverse discrete sine transform) unit 112, 206 addition unit 113, 208 Frame memory 114, 209 Signal prediction unit 201 Entropy decoding unit 207 Post-processing unit

Claims (7)

In a discrete sine transform circuit that performs discrete sine transform on an input signal,
A pre-processing unit that has an inverting element that inverts the sign of a part of the signal, and outputs a signal whose sign is inverted by the inverting element and another signal whose sign is not inverted;
A discrete cosine transform circuit for performing discrete cosine transform,
The preprocessing unit inverts the sign of a part of the input signal, and outputs the signal with the sign inverted and the other input signal with the sign not inverted as a signal for a discrete sign,
The discrete cosine transform circuit, wherein the discrete cosine transform circuit performs discrete cosine transform on the discrete sine signal output by the preprocessing unit. A combinational circuit having the discrete sine transform circuit according to claim 1 and performing discrete cosine transform or discrete sine transform by switching signals,
In addition to the preprocessing unit and the discrete cosine transform circuit, a switching circuit is provided,
The switching circuit inputs a discrete sine signal output from the preprocessing unit, inputs the input signal as a discrete cosine signal, and switches to one of the two input signals for output. ,
The combinational circuit, wherein the discrete cosine transform circuit performs discrete cosine transform on the signal output by the switching circuit. In an inverse discrete sine transform circuit that performs an inverse discrete sine transform on an input signal,
An inverse discrete cosine transform circuit for inverse discrete cosine transform of the input signal;
A post-processing unit that includes an inverting element that inverts the sign of a part of the signal converted by the inverse discrete cosine transform circuit, and that outputs a signal whose sign is inverted by the inverting element and another signal whose sign is not inverted And an inverse discrete sine transform circuit. A combinational circuit comprising the inverse discrete sine transform circuit according to claim 3 and performing inverse discrete cosine transform or inverse discrete sine transform by switching signals,
In addition to the inverse discrete cosine transform circuit and the post-processing unit, a switching circuit is provided,
The switching circuit switches the signal converted by the inverse discrete cosine transform circuit, outputs the signal after inverse discrete cosine transform, or outputs a signal for inverse discrete sine,
The post-processing unit inverts a part of the sign of the inverse discrete sine signal output by the switching circuit, and outputs the signal with the inverted sign and the other inverse discrete sine signal with the inverted sign. And a combined circuit that outputs the signal after inverse discrete sine transform. An encoding device comprising the combinational circuit of claim 2 and the combinational circuit of claim 4 for encoding an input signal and outputting an encoded signal,
The combinational circuit according to claim 2, wherein a signal to be encoded generated based on the input signal and the prediction signal is input, and a signal after discrete sine transform or a signal after discrete cosine transform is output.
A quantization unit for quantizing the signal after the discrete sine transform or the signal after the discrete cosine transform;
An inverse quantization unit that inversely quantizes the quantized signal;
The combined circuit according to claim 4, wherein the signal after inverse quantization is input, and the signal after inverse discrete sine transform or the signal after inverse discrete cosine transform is output.
A signal prediction unit that generates the prediction signal based on the signal after the inverse discrete sine transform or the signal after the inverse discrete cosine transform, and
An encoding apparatus that generates and outputs an encoded signal based on the quantized signal. A decoding device comprising the combinational circuit according to claim 4 for decoding an input encoded signal and outputting a decoded signal,
An inverse quantization unit that inversely quantizes the encoded signal;
The combined circuit according to claim 4, wherein the signal after inverse quantization is input, and the signal after inverse discrete sine transform or the signal after inverse discrete cosine transform is output.
A signal prediction unit that generates a prediction signal based on the signal after the inverse discrete sine transform or the signal after the inverse discrete cosine transform, and
A decoding apparatus, comprising: generating and outputting a decoded signal based on the signal after the inverse discrete sine transform or the signal after the inverse discrete cosine transform and the prediction signal.   The computer is a discrete sine transform circuit according to claim 1, an inverse discrete sine transform circuit according to claim 3, a combined circuit according to claim 2 or 4, an encoding device according to claim 5, or a claim. The program for functioning as a decoding apparatus of 6.

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