JP6534036B2 - Field-effect transistor using hydrogen-terminated diamond - Google Patents
Field-effect transistor using hydrogen-terminated diamond Download PDFInfo
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本発明は、表面が水素終端となっているダイヤモンドの表面伝導層をチャネルとした電界効果トランジスタに関する。 The present invention relates to a field effect transistor whose channel is a surface conduction layer of diamond whose surface is hydrogen terminated.
本出願人は、先に二硫化モリブデンをチャネルとし、ゲートに有機強誘電体を用いた電界効果トランジスタを提案している（非特許文献１）。
これに対して本発明は、水素終端ダイヤモンドの表面伝導層をチャネルとした電界効果トランジスタである。
The applicant has previously proposed a field effect transistor in which molybdenum disulfide is used as a channel and an organic ferroelectric is used as a gate (Non-Patent Document 1).
On the other hand, the present invention is a field effect transistor in which the surface conduction layer of hydrogen-terminated diamond is a channel.
本発明は、高い表面キャリア密度を有する水素終端表面からなるダイヤモンドを用いた電界効果トランジスタの提供を目的とする。 An object of the present invention is to provide a field effect transistor using a diamond comprising a hydrogen-terminated surface having a high surface carrier density.
本発明に係る電界効果トランジスタは、水素終端ダイヤモンドの表面伝導層からなるチャネルに、強誘電体からなるゲートを組み合せたことを特徴とする。 A field effect transistor according to the present invention is characterized in that a channel made of a surface conduction layer of hydrogen-terminated diamond is combined with a gate made of a ferroelectric.
表面が水素終端からなるダイヤモンドの表面には、低抵抗のｐ型表面伝導層を有する。
この表面伝導層は、高い表面キャリア密度（＞１０１３ｃｍ−２），低い表面準位密度（＞１０１１ｃｍ−２）を有するとともに、その層の厚みは約１０ｎｍ以下と電流制御に有利な浅いキャリア分布となっている点に特徴がある。
このような表面が水素終端表面になっているダイヤモンドは、マイクロプラズマＣＶＤ法等を用いてエピタキシャル成長させることで得られる。
また、ダイヤモンド表面を水素中でアニール処理することでも得られる。
A low resistance p-type surface conductive layer is provided on the surface of the diamond whose surface is hydrogen-terminated.
This surface conductive layer has high surface carrier density (> 10 13 cm -2 ), low surface state density (> 10 11 cm -2 ), and the thickness of the layer is about 10 nm or less, which is advantageous for current control It is characterized in that it has a shallow carrier distribution.
Such a diamond having a hydrogen-terminated surface can be obtained by epitaxial growth using a micro plasma CVD method or the like.
It can also be obtained by annealing the diamond surface in hydrogen.
ここで、強誘電体は前記水素終端ダイヤモンド表面に３００℃以下の低温で薄膜形成されたものであることが好ましい。
ダイヤモンドの水素終端表面は３００℃を越えると、一部が酸素終端表面に変化する恐れがあるからである。
Here, it is preferable that the ferroelectric is a thin film formed on the surface of the hydrogen-terminated diamond at a low temperature of 300 ° C. or less.
This is because when the hydrogen-terminated surface of diamond exceeds 300 ° C., a part may change to an oxygen-terminated surface.
本発明に係る電界効果トランジスタの具体的な形態例としては、水素終端ダイヤモンドの表面伝導層上にソース及びドレイン電極を形成し、前記ソース電極とドレイン電極との間であって前記水素終端ダイヤモンドの表面伝導層上に強誘電体の薄膜を積層し、前記強誘電体の薄膜にゲート電極を形成した例が挙げられる。 As a specific embodiment of the field effect transistor according to the present invention, source and drain electrodes are formed on a surface conduction layer of hydrogen-terminated diamond, and the hydrogen-terminated diamond is between the source electrode and the drain electrode. The example which laminated | stacked the ferroelectric thin film on the surface conduction layer, and formed the gate electrode in the thin film of the said ferroelectric substance is mentioned.
本発明において強誘電体は、ダイヤモンドの水素終端表面にこの水素終端構造を破壊することなく積層できるものであれば特に限定はないが、約１００〜１５０℃の低温で積層できる点でフッ素系の有機薄膜が好ましく、例えばフッ化ビニリデン（ＶＤＦ）と、三フッ化エチレン（ＴｒＦＥ）との共重合体薄膜が例として挙げられる。
また、本発明において強誘電体とは、外部に電場がなくても電気双極子が整列しており、且つ、双極子の方向が電場によって変化できる物質をいう。
In the present invention, the ferroelectric is not particularly limited as long as it can be laminated on the hydrogen-terminated surface of diamond without destroying this hydrogen-terminated structure, but it is fluorine-based in that it can be laminated at a low temperature of about 100 to 150 ° C. An organic thin film is preferable, for example, a copolymer thin film of vinylidene fluoride (VDF) and ethylene trifluoride (TrFE) can be mentioned as an example.
Further, in the present invention, a ferroelectric refers to a substance in which electric dipoles are aligned without an external electric field, and the direction of the dipole can be changed by the electric field.
本発明に係る電界効果トランジスタは、水素終端ダイヤモンドの表面伝導層をチャネルとし、ゲートに強誘電体を用いたことにより、この強誘電体の強い分極により効率的にキャリアを誘起することができ、自発分極によるノーマリーオフ動作の実現が期待される。 In the field effect transistor according to the present invention, the surface conduction layer of hydrogen-terminated diamond is a channel, and by using a ferroelectric for the gate, carriers can be efficiently induced by the strong polarization of the ferroelectric, The realization of a normally-off operation by spontaneous polarization is expected.
本発明に係る電界効果トランジスタ（ＦＥＴ）の構造例を図１に模式的に示す。
水素終端表面構造からなる表面伝導層有するダイヤモンド基板を用いて、この表面伝導層の上にソース（Ｓｏｕｒｃｅ）電極とドレイン（Ｄｒａｉｎ）電極とを形成してある。
ソース電極とドレイン電極との間であって、この表面伝導層の上にゲートとなるように強誘電体、例えばＶＤＦ／ＴｒＦＥの薄膜を形成し、この薄膜の上にゲート（Ｇａｔｅ）電極を形成してある。
A structural example of a field effect transistor (FET) according to the present invention is schematically shown in FIG.
A source (Source) electrode and a drain (Drain) electrode are formed on the surface conduction layer using a diamond substrate having a surface conduction layer having a hydrogen-terminated surface structure.
A thin film of a ferroelectric such as VDF / TrFE is formed between the source electrode and the drain electrode to be a gate on the surface conductive layer, and a gate electrode is formed on the thin film Yes.
このような構造のＦＥＴを試作し評価したので、以下説明する。
マイクロ波プラズマＣＶＤ法を用いて、人工ダイヤモンドをエピタキシャル成長させて製作したダイヤモンド基板の表面を必要に応じて洗浄し、次にこの表面にフォトリソグラフィ法により、白金又は金等からなるソース電極とドレイン電極を形成した。
次に必要に応じてマスキング処理し、ゲート絶縁膜として７５／２５ｍｏｌ％のＶＤＦ／ＴｒＦＥコポリマーをスピンコート法により塗布し、その後に１１０〜１２０℃にて乾燥させた。
形成されたＶＤＦ／ＴｒＦＥの薄膜の膜厚は、約１３０ｎｍであった。
次にフォトリソグラフィ法により、ＶＤＦ／ＴｒＦＥ薄膜の上に白金又は金等からなるゲート電極を形成した。
そのパターンの表面写真を図２に示す。
また、ＶＤＦ／ＴｒＦＥ薄膜のＡＦＭ（原子間力顕微鏡）像を図３に示す。
これにより、ＶＤＦ／ＴｒＦＥ薄膜にホール等の欠陥が無いことを確認した。
このようにして得られた評価品の直流バイアスによるＩＤＳ−ＶＤＳ特性を示すグラフを図４に示した。
観測されたＩＤＳ−ＶＤＳ特性の近似直線の傾きからシート抵抗値を求めた。
このことから、チャネルとして水素終端表面伝導層が形成されているのを確認できた。
次に測定周波数１ＨｚにおけるＰ−Ｖ特性を図５のグラフに示す。
これにより、強誘電性ヒステリシスを確認することができた。
The trial manufacture and evaluation of the FET having such a structure will be described below.
The surface of a diamond substrate manufactured by epitaxially growing artificial diamond using microwave plasma CVD method is cleaned if necessary, and then the source electrode and drain electrode made of platinum or gold etc. are formed on this surface by photolithography. Formed.
Next, masking treatment was carried out if necessary, and 75/25 mol% of VDF / TrFE copolymer was applied by spin coating as a gate insulating film, and then dried at 110 to 120 ° C.
The film thickness of the VDF / TrFE thin film formed was about 130 nm.
Next, a gate electrode made of platinum, gold or the like was formed on the VDF / TrFE thin film by photolithography.
The surface photograph of the pattern is shown in FIG.
Further, an AFM (atomic force microscope) image of the VDF / TrFE thin film is shown in FIG.
As a result, it was confirmed that the VDF / TrFE thin film was free of defects such as holes.
The graph showing the I DS -V DS characteristics due to the DC bias of the thus obtained evaluation items shown in FIG.
The sheet resistance value was determined from the slope of the approximate straight line of the observed I DS- V DS characteristics.
From this, it could be confirmed that a hydrogen-terminated surface conduction layer was formed as a channel.
Next, the PV characteristics at a measurement frequency of 1 Hz are shown in the graph of FIG.
As a result, ferroelectric hysteresis could be confirmed.
次に図６に示すような測定回路を用いて、ゲートに直流バイアスＶＧＳを印加したまま、ＩＤＳを測定した結果を図７及び図８に示す。
図７は、ＩＤＳ−ＶＤＳ特性であり、電流Ｏｎ／Ｏｆｆ比は１０７倍以上を示した。
図８は、ＩＤＳ−ＶＧ特性であり、ゲートが強誘電体として機能しているのが分かる。
Next, using the measurement circuit as shown in FIG. 6, the results of measuring I DS with the DC bias V GS applied to the gate are shown in FIG. 7 and FIG.
FIG. 7 shows I DS -V DS characteristics, and the current on / off ratio showed 10 7 times or more.
FIG. 8 shows I DS -V G characteristics, and it can be seen that the gate functions as a ferroelectric.
次に、図９に示すような測定回路を用いて、ゲートに所定のパルス電圧を５ｓｅｃ間印可し、ＶＤＦ／ＴｒＦＥの薄膜を分極させた後にゲート端子を開放してからＩＤＳを測定した。
その残留分極（自発分極）によるＩＤＳ−Ｖ’ＤＳ特性の測定結果を図１０に、ＩＤＳ−Ｖ’Ｇ特性を図１１に示す。
このことから、本発明に係るＦＥＴは自発分極によりゲート電圧ゼロ状態でチャネル電流に変調を与えることが可能であり、ノーマリーオフ動作の実現も可能と思われる。
Next, using a measurement circuit as shown in FIG. 9, a predetermined pulse voltage was applied to the gate for 5 seconds to polarize the VDF / TrFE thin film, and then the gate terminal was opened to measure I DS .
The measurement results of I DS -V ' DS characteristics by the residual polarization (spontaneous polarization) are shown in FIG. 10, and the I DS -V' G characteristics are shown in FIG.
From this, it is possible that the FET according to the present invention can modulate the channel current at the gate voltage zero state by the spontaneous polarization, and also realize the normally-off operation.
Claims (1)
前記ソース電極とドレイン電極との間であって前記水素終端ダイヤモンドの表面伝導層上に強誘電体の薄膜を積層してあり、
前記強誘電体の薄膜にゲート電極を形成してあり、
前記強誘電体はフッ化ビニリデンと三フッ化エチレンとの共重合体薄膜であることを特徴とする電界効果トランジスタ。 Forming source and drain electrodes on the surface conductive layer of hydrogen terminated diamond,
Between the source electrode and the drain electrode, a ferroelectric thin film is laminated on the surface conductive layer of the hydrogen-terminated diamond ,
A gate electrode is formed on the ferroelectric thin film ,
The field effect transistor is characterized in that the ferroelectric is a copolymer thin film of vinylidene fluoride and trifluoride ethylene .
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