JP2016157874A - Semiconductor laminate structure and manufacturing method of the same, and semiconductor element and manufacturing method of the same - Google Patents

Semiconductor laminate structure and manufacturing method of the same, and semiconductor element and manufacturing method of the same Download PDF

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JP2016157874A
JP2016157874A JP2015035893A JP2015035893A JP2016157874A JP 2016157874 A JP2016157874 A JP 2016157874A JP 2015035893 A JP2015035893 A JP 2015035893A JP 2015035893 A JP2015035893 A JP 2015035893A JP 2016157874 A JP2016157874 A JP 2016157874A
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崇史 上村
Takashi Kamimura
崇史 上村
東脇　正高
Masataka Towaki
正高 東脇
公平 佐々木
Kohei Sasaki
公平 佐々木
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National Institute of Information and Communications Technology
Tamura Corp
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Tamura Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor laminate structure which has an AlOfilm deposited on a GaOlayer and which does not have hysteresis characteristics; and provide a manufacturing method of the semiconductor laminate structure, a semiconductor element and a manufacturing method of the same.SOLUTION: A semiconductor laminate structure 10 having no hysteresis characteristics comprises: a GaOlayer 11 which is composed of GaOsingle crystal and has a principal surface of a plane direction of (-201); and an AlOfilm 12 which is formed on the GaOlayer 11 and composed of only a layer consisting primarily of amorphous AlO.SELECTED DRAWING: Figure 1

Description

本発明は、半導体積層構造体及びその製造方法、並びに半導体素子及びその製造方法に関する。   The present invention relates to a semiconductor multilayer structure and a manufacturing method thereof, and a semiconductor element and a manufacturing method thereof.

従来の半導体素子として、主面の面方位が（０１０）であるＧａ２Ｏ３基板上に、酸素プラズマを酸化剤に用いたプラズマＡＬＤ（ALD：Atomic Layer Deposition）法により２５０℃の成長温度で形成されたＡｌ２Ｏ３からなるゲート絶縁膜を有する、トランジスタが知られている（例えば、非特許文献１、２参照）。 As a conventional semiconductor element, a growth temperature of 250 ° C. is applied to a Ga 2 O 3 substrate having a main surface orientation of (010) by a plasma ALD (ALD: Atomic Layer Deposition) method using oxygen plasma as an oxidizing agent. A transistor having a formed gate insulating film made of Al 2 O 3 is known (see, for example, Non-Patent Documents 1 and 2).

また、他の従来の半導体素子として、主面の面方位が（−２０１）であるＧａ２Ｏ３層上に形成されたＡｌ２Ｏ３からなる酸化物絶縁膜を有する半導体素子が知られている（例えば、特許文献１）。 As another conventional semiconductor element, a semiconductor element having an oxide insulating film made of Al 2 O 3 formed on a Ga 2 O 3 layer whose principal surface has a plane orientation of (−201) is known. (For example, Patent Document 1).

特許文献１には、Ａｌ２Ｏ３からなる酸化物絶縁膜が、結晶質層と非晶質層を有し、結晶質層が酸化物絶縁膜とＧａ２Ｏ３基板との界面の界面準位を低減することが開示されている。 In Patent Document 1, an oxide insulating film made of Al 2 O 3 has a crystalline layer and an amorphous layer, and the crystalline layer is an interface state of the interface between the oxide insulating film and the Ga 2 O 3 substrate. Reducing the position is disclosed.

また、他の従来の半導体素子として、主面の面方位が（−２０１）であるＧａ２Ｏ３層上に、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により形成された非晶質のＡｌ２Ｏ３のみからなる酸化物絶縁膜を有する半導体素子が知られている（例えば、特許文献２）。 In addition, as another conventional semiconductor element, amorphous Al formed on a Ga 2 O 3 layer whose principal surface has a plane orientation of (−201) by a plasma ALD method using oxygen plasma as an oxidizing agent. A semiconductor element having an oxide insulating film made of only 2 O 3 is known (for example, Patent Document 2).

特開２０１５―２３４３号公報JP-A-2015-2343 特開２０１５―２２９３号公報Japanese Unexamined Patent Publication No. 2015-2293

Masataka Higashiwaki, et al., “Depletion-mode Ga2O3metal-oxide-semiconductor field-effect transistors on β-Ga2O3(010) substrates and temperature dependence of their device characteristics,” Applied Physics Letters 103, 123511 (2013)Masataka Higashiwaki, et al., “Depletion-mode Ga2O3metal-oxide-semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics,” Applied Physics Letters 103, 123511 (2013) Masataka Higashiwaki, et al., “Depletion-mode Ga2O3MOSFETs on β-Ga2O3 (010) substrates with Si-ion-implanted channel and contacts,” Technical Digest - International Electron Devices Meeting 28.7.1 (2013)Masataka Higashiwaki, et al., “Depletion-mode Ga2O3MOSFETs on β-Ga2O3 (010) substrates with Si-ion-implanted channel and contacts,” Technical Digest-International Electron Devices Meeting 28.7.1 (2013)

一般に、電界効果型の半導体素子が安定して動作するためには、その半導体素子を構成する、絶縁膜を含む積層構造体が、ヒステリシス特性を有しないことが求められる。   In general, in order for a field effect semiconductor element to operate stably, a stacked structure including an insulating film constituting the semiconductor element is required not to have hysteresis characteristics.

Ｇａ２Ｏ３層上に成膜されたＡｌ２Ｏ３膜を有し、Ａｌ２Ｏ３膜を介して電界効果を及ぼす半導体素子において、ヒステリシス特性を低減するためには、特許文献２に開示された半導体素子のように、Ａｌ２Ｏ３膜が非晶質のＡｌ２Ｏ３のみからなることが求められる。 Ga 2 O 3 layer on have the formed an Al 2 O 3 film in a semiconductor device on the field effect through the Al 2 O 3 film, in order to reduce the hysteresis characteristic is disclosed in Patent Document 2 As in the case of the manufactured semiconductor element, it is required that the Al 2 O 3 film is made of only amorphous Al 2 O 3 .

しかしながら、Ａｌ２Ｏ３膜が非晶質のＡｌ２Ｏ３のみからなることは、ヒステリシス特性を低減するための条件の一つに過ぎず、半導体素子がヒステリシス特性を有しないことを意味するものではない。特許文献２には、半導体素子がヒステリシス特性を有しないことは開示されておらず、また、Ａｌ２Ｏ３膜のＡＬＤ法による成膜条件についても、酸素プラズマを酸化剤に用いることが開示されているのみである。 However, the fact that the Al 2 O 3 film is made of only amorphous Al 2 O 3 is only one of the conditions for reducing the hysteresis characteristic, and means that the semiconductor element does not have the hysteresis characteristic. is not. Patent Document 2 does not disclose that the semiconductor element does not have hysteresis characteristics, and also discloses that oxygen plasma is used as an oxidizing agent for the film formation conditions of the Al 2 O 3 film by the ALD method. Only.

本発明の目的は、Ｇａ２Ｏ３層上に成膜されたＡｌ２Ｏ３膜を有する、ヒステリシス特性を有しない半導体積層構造体及びその製造方法、並びに半導体素子及びその製造方法を提供することにある。 An object of the present invention is to provide a semiconductor multilayer structure having an Al 2 O 3 film formed on a Ga 2 O 3 layer and having no hysteresis characteristics, a manufacturing method thereof, a semiconductor element, and a manufacturing method thereof. It is in.

本発明の一態様は、上記目的を達成するために、以下の［１］の半導体積層構造体、［２］の半導体素子、［３］の半導体積層構造体の製造方法、又は［４］の半導体素子の製造方法を提供する。   In one embodiment of the present invention, in order to achieve the above object, the following [1] semiconductor stacked structure, [2] semiconductor element, [3] semiconductor stacked structure manufacturing method, or [4] A method for manufacturing a semiconductor device is provided.

［１］Ｇａ２Ｏ３単結晶からなり、主面の面方位が（−２０１）であるＧａ２Ｏ３層と、前記Ｇａ２Ｏ３層上に形成された、非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜と、を有する、ヒステリシス特性を有しない半導体積層構造体。 [1] consists of Ga 2 O 3 single crystal, and Ga 2 O 3 layer, which is a plane orientation of main surface (-201), which is formed on the Ga 2 O 3 layer on an amorphous Al 2 O And an Al 2 O 3 film composed only of a layer containing 3 as a main component, and a semiconductor multilayer structure having no hysteresis characteristics.

［２］前記Ａｌ２Ｏ３膜上に電極を有し、前記Ａｌ２Ｏ３膜を介して電界効果を及ぼす、上記［１］に記載の半導体積層構造体を含む、半導体素子。 [2] has an electrode on the the Al 2 O 3 film, exerts a field effect through the the Al 2 O 3 film, comprising a semiconductor stacked structure according to [1], the semiconductor element.

［３］Ｇａ２Ｏ３単結晶からなり、主面の面方位が（−２０１）であるＧａ２Ｏ３層の表面上に、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により、非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜を２５０℃以下の成長温度で形成する工程を含む、半導体積層構造体の製造方法。 [3] The surface of a Ga 2 O 3 layer made of a Ga 2 O 3 single crystal and having a main surface orientation of (−201) is amorphous by a plasma ALD method using oxygen plasma as an oxidizing agent. including the Al 2 O 3 to form an Al 2 O 3 film formed of only a layer composed mainly at 250 ° C. below the growth temperature process, a method of manufacturing a semiconductor stacked structure.

［４］前記Ａｌ２Ｏ３膜上に電極を形成する工程を含む、上記［３］に記載の半導体積層構造体の製造方法を含む、前記Ａｌ２Ｏ３膜を介して電界効果を及ぼす半導体素子の製造方法。 [4] comprising the step of forming the electrodes on the the Al 2 O 3 film, including a method of manufacturing a semiconductor stacked structure according to [3], the semiconductor on the field effect through the the Al 2 O 3 film Device manufacturing method.

本発明によれば、Ｇａ２Ｏ３層上に成膜されたＡｌ２Ｏ３膜を有する、ヒステリシス特性を有しない半導体積層構造体及びその製造方法、並びに半導体素子及びその製造方法を提供することができる。 According to the present invention, there are provided a semiconductor laminated structure having an Al 2 O 3 film formed on a Ga 2 O 3 layer and having no hysteresis characteristic, a manufacturing method thereof, a semiconductor element, and a manufacturing method thereof. Can do.

図１は、第１の実施の形態に係る半導体積層構造体の垂直断面図である。FIG. 1 is a vertical cross-sectional view of the semiconductor multilayer structure according to the first embodiment. 図２は、第２の実施の形態に係るキャパシタの垂直断面図である。FIG. 2 is a vertical sectional view of the capacitor according to the second embodiment. 図３（ａ）、（ｂ）は、それぞれ、実施例に係る半導体積層構造体試料と、比較例に係る半導体積層構造体試料の垂直断面のＴＥＭ（Transmission Electron Microscope）観察像である。FIGS. 3A and 3B are TEM (Transmission Electron Microscope) observation images of the vertical cross sections of the semiconductor multilayer structure sample according to the example and the semiconductor multilayer structure sample according to the comparative example, respectively. 図４（ａ）、（ｂ）は、それぞれ、実施例に係るキャパシタ試料と、比較例に係るキャパシタ試料のアノード電圧を往復スイープしたときの容量特性を示すグラフである。4A and 4B are graphs showing capacitance characteristics when the anode voltage of the capacitor sample according to the example and the capacitor sample according to the comparative example are reciprocally swept, respectively.

本発明は、Ｇａ２Ｏ３単結晶からなり、主面の面方位が（−２０１）であるＧａ２Ｏ３層と、Ｇａ２Ｏ３層上に酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により形成された、非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜とを有する、ヒステリシス特性を有しない半導体積層構造体、及びそれを含む半導体素子に関するものである。 The present invention is, Ga 2 O 3 made of single-crystal, and Ga 2 O 3 layer, which is a plane orientation of main surface (-201), a plasma ALD method using oxygen plasma oxidant Ga 2 O 3 layer on the And a semiconductor multilayer structure having no hysteresis characteristic, having an Al 2 O 3 film composed only of amorphous Al 2 O 3 as a main component, and a semiconductor element including the same is there.

本発明者らは、鋭意研究の結果、Ｇａ２Ｏ３層の主面の面方位により、Ａｌ２Ｏ３膜中に結晶質層が形成されるか否かを制御できること、さらには、非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜を特定の成膜条件下で形成することにより、半導体積層構造体のヒステリシス特性を除去できることを新規に見出し、本発明に至った。 As a result of intensive studies, the inventors have been able to control whether or not a crystalline layer is formed in an Al 2 O 3 film depending on the orientation of the main surface of the Ga 2 O 3 layer. It has been newly found that the hysteresis characteristics of a semiconductor multilayer structure can be removed by forming an Al 2 O 3 film consisting of only a layer composed mainly of high- quality Al 2 O 3 under specific film-forming conditions. It came to.

以下、本発明の実施の形態について、詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail.

〔第１の実施の形態〕
図１は、第１の実施の形態に係る半導体積層構造体１０の垂直断面図である。半導体積層構造体１０は、Ｇａ２Ｏ３層１１と、Ｇａ２Ｏ３層１１上に形成されたＡｌ２Ｏ３膜１２を有する。 [First Embodiment]
FIG. 1 is a vertical cross-sectional view of a semiconductor multilayer structure 10 according to the first embodiment. The semiconductor multilayer structure 10 includes a Ga 2 O 3 layer 11 and an Al 2 O 3 film 12 formed on the Ga 2 O 3 layer 11.

Ｇａ２Ｏ３層１１は、Ｇａ２Ｏ３単結晶からなり、主面の面方位が（−２０１）の板状又は膜状の部材である。Ｇａ２Ｏ３層１１は、Ｓｉ、Ｓｎ等のドーパントを含んでもよい。 The Ga 2 O 3 layer 11 is made of a Ga 2 O 3 single crystal, and is a plate-like or film-like member whose principal surface has a plane orientation of (−201). The Ga 2 O 3 layer 11 may contain a dopant such as Si or Sn.

図１に示される例では、Ｇａ２Ｏ３層１１はＧａ２Ｏ３基板である。しかしながら、Ｇａ２Ｏ３層１１の形態は基板に限られず、例えば、他の基板上に成長したＧａ２Ｏ３膜であってもよい。 In the example shown in FIG. 1, the Ga 2 O 3 layer 11 is a Ga 2 O 3 substrate. However, the form of the Ga 2 O 3 layer 11 is not limited to the substrate, and may be, for example, a Ga 2 O 3 film grown on another substrate.

Ａｌ２Ｏ３膜１２は、非晶質のＡｌ２Ｏ３を主成分とする層のみからなり、結晶質の層を含まない。 The Al 2 O 3 film 12 is composed only of a layer containing amorphous Al 2 O 3 as a main component and does not include a crystalline layer.

非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜１２は、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法によって、主面の面方位が（−２０１）であるＧａ２Ｏ３層１１上にＡｌ２Ｏ３を堆積させることにより形成される。 The Al 2 O 3 film 12 consisting only of a layer containing amorphous Al 2 O 3 as a main component has a main surface orientation of (−201) by plasma ALD using oxygen plasma as an oxidizing agent. It is formed by depositing Al 2 O 3 on the Ga 2 O 3 layer 11.

半導体積層構造体１０は、Ｇａ２Ｏ３層１１と、その上に形成された非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜１２から構成され、ヒステリシス特性を有しない。 The semiconductor laminated structure 10 is composed of a Ga 2 O 3 layer 11 and an Al 2 O 3 film 12 made only of a layer mainly composed of amorphous Al 2 O 3 formed thereon, and has hysteresis characteristics. Does not have.

Ａｌ２Ｏ３膜１２の結晶化を防ぎ、かつＧａ２Ｏ３層１１とＡｌ２Ｏ３膜１２の界面の界面準位密度を低減してヒステリシス特性を抑制するためには、Ａｌ２Ｏ３膜１２の成長温度は、２５０℃以下であることが求められる。 Al 2 O 3 prevents crystallization of the film 12, and to suppress the Ga 2 O 3 layer 11 and the Al 2 O 3 to reduce the interface state density at the interface of the film 12 hysteresis characteristics, Al 2 O 3 The growth temperature of the film 12 is required to be 250 ° C. or lower.

〔第２の実施の形態〕
第２の実施の形態は、第１の実施の形態に係る半導体積層構造体１０を含む半導体素子の一例としての、ＭＯＳ（Metal Oxide Semiconductor）キャパシタについての形態である。 [Second Embodiment]
The second embodiment relates to a MOS (Metal Oxide Semiconductor) capacitor as an example of a semiconductor element including the semiconductor multilayer structure 10 according to the first embodiment.

図２は、第２の実施の形態に係るキャパシタ２０の垂直断面図である。キャパシタ２０は、半導体積層構造体１０と、半導体積層構造体１０のＧａ２Ｏ３層１１の裏面（Ａｌ２Ｏ３膜１２の反対側の面）上に形成されたカソード電極２１と、半導体積層構造体１０のＡｌ２Ｏ３膜１２の表面（Ｇａ２Ｏ３層１１の反対側の面）上に形成されたアノード電極２２を有する。 FIG. 2 is a vertical sectional view of the capacitor 20 according to the second embodiment. The capacitor 20 includes a semiconductor multilayer structure 10, a cathode electrode 21 formed on the back surface of the Ga 2 O 3 layer 11 of the semiconductor multilayer structure 10 (a surface opposite to the Al 2 O 3 film 12), and a semiconductor multilayer structure. An anode electrode 22 is formed on the surface of the Al 2 O 3 film 12 of the structure 10 (the surface on the opposite side of the Ga 2 O 3 layer 11).

キャパシタ２０のＧａ２Ｏ３層１１は、例えば、Ｓｉ等のドーパントを含むＧａ２Ｏ３基板である。 The Ga 2 O 3 layer 11 of the capacitor 20 is a Ga 2 O 3 substrate containing a dopant such as Si, for example.

カソード電極２１は、例えば、Ｔｉ／Ａｕの積層構造を有する、Ｇａ２Ｏ３層１１の裏面の全面に形成される電極である。 The cathode electrode 21 is an electrode formed on the entire back surface of the Ga 2 O 3 layer 11 having, for example, a Ti / Au laminated structure.

アノード電極２２は、例えば、Ａｕからなる円形電極である。   The anode electrode 22 is a circular electrode made of, for example, Au.

キャパシタ２０は、ヒステリシス特性を有しない半導体積層構造体１０を用いて作製されているため、動作の安定性が高い。   Since the capacitor 20 is manufactured using the semiconductor multilayer structure 10 having no hysteresis characteristic, the operation stability is high.

（実施の形態の効果）
上記第１、２の実施の形態によれば、ヒステリシス特性を有しない半導体積層構造体を得ることができ、その半導体積層構造体を用いて、動作特性に優れた半導体素子を製造することができる。 (Effect of embodiment)
According to the first and second embodiments, a semiconductor multilayer structure having no hysteresis characteristic can be obtained, and a semiconductor element having excellent operating characteristics can be manufactured using the semiconductor multilayer structure. .

実施例として、第１の実施の形態に係る半導体積層構造体１０の一形態である半導体積層構造体（以下、試料Ａ１と呼ぶ）を作製し、その垂直断面のＴＥＭによる観察を行った。   As an example, a semiconductor multilayer structure (hereinafter referred to as sample A1), which is one form of the semiconductor multilayer structure 10 according to the first embodiment, was manufactured, and the vertical cross section thereof was observed with a TEM.

また、比較例として、Ｇａ２Ｏ３層の主面の面方位が（−２０１）と異なる半導体積層構造体（以下、試料Ｂ１と呼ぶ）を作製し、その垂直断面のＴＥＭによる観察を行った。 Further, as a comparative example, a semiconductor stacked structure (hereinafter referred to as sample B1) having a surface orientation of the main surface of the Ga 2 O 3 layer different from (−201) was prepared, and the vertical cross section was observed by TEM. .

（試料Ａ１の作製）
まず、Ｇａ２Ｏ３層１１として、（−２０１）面を主面とするＧａ２Ｏ３基板を用意し、裏面にＢＣｌ３ＲＩＥ（Reactive Ion Etching）処理を施した。 (Preparation of sample A1)
First, as the Ga 2 O 3 layer 11, a Ga 2 O 3 substrate having a (−201) plane as a main surface was prepared, and the back surface was subjected to BCl 3 RIE (Reactive Ion Etching) treatment.

次に、Ａｌ２Ｏ３膜１２として、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により、厚さ２０ｎｍのＡｌ２Ｏ３膜を２５０℃でＧａ２Ｏ３層１１上に成膜し、試料Ａ１を得た。具体的には、Ａｌの有機金属を原子層レベルの厚さで一層堆積させた後、酸化剤によりＡｌを酸化し、Ａｌ２Ｏ３の薄膜を形成する。これを２１６サイクル繰り返すことにより、厚さ２０ｎｍのＡｌ２Ｏ３膜を得た。 Next, as the Al 2 O 3 film 12, an Al 2 O 3 film having a thickness of 20 nm is formed on the Ga 2 O 3 layer 11 at 250 ° C. by a plasma ALD method using oxygen plasma as an oxidizing agent. A1 was obtained. Specifically, after depositing an organic metal of Al with a thickness of an atomic layer level, Al is oxidized with an oxidizing agent to form a thin film of Al 2 O 3 . By repeating this for 216 cycles, an Al 2 O 3 film having a thickness of 20 nm was obtained.

（試料Ｂ１の作製）
まず、比較例に係るＧａ２Ｏ３層５１として、（０１０）を主面とするＧａ２Ｏ３基板を用意し、裏面から深さ１５０ｎｍ、濃度５×１０１９ｃｍ−３の条件でＳｉをイオン注入した後、有機洗浄を施し、さらに、温度９５０℃、時間３０ｍｉｎの条件で活性化アニールを施した。 (Preparation of sample B1)
First, as a Ga 2 O 3 layer 51 according to the comparative example, a Ga 2 O 3 substrate having (010) as a main surface is prepared, and Si is formed under conditions of a depth of 150 nm and a concentration of 5 × 10 19 cm −3 from the back surface. After ion implantation, organic cleaning was performed, and activation annealing was further performed under conditions of a temperature of 950 ° C. and a time of 30 minutes.

次に、比較例に係るＡｌ２Ｏ３膜５２として、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により、試料Ａ１のＡｌ２Ｏ３膜１２と同様に、厚さ２０ｎｍのＡｌ２Ｏ３膜を２５０℃でＧａ２Ｏ３層５１上に成膜し、試料Ｂ１を得た。 Then, as the Al 2 O 3 film 52 of the comparative example, the oxygen plasma plasma ALD method using the oxidizing agent, as with the Al 2 O 3 film 12 of the sample A1, the thickness of 20 nm the Al 2 O 3 film Was formed on the Ga 2 O 3 layer 51 at 250 ° C. to obtain a sample B1.

（断面の観察）
図３（ａ）、（ｂ）は、それぞれ、実施例に係る試料Ａ１と、比較例に係る試料Ｂ１の垂直断面のＴＥＭ観察像である。 (Section observation)
3A and 3B are TEM observation images of vertical cross sections of the sample A1 according to the example and the sample B1 according to the comparative example, respectively.

図３（ａ）は、試料Ａ１のＡｌ２Ｏ３膜１２が、非晶質のＡｌ２Ｏ３を主成分とする層のみからなることを示している。 FIG. 3A shows that the Al 2 O 3 film 12 of the sample A1 is composed only of a layer containing amorphous Al 2 O 3 as a main component.

一方、図３（ｂ）は、試料Ｂ１のＡｌ２Ｏ３膜５２に、Ｇａ２Ｏ３層５１に接する結晶質層５２ａと、その上の非晶質層５２ｂが含まれることを示している。 On the other hand, FIG. 3B shows that the Al 2 O 3 film 52 of the sample B1 includes a crystalline layer 52a in contact with the Ga 2 O 3 layer 51 and an amorphous layer 52b thereon. .

試料Ｂ１のＡｌ２Ｏ３膜５２は、試料Ａ１のＡｌ２Ｏ３膜１２と同様に、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により、２５０℃で成膜されたものである。このことは、下地となるＧａ２Ｏ３層の主面の面方位により、結晶質層が形成されるか否かが決定されることを示している。 Similar to the Al 2 O 3 film 12 of the sample A1, the Al 2 O 3 film 52 of the sample B1 is formed at 250 ° C. by a plasma ALD method using oxygen plasma as an oxidizing agent. This indicates that whether or not the crystalline layer is formed is determined by the plane orientation of the main surface of the Ga 2 O 3 layer serving as the base.

なお、試料Ａ１のＡｌ２Ｏ３膜１２上の層１３は、Ａｕ膜である。また、試料Ｂ１のＡｌ２Ｏ３膜５２上の層５３は、カーボン系材料からなる保護膜である。 The layer 13 on the Al 2 O 3 film 12 of the sample A1 is an Au film. The layer 53 on the Al 2 O 3 film 52 of the sample B1 is a protective film made of a carbon-based material.

実施例として、上記の試料Ａ１を用いて第２の実施の形態に係るキャパシタ２０に相当するキャパシタ（以下、試料Ａ２と呼ぶ）を作製し、そのヒステリシス特性を調べた。   As an example, a capacitor (hereinafter referred to as sample A2) corresponding to the capacitor 20 according to the second embodiment was manufactured using the sample A1, and the hysteresis characteristics thereof were examined.

また、比較例として、上記の試料Ｂ１を用いてキャパシタ（以下、試料Ｂ２と呼ぶ）を作製し、そのヒステリシス特性を調べた。   As a comparative example, a capacitor (hereinafter referred to as sample B2) was prepared using the sample B1, and the hysteresis characteristics thereof were examined.

（試料Ａ２の作製）
まず、試料Ａ１のＧａ２Ｏ３層１１の裏面に厚さ２０ｎｍのＴｉ膜と厚さ２３０ｎｍのＡｕ膜を蒸着により積層することにより、カソード電極２１に相当するカソード電極を形成した。 (Preparation of sample A2)
First, a 20-nm-thick Ti film and a 230-nm-thick Au film were stacked by vapor deposition on the back surface of the Ga 2 O 3 layer 11 of the sample A1, thereby forming a cathode electrode corresponding to the cathode electrode 21.

次に、試料Ａ１のＡｌ２Ｏ３膜１２の表面に蒸着した厚さ２５０ｎｍのＡｕ膜を、リフトオフによって直径２００μｍの円形に残すことにより、アノード電極２２に相当するアノード電極を形成した。これにより、試料Ａ２を得た。 Next, an anode electrode corresponding to the anode electrode 22 was formed by leaving the Au film having a thickness of 250 nm deposited on the surface of the Al 2 O 3 film 12 of the sample A1 in a circular shape having a diameter of 200 μm by lift-off. This obtained sample A2.

（試料Ｂ２の作製）
試料Ｂ１に、試料Ａ２と同様の条件でカソード電極及びアノード電極を形成し、試料Ｂ２を得た。 (Preparation of sample B2)
A cathode electrode and an anode electrode were formed on Sample B1 under the same conditions as Sample A2, and Sample B2 was obtained.

（ヒステリシス特性の評価）
図４（ａ）、（ｂ）は、それぞれ、実施例に係る試料Ａ２と、比較例に係る試料Ｂ２のアノード電圧を往復スイープしたときの容量特性を示すグラフである。 (Evaluation of hysteresis characteristics)
FIGS. 4A and 4B are graphs showing capacity characteristics when the anode voltages of the sample A2 according to the example and the sample B2 according to the comparative example are swept back and forth, respectively.

図４（ａ）は、試料Ａ２がヒステリシス特性を有しないことを示している。一方、図４（ｂ）は、試料Ｂ２がヒステリシス特性を有することを示している。   FIG. 4A shows that the sample A2 does not have hysteresis characteristics. On the other hand, FIG. 4B shows that the sample B2 has hysteresis characteristics.

試料Ｂ２のヒステリシス特性は、結晶質層５２ａと非晶質層５２ｂとの界面に捕獲される電荷に起因していると考えられる。   It is considered that the hysteresis characteristic of the sample B2 is caused by charges captured at the interface between the crystalline layer 52a and the amorphous layer 52b.

試料Ａ２のＡｌ２Ｏ３膜１２は、非晶質層のみから構成され、結晶質層を有しないために、電荷捕獲サイトの形成が抑制され、試料Ａ２のヒステリシス特性が抑制されているものと考えられる。 Since the Al 2 O 3 film 12 of the sample A2 is composed of only an amorphous layer and does not have a crystalline layer, formation of charge trapping sites is suppressed, and hysteresis characteristics of the sample A2 are suppressed. Conceivable.

以上、本発明の実施の形態及び実施例を説明したが、本発明は、上記実施の形態及び実施例に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。   Although the embodiments and examples of the present invention have been described above, the present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the spirit of the invention.

例えば、第２の実施の形態において、第１の実施の形態に係る半導体積層構造体１０を含む半導体素子の一例として、キャパシタ２０を挙げたが、半導体積層構造体１０を含む半導体素子はこれに限られず、ＭＯＳＦＥＴ等、Ａｌ２Ｏ３膜１２を介した電界効果によってチャネル領域の導電性が制御される素子であればよい。 For example, in the second embodiment, the capacitor 20 is given as an example of the semiconductor element including the semiconductor multilayer structure 10 according to the first embodiment, but the semiconductor element including the semiconductor multilayer structure 10 is included in this. Any element can be used as long as the conductivity of the channel region is controlled by the field effect through the Al 2 O 3 film 12 such as a MOSFET.

また、上記に記載した実施の形態及び実施例は特許請求の範囲に係る発明を限定するものではない。また、実施の形態及び実施例の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。   The embodiments and examples described above do not limit the invention according to the claims. It should be noted that not all combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention.

１０…半導体積層構造体、 １１…Ｇａ２Ｏ３層、 １２…Ａｌ２Ｏ３膜、 ２０…キャパシタ 10 ... semiconductor stack, 11 ... Ga 2 O 3 layer, 12 ... Al 2 O 3 film, 20 ... capacitor

Claims (4)

Ｇａ２Ｏ３単結晶からなり、主面の面方位が（−２０１）であるＧａ２Ｏ３層と、
前記Ｇａ２Ｏ３層上に形成された、非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜と、
を有する、
ヒステリシス特性を有しない半導体積層構造体。 Consists Ga 2 O 3 single crystal, and Ga 2 O 3 layer, which is a plane orientation of main surface (-201)
An Al 2 O 3 film formed only on a layer mainly composed of amorphous Al 2 O 3 formed on the Ga 2 O 3 layer;
Having
A semiconductor laminated structure having no hysteresis characteristics. 前記Ａｌ２Ｏ３膜上に電極を有し、
前記Ａｌ２Ｏ３膜を介して電界効果を及ぼす、
請求項１に記載の半導体積層構造体を含む、半導体素子。 Having an electrode on the Al 2 O 3 film;
An electric field effect is exerted through the Al 2 O 3 film.
A semiconductor device comprising the semiconductor multilayer structure according to claim 1. Ｇａ２Ｏ３単結晶からなり、主面の面方位が（−２０１）であるＧａ２Ｏ３層の表面上に、酸素プラズマを酸化剤に用いたプラズマＡＬＤ法により、非晶質のＡｌ２Ｏ３を主成分とする層のみからなるＡｌ２Ｏ３膜を２５０℃以下の成長温度で形成する工程を含む、
半導体積層構造体の製造方法。 An amorphous Al 2 film is formed on the surface of a Ga 2 O 3 layer made of a Ga 2 O 3 single crystal and having a principal plane orientation of (−201) by plasma ALD using oxygen plasma as an oxidizing agent. Including a step of forming an Al 2 O 3 film composed only of a layer mainly composed of O 3 at a growth temperature of 250 ° C. or lower.
Manufacturing method of semiconductor laminated structure. 前記Ａｌ２Ｏ３膜上に電極を形成する工程を含む、
請求項３に記載の半導体積層構造体の製造方法を含む、前記Ａｌ２Ｏ３膜を介して電界効果を及ぼす半導体素子の製造方法。 Forming an electrode on the Al 2 O 3 film,
A method for manufacturing a semiconductor element that exerts an electric field effect via the Al 2 O 3 film, including the method for manufacturing a semiconductor multilayer structure according to claim 3.
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