JP6523702B2 - Differential circuit - Google Patents

Description

  The present invention relates to a differential circuit.

  Conventionally, a differential circuit in which a current corresponding to the difference between two input voltages is output is known. An example of a conventional differential circuit is shown in FIG.

  The conventional differential circuit DF100 shown in FIG. 7 includes transistors 101 to 108 and a constant current circuit 109. The sources of the transistors 101 and 102, which are p-channel MOSFETs (MOS field effect transistors) forming a differential pair, are connected to the application end of the power supply voltage via the constant current source 109. The input voltage Vp is applied to the gate of the transistor 101, and the input voltage Vm is applied to the gate of the transistor 102.

  A first current mirror is configured from a transistor 103 which is an n-channel MOSFET whose drain and gate are shorted and a transistor 104 which is an n-channel MOSFET, and the drain of the transistor 101 is connected to the drain of the transistor 103. Each source of the transistors 103 and 104 is connected to the ground terminal.

  A second current mirror is configured from a transistor 105 which is an n-channel MOSFET whose drain and gate are shorted and a transistor 106 which is an n-channel MOSFET, and the drain of the transistor 105 is connected to the drain of the transistor 102. Each source of the transistors 105 and 106 is connected to the ground terminal.

  A third current mirror is configured from the transistor 107 which is a p-channel MOSFET whose drain and gate are shorted and the transistor 108 which is a p-channel MOSFET, the drain of the transistor 106 is connected to the drain of the transistor 107 and the drain of the transistor 108 The drain of the transistor 104 is connected. The sources of the transistors 107 and 108 are connected to the application terminal of the power supply voltage. The connection point between the drain of the transistor 108 and the drain of the transistor 104 is connected to the output end Tout.

  A drain current flows in each of the transistors 101 and 102 in a distribution according to the input voltages Vp and Vm. Then, with the drain current flowing to the transistor 101 as an input, an output current I101 flows from the first current mirror. Further, with the drain current flowing through the transistor 102 as an input, an output current I102 flows through the second current mirror and the third current mirror.

JP 2009-156835 A (FIG. 5)

  Essentially, if the input voltages Vp and Vm are the same voltage, the output currents I101 and I102 should be balanced, and no current should be output from the output end Tout, but in practice the characteristic variation of the transistors 101 and 102 forming a differential pair As a result, the balance between the output currents I101 and I102 may be lost. That is, a current is output from the output end Tout, and an offset may occur.

  Therefore, it is conceivable to suppress the offset by increasing the gain by increasing the gate width of the transistors Vp and Vm and / or by shortening the gate length, and suppressing the characteristic variation. However, in this case, there is a problem that the mirror capacity becomes large and the response speed becomes slow because the gain becomes large.

  Therefore, for example, as shown in FIG. 8, a configuration including the constant current circuit 110, the transistors 111 and 112, and the resistors 113 and 114 is provided on the front side of the transistors 101 and 102 shown in FIG. It is also conceivable to adopt a multistage configuration in which the configuration including the constant current circuit 115, the transistors 116 and 117, and the resistors 118 and 119 is applied and the input voltage Vp is applied to the gate of the transistor 116 and the input voltage Vm is applied to the gate of the transistor 117. As a result, the gain of each transistor can be reduced to reduce the mirror capacitance, but the overall gain can be increased. However, there is a problem that the number of elements increases.

  In addition, although the conventional example of the overcurrent protective circuit using a differential circuit is shown by patent document 1, and the structure using a bipolar transistor is disclosed, the gate size in MOSFET etc. as mentioned above Patent Document 1 has not suggested anything about the suppression of the characteristic variation due to the setting of and the problem of the response speed associated therewith.

  In view of the above situation, the present invention has an object to provide a differential circuit capable of suppressing the number of elements while suppressing the offset and suppressing the decrease in response speed.

In order to achieve the above object, a differential circuit according to an aspect of the present invention is
A first constant current circuit,
A second constant current circuit having the same constant current value as the first constant current circuit,
A first transistor having a current inflow end connected to a first constant current circuit, a current outflow end to which a first input voltage is applied, and a gate shorted to the current inflow end; and the current inflow end of the first transistor A current mirror including a second transistor having a gate connected thereto and a current output terminal to which a second input voltage is applied;
The configuration includes a current output end connected to a connection point between a location where a current based on the output current of the current mirror flows and a connection point with the second constant current circuit (first configuration).

  According to such a configuration, by increasing the gain of the first transistor and the second transistor by increasing the gate width and / or shortening the gate length to suppress the characteristic variation, the first input voltage and the second input voltage can be reduced. The offset of the current output from the current output terminal when the two input voltages are balanced can be suppressed. In addition, even if the gain is increased and the mirror capacitance is increased as described above, the change in the first input voltage or the second input voltage is immediately converted to the change in the output current of the current mirror. It can be suppressed. Furthermore, the number of elements constituting the differential circuit can be reduced.

  In the first configuration, the second current mirror further includes a second current mirror in which the current inflow end and the input end of the second transistor are connected and the second constant current circuit and the output end are connected; The current output end may be connected to a connection point between the output end and the second constant current circuit (second configuration).

  Further, in the second configuration, the second current mirror has a drain and a gate short-circuited, and the source is connected to the first power channel voltage application terminal, and the gate and gate of the first p channel MOSFET are connected. And the source may include a second p-channel MOSFET connected to the application terminal of the power supply voltage (third configuration).

  In any one of the first to third configurations, an inverter stage including at least one inverter connected to a subsequent stage of the current output terminal may be further included (fourth configuration).

  In any one of the first to fourth configurations, the first transistor is an n-channel MOSFET to which the first input voltage is applied to the source, and the second transistor has the second input voltage applied to the source. May be an n-channel MOSFET (fifth configuration).

  Further, in any one of the first to fifth configurations, the voltage signal for current detection and the reference voltage may be respectively applied as either the first input voltage or the second input voltage (sixth Constitution).

  In the sixth configuration, the voltage signal for current detection may be a voltage signal based on a current flowing through a synchronous rectification transistor in a synchronous rectification switching power supply device, and the reference voltage may be a ground potential. (Seventh configuration).

  A power supply device according to another aspect of the present invention includes the differential circuit having the sixth or seventh configuration (eighth configuration).

A power supply device according to another aspect of the present invention is an output stage that generates a desired output voltage from an input voltage according to on / off control of an upper stage output transistor and a lower stage synchronous rectification transistor.
The voltage signal for current detection includes a differential circuit of the seventh configuration, which is a voltage signal of a connection point between the output transistor and the synchronous rectification transistor (ninth configuration).

  An electronic device according to another aspect of the present invention includes the power supply device having the eighth or ninth configuration.

  According to the differential circuit of the present invention, the number of elements can be suppressed while suppressing the offset and suppressing the decrease in response speed.

It is a circuit diagram of a differential circuit concerning one embodiment of the present invention. It is a figure showing the modification of the differential circuit concerning one embodiment of the present invention. FIG. 1 is a block diagram showing an overall configuration of a switching power supply device according to an embodiment of the present invention. It is a timing chart which shows switching operation at the time of heavy load. It is a timing chart which shows the backflow interception operation at the time of light load. It is an outline view of a smart phone concerning one embodiment of the present invention. It is a circuit diagram of a differential circuit concerning a conventional example. It is a figure which shows the modification of the differential circuit which concerns on a prior art example.

  An embodiment of the present invention will be described below with reference to the drawings. A circuit diagram of a differential circuit according to an embodiment of the present invention is shown in FIG.

  In FIG. 1, the differential circuit DF1 includes transistors 1 to 4 and constant current circuits 5 and 6. A first current mirror is configured from a transistor 1 which is an n-channel MOSFET whose drain and gate are shorted and a transistor 2 which is an n-channel MOSFET. The application terminal of the power supply voltage is connected to the drain of the transistor 1 via the constant current circuit 5. An input voltage Vm is applied to the source of the transistor 1.

  An input voltage Vp is applied to the source of the transistor 2. A second current mirror is configured from a transistor 3 which is a p-channel MOSFET whose drain and gate are shorted and a transistor 4 which is a p-channel MOSFET. The drain of the transistor 2 is connected to the drain of the transistor 3. An application terminal of a power supply voltage is connected to each source of the transistors 3 and 4. The drain of the transistor 4 is connected to the ground via the constant current circuit 6. The connection point between the drain of the transistor 4 and the constant current circuit 6 is connected to the output end Tout.

  Ideally, when the input voltages Vm and Vp are balanced at the same voltage, a current having the same value as the constant current by the constant current circuit 5 flowing in the transistor 1 flows in the transistor 2. An output current I2 flows through the second current mirror with the flowing current as an input. Since the constant currents flowing to the constant current circuits 5 and 6 are set to the same value, the output current I2 and the current flowing to the constant current circuit 6 are balanced, and no current is output from the output end Tout. When the balance between the input voltages Vp and Vm is broken, a current different from the constant current of the constant current circuit 5 flows to the transistor 2 accordingly, so the balance between the output current I2 and the current flowing through the constant current circuit 6 is The current is output from the output terminal Tout.

  However, in reality, even if the balance between the input voltages Vm and Vp is maintained due to the characteristic variation of the transistors 1 and 2, the balance between the output current I2 and the current flowing through the constant current circuit 6 is broken and the current from the output end Tout It may happen that it is output. That is, an offset may occur.

  Therefore, by increasing the gate width of the transistors 1 and 2 and / or shortening the gate length, the gain can be increased, and the characteristic variation can be suppressed to suppress the offset. Further, even if the gain is increased and the mirror capacitance is increased as described above, in this embodiment, the input voltage Vp is applied to the source, not to the gate of the transistor 2, so the change of the input voltage Vp Is immediately converted to a change in drain current, and does not cause a decrease in response speed (this also applies to a change in input voltage Vm). Also, the number of elements constituting the differential circuit DF1 can be reduced.

  Further, as in the differential circuit DF1 'shown in FIG. 2, an inverter stage IV11 composed of at least one inverter may be provided downstream of the output terminal Tout. According to such a configuration, the differential circuit DF1 'can function as a comparator.

<Example of application to power supply device>
Next, a power supply device will be described as a preferred application example of the differential circuit according to the present embodiment.
<< Switching Power Supply >>
FIG. 3 is a block diagram showing the overall configuration of the switching power supply device. The switching power supply device 25 of this configuration example is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a non-linear control method (bottom detection on-time fixed method). Switching power supply device 25 is formed of semiconductor device 10 and various discrete components (n-channel MOS field effect transistors N1 and N2, coil L1, capacitor C1, and resistors R1 and R2) externally attached to semiconductor device 10. And a switch output stage 20.

  The semiconductor device 10 is a main body (so-called power control IC) that controls the overall operation of the switching power supply device 25 in an integrated manner. The semiconductor device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5) as means for establishing electrical connection with the outside of the device. , And an output voltage terminal T6 and a ground terminal T7).

  The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to an application terminal of the switch voltage Vsw (a connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to an application terminal of the divided voltage Vdiv (a connection node between the resistor R1 and the resistor R2). The external terminal T5 is connected to the application terminal of the input voltage Vin. The external terminal T6 is connected to the application terminal of the output voltage Vout. The external terminal T7 is connected to the ground end.

  Next, the connection relationship of discrete components externally attached to the semiconductor device 10 will be described. The drain of the transistor N1 is connected to the application terminal of the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first end of the coil L1. The second end of the coil L1 and the first end of the capacitor C1 are both connected to the application end of the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

  The transistor N1 is an output transistor that is on / off controlled according to a gate signal G1 input from the external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled according to the gate signal G2 input from the external terminal T2. Note that a diode may be used instead of the transistor N2 as the rectifying element. The transistors N1 and N2 can also be incorporated in the semiconductor device 10. The coil L1 and the capacitor C1 function as a rectifying and smoothing unit that rectifies and smoothes a rectangular wave switch voltage Vsw appearing at the external terminal T3 to generate an output voltage Vout. The resistors R1 and R2 function as a divided voltage generation unit that divides the output voltage Vout to generate a divided voltage Vdiv.

  Next, the internal configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip flop 15, an on time setting circuit 16, and a gate driver circuit 17. , And the backflow detection circuit 18 are integrated.

  The ripple injection circuit 11 adds the ripple voltage Vrpl (a pseudo ripple component simulating the coil current IL flowing through the coil L1) to the divided voltage Vdiv to generate a feedback voltage Vfb (= Vdiv + Vrpl). If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage Vout (and the divided voltage Vdiv as a whole) is not so large. It is possible to use a ceramic capacitor or the like. However, when the ripple component of the output voltage Vout is sufficiently large, the ripple injection circuit 11 can be omitted.

  The reference voltage generation circuit 12 generates a predetermined reference voltage Vref.

  The main comparator 13 compares the feedback voltage Vfb input to the inverting input terminal (-) with the reference voltage Vref input to the non-inverting input terminal (+) to generate a comparison signal S1. The comparison signal S1 is low when the feedback voltage Vfb is higher than the reference voltage Vref, and is high when the feedback voltage Vfb is lower than the reference voltage Vref.

  One shot pulse generation circuit 14 generates a one shot pulse as set signal S2 using the rising edge of comparison signal S1 as a trigger.

  The RS flip flop 15 sets the output signal S4 to high level at the rising edge of the set signal S2 input to the set end (S), and the output signal at the rising edge of the reset signal S3 input to the reset end (R) Reset S4 to low level.

  The on-time setting circuit 16 sets the reset signal S3 to one after a predetermined on-time Ton elapses after the inverted output signal S4B (the logic inverted signal of the output signal S4) of the RS flip-flop 15 falls to low level. Generate a shot pulse.

  The gate driver circuit 17 generates gate signals G1 and G2 in accordance with the output signal S4 of the RS flip flop 15, and switches the transistors N1 and N2 complementarily. The term "complementary" used in the present specification includes the case where on / off of the transistors N1 and N2 is completely reversed, and also the transistor N1 and N2 from the viewpoint of through current prevention. It also includes the case where the on / off transition timing is delayed (when the simultaneous off period (dead time) is provided).

  The backflow detection circuit 18 monitors the backflow of the coil current IL (the coil current IL flowing from the coil L1 to the ground terminal via the transistor N2) to generate a backflow detection signal S5. The backflow detection signal S5 is latched at high level (logic level at the time of backflow detection) when backflow of the coil current IL is detected, and low level at the rising edge of the gate signal G1 in the next cycle (logic when no backflow detection) Reset to level). As a method of monitoring the backflow of the coil current IL, for example, a zero crossing point at which the switch voltage Vsw switches from negative to positive may be detected during the on period of the transistor N2. When the backflow detection signal S5 is at high level, the gate driver circuit 17 generates the gate signal G2 so as to forcibly turn off the transistor N2 without depending on the output signal S4.

  The ripple injection circuit 11, the reference voltage generation circuit 12, the main comparator 13, the one-shot pulse generation circuit 14, the RS flip flop 15, the on time setting circuit 16, the gate driver circuit 17, and the backflow detection circuit 18 A non-linear control method of generating the output voltage Vout from the input voltage Vin by performing on / off control of the transistors N1 and N2 according to the comparison result of the feedback voltage Vfb and the reference voltage Vref (bottom detection on time in this configuration example Functions as a fixed type switching control circuit.

<< Switching operation >>
FIG. 4 is a timing chart showing the switching operation under heavy load (in the continuous current mode), in which the feedback voltage Vfb, the set signal S2, the reset signal S3, and the output signal S4 are depicted sequentially from the top.

  At time t11, when the feedback voltage Vfb decreases to the reference voltage Vref, the set signal S2 rises to the high level, and the output signal S4 transitions to the high level. Therefore, the transistor N1 is turned on, and the feedback voltage Vfb turns to rise.

  Thereafter, when the reset signal S3 rises to the high level at time t12 due to the elapse of the on time Ton, the output signal S4 is shifted to the low level. Therefore, the transistor N1 is turned off, and the feedback voltage Vfb falls again.

  The gate driver circuit 17 generates gate signals G1 and G2 according to the output signal S4, and performs on / off control of the transistors N1 and N2 using these. Specifically, when the output signal S4 is at high level, basically, the gate signal G1 is set to high level to turn on the transistor N1, and the gate signal G2 is set to low level to turn off the transistor N2 Be done. Conversely, when the output signal S4 is at low level, basically, the gate signal G1 is at low level to turn off the transistor N1, and the gate signal G2 is at high level to turn on the transistor N2.

  Due to the on / off control of the transistors N1 and N2 described above, a switch voltage Vsw having a rectangular wave shape appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1 to generate an output voltage Vout. The output voltage Vout is divided by the resistors R1 and R2 to generate a divided voltage Vdiv (and thus a feedback voltage Vfb). By such output feedback control, in the switching power supply device 25, a desired output voltage Vout is generated from the input voltage Vin with an extremely simple configuration.

<< back flow blocking operation >>
FIG. 5 is a timing chart showing the reverse current blocking operation at light load (in discontinuous current mode), and from top to bottom, gate signals G1 and G2, reverse current detection signal S5, coil current IL, and switch voltage Vsw It is depicted.

  During time t21 to t22, the gate signal G1 is at the high level, and the gate signal G2 is at the low level. Thus, the transistor N1 is turned on and the transistor N2 is turned off. Therefore, from time t21 to t22, the switch voltage Vsw rises to almost the input voltage Vin, and the coil current IL increases.

  At time t22, when the gate signal G1 falls to low level and the gate signal G2 rises to high level, the transistor N1 is turned off and the transistor N2 is turned on. Accordingly, the switch voltage Vsw drops to a negative voltage (= GND−IL × RN2, where RN2 is the on-resistance value of the transistor N2), and the coil current IL starts to decrease.

  Here, when the output current Iout flowing to the load is heavy enough, the energy stored in the coil L1 is large, so the coil current IL has a zero value until time t24 when the gate signal G1 is raised to the high level again. Continues to flow toward the load, and the switch voltage Vsw is maintained at a negative voltage. On the other hand, at the time of light load where the output current Iout flowing to the load is small, the energy stored in the coil L1 is small, so at time t23 the coil current IL falls below the zero value and backflow of the coil current IL occurs. The polarity of the voltage Vsw switches from negative to positive. In such a state, since the charge stored in the capacitor C1 is discarded to the ground terminal, the efficiency at light load decreases.

  Therefore, switching power supply device 25 detects backflow of coil current IL (reverse polarity of switch voltage Vsw) using backflow detection circuit 18, and transistor N2 in the high level period (time t23 to t24) of backflow detection signal S5. Is configured to force off. With such a configuration, the backflow of the coil current IL can be cut off promptly, so that it is possible to eliminate the efficiency drop at the time of light load.

  The differential circuit according to the present embodiment can be applied to the backflow detection circuit 18. For example, the ground terminal may be connected to the application terminal of the input voltage Vm in the differential circuit DF1 '(FIG. 2) as a comparator, and the switch voltage Vsw may be applied to the application terminal of the input voltage Vp. For example, in an embodiment in which a normal current detection resistor is connected to the application end of the input voltage Vp, the current flowing through the transistor 2 is added as a bias current to the current flowing through the resistor. In the circuit 18, even if current flows in the transistor 2, the current flowing in the transistor N2 is not affected.

<Example of Electronic Device>
The power supply device having the differential circuit according to the present embodiment can be applied to various electronic devices. An external view of a smartphone is shown in FIG. 6 as an example of the electronic device.

  In appearance, the smartphone X illustrated in FIG. 6 has an imaging unit X1 mounted on the front or back of the main unit, an operation unit X2 (such as various buttons) that receives a user operation, and a display unit X3 that displays characters and images. Have. The display unit X3 has a touch panel function for receiving a touch operation of the user.

  By mounting the power supply device having the above-described differential circuit in various electronic devices such as a smartphone, it is possible to receive the advantages.

  In addition to the above embodiments, various modifications can be made to the various technical features disclosed in the present specification without departing from the scope of the technical creation thereof. That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not the description of the above embodiment but by the claims. It is to be understood that all changes which come within the meaning and range of equivalency of the claims are to be included.

  The differential circuit disclosed in the present specification can be used, for example, in a power supply device mounted in various electronic devices.

DF1, DF1 'differential circuit 1, 2 transistors (n-channel MOSFET)
3, 4 transistors (p-channel MOSFET)
5, 6 Constant current circuit IV11 Inverter stage Tout Output end 25 Switching power supply 10 Semiconductor device (power control IC)
11 ripple injection circuit 12 reference voltage generation circuit 13 main comparator 14 one shot pulse generation circuit 15 RS flip flop 16 ON time setting circuit 17 gate driver circuit 18 reverse current detection circuit 20 switch output stage N1 output transistor (n channel MOSFET)
N2 synchronous rectification transistor (n-channel MOSFET)
L1 coil R1, R2 resistance C1 capacitor T1 to T7 external terminal

Claims (9)

A first constant current circuit,
A second constant current circuit having the same constant current value as the first constant current circuit,
A drain connected to a first constant current circuit, the source first input voltage is applied, and a first n-channel MOSFET having a drain shorted gates, is connected to the drain of the first n-channel MOSFET A current mirror comprising a second n-channel MOSFET having a gate and a source to which a second input voltage is applied;
A differential circuit comprising: a point through which a current based on an output current of the current mirror flows, and a current output terminal connected to a connection point with a second constant current circuit. The second current mirror further includes a second current mirror in which the drain and the input end of the second n-channel MOSFET are connected and the second constant current circuit and the output end are connected, and the output end of the second current mirror and the second constant current circuit The differential circuit according to claim 1, wherein the current output terminal is connected to a connection point between the two.   In the second current mirror, the drain and the gate are short-circuited and the source is connected to the application terminal of the power supply voltage, the gate and the gate of the first p-channel MOSFET are connected, and the source is the application of the power supply voltage The differential circuit according to claim 2, further comprising a second p-channel MOSFET connected to the end.   The differential circuit according to any one of claims 1 to 3, further comprising an inverter stage including at least one inverter connected to a subsequent side of the current output terminal. The differential circuit according to any one of claims 1 to 4 , wherein a voltage signal for current detection and a reference voltage are respectively applied as either the first input voltage or the second input voltage. . The differential signal according to claim 5 , wherein the voltage signal for current detection is a voltage signal based on a current flowing through a synchronous rectification transistor in a synchronous rectification switching power supply device, and the reference voltage is a ground potential. circuit. Power apparatus comprising a differential circuit according to claim 5 or claim 6. An output stage that generates a desired output voltage from an input voltage according to on / off control of the upper stage output transistor and the lower stage synchronous rectification transistor;
The differential circuit according to claim 6 , wherein the voltage signal for current detection is a voltage signal at a connection point between the output transistor and the synchronous rectification transistor. The electronic device provided with the power supply device of Claim 7 or Claim 8 .

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