JP6503072B2 - Semiconductor system and calculation method - Google Patents

Description

  The present invention relates to a semiconductor system and a calculation method, and is particularly suitable to be applied to a semiconductor system and a calculation method for calculating a large-scale and complex interaction model.

  Various physical phenomena and social phenomena can be expressed by interaction models. The interaction model is a model defined by a plurality of nodes constituting the model, interactions among the nodes, and, if necessary, a bias for each node. Various models have been proposed in physics and social sciences, but they can all be interpreted as a form of interaction model.

  The Ising model can be mentioned as an example of a typical interaction model in the world of physics. The Ising model is a model of statistical mechanics for explaining the behavior of a magnetic substance. The Ising model is defined by binary spins of + 1 / -1 (or 0/1, up / down), an interaction coefficient indicating an interaction between spins, and an external magnetic field coefficient for each spin .

  The Ising model can calculate the energy at that time from the given spin arrangement, interaction coefficient, and external magnetic field coefficient. The energy function of the Ising model is generally expressed by the following equation.

Note that σ _i and σ _j are the values of the i-th and j-th spins, J _ij is the interaction coefficient between the i-th and j-th spins, h _i is the external magnetic field coefficient for the i-th spin, and σ is Let us denote the arrangement of spins.

In the equation (1), the first term is to calculate the energy resulting from the interaction between spins. In general, the Ising model is expressed as an undirected graph, and does not distinguish the interaction from the i-th spin to the j-th spin and the interaction from the j-th spin to the i-th spin. Therefore, in the first term, the influence of the interaction coefficient is calculated for the combination of σ _i and σ _j satisfying i <j. The second term is to calculate the energy attributable to the external magnetic field for each spin.

  The ground state search of the Ising model is an optimization problem for finding an arrangement of spins that minimizes the energy function of the Ising model. It is known that finding the ground state of the Ising model in which the topology becomes a nonplanar graph is an NP-hard problem when the value range of the interaction coefficient and the external magnetic field coefficient is not limited.

  The ground state search of the Ising model is used not only for explaining the behavior of the magnetic substance originally intended for the Ising model but also for various applications. This is because Ising's model is the simplest model based on interaction, and also has the ability to represent various events resulting from interaction.

  Also, the ground state search of the Ising model corresponds to the maximum cut problem known as the NP-hard graph problem. Such graph problems have wide applications, such as community detection in social networks and segmentation in image processing. Therefore, if there is a solver that searches the ground state of Ising model, it can be applied to such various problems.

  Finding the ground state of the Ising model is an NP-hard problem as described above. Therefore, solving with a von Neumann computer involves difficulties in terms of calculation time. An algorithm for speeding up with the introduction of heuristics has also been proposed, but a calculation using physical phenomena instead of a von Neumann computer, that is, a method for rapidly obtaining the ground state of Ising model by an analog computer has been proposed. For example, as such an apparatus, there is an apparatus described in Patent Document 1.

International Publication No. 2012/118064

  In the apparatus described in Patent Document 1, the degree of parallelism corresponding to the problem to be solved is required. In the case of the Ising model, elements corresponding to the spins of the Ising model for which a ground state is to be searched, and interactions with other spins in the spins (hereinafter referred to as unit elements )Is required. For example, in the device disclosed in Patent Document 1, since the spin and the laser correspond to each other, the number of lasers proportional to the number of spins is required. That is, it is necessary to have a high degree of scalability capable of mounting a large number of unit elements.

  In consideration of the above, it is desirable that the ground state search of the Ising model can be performed by a solid element such as a semiconductor which can be realized by arranging a large number of unit elements regularly. In particular, it has an array structure represented by a storage device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), and has a simple unit element so as to improve integration. desirable.

  For example, in order to construct a semiconductor system capable of searching for the ground state of a large scale Ising model including a large number of spins, it is necessary to mount unit elements on the semiconductor chip in a number corresponding to the number of spins. Then, it is desirable that the number of spins that the semiconductor chip can handle is larger than the size of the Ising model, and that the Ising model can be mapped onto the semiconductor chip without leakage. However, considering that the problem size of the problem to be solved increases, if only one semiconductor chip is used, the chip size increases and the manufacturing cost also increases. Therefore, in order to realize such a semiconductor system, it is desirable to construct a plurality of semiconductor chips on which a certain number of unit elements are mounted.

  Furthermore, in the case of using a plurality of identical semiconductor chips, for example, in the case of the simplest two-dimensional lattice, semiconductor chips are arranged in a tile in the X direction and Y direction, and adjacent semiconductor chips are connected by wiring Be done. In this case, the connection of the semiconductor chip can be performed in four directions of the chip, data transmission between adjacent chips is possible, and it is possible to solve a large-scale problem by up, down, left, and right chip expansion. However, when solving a more complicated large-scale problem, it is necessary to cope with the complexity of the extension method accordingly.

  An object of the present invention is to provide an inexpensive and easily manufacturable semiconductor system and calculation method capable of calculating a large scale and complex interaction model such as Ising model.

  The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

  The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.

  The semiconductor system in one embodiment is a semiconductor system provided with a plurality of semiconductor chips and a controller connected to the plurality of semiconductor chips. Each of the plurality of semiconductor chips includes: a first memory in which the value of each node of the problem data represented by the interaction model in which processing is executed by interaction among the plurality of nodes; A plurality of units are provided including a second memory in which coefficients related to each node are stored, and an arithmetic circuit that updates the value of each node stored in the first memory.

  The controller is a third memory in which the value of each node of the problem data to be processed is stored, a fourth memory in which a coefficient related to each node of the problem data to be processed is stored, and the processing object The third and the third are based on a register for setting the size of problem data to be taken, the number of chips of the semiconductor chip to be controlled, and the size of problem data that can be processed in one chip, and the set value of the register. An address generation unit for setting a correspondence between an address of a fourth memory and an address of each of the plurality of semiconductor chips; and each of the nodes stored in the third and the fourth memories based on the correspondence. And a data expansion unit for transmitting the coefficient and the coefficient to the plurality of semiconductor chips, and the values of the respective nodes stored in the first memory of the plurality of semiconductor chips Receiving, and a data aggregation unit for storing said to correspond based on the relationship the third memory.

  The calculation method in one embodiment is a calculation method of a semiconductor system including a plurality of semiconductor chips and a controller connected to the plurality of semiconductor chips. The semiconductor system has the same configuration as the semiconductor system in the above-described embodiment. Then, the address generation unit sets the correspondence between the addresses of the third and fourth memories and the addresses of the plurality of semiconductor chips based on the set value of the register. The data expansion unit transmits the values of the nodes and the coefficients stored in the third and fourth memories to the plurality of semiconductor chips based on the correspondence relationship. The data aggregation unit receives the value of each of the nodes stored in the first memory of the plurality of semiconductor chips, and stores the value in the third memory based on the correspondence.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  According to one embodiment, a large-scale and complex interaction model such as Ising model can be calculated, and an inexpensive and easily manufacturable semiconductor system and calculation method can be realized.

FIG. 1 is a block diagram showing an example of the overall configuration of an information processing system including a semiconductor system according to a first embodiment. FIG. 1 is a block diagram showing an example of the configuration of a semiconductor system in a first embodiment. FIG. 8 is a diagram showing an example of control of a controller in the first embodiment. FIG. 2 is a block diagram showing an example of a configuration of a semiconductor chip in the first embodiment. FIG. 6 is a diagram showing an example of the configuration of an Ising model in the first embodiment. FIG. 7 is a diagram showing an example of a configuration of a spin unit in the first embodiment. FIG. 7 is a diagram showing a relationship between problem data expressed by Ising model and a semiconductor chip in the first embodiment. FIG. 7 is a diagram showing a relationship between problem data expressed by Ising model and a semiconductor chip in the first embodiment. FIG. 6 is a diagram showing an example of mounting of a semiconductor chip in the first embodiment. FIG. 6 is a diagram showing an example corresponding to a large scale and complicated problem with a plurality of semiconductor chips in the first embodiment. FIG. 6 is a diagram showing an example corresponding to a large scale and complicated problem with a plurality of semiconductor chips in the first embodiment. FIG. 6 is a diagram showing an example corresponding to a large scale and complicated problem with a plurality of semiconductor chips in the first embodiment. FIG. 10 is a diagram summarizing an example of the relationship between the address of the spin data storage unit, the chip number of the expansion destination, and the local address in the first embodiment. FIG. 7 is a diagram showing an example of defining a connection between chips in the first embodiment. FIG. 7 is a block diagram showing an example of a configuration of an adjacent chip connection portion in the first embodiment. FIG. 7 is a block diagram showing an example of a configuration of an adjacent chip connection portion in the first embodiment. FIG. 8 is a diagram showing an example of a flowchart of the entire operation by the controller in the first embodiment. It is the figure which showed an example of the energy transition for every calculation step which makes a premise in 2nd Embodiment. It is a figure showing an example of change of a data transmission specification in a 2nd embodiment. It is a block diagram showing an example of composition of a semiconductor system in a 3rd embodiment. FIG. 21 is a block diagram showing an example of the entire configuration of a network system including a computing system according to a fourth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but unless specifically stated otherwise, they are not mutually unrelated, one is the other And some or all of the variations, details, and supplementary explanations. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated or considered to be obviously essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail based on the drawings. Note that, in all the drawings for describing the embodiments, the same symbol is attached to the same member in principle, and the same symbol or a related symbol is attached, and the repeated explanation thereof is omitted. Further, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly required.
First Embodiment

The first embodiment relates to an inexpensive and easily manufacturable semiconductor system capable of calculating a large-scale and complex interaction model such as Ising model, for example.
<Interaction model>

  Various physical phenomena and social phenomena can be expressed by interaction models. The interaction model is a model defined by a plurality of nodes constituting the model, interactions among the nodes, and, if necessary, a bias for each node. Various models have been proposed in physics and social sciences, but they can all be interpreted as a form of interaction model.

  Also, as a feature of the interaction model, the influence between nodes is limited to the interaction between two nodes (the interaction between two bodies). For example, considering the dynamics of planets in space, it can be interpreted as a kind of interaction model in that there is universal interaction between nodes called planets, but the inter-planet effect is between two planets Besides, three or more planets interact with each other to show complicated behavior (a problem called so-called three-body problem or many-body problem).

  The Ising model can be mentioned as an example of a typical interaction model in the world of physics. The Ising model is an interaction coefficient that determines the interaction between two spins with a spin taking two states of + 1 / -1 (or up, down, etc.) as a node, and an external magnetic field coefficient that is a bias for each spin The model is defined by

  Also, in the world of biology, neural networks that model the brain are an example of interaction models. A neural network is an artificial neuron that simulates a neuron of a neural cell as a node, and the artificial neuron has an interaction of synaptic connection. In addition, each neuron may be biased.

  In the social sciences world, for example, considering human communication, it can be easily understood that there is an interaction between human nodes and language and communication. You can also imagine that each person has its own bias. For this reason, research has also been made to imitate human communication as an Ising model common in terms of interaction models and clarify its characteristics.

In the following, an example of a semiconductor system for performing a ground state search of Ising model and an information processing system including the semiconductor system will be described.
<Ising model>

  In the present embodiment, a model expressed by the following equation (2), which is an extension of the Ising model, is hereinafter referred to as the Ising model.

The difference from the Ising model shown by the equation (1) is that the interaction as shown by the digraph in the equation (2) is allowed. In general, the Ising model can be drawn as an undirected graph in graph theory. That is because the interaction of Ising model does not distinguish the interaction coefficient J _{i, j} from the i-th spin to the _j- th spin and the interaction coefficient J _{j, i} from the j-th spin to the i-th spin .

In this embodiment, since the Ising model can be extended and applied even if J _{i, j} and J _{j, i} are distinguished, a directed graphing Ising model is handled. When the Ising model of an undirected graph is handled in a directed graph Ising model, it is possible by simply defining the same interaction coefficient in both directions of J _{i, j} and J _{j, i} . In this case, even with the same model, the energy value of the equation (2) is doubled with respect to the energy function of the equation (1).

Based on the above, hereinafter, the semiconductor system according to the present embodiment and an information processing system including the same will be described.
<Information processing system including semiconductor system>

  FIG. 1 is a block diagram showing an example of the entire configuration of an information processing system including a semiconductor system according to the present embodiment. In the information processing system shown in FIG. 1, 101 is a CPU (Central Processing Unit), 102 is a memory, 103 is a storage device, 104 is a semiconductor system, and 105 is a system bus. The information processing system includes a personal computer, a work station or a server, and the CPU 101, the memory 102, the storage device 103, and a plurality of semiconductor systems 104 are connected via the system bus 105.

  The CPU 101 is a processor that controls the operation of the entire information processing system. The CPU 101 corresponds to an arithmetic device. The memory 102 is, for example, a volatile semiconductor memory and is used to store various programs. The storage device 103 is configured of, for example, a hard disk drive or a solid state drive (SSD), and is used to hold programs and data for a long time.

  The storage device 103 stores Ising type problem data (calculation data) to be solved by the information processing system.

The semiconductor system 104 is dedicated hardware for performing a ground state search of the Ising model. Although two semiconductor systems 104 are illustrated in FIG. 1, there may be one or more than two.
<Semiconductor system>

  FIG. 2 is a block diagram showing an example of the configuration of the semiconductor system 104. As shown in FIG. As shown in FIG. 2, the semiconductor system 104 includes the controller 106, system I / F 107, register 108, data processing unit 109, clock generation unit 110, problem data storage unit 111, spin data storage unit 112, interaction control signal generation. The unit 127 includes a random number generation unit 128, a data I / F 113, a switch 114, and a semiconductor chip group 115, and transmits and receives commands and data with the CPU 101 via the system I / F 107 and the system bus 105.

  The semiconductor chip group 115 is composed of a plurality of semiconductor chips 116 each of which is dedicated hardware for performing a ground state search of the Ising model alone. The semiconductor chips 116 are connected by interchip interconnects 117, and the semiconductor chips 116 transmit and receive necessary information via the interchip interconnects 117.

  The system I / F 107 receives commands, parameter values, and various data via the system bus 105, and transfers the input commands, parameter values, and various data to the register 108 and the data processing unit 109.

  The problem data storage unit 111 is a block that stores the interaction coefficient of the Ising model and the external magnetic field coefficient, and the problem data stored in the storage device 103 is transferred via the system I / F 107. That is, the problem data storage unit 111 is a first storage area for storing calculation data for performing a base state search of the Ising model stored in the storage device 103.

  The spin data storage unit 112 is a block for storing the spin value of the Ising model, and the spin data stored in the storage device 103 is transferred via the system I / F 107. The spin data storage unit 112 is a second storage area for storing the result of counting by the data counting unit 126.

  For example, in the case of FIG. 2, the register 108 is a problem setting register 118 that defines the size of the problem represented by the interaction coefficient, the external magnetic field coefficient, and the spin, and the number of chips of the semiconductor chip 116 to be controlled by the controller 106. And a chip specification setting register 121 for specifying the size of the problem that can be dealt with in one chip. This register value is set via the system I / F 107 and referred to in the controller 106, for example, the data processing unit 109.

  The data processing unit 109 includes an inter-chip connection unit 122, an address generation unit 123, a data generation unit 124, an expansion unit 125, and a data collection unit 126, and via the system bus 105 and the system I / F 107. A process for expanding the problem data transmitted from the storage device 103 to a plurality of semiconductor chips 116 is performed.

  Although the details will be described later, the address generation unit 123 is stored in the problem data storage unit 111 and the spin data storage unit 112 with reference to the problem setting register 118, the chip number setting register 120, and the chip specification setting register 121. It defines the relationship between the address of each data, the chip number as the transmission destination, and the local address.

  The data generation unit 124 reads out the problem data corresponding to the designated address from the problem data storage unit 111 and reads out the spin data from the spin data storage unit 112. Then, in order to realize data transmission for each semiconductor chip 116, the expansion unit 125 adds the chip number of the transmission destination and the determination data of the problem data / spin data to the transmission data, and transfers it to the data I / F 113.

  The data totaling unit 126 collects the results processed by the plurality of semiconductor chips 116 via the switch 114 and the data I / F 113, and totals them, and writes the spin value as the processing result in the spin data storage unit 112. The data totaling unit 126 performs reverse conversion on the relationship between the address of each data realized by the address generation unit 123 described above, the chip number as the transmission destination, and the local address. That is, the chip number input through the switch 114, the problem data / spin data determination signal and the local address are converted into the address of the spin data storage unit 112, and the spin value on the spin data storage unit 112 is data. Update.

  The chip-to-chip connection unit 122 is a block that carries out a process as if the chips were connected to each other on mounting. Although the detailed operation will be described later, the inter-chip connection unit 122 is a block that processes the spin value stored in the spin data storage unit 112, and overwrites the spin value of an arbitrary address A on the spin of another address B. Then, the operation of reflecting the calculation result corresponding to the address A on the spin value corresponding to the address B is performed.

  The data I / F 113 is an interface for transmitting and receiving data between the controller 106 and the semiconductor chip group 115. For example, although not shown in FIG. 2, it has a buffer and is controlled so that all data transferred from the expansion unit 125 is transferred to the semiconductor chip group 115 through the switch 114.

  The clock generation unit 110 operates based on a base clock CLK input from the outside of the controller 106, between the clock 1 for operating the logic circuit in the controller 106, the clock 2 for operating the plurality of semiconductor chips 116, and the semiconductor chips 116. The clock 3 used to transmit data is generated.

  The interaction control signal generation unit 127 is a block that generates an address signal and a clock signal for realizing an interaction operation in the semiconductor chip 116.

  The random number generation unit 128 is a block that generates an RND signal supplied to the semiconductor chip 116. Although details will be described later, by using the RND signal, the local optimal solution in the graph problem is escaped, and the convergence to the global optimal solution is improved.

The switch 114 is connected to the controller 106 and the plurality of semiconductor chips 116 constituting the semiconductor chip group 115, and develops the problem data and spin data to the plurality of semiconductor chips 116 according to the rule generated by the data processing unit 109. Recovery of spin data from the semiconductor chip 116 of FIG. Thereby, data transmission between the semiconductor chips 116 is also realized.
<Control of controller>

  FIG. 3 is a diagram showing an example of control of the controller 106. As shown in FIG. In the present embodiment, the controller 106 causes the data processing unit 109 to refer to the register 108 including the problem setting register 118, the chip number setting register 120, and the chip specification setting register 121 to set the problem size to be solved. In contrast, it can be determined whether the number of semiconductor chips 116 to be controlled is large or small.

  In FIG. 3, Case 1, Case 2, and Case 3 are shown as control examples of the controller 106 when the register 108 is referred to. In any case, the problem size that can be handled by one of the semiconductor chips set in the chip specification setting register 121 is 128 (size width) × 80 (number of lines) × 2 (Z direction) and is a three-dimensional lattice I assume.

  In Case 1, the number of chips set in the chip number setting register 120 is set to 1 and the problem size set in the problem setting register 118 is also 128 × 80 × 2. In this case, since the problem size is equal to the size that can be handled by the semiconductor chip group 115, it can be determined that there is no failure and that the solution is possible "ok". In case 1, all chips are turned on in power control.

  Case 2 is a case where the number of chips (4) is smaller than the problem size (260 × 160 × 2), and it can be determined that the solution is not possible “NG”. In this case, for example, a warning may be issued to the problem conversion program.

  Also, Case 3 has a large number of chips (6) for the problem size (256 × 160 × 2), and excessive power can be turned off (2 chips off) to reduce power consumption. The case is shown. In case 3, the determination is “ok”.

  Although FIG. 3 illustrates the problem and the structure of the spin array of the semiconductor chip 116 as a three-dimensional simple lattice in order to facilitate the description, the controller 106 may use any rule even if the structure is complicated. In accordance with, it is possible to judge whether the set problem can be solved or not in terms of the scale.

As described above, it is assumed that the ground state search of the Ising model using a plurality of chips is performed by the operation of each configuration block shown in FIG.
<Configuration of semiconductor chip>

  FIG. 4 is a block diagram showing an example of the configuration of the semiconductor chip 116. As shown in FIG. In the semiconductor chip 116 shown in FIG. 4, 401 is an I / F, 402 is an interchip transmission I / F, 403 is a register, 404 is a memory controller, 405 is a spin array, 406 is an interaction I / F, and 407 is an interaction. The address decoder 408 is an inter-chip transmission unit controller, 409 is a boundary spin control unit, 410 is a transmission buffer, and 411 is a reception buffer. In the present embodiment, the semiconductor chip 116 is described as being implemented as a CMOS (Complementary Metal-Oxide Semiconductor) integrated circuit widely used at present, but other solid elements may be used. I do not care.

  The I / F 401 is a block in which the semiconductor chip 116 is connected to the switch 114, and is an interface for transmitting and receiving problem data and spin data with the controller 106.

In the semiconductor chip 116, the spin array 405 is configured by an SRAM. Thus, the memory controller 404 operates as an SRAM controller. More specifically, the spin σ _{i of the} Ising model, the interaction coefficient J _{i, j} and the external magnetic field coefficient h _i are all expressed by information stored in memory cells in the spin array 405. The setting of the initial state of the spin σ _i and the reading of the solution after the completion of the ground state search are performed via the memory controller 404.

Further, in the semiconductor chip 116, the read / write of the interaction coefficient J _{i, j} and the external magnetic field coefficient h _i for setting the Ising model whose ground state should be searched to the spin array 405 is also implemented via the memory controller 404. . Therefore, an address is given to the spin σ _i , the interaction coefficient J _{i, j} and the external magnetic field coefficient h _i in the spin array 405. Then, when reading / writing the spin σ _i , the interaction coefficient J _{i, j} or the external magnetic field coefficient h _i , the memory controller 404 outputs an address and R / W (read / write) control signal and outputs a data bus Read and write through.

  The semiconductor chip 116 also has an interaction I / F 406 and an interaction address decoder 407 for performing a ground state search of Ising model, and the ground state search interacts between the spins inside the spin array 405. Realize by implementing. The interaction I / F 406 transfers the address and clock input from the controller 106 to the interaction address decoder 407. Then, the interaction address decoder 407 designates spin groups to perform interaction based on the transferred address, and the clock operates the interaction circuit mounted on the spin array 405.

Although the details of the interaction circuit will be described later, the flow of ground state search will be briefly described here. First, the interaction address decoder 407 receives the interaction coefficient J _{i, j} and the external magnetic field coefficient h _i stored in the memory cell in the spin array 405 based on the address input through the interaction I / F 406 _. And read the spin value. Then, after the interaction is implemented in the mounted interaction circuit, read / write is performed.

  In addition, the semiconductor chip 116 has a random number injection line for injecting a random number which stochastically inverts the value of the memory cell representing the spin of the Ising model as described later. The RND signal generated by the random number generation unit 128 described with reference to FIG. 2 is applied to the spin array 405 via the random number injection line.

  Next, data transmission between adjacent chips will be described. Data transmission between adjacent chips is realized by the register 403, the inter-chip transmission unit controller 408, the boundary spin control unit 409, the transmission buffer 410, the reception buffer 411, and the inter-chip transmission I / F 402. First, the boundary spin control unit 409 reads the spin value at the boundary of the spin array 405 every m bits. Then, in the chip, the chip is finally transferred to the chip-to-chip transmission I / F 402, and the n-bit width chip-to-chip transmission I / F 402 transmits the spin value at the boundary to another chip. Here, the transmission buffer 410 plays the role of arbitrating between the bit width m of the boundary spin control unit 409 and the bit width n of the inter-chip transmission I / F 402.

For example, if m> n, the bit width n of the inter-chip transmission I / F 402 is small, so the m-bit spin value is temporarily stored in the transmission buffer 410, and the inter-chip transmission I / F 402 is divided into n bits each. Separately read out and transmit to other chips. When m <n, since the bit width m of boundary spin control section 409 is small, the spin value is read m bits at a time, and when n bits of data are stored in transmission buffer 410, inter-chip transmission I / F402 transmits to the other chip. The spin value transmission from the other chip to the semiconductor chip 116 is realized through the reception buffer 411 by the same operation as the transmission side described above.
<Configuration of Ising model>

  FIG. 5 is a diagram showing an example of the configuration of the Ising model. FIG. 5 shows an example in which an Ising model having a three-dimensional lattice topology is configured by arranging a plurality of spin units. In FIG. 5, 501 and 502 are spins, 503 and 504 are interaction coefficients, 505 is an external magnetic field coefficient, and 506 is a spin unit. The example of FIG. 5 is a three-dimensional lattice having a size of 3 (X-axis direction) × 3 (Y-axis direction) × 2 (Z-axis direction). As shown in the figure, the coordinate axes are defined as X axis in the right direction of the drawing, Y axis in the down direction of the drawing, and Z axis in the depth direction of the drawing, but when using a topology other than a three dimensional grid, such as a tree topology. Is expressed by the number of steps of the tree separately from the coordinate axes. In the three-dimensional lattice topology of FIG. 5, when the interaction between spins is viewed as a graph, spins (vertices) of order 5 are required at the maximum. In addition, considering the connection of the external magnetic field coefficient, the order 6 is required at the maximum.

In one spin unit 506 shown in FIG. 5, values of adjacent spins (for example, σ _j , σ _k , σ _l , σ _m , σ _{n in} the case of five adjacent spins) are input. The spin unit 506 then determines the spin value, the external magnetic field coefficient, and the interaction coefficient existing between adjacent spins (J _{j, i} , J _{k, i} , J _{l, i} , J _{m, i} , J _{n, i} ), and the semiconductor chip 116 has corresponding memory cells.

By the way, as described above, the Ising model generally has an interaction represented by an undirected graph. In the above-mentioned equation (1), there is J _{i, j} × σ _i × σ _j as a term representing the interaction, which indicates the interaction from the i-th spin to the j-th spin. In this case, the general Ising model does not distinguish between the interaction from the i-th spin to the j-th spin and the interaction from the j-th spin to the i-th spin. That is, J _{i, j} and J _{j, i} are the same. However, in the semiconductor chip 116 of the present embodiment, as described above, this Ising model is extended to a directed graph (equation (2)), and the interaction from the i-th spin to the j-th spin and the j-th spin It is realized to make the interaction to the i-th spin asymmetric. This increases the expressive power of the model and allows many problems to be expressed in smaller models.

Therefore, when one spin unit 506 is considered as the i-th spin σ _i , the interaction coefficients J _{j, i} , J _{k, i} , J _{l, i} , J _{m, i which} are held by the spin unit 506 , J _{n, i} are interactions from the adjacent j-th, k-th, l-th, m-th, n-th spins σ _j , σ _k , σ _l , σ _m , σ _n to the ith spin σ _i The decision is This means that, in FIG. 5, an arrow (interaction) corresponding to the interaction coefficient included in the spin unit 506 is from a spin outside the illustrated spin unit 506 to a spin inside the spin unit 506. It corresponds to what is heading.
<Configuration of spin unit>

  FIG. 6 is a diagram showing an example of the configuration of the spin unit 506. As shown in FIG. In the spin unit 506 shown in FIG. 6, 601 is a memory cell group, 602 is a logic block, 603 to 615 are memory cells, 616 is an XNOR (exclusive exclusive OR) circuit, 617 is a switch, and 618 is majority logic A circuit 619 is an inverting logic circuit, and 620 is a selector.

The spin unit 506 has a memory cell group 601 for holding the spin σ _{i of the} Ising model, the interaction coefficient J _{j, i to} J _{n, i} and the external magnetic field coefficient h _i , and the breakdown is a plurality Memory cells 603 to 615 (N, IS0, IS1, IU0, IU1, IL0, IL1, IR0, IR1, ID0, ID1, IF0, IF1). Note that the memory cells 604 and 605, the memory cells 606 and 607, the memory cells 608 and 609, the memory cells 610 and 611, the memory cells 612 and 613, and the memory cells 614 and 615 play a role of two in a set, respectively. .

Here, as the spin unit 506 represents the i-th spin, the definition of data stored in the memory cell will be described. A memory cell 603 (for N) is a memory cell for expressing spin σ _i and holds the value of spin. The value of spin is + 1 / -1 (+1 is also expressed as up and -1 below) in the Ising model, but this corresponds to 0/1, which is a binary value that can be held by a memory cell. For example, +1 corresponds to 1 and -1 to 0.

  Memory cells 604 to 615 (ISx, IUx, ILx, IRx, IDx and IFx) have two memory cells with numbers 0 and 1 at the end (e.g., memory cell IS0 in the case of memory cells 604 to 605 (ISx) The combination of IS1) represents three values of + 1/0 / -1. For example, in the case of the memory cells 604 to 605 (ISx), + 1 / -1 is expressed in the memory cell 605 (IS1), and when the value held by the memory cell 605 (IS1) is 1, +1. When the value held by (IS1) is 0, it represents -1.

  In addition to this, when the value held by the memory cell 604 (IS0) is 0, the external magnetic field coefficient is regarded as 0, and when the value held by the memory cell 604 (IS0) is 1, the memory cell 605 (IS1) is held. One of + 1 / -1 determined by the value is used as the external magnetic field coefficient. If it is considered that the external magnetic field coefficient is disabled when the external magnetic field coefficient is 0, it can be said that the value held in the memory cell 604 (IS0) is the enable bit of the external magnetic field coefficient (IS0 = 1 External field coefficient is enabled). The memory cells 606 to 615 (IUx, ILx, IRx, IDx, and IFx) storing the interaction coefficient similarly associate the coefficient with the value of the bit.

  The memory cells 603 to 615 (N, IS0, IS1, IU0, IU1, IL0, IL1, IR1, ID1, ID1, IF0 and IF1) in the spin unit 506 are each read from the outside of the semiconductor chip 116. Make light possible. Then, the memory controller 404 drives, controls, or reads these spin units 506 to read / write the memory cells 603 to 615 in the spin units 506 as in a general SRAM (Static Random Access Memory). To be able to

  Next, referring to memory cells 603-615, logic block 602 will be described which actually performs the interaction.

  The logic block 602 is composed of an interaction circuit consisting of an XNOR (exclusive-OR NOT) circuit 616 and a switch 617, a majority logic circuit 618, an inversion logic circuit 619, and a selector 620. And the interaction circuit which determines the state of spin according to the interaction result is installed independently for every spin unit 506. The independent installation enables simultaneous updating of spin values.

  The spin unit 506 has signal lines EN, NU1, NL1, NR1, ND1, NF1, NOUT and RND as interfaces with the outside. The signal line EN is an interface for inputting a switching signal for permitting updating of the spin of the spin unit 506. By controlling selector 620 with this switching signal, it is possible to update the spin value held in memory cell 603 (N) to a value given via majority logic circuit 618 and inversion logic circuit 619 described later. .

  The signal line NOUT is an interface that outputs the spin value of the spin unit 506 to another spin unit 506 (adjacent unit in the topology of FIG. 5). Signal lines NU, NL, NR, ND and NF are interfaces for inputting the spin values held by the other spin units 506 (adjacent units in the topology of FIG. 5). The signal line NU is the upper spin (-1 in the Y-axis direction), the signal line NL is the left spin (-1 in the X-axis direction), the signal line NR is the spin on the right (+1 in the X-axis direction), the signal line ND Is an input from the lower spin (+1 in the Y-axis direction), and the signal line NF is a spin (+1 or -1 in the Z-axis direction) connected in the depth direction.

The spin unit 506 determines the next state of spins to minimize energy between adjacent spins, which is a product of the adjacent spins and the interaction coefficient, and a positive value when looking at the external magnetic field coefficient It is equivalent to judging which is the dominant or negative value. For example, the i-th spin sigma _i, as a spin _{σ j, σ k, σ l} , the sigma _m and sigma _n are adjacent, next state of the spin sigma _i is determined as follows.

First, the values of adjacent spins are σ _j = + 1, σ _k = −1, σ _l = + 1, σ _m = −1, σ _n = + 1, and the interaction coefficients are J _{j, i} = + 1, J _{k, i} It is assumed that = + 1, J _{l, i} = + 1, J _{m, i} = -1, J _{n, i} = -1 and the external magnetic field coefficient h _i = + 1. At this time, if the product of the interaction coefficient and the adjacent spin and the external magnetic field coefficient are arranged respectively, then σ _j × J _{j, i} = + 1, σ _k × J _{k, i} = −1, σ _l × J _{l, i} = +1, σ _m × J _{m, i} = +1, σ _n × J _{n, i} = -1, h _i = +1. The external magnetic field coefficient may always be read as an interaction coefficient with a spin having a value of +1.

  Here, the local energy between the i-th spin and the adjacent spin is obtained by multiplying the above-mentioned coefficient by the value of the i-th spin and further inverting the sign. For example, the local energy with the j-th spin is -1 when the i-th spin is +1, and +1 when the i-th spin is -1, so it is better to make the i-th spin +1, It works to reduce the local energy here.

  When such local energy is considered between all adjacent spins and the external magnetic field coefficient, it is calculated which of + 1 / -1 the i-th spin can reduce the energy. This can be done by counting which of +1 and -1 is more in the arrangement of the product of the interaction coefficient and the adjacent spin shown earlier and the external magnetic field coefficient. In the previous example, there are four + 1's and two -1's. Assuming that the ith spin is +1, the sum of energy is -2 and the ith spin is -1, the sum of energy is +2. Therefore, when the number of +1 is large, the next state of the i-th spin is set to +1, and when the number of -1 is large, the next state of the i-th spin is set to -1. The state can be determined.

  Here, the relationship between the interaction operation described above and the circuit block shown in FIG. 6 will be described. First, the memory cell 607 (IU1), the memory cell 609 (IL1), the memory cell 611 (IR1), the memory cell 613 (ID1), the memory cell 615 (the memory cell 607 (IU1) showing the state of adjacent spins and + 1 / -1 of the interaction coefficient. The negation of the exclusive OR with the value held by IF1) is obtained by the XNOR circuit 616. In this way, it is possible to calculate the next state of the spin which minimizes the energy when seeing only the interaction (assuming that +1 is encoded to 1 and -1 to 0).

  If the interaction coefficient is only + 1 / -1, then the majority logic determines in the majority logic whether the + 1 / -1 of the outputs of the XNOR circuit 616 is greater by determining the next state of the spin. Can. Regarding the external magnetic field coefficient, the value of the external magnetic field coefficient is simply the value to be input to the majority logic circuit 618 which determines the next state of the spin, assuming that it always corresponds to the interaction coefficient with the spin of state +1. .

  Next, consider how to realize the coefficient 0. The following proposition can be said to be true when there is an n-input majority logic f (I1, I2, I3,..., In). First, suppose that there are duplicates I'1, I'2, I'3, ..., I 'n of the inputs I1, I2, I3, ..., In (for any k, I k = I' k ). At this time, the output of f (I1, I2, I3, ..., In) is f (I1, I2, I3, ..., In, I'1, I'2, I'3), which is also input together with the duplicate. , ..., I'n). That is, even if two input variables are inserted, the output remains unchanged. Furthermore, in addition to the inputs I1, I2, I3, ..., In, another input Ix and its inverse! Suppose there is Ix. At this time, the output of f (I1, I2, I3, ..., In, Ix,! Ix) is equal to f (I1, I2, I3, ..., In). That is, when an input variable and its inverse are input, the majority rule acts to cancel the influence of the input variable. We use this property of majority logic to realize a coefficient of zero.

  Specifically, as shown in FIG. 6, according to the value of the bit (the bit cells held in bit cells IS0, IU0, IL0, IR0, ID0 and IF0) which determine the enable of the coefficient using XNOR circuit 616, The majority logic circuit 618 simultaneously inputs a duplicate of the candidate value of the next state of the spin described above or its inversion. For example, when the value of the bit held by the memory cell 604 (IS0) is 0, the value obtained by inverting the value of the bit held by the memory cell 605 (IS1) and the value of the bit held by the memory cell 605 (IS1) Are simultaneously input to the majority logic circuit 618, so that there is no influence of the external magnetic field coefficient (the external magnetic field coefficient corresponds to 0). When the value of the bit held by the memory cell 604 (IS0) is 1, the majority logic circuit 618 simultaneously has the value of the bit held by the memory cell 605 (IS1) and the same value (replication) as that value. It will be input.

  Although the energy minimization by the interaction between the spins described above can realize the ground state search of the applied Ising model, this alone may result in a local optimum solution. Basically, there is only movement in the direction of reducing energy, so once it gets into a local optimum it can not get out of it and does not reach a global optimum. Therefore, the spin unit 506 has a random number injection line as an interface to stochastically invert the value of the memory cell 603 expressing spin as a measure to escape from the local optimum solution.

  Then, in the spin unit 506, the RND given to the spin array 405 from the random number generation unit 128 shown in FIG. 2 is connected to this random number injection line, and this RND is input to the inversion logic circuit 619 to obtain the spin value. Is probabilistically inverted.

The individual semiconductor chips 116 realize the interaction for each spin unit 506 by the configuration of FIG. 4, FIG. 5 and FIG. 6 and the respective operations, and the ground state search of Ising model by combining control by RND. To achieve.
<Corresponding to Large-scale and Complex Problems>

  Here, dealing with large-scale and complicated problems will be described with reference to FIGS. 7 to 12. FIGS. 7-8 is a figure which shows the relationship between the problem data represented by Ising model, and a semiconductor chip. FIG. 9 is a view showing an example of mounting of a semiconductor chip. 10 to 12 are diagrams showing an example corresponding to a large scale and complicated problem with a plurality of semiconductor chips.

  For example, in order to construct a semiconductor chip capable of searching for the ground state of a large scale Ising model including a large number of spins, it is necessary to mount unit elements on the semiconductor chip by the number according to the number of spins. Then, as shown in FIG. 7, the number of spins that the semiconductor chip 205 can handle is larger than the size of the Ising model (Problems 201, 202 and 203 indicate spins, and 204 indicates interaction), and the Ising model does not leak It is desirable to be able to map onto a semiconductor chip. However, considering that the problem size of the problem to be solved increases, the semiconductor chip has a large chip size and a high manufacturing cost. Therefore, in order to realize a semiconductor chip capable of coping with the large-scale problem 206, as shown in FIG. 8, a plurality of semiconductor chips 207 and 208 on which a certain number of unit elements are mounted are used. Is desirable.

  Furthermore, in the case where a plurality of identical semiconductor chips are used, for example, as illustrated in the simplest two-dimensional lattice, as shown in FIG. 9, semiconductor chips are tiled in the X direction and Y direction and adjacent semiconductors The chips, for example, the semiconductor chip 701 and the semiconductor chip 702 are connected by wiring. In this case, the connection of the semiconductor chip can be performed in four directions of the chip, data transmission between adjacent chips is possible, and it is possible to solve a large-scale problem by up, down, left, and right chip expansion. However, when solving a more complicated large-scale problem, it is necessary to cope with the complexity of the extension method accordingly. Referring to FIG. 9, a corresponding example in the case where the problem is complicated will be described based on chip 1, for example, not only chip 2 and chip 5 which are adjacent but also chip 3 and chip 4 which are not adjacent, Build connections to chip 6, ..., chip 12.

  Usually, when adjacent chips are connected, the outer peripheries (boundary portions) of the respective chips are connected to each other. On the other hand, connection of the spin 803 and the spin 804 other than the outer periphery of the chips 801 and 802 shown in FIG. 10 is considered. Specifically, as shown in FIG. 11, the state of the spin 805 (spin 803 = spin 804) is realized by overwriting the spin 804 with the value of the spin 803. This makes it possible to add a connection by spin 805 to the connection between the outer peripheries of ordinary chips. Further, as shown in FIG. 12, it is considered to connect not only the adjacent chips 801 and 802 but also the chip 807 separated in mounting. Specifically, the spin 809 on the chip 807 is overwritten with the value of the spin 808 on the chip 801. Thus, not only expansion of the adjacent chips 801 and 802 but also expansion of non-adjacent chips 801 and 807 is realized. In FIG. 12, reference numeral 806 denotes connection between the outer peripheries of the adjacent chips 801 and 802.

  The present embodiment has been made to realize the above contents, and proposes a semiconductor system which can search for the ground state of a large-scale complex Ising model and which can be manufactured inexpensively and easily. . In order to realize such a semiconductor system, it has a controller 106 which develops parameters representing the Ising model in a plurality of semiconductor chips and controls data transmission between the semiconductor chips, and a single Ising model with a plurality of semiconductor chips. Perform a ground state search of

As a result, in the Ising model exceeding the size that can be solved by one semiconductor chip, the controller 106 generates spin values that constitute the Ising model with respect to the storage elements of the array structure built in each of the semiconductor chips. Write and expand the interaction coefficient and external magnetic field coefficient associated with the spin. Further, the controller 106 recovers the value of spin, which is the result of the ground state search of the Ising model, by reading out the values stored in the storage elements of the array structure built in each of the semiconductor chips. In addition, the controller 106 enables transmission of the recovered spin value to a chip different from the chip from which it is recovered, for example, not adjacent in mounting, to search for the ground state of a single Ising model with a plurality of semiconductor chips. Conduct.
<Details of controller>

  Next, the controller 106 will be described in detail with reference to FIGS. 13 to 17. FIG. 13 is a diagram summarizing an example of the relationship between the address of the spin data storage unit 112, the chip number of the expansion destination, and the local address. FIG. 14 is a diagram showing an example in the case of defining connections between chips. FIG. 15 to FIG. 16 are block diagrams showing an example of the configuration of the adjacent inter-chip connection unit. FIG. 17 is a diagram showing an example of a flowchart of the entire operation by the controller 106.

  First, the controller 106 develops each data stored in the problem data storage unit 111 and the spin data storage unit 112 in a plurality of semiconductor chips 116 via the data processing unit 109.

  FIG. 13 illustrates an example in which transmission of problem data and spin data is realized for each of a plurality of semiconductor chip groups 115 installed from the controller 106. First, data stored in the storage device 103 is sequentially transferred from the address 0x00000 to the problem data storage unit 111 and the spin data storage unit 112. The size of the problem data is set by the problem setting register 118 included in the register 108, and the size that each semiconductor chip can handle is set by the chip specification setting register 121. In FIG. 13, in order to simplify the description, the problem setting register 118 defines the problem size in the X direction and the Y direction on the assumption that the problem is a two-dimensional lattice configuration, for example, 512 (X direction) dec), the Y direction is 80 (dec). Further, the chip specification setting register 121 also defines the spin array size in the X direction and the Y direction. For example, the X direction is 256 (dec) and the Y direction is 80 (dec). In this case, if the chip number setting register 120 is set to 2, two chips can be aligned in the X direction without failure and a single problem can be solved.

  First, focusing on the addresses used by the problem data storage unit 111 and the spin data storage unit 112, the problem data and the spin data consist of 40,960 (= 512 × 80), and are shown in the data column and the address column of FIG. Thus, each data is given the address 0x00000 to 0x09FFF. When this address is divided by the setting value 512 (dec) of the problem size and then +1, the solution corresponds to the number of lines in the Y direction of the data, and the remainder corresponds to the position in the X direction. Further, by dividing the above-mentioned remainder value by the setting value 256 (dec) of the spin array size in the X direction and adding +1, a chip number (one of 1 and 2) when arranged in the X direction can be derived. Referring to FIG. 13, when the address 0x001FF (hex) corresponding to the 512th data is divided by 512 (dec) and then +1, the solution is 1 and the remainder +1 becomes 512 (dec). Thus, it can be seen that the 512th data is data corresponding to the 512th spin unit in the X direction in the first line in the graph problem. Further, when 512 (dec) which is the remainder + 1 is divided by the set value 256 (dec) in the X direction of the spin array size, the solution becomes 2 and it can be seen that the data is the data developed on the chip 2.

  By these processes, the data processing unit 109 can assign a chip number to the spin data stored in the spin data storage unit 112. If the relationship between the address of the spin data storage unit 112 and the chip number of the distribution destination can be clarified, the spin value of an arbitrary address in the spin data storage unit 112 can be overwritten with the spin value of another arbitrary address. That is, the connection on the graph problem can be implemented only by addressing on the spin data storage unit 112.

  In FIG. 14, the transmission table is created on the premise that the spin value of an arbitrary address in the spin data storage unit 112 is overwritten with the spin value of another arbitrary address in relation to the operation of the inter-chip connection unit 122. An example of the case is shown. For example, if the 257th data (address 0x00100) in the spin data storage unit is selected as the read side, and the 40449th data (address 0x9E00) is selected as the write side, the chip number and the local address are selected by the data processing unit 109. It is shown that the 257th data, which is the result of calculation assigned to chip number 2, can be reflected in the 40449th data assigned to chip number 1, after transmission and reception after conversion to . If R (read) / W (write) settings and address settings are arbitrarily combined, various data transmissions become possible.

  In the present embodiment, the method of performing data transmission between non-adjacent chips has been described on the premise of creating a transmission table, but the problem of a single model using a plurality of semiconductor chips is described. When the connection processing is performed via the controller in the case of solving, the detailed processing method may be different.

  Further, although two chips are provided in the example of FIGS. 13 and 14, two or more chips can be supported, and spin data can be transmitted via the controller 106 even between chips separated in mounting. The calculation result of the transmission source semiconductor chip 116 can be reflected in the calculation of the transmission destination semiconductor chip 116. In the present embodiment, the method of distributing calculation data has been described by taking the simplest example, but if data transmission via the controller, which is a feature of the present embodiment, is realized, the distribution rule Is not limited to this.

  Next, the entire operation will be described using the flowchart of FIG. 17 on the premise of the configuration described above. The flowchart shown in FIG. 17 sets the spin value to an arbitrary initial value and shows the process until one ground state search is completed, and the number of calculation steps per ground state search is N times. Further, it is assumed that the data transmission cycle between chips described above is defined by P, and P can be set in calculation step units.

  First, it receives from the outside, the initial value of the spin value is set in the spin data storage unit 112 in the controller 106, and the count value n of the calculation step is set to "0" (S1, S2). Next, the spin value is developed from the spin data storage unit 112 to the semiconductor chip group 115 (S3). Then, the spin value developed on the semiconductor chip 116 is updated by executing the majority logic circuit described in FIG. 6, and when the count value n of the calculation step reaches N while being counted up, It is determined that one ground state search has ended (S4 to S7). The period from S4 to S7 is referred to herein as a search period by the semiconductor chip operation. In the search period, when one ground state search is completed, spin values are collected from the semiconductor chip group 115 and counted (S8).

  Among them, when the count value n of the calculation step reaches a multiple of the data transmission period P, the ground state search is temporarily interrupted, and the controller 106 carries out an inter-chip connection process. The period of the inter-chip connection process is referred to herein as a chip expansion period by the controller process. Specifically, when the count value n in the calculation step reaches a multiple of the data transmission cycle P, the controller 106 recovers the spin value from the semiconductor chip group 115, and overwrites the value of the spin data storage unit 112 with that value. (S9, S10). Then, the inter-chip connection unit 122 executes the data processing for chip connection described in FIG. 14 (S11). As a result, processing is performed as if the chips are not adjacent to each other, and the spin data after processing is developed again into the semiconductor chip group 115. After expansion, in the semiconductor chip 116, the calculation operation from another chip can be partially reflected and restarted by restarting each search operation.

  As described above, during the ground state search of the Ising model, all the ground state search results stored in the spin data storage unit 112 may be calculated for each ground state search calculation step or each calculation step. The search period to be updated and the part of the result of the ground state search stored in the spin data storage unit 112 are included in the spin data storage unit 112 for each calculation step of the ground state search or for each of a plurality of calculation steps. And a chip expansion period that is rewritten to another partial value.

  Further, an interval for updating the result of the ground state search in the search period and an interval at which the partial result of the ground state search in the chip extension period is rewritten are expressed in the calculation step of the ground state search. It is adjustable from In this case, a register may be provided to set each interval.

  When a plurality of semiconductor chips 116 are set, the plurality of semiconductor chips 116 are wired to set a wire transmission period for transmitting the result of the ground state search, and at the time of the chip extension period implemented by the controller 106. Rewrite the result of the ground state search.

  On the other hand, adjacent semiconductor chips such as the chip 1 and the chip 2 in FIG. 9 or the chip 1 and the chip 5 may transmit spin data between the chips without the intervention of the controller 106.

  For example, as shown in FIG. 15, paying attention to the connecting portion in the case of connecting the adjacent chip 801 and the chip 802, when the number of spins 1101 and 1102 at the boundary is n, the spins If it is 1 bit, it is desirable to draw n bits to the data transmission / reception unit (pad) 1103 and the data transmission / reception unit (pad) 1104 and connect them seamlessly. Therefore, when the bit width n of the boundary portion is small, the connection method shown in FIG. 15 is employed.

  However, it is known that if the seamless connection is performed under the condition that the number of spins 1101 and 1102 at the boundary is large, the number of pads increases and the wiring area becomes large, and the chip cost and the mounting cost increase. In addition, it is known that the semiconductor chip premised in this embodiment is not a von Neumann computer but a non-Neumann type, and a connection which is spatially or temporally thinned is acceptable. Therefore, a block configuration as shown in FIG. 16 is adopted to realize a transmission width of m bits (m <n) and reduce the number of connections.

  Here, the configuration of FIG. 16 for reducing the number of connections between chips will be described. In FIG. 16, 1101 and 1102 are spins at the boundary, 1105 is a data reading unit of the chip 801, 1106 is a transmission buffer of the chip 801, 1107 is a transmitting unit of the chip 801, 1108 is a receiving unit of the chip 802, 1109 11 is a data reading unit of the chip 802, 1111 is a data reading unit of the chip 802, 1112 is a transmission buffer of the chip 802, 1113 is a transmitting unit of the chip 802, 1114 is a receiving unit of the chip 801, Reference numeral 1115 denotes a data development unit of the chip 801, and 1116 denotes a latch circuit of the chip 801.

  The data read unit 1105 of the chip 801 reads the value of spin in the boundary region from the spin array 405 and transmits it to the transmission buffer 1106 every m bits. The transmission buffer 1106 transmits m-bit spin data to the data expanding unit 1109 of the chip 802 through the transmitting unit 1107 of the chip 801 and the receiving unit 1108 of the chip 802 which is an adjacent chip. The data developing unit 1109 develops the input spin data in the latch circuit 1110 while shifting the input spin data by m bits. Thereby, transmission of spin data from the chip 801 to the chip 802 is realized.

  Transmission of spin data from the chip 802 to the chip 801 is realized by installing circuits of connection portions in pairs of two systems. However, the number of pads may be reduced by performing data transmission in a time division manner so that the transmitting unit (pad) and the receiving unit (pad) are shared, and bidirectional buffering operations do not collide. Although the lattice-like spin model has been described on the premise of expansion in the X direction, in order to realize expansion in the Y direction or the like, a plurality of corresponding connection parts may be provided.

  The data transmission via the controller 106 described in the first half of the present embodiment enables data transmission in non-adjacent chips, for example, the chip 1 and the chip 3 etc. in FIG. It is desirable to combine data transmission between adjacent chips as described. Further, data transmission of spin values inside the boundary region as shown in FIGS. 10 to 12 is also enabled between adjacent chips by the controller 106, and the data between adjacent chips described in FIGS. Transmission may be combined. Of course, data transmission between all the chips may be performed via the controller 106 without using the wiring connection between the chips.

  Also, although the description has been made on the premise of the Ising model, other interaction models such as neural networks may be applied.

According to the first embodiment described above, it is possible to realize an inexpensive and easily manufacturable semiconductor system that can calculate large-scale and complex interaction models such as Ising model, for example. it can.
Second Embodiment

  The second embodiment is characterized in that, with respect to the first embodiment, the transmission specification is controlled in consideration of the accuracy and quality required for data transmission between chips. In the second embodiment, differences from the first embodiment will be mainly described.

  The present embodiment focuses on the fact that there is no need to always have high precision and no missing data, particularly in ground state search calculation of semiconductor chips and the like. In particular, in a block where RND is referred to in order to escape from the local optimum solution, control is performed to intentionally invert the calculation result in a region where the calculation step is small, and it is considered that accurate data transmission is not necessary. From this, in the area where the calculation step is small, data transmission is simplified, current consumption generated along with transmission is reduced, occupation of the bus and network by data transmission is suppressed, and other processes are performed without delay. Contribute to implementation.

  FIGS. 18 to 19 are diagrams for explaining the second embodiment, and FIG. 18 is a diagram showing an example of energy transition at each calculation step, which is premised in the present embodiment. FIG. 19 is a diagram showing an example of switching of data transmission specifications in the present embodiment. For example, as the calculation step of ground state search progresses, control specifications for performing rewriting of a part of results of ground state search in the chip expansion period and control of transmitting the ground state search results by wiring between a plurality of semiconductor chips Change the specifications or any of the control specifications. In the control of changing this specification, a plurality of calculation steps set at the change point of the control specification or an interval between calculation steps can be adjusted from the outside.

  FIG. 18 shows the energy transition in the case of performing the ground state search calculation, and 1301 is an example of the result of plotting with the calculation step on the horizontal axis and the energy on the vertical axis. The result 1301 that energy drops at a particular calculation step corresponds to the update of the temperature parameter in the ground state search calculation. In the semiconductor chip, the temperature parameter is expressed by the inversion probability by RND, and as the calculation step proceeds, the inversion probability by the RND of the spin value is lowered. Here, in the region where the calculation step is small, this embodiment focused on the fact that only the solution search with a high accuracy was performed with a high inversion probability of the spin value mainly for the purpose of escaping from the local optimum solution. In the form of Specifically, the specification of data transmission is changed in accordance with the range 1302, the range 1303, the range 1304, the range 1305, and the range 1306 of calculation steps.

  In FIG. 19, the data transmission clock frequency, the data transmission cycle, the data transmission compression rate, and the number of transmission bits are listed in a table as an example of the parameters for changing the data transmission specification in accordance with the calculation step. .

  The frequency of the data transmission clock (clock 3 shown in FIG. 2) is set to, for example, 10 MHz in the range 1302 where the calculation step is small, and the calculation step becomes higher as the range 1303, range 1304, range 1305, and range 1306 progress. In the range 1306, the frequency is set to 100 MHz. As a result, in the range 1306 in which accuracy is required, it is possible to reduce the time allocated to data transmission and allocate the reduced time to the calculation time.

  The data transmission period is, for example, data transmission every 16 steps in the range 1302 where the calculation step is small, and the data transmission interval is shortened as the calculation step proceeds to the range 1303, the range 1304, the range 1305, and the range 1306. This content corresponds to shortening of the inter-chip connection period P in the flowchart shown in FIG. Then, in the range 1306, if setting is made for each step, the update frequency of the calculation result of the connection source is set for each calculation step, and calculation can be performed under the condition that seamless connection is made.

  For the transmission data compression rate, in the range 1302 where the calculation step is small, for example, the data compression rate is increased to 1/10 to reduce the number of data, and the calculation step proceeds with the range 1303, range 1304, range 1305, range 1306 Lower the compression ratio and set it to 1 in the range 1306.

  In the range 1302 where the number of calculation steps is small, for example, the number of bits is reduced to 1 bit, and the number of bits is increased as the calculation step proceeds to the range 1303, range 1304, range 1305, range 1306, range 1306 Is set to 8 bits.

  The specifications and numerical values of the present embodiment shown in FIG. 19 are an example. The contents of specification and the numerical values may be different as long as the parameter in the ground state search calculation is common in that the parameter is changed at each calculation step.

According to the second embodiment described above, as an effect different from that of the first embodiment, data transmission is simplified in a region where the calculation step is small, and reduction of current consumption generated along with transmission is achieved. At the same time, it is possible to suppress the occupation of the bus and the network by data transmission and to carry out other processing smoothly.
Third Embodiment

  The third embodiment is characterized in that the controller and the plurality of semiconductor chips are connected by a bus, with respect to the first embodiment. In the third embodiment, differences from the first and second embodiments will be mainly described.

  FIG. 20 is a diagram for explaining the third embodiment, and is a block diagram showing an example of the configuration of the semiconductor system 104. As shown in FIG. In the semiconductor system 104 shown in FIG. 20, the controller 106 and the plurality of semiconductor chips 1402 are not connected to the switch, but are connected to the dedicated bus 1401 and do not require the switch.

  The second embodiment is the same as the first embodiment except that it is a bus connection. Therefore, the detailed explanation is omitted. Also, based on the block configuration of the present embodiment, the second embodiment may be applied to control the data transmission specification between chips.

According to the third embodiment described above, as an effect different from the first embodiment, the semiconductor system 104 can be configured by connecting the controller 106 and the plurality of semiconductor chips 1402 by the dedicated bus 1401. . As a result, the same effects as those of the first and second embodiments can be obtained.
Fourth Embodiment

  The fourth embodiment differs from the first, second, and third embodiments, and can calculate large-scale and complex interaction models such as Ising model, for example, and is inexpensive and easy. To a computer system that can be manufactured.

  FIG. 21 is a diagram for explaining the fourth embodiment, and is a block diagram showing an example of the overall configuration of a network system including a computing system. In the network system shown in FIG. 21, 1501 denotes a host, 1502 denotes a semiconductor system group, 1503 denotes a plurality of semiconductor systems constituting the semiconductor system group, and 1504 denotes a network. The present embodiment solves a large-scale single problem by performing data transmission between the host 1501 and each semiconductor system 1503 via the network 1504 when the semiconductor system 1503 is mounted on a different computer. Make it possible. The semiconductor system 1503 includes the same configuration as that of the first embodiment.

  Consider a case where there are a plurality of semiconductor systems 1503 shown in FIG. 21 and each is connected to a LAN. When performing ground state search of the Ising model that can not be solved by a plurality of semiconductor systems mounted on a single semiconductor system 1503, calculation resources are shared via the LAN, and the host 1501 develops the problem data And carry out data transmission. If expansion of problem data and data transmission between semiconductor systems are enabled, larger scale problems can be solved by the ground state search calculation method described in the first to third embodiments.

  Further, when the host 1501 is a notebook PC or a mobile device, data transmission is realized by connection with a line such as a wireless LAN to solve a large scale problem. For example, a mobile device issues a command to solve a problem, and a plurality of semiconductor systems 1503 present at remote locations receive the command. Then, an optimum value is derived from the result of performing the ground state search of the Ising model on the semiconductor system 1503, and transmitted to the mobile device. This makes it possible to refer to the result of solving the problem using a semiconductor system on a notebook PC or on a mobile device if it is a small-scale problem.

  According to the fourth embodiment described above, in the configuration different from the first to third embodiments, the same effect as the first to third embodiments can be obtained.

  As mentioned above, although the invention made by the present inventor was concretely explained based on the embodiment, the present invention is not limited to the embodiment, and can be variously changed in the range which does not deviate from the summary. Needless to say.

  For example, the above-described embodiment is described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to one having all the described configurations. Also, part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, with respect to a part of the configuration of each embodiment, it is possible to add, delete, and replace other configurations.

  In the above-described embodiment, although the Ising model representative in the world of physics has been described as an example, the present invention is not limited to this and various physical phenomena and social phenomena are expressed. It can be applied to all possible interaction models. In addition, although a semiconductor chip has been described as an example of an apparatus for performing base search of the Ising model, the present invention is not limited to this and can be applied to all apparatuses performing the same operation.

101 ... CPU, 102 ... memory, 103 ... storage device, 104 ... semiconductor system, 105 ... system bus, 106 ... controller, 107 ... system I / F, 108 ... register, 109 ... data processing unit, 110 ... clock generation unit, 111 problem data storage unit 112 spin data storage unit 113 data I / F 114 switch 115 semiconductor chip group 116 semiconductor chip 117 interchip wiring 118 problem setting register 120 Chip number setting register, 121: chip specification setting register, 122: inter-chip connection unit, 123: address generation unit, 124: data generation unit, 125: expansion unit, 126: data aggregation unit, 127: interaction control signal generation unit , 128 ... random number generator,
401 ... I / F, 402 ... inter-chip transmission I / F, 403 ... register, 404 ... memory controller, 405 ... spin array, 406 ... interaction I / F, 407 ... interaction address decoder, 408 ... inter-chip transmission unit Controller, 409: boundary spin control unit, 410: transmission buffer, 411: reception buffer,
1401: dedicated bus, 1402: semiconductor chip,
1501 ... host, 1502 ... semiconductor system group, 1503 ... semiconductor system, 1504 ... network.

Claims (4)

A semiconductor system comprising: a plurality of semiconductor chips; and a controller connected to the plurality of semiconductor chips,
Each of the plurality of semiconductor chips includes: a first memory in which the value of each node of the problem data represented by the interaction model in which processing is executed by interaction among the plurality of nodes; A plurality of units each including a second memory in which coefficients related to each node are stored, and an arithmetic circuit that updates the value of each node stored in the first memory,
The controller
A third memory in which the value of each node of the problem data to be processed is stored;
A fourth memory storing coefficients related to each node of the problem data to be processed;
A register for setting the size of problem data to be processed, the number of chips of the semiconductor chip to be controlled, and the size of problem data that can be processed by one chip;
An address generation unit configured to set correspondence between the addresses of the third and fourth memories and the respective addresses of the plurality of semiconductor chips based on the setting value of the register;
A data expansion unit for transmitting the values of the nodes and the coefficients stored in the third and fourth memories to the plurality of semiconductor chips based on the correspondence relationship;
A data totaling unit that receives the value of each node stored in the first memory of the plurality of semiconductor chips, and stores the value in the third memory based on the correspondence relationship ;
Bei to give a,
The controller
A table showing the correspondence between the first address and the second address of the third memory;
An inter-chip connection unit which refers to the table and writes a value read from the first address to the second address;
Equipped with
After execution of the transmission process of the data expansion unit, arithmetic processing is performed on the plurality of semiconductor chips, and after execution of the arithmetic process, aggregation processing of the data aggregation unit is performed.
After execution of the aggregation process of the data aggregation unit, reception and write processing by the inter-chip connection unit are executed, and after the execution of the write operation, the transmission process, the arithmetic process, and the aggregation process are executed.
The tallying process, the receiving and writing process, and the transmission process are repeatedly executed in a predetermined cycle.
The predetermined cycle is set to be gradually shorter,
Semiconductor system. The semiconductor system according to claim 1,
The semiconductor system, wherein the interaction model is an Ising model, the value of each of the nodes is a spin value, and the coefficient includes an interaction coefficient and an external magnetic field coefficient. A method of calculating a semiconductor system, comprising: a plurality of semiconductor chips; and a controller connected to the plurality of semiconductor chips,
Each of the plurality of semiconductor chips includes: a first memory in which the value of each node of the problem data represented by the interaction model in which processing is executed by interaction among the plurality of nodes; A plurality of units each including a second memory in which coefficients related to each node are stored, and an arithmetic circuit that updates the value of each node stored in the first memory,
The controller is a third memory in which the value of each node of the problem data to be processed is stored, a fourth memory in which a coefficient related to each node of the problem data to be processed is stored, and the processing object A register for setting the size of problem data to be processed, the number of semiconductor chips to be controlled, and the size of problem data that can be processed by one chip, an address generation unit, a data expansion unit, and a data aggregation unit Equipped with
The address generation unit sets the correspondence between the addresses of the third and fourth memories and the addresses of the plurality of semiconductor chips based on the set value of the register.
The data expansion unit transmits the values of the nodes and the coefficients stored in the third and fourth memories to the plurality of semiconductor chips based on the correspondence relationship.
The data tabulation unit, the stored plurality of the first memory of the semiconductor chip receiving said value of each node, and stores into said third memory based on the correspondence relation,
The controller includes a table indicating a correspondence between a first address and a second address of the third memory, and an inter-chip connection unit.
The inter-chip connection unit refers to the table and writes a value read from the first address to the second address;
After execution of the transmission processing of the data expansion unit, arithmetic processing is performed on the plurality of semiconductor chips, and after execution of the arithmetic processing, aggregation processing of the data aggregation unit is performed.
After execution of the aggregation process of the data aggregation unit, the reception and write process by the inter-chip connection unit are executed, and after the execution of the write process, the transmission process, the arithmetic process, and the aggregation process are executed.
Repeatedly executing the counting process, the receiving and writing process, and the transmission process in a predetermined cycle;
The predetermined cycle is set to be gradually shorter,
Method of calculation. The calculation method according to claim 3 , wherein
The calculation method, wherein the interaction model is an Ising model, the value of each of the nodes is a spin value, and the coefficient includes an interaction coefficient and an external magnetic field coefficient.

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