JP6498868B2 - Data transmitter, data communication system, data transmission method, and data transmission program - Google Patents

Description

  The present invention relates to a data transmitter, a data receiver, a data communication system, a data transmission method, and a data transmission program that perform communication using a frequency hopping technique.

  For the purpose of increasing the confidentiality of communication between communication devices, a frequency hopping technique for switching the frequency of a radio wave used for communication at a predetermined time interval is employed. In a communication system employing frequency hopping, the transmission side transmits a signal by switching the carrier frequency at an extremely short time interval such as 2.5 milliseconds or 4 milliseconds. The receiving side switches the received carrier frequency in accordance with the frequency switching timing of the transmitting side (synchronizes), and receives the transmitted signal.

  In a communication system employing frequency hopping, a transmitter-side modulator that modulates a carrier wave and a receiver-side demodulator that demodulates the modulated carrier wave are generally configured by dedicated hardware, respectively. .

  In the method described in Patent Document 1, the transmission side modulates a carrier wave with data including a predetermined synchronization word, packetizes and transmits the data. Then, the reception side detects the start position of the payload or the like based on the synchronization word included in the data obtained by demodulating the received packet.

  In the method described in Patent Document 2, a frame synchronization position is specified based on a notification signal and a synchronization word transmitted at a predetermined data interval.

JP 2001-45012 A JP 2004-153893 A

  However, when the transmitter-side modulator and the receiver-side demodulator are configured with dedicated hardware, both perform only predetermined operations, so that other than predetermined types of modulation schemes and frames. I can't respond.

  In the method described in Patent Document 1, each process on the transmission side and the reception side is performed for each bit. In the method described in Patent Document 2, each process is performed in a DSP (Digital Signal Processor) in accordance with data sampled based on a predetermined clock frequency.

  However, there is a problem that the processing efficiency is low when each processing is performed for each small unit of data sampled based on the bit or clock frequency. If the processing efficiency is low, the modulator on the transmission side and the demodulator on the reception side must be configured with dedicated hardware, and it is not possible to support other than a predetermined type of modulation scheme and frame.

  Therefore, the present invention provides a data transmitter, a data receiver, a data communication system, a data transmission method, and a data transmission program capable of synchronizing a transmission side and a reception side communicating with frequency hopping with high processing efficiency. For the purpose.

  A data transmitter according to the present invention includes a packet unit processing unit that generates a baseband signal by performing a predetermined sampling process in units of a predetermined packet based on input digital data, and a baseband generated by the packet unit processing unit. Output signal generating means for generating an output signal based on the signal, and transmission means for transmitting the output signal generated by the output signal generating means by frequency hopping at a predetermined timing. The packet unit processing means includes: Including frame adding means for adding predetermined frame data before the input digital data so that frequency hopping of the output signal is started at a predetermined timing, and the predetermined frame data is added by the frame adding means Predetermined sampling processing is applied to digital data in units of predetermined packets It is characterized in.

  A data receiver according to the present invention includes a receiving unit that performs reception processing of a radio wave whose frequency hopping starts at a predetermined timing, and digital data generation that performs digital data generation processing based on a received signal by reception processing in units of a predetermined packet. Means, frequency switching calculating means for calculating the timing at which frequency hopping is started based on predetermined data included in the digital data, and frequency hopping is started based on the timing calculated by the frequency switching calculating means. Frequency switching means for causing the reception means to perform reception processing of the received radio wave.

  A data communication system according to the present invention includes a data transmitter according to any aspect, a reception unit that performs reception processing of radio waves based on an output signal transmitted by the data transmitter, in which frequency hopping is started at a predetermined timing, and reception processing Digital data generation means for performing digital data generation processing based on a received signal by a predetermined packet unit, and frequency switching calculation for calculating timing at which frequency hopping is started based on predetermined data included in the digital data And a data receiver comprising: frequency switching means for causing the reception means to perform reception processing of a radio wave for which frequency hopping has been started based on the timing calculated by the frequency switching calculation means It is characterized by.

  A data transmission method according to the present invention includes a packet unit processing step for generating a baseband signal by performing a predetermined sampling process in a predetermined packet unit based on input digital data, and a baseband generated in the packet unit processing step. An output signal generation step for generating an output signal based on the signal, and a transmission step for transmitting the output signal generated in the output signal generation step by frequency hopping at a predetermined timing. Predetermined frame data is added to the input digital data so that frequency hopping of the output signal is started at a predetermined timing, and predetermined digital data is added to the digital data to which the predetermined frame data is added. The sampling process of To.

  The data transmission program according to the present invention includes a packet unit process for generating a baseband signal by performing a predetermined sampling process in a predetermined packet unit based on digital data input to a computer, and a base unit generated by the packet unit process. An output signal generation process for generating an output signal based on a band signal and a transmission process for transmitting the output signal generated by the output signal generation process by frequency hopping at a predetermined timing are executed. The frame adding process for adding predetermined frame data to the input digital data is executed so that the frequency hopping of the output signal is started at a predetermined timing in the frame. Predetermined packet unit for the added digital data And characterized in that subjected to a predetermined sampling process.

  ADVANTAGE OF THE INVENTION According to this invention, the transmission side and reception side which communicate by frequency hopping can be synchronized with high processing efficiency.

It is a block diagram which shows the structural example of the communication system of the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the transmission side communication apparatus. It is explanatory drawing which shows the structure of the bit data by which frame data was added to user data by the frame addition part. It is a flowchart which shows operation | movement of the receiving side communication apparatus. It is explanatory drawing which shows the processing result of the received signal in a receiving side communication apparatus. It is a block diagram which shows the structural example of the data transmitter of the 2nd Embodiment of this invention.

Embodiment 1. FIG.
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of a communication system according to the first embodiment of this invention. As shown in FIG. 1, the communication system 100 of the present embodiment includes a transmission side communication device 200 and a reception side communication device 300.

  The transmission-side communication device 200 includes a DSP 210 and a field-programmable gate array (FPGA) 220 that execute processing according to program control, a storage unit 230, and a communication unit 240. The DSP 210 includes a frame addition unit 211, a bit-symbol conversion unit 212, a band limiting filter unit 213, an upsampler unit 214, and a frequency setting unit 215, and is in a predetermined packet unit that is a unit of data of a predetermined size. Processes input user data. The FPGA 220 includes an orthogonal modulation unit 221 and a frequency switching timing generation unit 222. The communication unit 240 includes an analog transmission unit 241 that transmits an output signal via the antenna 243, and a frequency switching unit 242 that causes the analog transmission unit 241 to switch the transmission frequency of the output signal.

  In the transmission-side communication device 200, the frame adding unit 211 adds predetermined frame data to user data input by the user. The bit-symbol conversion unit 212 generates a baseband signal obtained by converting bit data obtained by adding frame data to user data into symbol data, and inputs the baseband signal to the band limiting filter unit 213. The baseband signal has an I (In-phase) component and a Q (Quadrature) component that are orthogonal to each other, and is orthogonally modulated by the orthogonal modulation unit 221 after passing through the band limiting filter unit 213 and the upsampler unit 214. Then, the quadrature modulation unit 221 generates, for example, a 16QAM (Quadrature Amplitude Modulation) signal based on the baseband signal that has passed through the upsampler unit 214.

  Further, the storage unit 230 stores frequencies used in frequency hopping in a table format in an order corresponding to a predetermined hopping pattern. The frequency setting unit 215 determines the transmission frequency of the output signal transmitted from the transmission-side communication device 200 based on the table stored in the storage unit 230. That is, the frequency setting unit 215 determines the transmission frequency of the output signal based on a predetermined hopping pattern, for example. The frequency switching timing generation unit 222 inputs frequency information indicating the transmission frequency determined by the frequency setting unit 215 to the frequency switching unit 242 at a timing based on the timing at which the frame adding unit 211 adds the frame data to the user data.

  When the frequency switching timing generation unit 222 receives frequency information, the frequency switching unit 242 switches the transmission frequency of the output signal transmitted by the analog transmission unit 241 to the frequency indicated by the frequency information, and performs frequency hopping. .

The receiving-side communication device 300 includes a DSP 310 and an FPGA 320 that execute processing according to program control, and a communication unit 340. The communication unit 340 includes an analog reception unit 341 that receives the transmitted output signal via the antenna 343, and a frequency switching unit 342 that causes the analog reception unit 341 to switch the frequency of the received signal to be received. The FPGA 320 includes an orthogonal demodulation unit 321 and a frequency switching timing generation unit 322. The DSP 310 includes a band limiting filter unit 311, a symbol timing detection unit 312, a symbol-bit conversion unit 313, a frame removal unit 314, a synchronization word detection unit 315, and a frequency switching timing calculation unit 316. The input signal is processed in units of a predetermined packet.
The predetermined packet unit that is a processing unit in the DSP 310 may have the same data size as the predetermined packet unit that is the processing unit of the DSP 210, or may have a different data size.

  In the reception-side communication device 300, the analog output unit 341 receives the transmitted output signal via the antenna 343, and inputs the received signal to the orthogonal demodulation unit 321. The orthogonal demodulator 321 generates a baseband signal having an I component and a Q component based on the input received signal and inputs the baseband signal to the band limiting filter unit 311. The band limiting filter unit 311 is realized by, for example, the DSP 310 that operates as a low-pass filter such as a root Nyquist filter that allows a signal having a frequency of several kHz to several tens of kHz or less to pass according to program control.

  The signal that has passed through the band limiting filter unit 311 is input to the symbol-bit conversion unit 313 via the symbol timing detection unit 312 and converted into bit data. The bit data is output after the frame data is removed by the frame removal unit 314. The bit data is also input to the synchronization word detector 315 to detect a synchronization word included in the frame data. The frequency switching timing calculation unit 316 calculates a timing for switching the frequency of the reception signal received by the analog reception unit 341 based on the synchronization word detected by the synchronization word detection unit 315. The frequency switching timing generation unit 322 instructs the frequency switching unit 342 on the frequency switching timing based on the timing calculated by the frequency switching timing calculation unit 316. The frequency switching unit 342 causes the analog reception unit 341 to switch the reception frequency in response to an instruction from the frequency switching timing generation unit 322.

  Note that the receiving-side communication device 300 includes, for example, a storage unit (not shown) in which frequencies used in frequency hopping are stored in a table format in an order corresponding to a predetermined hopping pattern. Then, for example, the frequency switching unit 342 reads the frequency stored in the storage unit, and causes the analog reception unit 341 to switch the reception frequency to the read frequency.

  Next, the operation of the communication system 100 according to the first embodiment of this invention will be described. First, the operation of the transmission side communication device 200 will be described. FIG. 2 is a flowchart showing the operation of the transmission side communication device 200. As shown in FIG. 2, when user data is input, the transmission side communication device 200 performs a process in which the frame adding unit 211 of the DSP 210 adds frame data in units of packets to the head of the user data (step S101). .

  Specifically, for example, when the frame data is composed of four packets, in step S101, the process of adding the frame data to the user data is performed four times. On the other hand, for example, when the frame data is divided into several tens of frames and is added to the user data sequentially at the sampling timing based on a predetermined sampling frequency, the frame data is added to the user data. The process is performed several tens of times. Therefore, according to the present embodiment, the number of times of processing can be reduced as compared with the case where frame data is added at the timing of sampling based on a predetermined sampling frequency. Therefore, the processing load on the DSP 210 can be reduced well. Since each process described below in the DSP 210 is also performed in units of packets, the processing load on the DSP 210 can be reduced well.

  FIG. 3 is an explanatory diagram showing a configuration of bit data in which frame data is added to user data by the frame adding unit 211. As shown in FIG. 3, the frame adding unit 211 adds frame data including a preamble, a synchronization word, and synchronization data to the head of user data. Further, the frame adding unit 211 divides user data in predetermined data units, and inserts guard bits indicated by “G” in FIG. 3 between the divided user data and frame data.

  The synchronization word is information indicating that frequency hopping is started, for example. The synchronization data is, for example, data having a predetermined length for setting the head of user data at a predetermined position.

  In this embodiment, frequency hopping is started when user data transmission is started after frame data is transmitted. Then, frequency hopping is performed at the timing at which each guard bit between user data divided in predetermined data units is transmitted.

  When the frame addition unit 211 of the DSP 210 adds the frame data to the head of the user data, the frame addition unit 211 notifies the frequency switching timing generation unit 222 of the FPGA 220 to that effect.

  The bit-symbol conversion unit 212 performs a process of converting the bit data in which the frame data is added to the user data by the frame addition unit 211 in the process of step S101 into symbol data (step S102), and converts the baseband signal into Generate. Then, the bit-symbol conversion unit 212 inputs a baseband signal having an I component and a Q component orthogonal to each other to the band limiting filter unit 213 in units of packets. The I component in the baseband signal is also referred to as an I signal, and the Q component in the baseband signal is also referred to as a Q signal.

  The band limiting filter unit 213 is realized by the DSP 210 that operates as a low-pass filter such as a root Nyquist filter according to program control, for example. Then, for example, the band limiting filter unit 213 performs a filtering process of allowing a signal having a frequency of several kHz to several tens of kHz or less to pass (Step S103).

  The baseband signal that has passed through the band limiting filter unit 213 is input to the upsampler unit 214 of the DSP 210. The upsampler unit 214 performs a process of sampling the input baseband signal at a frequency higher than the sampling rate (symbol rate) of the symbol data in units of packets (step S104). Specifically, for example, the upsampler unit 214 performs a process of sampling a baseband signal having a symbol rate of 8 kHz at 64 kHz, which is eight times the symbol rate. The upsampler unit 214 may sample the baseband signal at another frequency such as 10 times the symbol rate.

  Then, the upsampler unit 214 inputs the sampled baseband signal, that is, the upsampled baseband signal, to the quadrature modulation unit 221 of the FPGA 220. The quadrature modulation unit 221 performs quadrature amplitude modulation on the input I and Q signals of the baseband signal (step S105).

  The quadrature modulation unit 221 converts the I signal and the Q signal into, for example, QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), π / 4 QPSK, FSK (Frequency Shift Keying: Freq Quadrature amplitude modulation is performed by a modulation method such as Shift Keying.

  The quadrature modulation unit 221 inputs an output signal obtained by quadrature amplitude modulation of the I signal and Q signal of the baseband signal to the analog transmission unit 241 of the communication unit 240 (step S106).

  If the output signal input in step S106 is not an output signal based on user data (N in step S107), the analog transmission unit 241 outputs the output signal to the antenna 243 (step S108). The case where the output signal input in the process of step S106 is not an output signal based on user data is a case where the output signal is a signal based on frame data. As described above, in the present embodiment, frequency hopping is not performed when the output signal is a signal based on frame data. Therefore, when the output signal is a signal based on the frame data, the analog transmission unit 241 outputs the output signal to the antenna 243 at a predetermined transmission frequency. The output signal is converted into a radio wave by the antenna 243 and transmitted.

  When the output signal input in the process of step S106 is an output signal based on user data (Y in step S107), the following process is performed when it is the frequency switching timing (Y in step S109). Is called. That is, when the frequency switching timing generation unit 222 is notified from the frame addition unit 211 that frame data has been added to the head of user data, the frequency setting unit 215 sends a frequency corresponding to a predetermined hopping pattern from the storage unit 230. Is read. Then, the frequency setting unit 215 is caused to determine the frequency read from the storage unit 230 as the transmission frequency of the output signal (step S110).

  The frequency switching timing generation unit 222 inputs frequency information indicating the transmission frequency determined by the frequency setting unit 215 to the frequency switching unit 242. The frequency switching unit 242 performs the following processing when the frequency switching timing generation unit 222 inputs frequency information. That is, the frequency switching unit 242 causes the analog transmission unit 241 to switch the transmission frequency of the output signal to be transmitted to the frequency indicated by the frequency information (Step S111), and outputs the output signal to the antenna 243 (Step S111). S112).

  When it is not the frequency switching timing (N in Step S109), the analog transmission unit 241 outputs the output signal to the antenna 243 without switching the transmission frequency of the output signal to be transmitted (Step S112). The output signal is converted into a radio wave by the antenna 243 and transmitted.

  If all user data input to the transmitting communication device 200 has been transmitted (Y in step S113), the process ends, and if there is untransmitted user data (N in step S113), step The process proceeds to S102.

  Next, the operation of the receiving side communication device 300 will be described. FIG. 4 is a flowchart showing the operation of the receiving side communication device 300. FIG. 5 is an explanatory diagram showing the processing result of the received signal in the receiving side communication device 300.

  As shown in FIG. 4, in the receiving side communication device 300, when the output signal transmitted via the antenna 243 is received by the antenna 343 (step S201), it is converted into the received signal illustrated in FIG. Are sequentially input to the analog reception unit 341 that performs reception processing. The analog reception unit 341 sequentially inputs the reception signals sequentially input by the antenna 343 to the quadrature demodulation unit 321 of the FPGA 320. The orthogonal demodulator 321 performs a demodulation process for extracting a baseband signal having an I component and a Q component from the received signal (step S202). Specifically, the quadrature demodulation unit 321, for example, mixes the received signal with a sine wave and sequentially extracts the I signal. Further, the orthogonal demodulation unit 321, for example, mixes the cosine wave with the received signal and sequentially extracts the Q signal.

  The DSP 310 sequentially captures the I signal and the Q signal extracted by the FPGA 320 in predetermined packet units (see FIG. 5B), and passes the band limiting filter unit 311 of the DSP 310 (step S203). Then, the symbol timing detection unit 312 of the DSP 310 sequentially samples the I signal and the Q signal taken in sequence at a predetermined sampling frequency in units of packets. The symbol timing detection unit 312 sequentially performs a process of detecting a break between each symbol in the sampling result of the I signal and the Q signal in units of packets described above (step S204).

  The symbol-bit conversion unit 313 of the DSP 310 converts each symbol into bit data in units of packets as described above based on the delimiter between the symbols detected by the symbol timing detection unit 312 in step S204 (step S205). .

  Therefore, the bit data similar to the transmitted bit data shown in FIG. 3 can be sequentially obtained in packet units by the processing in step S205 in packet units by the symbol-bit conversion unit 313 of the DSP 310 (see FIG. 5C). ).

  Then, the symbol-bit conversion unit 313 sequentially inputs the converted bit data to the frame removal unit 314 and the synchronization word detection unit 315 in units of packets. If the input bit data includes frame data, the frame removal unit 314 removes the frame data and outputs the frame data from the reception-side communication device 300 (step S206). Then, when the data processing based on the reception signal input to the analog reception unit 341 is completed (Y in step S207), the processing is ended.

When the processing of data based on the received signal input to the analog reception unit 341 has not been completed (N in step S207), the synchronization word detection unit 315 performs the following processing. That is, the symbol-bit conversion unit 313 attempts to detect a synchronization word from the bit data shown in FIG. In the example shown in FIGS. 5B and 5C, the synchronization word detection unit 315 detects a synchronization word from the bit data obtained by converting the packet c. It is assumed that the synchronization word detection unit 315 detects the synchronization word at the timing indicated by “t ₁ ” in FIG. 5C, which is the tail of the synchronization word in the bit data.

Then, the synchronization word detection unit 315 inputs synchronization word detection timing information indicating the detected timing “t ₁ ” to the frequency switching timing calculation unit 316. The frequency switching timing calculation unit 316 of the DSP 310 calculates timing “t ₂ ” for starting frequency hopping based on the input synchronization word detection timing information.

Specifically, the frequency switching timing calculation unit 316 performs step S204 between the timing “t ₃ ” and the timing “t ₂ ” when the bit corresponding to the tail of the packet c including the synchronization word is input. The number “D” of samplings in the process is calculated. The number of times “D” is calculated by the following equation (1) as shown in FIG.

D = A− (B−C) (1)
A is the number of times sampling is performed at a predetermined sampling frequency between the timing “t ₁ ” and the timing “t ₂ ”, and is a fixed value set in advance. B is the number of times sampling is performed at a predetermined sampling frequency between the time when a bit corresponding to the head is input and the time when the bit corresponding to the tail is input in one packet. It is a fixed value. C is the number of times sampling is performed at a predetermined sampling frequency from the time when the bit corresponding to the head is input in the packet c until the timing “t ₁ ” arrives. The timing “t ₂ ” is calculated based on D calculated by the equation (1), the timing “t ₃ ”, and a predetermined sampling frequency.

The frequency switching timing calculation unit 316 inputs timing information indicating the calculated timing “t ₂ ” to the frequency switching timing generation unit 322. Specifically, the frequency switching timing calculation unit 316 inputs, for example, timing information indicating the number of times sampling is performed until the timing “t ₂ ” comes from the present to the frequency switching timing generation unit 322.

Further, when the frequency switching timing generation unit 322 determines that the timing “t ₂ ” has arrived based on the input timing information (Y in step S208), for example, the frequency switching timing generation unit 322 receives a predetermined value from the storage unit (not illustrated) described above. Reads the frequency according to the hopping pattern. Then, the frequency switching timing generation unit 322 determines the read frequency as the reception frequency in the analog reception unit 341 (step S209).

  The frequency switching timing generation unit 222 inputs frequency information indicating the determined reception frequency to the frequency switching unit 342. When the frequency switching timing generation unit 322 inputs frequency information, the frequency switching unit 342 causes the analog reception unit 341 to switch the reception frequency for performing reception processing to the frequency indicated by the frequency information (step S210). Then, the process proceeds to step S201. Then, in step S201, reception processing is performed at the switched frequency, that is, the frequency on which frequency hopping has been performed. Therefore, the frequency hopping timing of the receiving communication device 300 can be synchronized with the frequency hopping timing of the transmitting communication device 200.

  According to the present embodiment, since processing of input user data is performed in units of packets in the transmission-side communication device 200, as compared with a case where data is sampled based on bits and clock frequencies and is performed in small units. Processing efficiency can be improved. Therefore, it is possible to cause the DSP 210 and the FPGA 220 that execute processing according to program control to execute each processing.

  In addition, when each process is configured to be performed by dedicated hardware, it is not possible to support other than a predetermined type of modulation scheme and frame. However, according to the present embodiment, the DSP 210 and the FPGA 220 that execute the processing according to the program control execute each processing, so that it is possible to flexibly cope with various types of modulation schemes and frames by changing the program. become.

  In addition, according to the present embodiment, since the received communication device 300 processes the received signal in units of packets, as compared with the case where the processing is performed for each small unit of data sampled based on bits and clock frequency, Processing efficiency can be improved. Therefore, each process can be executed by the DSP 310 and the FPGA 320 that execute processes according to program control.

  In addition, when each process is configured to be performed by dedicated hardware, it is not possible to support other than a predetermined type of modulation scheme and frame. However, according to the present embodiment, the DSP 310 and the FPGA 320 that execute the processing according to the program control execute each processing, so that it is possible to flexibly cope with various types of modulation schemes and frames by changing the program. become.

  Therefore, according to this embodiment, it is possible to perform communication by performing frequency hopping by synchronizing the receiving communication device 200 and the transmitting communication device 300 with high processing efficiency.

  In the present embodiment, the frequency switching timing of frequency hopping is synchronized between the transmission-side communication device 200 and the reception-side communication device 300, but one communication device is used in TDMA (Time Division Multiple Access) or the like. It can also be applied to synchronization of transmission / reception timing between the communication device and the other communication device. Specifically, for example, when one communication device is the data transmission side, information indicating the timing of switching to the reception side is transmitted to the other communication device, and the other communication device is configured to perform timing based on the information. To start sending data.

  Further, the present invention can also be applied to frequency division multiple access such as SCPC (Single Channel Per Carrier).

Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram illustrating a configuration example of the data transmitter according to the second embodiment of this invention. As shown in FIG. 6, the data transmitter 20 according to the second embodiment of the present invention includes a packet unit processing means 21 (corresponding to the DSP 210 shown in FIG. 1) and an output signal generating means 22 (corresponding to the FPGA 220 shown in FIG. 1). ) And transmission means 24 (corresponding to the communication unit 240 shown in FIG. 1). Further, the packet unit processing means 21 includes a frame adding means 25 (corresponding to the frame adding section 211 shown in FIG. 1).

  The packet unit processing means 21 generates a baseband signal by performing a predetermined sampling process in a predetermined packet unit based on the input digital data. The output signal generation unit 22 generates an output signal based on the baseband signal generated by the packet unit processing unit 21. The transmission means 24 transmits the output signal generated by the output signal generation means 22 by frequency hopping at a predetermined timing. The frame adding unit 25 adds predetermined frame data to the input digital data so that the transmission unit 24 starts frequency hopping of the output signal at a predetermined timing.

  Then, the packet unit processing means 21 performs a predetermined sampling process in predetermined packet units on the digital data to which the predetermined frame data is added by the frame adding means 25.

  According to the present embodiment, it is possible to synchronize the transmission side and the reception side communicating by frequency hopping with high processing efficiency.

20 data transmitter 21 packet unit processing means 22 output signal generating means 24 transmitting means 25 frame adding means 100 communication system 200 transmitting side communication equipment 210, 310 DSP
211 Frame addition unit 212 Bit-symbol conversion unit 213, 311 Band limiting filter unit 214 Upsampler unit 215 Frequency setting unit 220, 320 FPGA
221 Orthogonal modulation unit 222, 322 Frequency switching timing generation unit 230 Storage unit 240 Communication unit 241 Analog transmission unit 242, 342 Frequency switching unit 243, 343 Antenna 312 Symbol timing detection unit 313 Symbol-bit conversion unit 314 Frame removal unit 315 Synchronization word Detection unit 316 Frequency switching timing calculation unit 321 Orthogonal demodulation unit 341 Analog reception unit 300 Reception side communication device

Claims (8)

Packet unit processing means for generating a baseband signal by performing predetermined sampling processing in predetermined packet units based on the input digital data;
Output signal generating means for generating an output signal based on the baseband signal generated by the packet unit processing means;
Transmitting means for transmitting the output signal generated by the output signal generating means by frequency hopping at a predetermined timing;
The packet unit processing means includes:
Predetermined frame data before the input digital data that starts transmission when the frequency hopping is started so that the transmission means starts the frequency hopping of the output signal at a predetermined timing. Frame adding means for adding
The data transmitter, wherein the predetermined sampling processing is performed in units of the predetermined packet on the digital data to which the predetermined frame data is added by the frame adding means. The packet unit processing means performs the predetermined sampling process at a predetermined sampling frequency on the digital data to which the predetermined frame data is added, and generates the baseband signal having an I component and a Q component. The data transmitter according to 1. 3. The data transmitter according to claim 1, wherein the predetermined timing is when transmission of a portion of the output signal corresponding to the input digital data is started. The frame adding means includes the frame data including data configured such that an interval between the timing at which the frequency hopping starts and the timing at which the digital data starts to be transmitted is a predetermined interval in the output signal. The data transmitter according to any one of claims 1 to 3, wherein the data transmitter is added before the digital data. The data transmitter according to any one of claims 1 to 4, wherein the packet unit processing means is a processor that executes processing according to program control. A data transmitter according to any of claims 1 to 5;
Data communication system, wherein the data transmitter and a data receiver which receives based Ku electric wave to the output signal transmitted.
A packet unit processing step for generating a baseband signal by performing a predetermined sampling process in a predetermined packet unit based on the input digital data;
An output signal generating step for generating an output signal based on the baseband signal generated in the packet unit processing step;
A transmission step of transmitting the output signal generated in the output signal generation step by frequency hopping at a predetermined timing,
In the packet unit processing step,
Predetermined frame data before the input digital data that is started to be transmitted when the frequency hopping is started so that the frequency hopping of the output signal is started at a predetermined timing in the transmission step. And performing the predetermined sampling process in units of the predetermined packet on the digital data to which the predetermined frame data is added. On the computer,
Packet unit processing for generating a baseband signal by performing predetermined sampling processing in predetermined packet units based on input digital data;
Output signal generation processing for generating an output signal based on the baseband signal generated by the packet unit processing;
A transmission process for transmitting the output signal generated by the output signal generation process by frequency hopping at a predetermined timing;
In the packet unit processing,
The transmission process starts when the frequency hopping is started so that the frequency hopping of the output signal is started at a predetermined timing in the transmission process. Execute the frame addition process to add data,
A data transmission program for performing the predetermined sampling process in units of the predetermined packet on the digital data to which the predetermined frame data is added by the frame addition process.

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