JP6492453B2 - Error packet generation apparatus and error packet generation method - Google Patents

Description

  The present invention relates to an error packet generation device and an error packet generation method.

  In recent years, the importance of information systems in various business activities has been increasing. Therefore, system evaluation for evaluating the reliability of information systems is also important. In system evaluation, it is desired to evaluate an information system from various angles.

  As one of such system evaluations, there is verification of how the system behaves when an error packet occurs in a LAN (Local Area Network) interface. In such verification, an error packet may be generated in a pseudo manner, and the generated error packet may be transmitted to the network and the information communication device to verify the operation of the communication system when the error packet occurs.

  Therefore, as one method for generating an error packet, there is a method for generating an error packet at the relay section of the LAN transmission path. For example, an error packet generation device that relays data is arranged between the LAN interfaces of two information communication devices connected by a LAN. This error packet generation device is realized as hardware using a MAC (Media Access Control) interface. The error packet generation device has functions such as preamble addition and IFG (Inter Frame Gap) insertion, which are the roles of the MAC sublayer, in order to pass the packet to the MAC layer. These functions can be realized with off-the-shelf products embedded in a semiconductor. A semiconductor in which such a specific function is embedded may be called an IP (Intellectual Property) core. By using a semiconductor in which these functions are embedded, the error packet generation device can be easily adapted to the Ethernet (registered trademark) standard.

  Furthermore, information communication devices use interfaces such as MII (Media Independent Interface) and GMII (Gigabit Media Independent Interface), which are Ethernet standards, in order to connect an IP core that performs data processing and Ethernet. In recent years, GMII is increasingly used for connection with Ethernet.

  Here, there is a short packet as one of the error packets. In Ethernet, the size of a packet to be transmitted is defined as a minimum of 64 bytes (512 bits). A short packet is a packet having a data length of less than 64 bytes of the Ethernet standard.

  Here, many IP cores that perform processing in the MAC sublayer are provided with a function of inserting a pad to adjust the data length to 64 bits when a short packet is received. Therefore, even if a packet of less than 64 bytes is input from the MAC layer to the MAC sublayer to transmit a short packet, a pad is inserted in the MAC sublayer, and the packet is aligned to 64 bytes.

  There is a conventional technique for performing an abnormality diagnosis of a network system using a short packet. In addition, there is a conventional technique for generating a short packet by stopping pad insertion.

JP 2000-299696 A JP 2000-261479 A

  However, an existing IP core having a MAC sublayer function and having a GMII interface does not have a function to invalidate pad insertion. Therefore, when an existing IP core is used, it is difficult to generate a short packet by invalidating pad insertion. In addition, in order to provide an IP core having a MAC sublayer function and a GMII interface with a function of invalidating pad insertion, it must be performed from the development of the semiconductor, which is costly and cumbersome. It is difficult to easily generate a short packet from the aspect.

  The disclosed technology has been made in view of the above, and an object thereof is to provide an error packet generation device and an error packet generation method that easily generate a short packet.

The error packet generation device and the error packet generation method disclosed in the present application are, in one aspect, the physical layer transmits a packet input from the media access control layer to an external device. The permission unit instructs permission or non-permission of packet transmission to the physical layer . The generation unit monitors transmission of the input packet by the physical layer, and when the length transmitted from the physical layer reaches a predetermined length shorter than a predetermined packet length , the input packet The permission unit is instructed not to permit packet transmission, and the physical layer is caused to generate and transmit an error packet.

  According to one aspect of the error packet generation device and the error packet generation method disclosed in the present application, there is an effect that a short packet can be easily generated.

FIG. 1 is a configuration diagram of an information communication system in which an error packet generation device according to an embodiment is arranged. FIG. 2 is a block diagram of the error packet generator according to the embodiment. FIG. 3 is a circuit block diagram illustrating an example of a short packet generation circuit. FIG. 4 is a diagram for explaining the transition of the transmission packet. FIG. 5 is a diagram for explaining packet states in each layer of protocol communication. FIG. 6A is a diagram illustrating a signal input to the MAC layer processing unit. FIG. 6B is a diagram illustrating an output signal from the PHY layer processing unit when a short packet is not generated. FIG. 6C is a diagram illustrating an output signal from the PHY layer processing unit when a short packet is generated. FIG. 7 is a flowchart of the error packet generation process of the error packet generation device according to the embodiment.

  Hereinafter, embodiments of an error packet generation apparatus and an error packet generation method disclosed in the present application will be described in detail with reference to the drawings. The error packet generating apparatus and the error packet generating method disclosed in the present application are not limited by the following embodiments.

  FIG. 1 is a configuration diagram of an information communication system in which an error packet generation device according to an embodiment is arranged. As shown in FIG. 1, the information communication system according to the present embodiment includes an error packet generation device 1, information processing devices 2 and 3, and a control PC (Personal Computer) 4.

  The information processing apparatus 2 is a router or a switch, for example. The information processing device 3 is a server or a switch. However, the information processing apparatuses 2 and 3 are examples, and other apparatuses may be used as long as they transmit and receive data via Ethernet. The information processing units 2 and 3 transmit the packet to the other device via the error packet generation device 1. Further, the information processing units 2 and 3 receive a packet transmitted from the other device via the error packet generation device 1.

  The control PC 4 is connected to the error packet generation device 1 via, for example, a USB (Universal Serial Bus) port.

  The error packet generation device 1 is connected to the information processing devices 2 and 3 via Ethernet. That is, the error packet generation device 1 relays data transmission / reception between the information processing devices 2 and 3 on the Ethernet. Thus, the error packet generation device 1 is inserted between the two information processing devices. The error packet generation device 1 converts the received packet received from the information processing device 2 or 3 into a short packet and transmits it to the other device.

  Next, the error packet generation device 1 will be described in more detail with reference to FIG. FIG. 2 is a block diagram of the error packet generator according to the embodiment. As shown in FIG. 2, the error packet generator 1 according to the present embodiment includes a control PC interface 101, an overall control unit 102, a network layer processing unit 103, a MAC layer processing unit 104, and a PHY (Physical) layer processing unit 106. Have. Furthermore, the error packet generation device 1 includes an SOF (Start Of Flame) detection unit 107, a clock count unit 108, an enable signal control unit 109, a network layer processing unit 110, a MAC layer processing unit 111, and a PHY layer processing unit 113.

  The MAC layer processing unit 104 and the PHY layer processing unit 106 use the GMII interface 105 as a connection interface. Further, the MAC layer processing unit 111 and the PHY layer processing unit 113 use the GMII interface 105 as a connection interface.

  In response to an instruction from the operator, the control PC 4 sends a start instruction for instructing start of short packet generation, a stop instruction for instructing stop of short packet generation, and an instruction for the data length of the short packet to be generated to the overall control unit 102. Output. Hereinafter, the data length of the generated short packet designated by the operator may be referred to as “designated length”.

  The control PC interface 101 is an interface for connection with the control PC 4. The control PC interface 101 receives information on the start instruction, the stop instruction, and the specified length from the control PC 4. Then, the control PC interface 101 outputs the received start instruction, stop instruction, and specified length information to the overall control unit 102. The control PC interface 101 is realized by an integrated circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

  Upon receiving an activation instruction input from the control PC interface 101, the overall control unit 102 activates the SOF detection unit 107, the clock count unit 108, and the enable signal control unit 109. Further, when the overall control unit 102 receives an input of a stop instruction from the control PC interface 101, the overall control unit 102 stops the operations of the SOF detection unit 107, the clock count unit 108, and the enable signal control unit 109. The overall control unit 102 is realized by an integrated circuit such as an ASIC or FPGA.

  The PHY layer processing units 106 and 113 have the same function except for the connection destination. Therefore, the PHY layer processing unit 106 will be described as an example.

  The PHY layer processing unit 106 performs processing for establishing, maintaining, and releasing a physical connection with the information processing apparatus 2. The PHY layer processing unit 106 connects to the MAC layer processing unit 104 using the GMII interface 105. The PHY layer processing unit 106 transmits and receives signals to and from the MAC layer processing unit 104 via the GMII interface 105.

  Specifically, the PHY layer processing unit 106 receives from the information processing apparatus 2 a received packet that is a signal that satisfies a physical standard such as electricity or light. Then, the PHY layer processing unit 106 converts the received packet into a signal that satisfies the GMII electrical standard. Thereafter, the PHY layer processing unit 106 outputs the reception enable signal and the reception clock to the MAC layer processing unit 104 via the GMII interface 105. Furthermore, the PHY layer processing unit 106 transmits the received packet converted to satisfy the GMII electrical standard to the MAC layer processing unit 104 via the GMII interface 105.

  Further, the PHY layer processing unit 106 outputs a transmission clock to the MAC layer processing unit 104 via the GMII interface 105. Thereafter, the PHY layer processing unit 106 receives from the MAC layer processing unit 104 via the GMII interface 105 an input of a transmission packet that is a signal that satisfies the GMII electrical standard transmitted based on the transmission clock. The PHY layer processing unit 106 receives an input of a transmission enable signal from the MAC layer processing unit 104 via the GMII interface 105.

  If the transmission enable signal is received at the timing when the transmission packet is received, the PHY layer processing unit 106 converts the transmission packet received at the timing into a signal that satisfies a physical standard such as electricity or light. Thereafter, the PHY layer processing unit 106 transmits the transmission packet converted so as to satisfy the physical standard to the information processing apparatus 2. On the other hand, when the transmission enable signal is not received at the timing when the transmission packet is received, the PHY layer processing unit 106 discards the transmission packet received at that timing. The PHY layer processing unit 106 is realized by an integrated circuit such as an LSI (Large Scale Integration). The PHY layer processing unit 106 is an example of a “transmission unit”.

  The GMII interfaces 105 and 112 have the same function. Therefore, the GMII interface 105 will be described below as an example. The GMII interface 105 is an interface that connects the MAC layer processing unit 104 and the PHY layer processing unit 106.

  The GMII interface 105 receives an input of a reception enable signal from the PHY layer processing unit 106. Then, the GMII interface 105 transmits the received reception enable signal to the MAC layer processing unit 104. Further, the GMII interface 105 receives an input of the received packet from the PHY layer processing unit 106. Then, the GMII interface 105 transmits the received reception packet to the MAC layer processing unit 104. Further, the GMII interface 105 receives the input of the reception clock from the PHY layer processing unit 106. Then, the GMII interface 105 transmits the received reception clock to the MAC layer processing unit 104.

  Further, the GMII interface 105 receives a transmission clock input from the PHY layer processing unit 106. Then, the GMII interface 105 outputs the transmission clock to the MAC layer processing unit 104.

  The GMII interface 105 receives the transmission enable signal from the MAC layer processing unit 104. Further, the GMII interface 105 receives control of transmission permission or stop of the transmission enable signal from the enable signal control unit 109. When the transmission permission of the transmission enable signal is received from the enable signal control unit 109, the GMII interface 105 outputs the transmission enable signal to the PHY layer processing unit 106. Further, when the stop control of the transmission enable signal is received from the enable signal control unit 109, the GMII interface 105 discards the received transmission enable signal.

  Further, the GMII interface 105 receives an input of a transmission packet transmitted based on the transmission clock from the MAC layer processing unit 104. Then, the GMII interface 105 outputs the received transmission packet to the PHY layer processing unit 106. The GMII interface 105 is an example of a “permission unit”.

  The MAC layer processing units 104 and 111 have the same function. Therefore, hereinafter, the MAC layer processing unit 104 will be described as an example. The MAC layer processing unit 104 is connected to the PHY layer processing unit 106 using the GMII interface 105.

  The MAC layer processing unit 104 receives an input of a reception enable signal from the PHY layer processing unit 106 via the GMII interface 105. Further, the MAC layer processing unit 104 receives an input of a reception clock from the PHY layer processing unit 106 via the GMII interface 105.

  Then, when receiving the reception enable signal, the MAC layer processing unit 104 receives a reception packet transmitted from the PHY layer processing unit 106 via the GMII interface 105 using the reception clock. Thereafter, the MAC layer processing unit 104 disassembles the bit string of the received packet and deletes the control information including the preamble and SFD (Start Frame Delimiter). Thereafter, the MAC layer processing unit 104 transmits the header and data to the network layer processing unit 103.

  Further, the MAC layer processing unit 104 receives an input of SOF (Start Of Frame), header, data, and EOF (End Of Frame) from the network layer processing unit 103. Then, the MAC layer processing unit 104 adds a preamble and SFD to the received SOF, header, data, and EOF. Further, the MAC layer processing unit 104 inserts IFG (Inter Frame Gap) or the like to generate a transmission packet. At this time, if the data is less than 64 bytes which is the lower limit of the data length defined by Ethernet, the MAC layer processing unit 104 performs padding such as adding empty data to the received data, and the data is converted to 64-byte data. Correct to long. Then, the MAC layer processing unit 104 transmits the generated transmission packet to the PHY layer processing unit 106 via the GMII interface 105. The MAC layer processing unit 104 is realized by an IP core. The MAC layer processing unit 104 is an example of a “data correction unit”. 64 bytes is an example of the lower limit data length.

  The network layer processing unit 103 receives a header and data input from the MAC layer processing unit 104. The network layer processing unit 103 performs data transmission path selection and packet quality control. Thereafter, a signal from the information processing apparatus 2 processed by the network layer processing unit 103 is transmitted to the information processing apparatus 3 via the network layer processing unit 110, the MAC layer processing unit 111, the GMII interface 112, and the PHY layer processing unit 113. Sent to.

  Further, the network layer processing unit 103 receives a signal transmitted from the information processing apparatus 3 via the network layer processing unit 110, the MAC layer processing unit 111, the GMII interface 112, and the PHY layer processing unit 113. Then, the network layer processing unit 103 transmits a header and data to the MAC layer processing unit 104 after performing a data transmission path selection and packet quality control in order to transmit data to the information processing apparatus 2. The network layer processing unit 103 is realized by an integrated circuit such as an ASIC or FPGA.

  Next, the SOF detection unit 107, the clock count unit 108, and the enable signal control unit 109 will be described. The SOF detection unit 107, the clock count unit 108, and the enable signal control unit 109 all perform processing on a signal sent to the information processing apparatus 2 or 3. Therefore, hereinafter, operations of the SOF detection unit 107, the clock count unit 108, and the enable signal control unit 109 in the processing for the network layer processing unit 103, the MAC layer processing unit 104, the GMII interface 105, and the PHY layer processing unit 106 will be described. However, the SOF detection unit 107, the clock count unit 108, and the enable signal control unit 109 operate in the same manner for the network layer processing unit 110, the MAC layer processing unit 111, the GMII interface 112, and the PHY layer processing unit 113.

  When the SOF detection unit 107 receives an activation command from the overall control unit 102, the SOF detection unit 107 starts monitoring a signal transmitted from the network layer processing unit 103 to the MAC layer processing unit 104. When the SOF detection unit 107 detects that the SOF is transmitted from the overall control unit 102 to the MAC layer processing unit 104, the SOF detection unit 107 notifies the clock count unit 108 of the detection of the SOF.

  When the SOF detection unit 107 receives a stop command from the overall control unit 102, the SOF detection unit 107 stops monitoring the signal transmitted from the network layer processing unit 103 to the MAC layer processing unit 104. The SOF detection unit 107 is realized by an integrated circuit such as an ASIC or FPGA.

  The clock count unit 108 has a clock counter that counts clocks. When the clock count unit 108 receives the activation command from the overall control unit 102, the clock count unit 108 sets its own clock counter to 0 after activation. Further, the clock count 108 acquires the designated length from the overall control unit 102.

  The clock count unit 108 receives an input of a transmission clock from the MAC layer processing unit 104. Thereafter, when a notification of SOF detection is received from the SOF detection unit 107, the clock counter is incremented by one for each clock and clock counting is started. When the clock counter reaches the specified length, the enable signal control unit 109 is instructed to stop the enable signal.

  Further, when receiving a stop command from the overall control unit 102, the clock count unit 108 stops its operation. The clock count unit 108 is realized by an integrated circuit such as an ASIC or FPGA.

  When the enable signal control unit 109 receives the start command from the overall control unit 102, the enable signal control unit 109 starts and then permits the GMII interface 105 to transmit an enable signal. Thereafter, when the enable signal control unit 109 receives an instruction to stop the enable signal from the clock count unit 108, the enable signal control unit 109 stops the transmission of the enable signal by the GMII interface 105. Thereafter, after the transmission of the transmission packet from the MAC layer processing unit 104 to the PHY layer processing unit 106 is completed, the enable signal control unit 109 permits the GMII interface 105 to transmit the enable signal.

  Further, when the enable signal control unit 109 receives a stop command from the overall control unit 102, the enable signal control unit 109 stops its operation. The enable signal control unit 109 is an example of an “abnormal signal generation unit”.

  Next, an example of the short packet generation circuit will be described with reference to FIG. FIG. 3 is a circuit block diagram illustrating an example of a short packet generation circuit. In FIG. 3, the movement of a transmission packet is represented using a hierarchy of communication protocols. The MAC layer 11 and the MAC sublayer 12 are layers in which processing by the MAC layer processing unit 104 is performed. The PHY layer 13 is a layer on which processing by the PHY layer processing unit 106 is performed.

  The MAC layer 11 receives a clock (clock), data (data), SOF, EOF, source side ready signal (scr_rdy: source_ready), and destination side ready signal (dst_rdy: destination_ready) from the upper layer.

  The MAC layer 11 starts data transfer by receiving the source-side preparation completion signal and the destination-side preparation completion signal.

  In the MAC layer 11 and the MAC sublayer 12, the preamble and SFD are added to the received data. Further, the MAC sublayer 12 performs padding on the received data. As a result, data of less than 64 bytes is aligned to 64 bytes.

  The MAC sublayer 12 and the PHY layer 13 are connected using GMII. A transmission clock (txclk: transmit clock) is transmitted from the PHY layer 13 to the MAC sublayer 12. Then, a transmission enable signal (txen: transmit enable) and a transmission packet (txd: transmit data) are transmitted from the MAC sublayer 12 using the transmission clock.

  Here, in FIG. 3, the enable signal control unit 109 includes an AND circuit 150. Here, the enable signal control unit 109 will be described as an AND circuit 150. The AND circuit 150 receives a High signal from the clock count unit 108 while the clock count unit 108 counts the clock. In this case, the AND circuit 150 outputs the input transmission enable signal to the PHY layer 13 as it is.

  Next, when the clock count unit 108 instructs the stop of the enable signal, the AND circuit 150 receives a Low signal input from the clock count unit 108. In this case, the AND circuit 150 stops outputting the transmission enable signal.

  A transmission packet of 64 bytes or more is input to the PHY layer 13 from the MAC sublayer 12. However, in the PHY layer 13, the transmission enable signal is stopped during reception of the transmission packet. In that case, when the input of the transmission enable signal is stopped, the output of the transmission packet from the PHY layer 13 is stopped. That is, a transmission packet (TX: Transmit) output from the PHY layer 13 has a data length of less than 64 bytes and becomes a short packet.

  Next, with reference to FIG. 4, the transition of transmission packets at the time of normal transmission of data and creation of a short packet will be described together. FIG. 4 is a diagram for explaining the transition of the transmission packet. Again, the movement of the transmission packet is represented using a hierarchy of communication protocols.

  For example, a case where the packet 14 is a packet having a data length of 64 bytes or more will be described. The packet 14 is added with a preamble and SFD at the MAC layer 11 and the MAC sublayer 12. The processed packet is sent from the MAC sublayer 12 to the PHY layer 13 via the GMII interface 105. A packet 15 having a data length of 64 bytes or more is output from the PHY layer 13.

  Next, the case where the packet 14 is a packet having a data length of less than 64 bytes will be described. For example, consider a case where the error packet generation method according to the present embodiment is not used. The packet 14 is added with a preamble and SFD at the MAC layer 11 and the MAC sublayer 12. Further, the packet 14 is subjected to padding processing in the MAC sublayer 12 and is corrected to a data length of 64 bytes. The packet having a data length of 64 bytes is sent to the PHY layer 13. Thereafter, a packet 15 having a data length of 64 bytes is output from the PHY layer 13. In this case, the packet 15 is a packet within the Ethernet standard.

  On the other hand, consider a case where the error packet generation method according to the present embodiment is used. The packet 14 is added with a preamble and SFD at the MAC layer 11 and the MAC sublayer 12. Furthermore, if the packet 14 is less than 64 bytes, it is subjected to padding processing by the MAC sublayer 12 and is corrected to a data length of 64 bytes. A packet having a data length of 64 bytes is output from the MAC sublayer 12 using the GMII interface 105. However, the GMII interface 105 stops the transmission enable signal when data of a specified length is output from the transmission packet. As a result, the packet 15 is output from the PHY layer 13 as a packet having a specified data length among the transmission packets. The data length of the packet 15 is shorter than 64 bits. That is, a non-Ethernet standard short packet is output from the PHY layer 13.

  Next, referring to FIG. 5, the state of packets in each layer of protocol communication will be described together. FIG. 5 is a diagram for explaining packet states in each layer of protocol communication.

  A packet having an SOF 201, a data part 202 including a header and data, and an EOF 203 is transmitted from the network layer to the MAC layer.

  Then, in the MAC layer and the MAC sublayer, the preamble 204 and the SFD 205 are added to the packet. Further, when the data length of the data portion 202 is less than 64 bytes, padding is performed on the data portion 202 in the MAC sublayer. Then, a packet having a data part 202 of 64 bits or more is transmitted to the PHY layer.

  Thereafter, if the error packet generation method according to the present embodiment is not used, the packet input to the PHY layer is output to the information processing apparatus 2 after undergoing physical conversion. That is, a packet within the Ethernet standard is output.

  On the other hand, when the error packet generation method according to the present embodiment is used, only a signal for a specified length in the packet is output to the information processing apparatus 2 after being input to the PHY layer. That is, the error packet generation device 1 according to the present embodiment can output a packet that is not in Ethernet standard.

  Next, signals output from the PHY layer processing unit 106 will be described with reference to FIGS. FIG. 6A is a diagram illustrating a signal input to the MAC layer processing unit. The uppermost waveform in FIG. 6A represents a clock input from the network layer processing unit 103 to the MAC layer processing unit 104. The waveform in the lower stage represents data input from the network layer processing unit 103 to the MAC layer processing unit 104. The waveform in the lower stage is an SOF input waveform to the MAC layer processing unit 104. The waveform at the bottom is an EOF input waveform to the MAC layer processing unit 104.

  FIG. 6B is a diagram illustrating an output signal from the PHY layer processing unit when a short packet is not generated. The uppermost waveform in FIG. 6B represents the transmission clock input to the MAC layer processing unit 104. The waveform in the lower stage represents a transmission enable signal output from the MAC layer processing unit 104. The waveform in the lower stage represents data output from the MAC layer processing unit 104. The bottom waveform represents a packet output from the PHY layer processing unit 106.

  FIG. 6C is a diagram illustrating an output signal from the PHY layer processing unit when a short packet is generated. The uppermost waveform in FIG. 6C represents the transmission clock input to the MAC layer processing unit 104. The waveform in the lower stage represents a transmission enable signal output from the MAC layer processing unit 104. The waveform in the lower stage represents data output from the MAC layer processing unit 104. The bottom waveform represents a packet output from the PHY layer processing unit 106.

  As shown in FIG. 6A, the MAC layer processing unit 104 receives the data 301 after receiving the SOF, and finally receives the EOF. Here, the data 301 received by the MAC layer processing unit 104 has a size of 64 bytes including the header and data as shown in FIG. 6A.

  The MAC layer processing unit 104 adds a 1-byte SOF, a 6-byte preamble, a 1-byte SFD, and a 1-byte EOF to the received data 301 to generate a 64-byte packet. Then, the MAC layer processing unit 104 transmits the generated packet to the PHY layer processing unit 106 via the GMII interface 105.

  Next, an output signal from the PHY layer processing unit 106 when the short packet is not generated when the signal shown in FIG. 6A is input to the MAC layer processing unit 104 will be described with reference to FIG. 6B. When the short packet is not generated, the PHY layer processing unit 106 receives the transmission enable signal from the beginning to the end of the packet. That is, the PHY layer processing unit 106 starts receiving the transmission enable signal at the timing 321 and then outputs the data 302 following the SOF, preamble, and SFD. In this case, since the PHY layer processing unit 106 receives the transmission enable signal from the beginning to the end of the packet, the PHY layer processing unit 106 outputs the same 64-byte data 302 as the data 301 received by the MAC layer processing unit 104. Then, the PHY layer processing unit 106 stops receiving the transmission enable signal at timing 322. Thereafter, the PHY layer processing unit 106 outputs the EOF 323 in one clock immediately after the input of the transmission enable signal is stopped, and completes the output of the packet.

  Next, an output signal from the PHY layer processing unit 106 when a short packet is generated when the signal shown in FIG. 6A is input to the MAC layer processing unit 104 will be described with reference to FIG. 6C. . Here, a case will be described where creation of a 14-byte short packet is instructed. The PHY layer processing unit 106 starts receiving a transmission enable signal at timing 331, and then outputs data 303 following the SOF, preamble, and SFD. In this case, the PHY layer processing unit 106 does not receive the input of the transmission enable signal at the timing 332 when the data for 13 bytes is output. Thereafter, the PHY layer processing unit 106 outputs the data 333 for one byte in one clock immediately after the input of the transmission enable signal is stopped, and completes the output of the packet. In this case, the data 303 has only 14 bytes as shown in FIG. 6C. That is, the PHY layer processing unit 106 outputs a 14-byte short packet that is out of Ethernet standards.

  Next, a flow of error packet generation processing of the error packet generation device 1 according to the present embodiment will be described with reference to FIG. FIG. 7 is a flowchart of the error packet generation process of the error packet generation device according to the embodiment.

  The SOF detection unit 107 detects the SOF from the signal transmitted from the network layer processing unit 103 to the MAC layer processing unit 104 (step S1). When detecting the SOF, the SOF detection unit 107 notifies the clock count unit 108 of the detection of the SOF.

  In response to the notification of SOF detection from the SOF detector 107, the clock count unit 108 starts counting the number of clocks (step S2).

  The clock count unit 108 determines whether the data length transmitted from the MAC layer processing unit 104 to the PHY layer processing unit 106 matches the specified length (step S3). If the count does not match the specified length (No at Step S3), the clock count unit 108 waits until the count matches the specified length.

  On the other hand, when the count matches the specified length (step S3: affirmative), the clock count unit 108 instructs the enable signal control unit 109 to stop the transmission enable signal. In response to the instruction to stop the transmission enable signal, the enable signal control unit 109 turns off the transmission enable signal output from the GMII interface 105 and stops transmission of the transmission enable signal (step S4).

  As described above, the error packet generation apparatus according to the present embodiment generates a short packet by stopping the transmission enable signal in the GMII interface that connects the existing IP core having the MAC layer function. In other words, since the transmission enable signal of the GMII interface is simply stopped, a short packet can be generated without modifying the IP core having the MAC layer function, and a short packet can be generated with a simple circuit design. A short packet can be generated. Further, since it is not necessary to generate a short packet in the upper layer above the MAC layer, it is possible to avoid complication of circuit design.

1 Error packet generator 2, 3 Information processor 4 Control PC
DESCRIPTION OF SYMBOLS 101 Control PC interface 102 Overall control part 103,110 Network layer process part 104,111 MAC layer process part 105,112 GMII interface 106,113 PHY layer process part 107 SOF detection part 108 Clock count part 109 Enable signal control part

Claims (5)

A physical layer that transmits packets input from the media access control layer to an external device; and
A permission unit that instructs the physical layer to permit or disallow packet transmission;
The transmission of the input packet by the physical layer is monitored, and when the length transmitted from the physical layer reaches a predetermined length shorter than a predetermined packet length, the transmission of the input packet is transmitted. An error packet generation device, comprising: a generation unit that instructs the permission unit to prohibit, and causes the physical layer to generate and transmit an error packet.   The error packet generation device according to claim 1, wherein the generation unit does not pad the input packet when the input packet is shorter than the predetermined packet length.   If the packet input to the media access control layer is shorter than the predetermined packet length, the input packet is padded, corrected to a normal packet having the predetermined packet length, and output to the physical layer The error packet generation device according to claim 1, further comprising a correction unit. The error packet generation apparatus according to claim 1, wherein the media access control layer and the physical layer are connected using a Gigabit Media Independent Interface (GMII). Input packets from the media access control layer to the physical layer,
Causing the physical layer to start transmitting the input packet to an external device;
The transmission of the input packet is monitored by the physical layer, and when the length transmitted from the physical layer reaches a predetermined length shorter than a predetermined packet length, the transmission of the input packet is performed. An error packet generation method comprising: disabling and causing the physical layer to generate and transmit an error packet.

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