JP6492083B2 - インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法 - Google Patents

インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法 Download PDF

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JP6492083B2
JP6492083B2 JP2016536668A JP2016536668A JP6492083B2 JP 6492083 B2 JP6492083 B2 JP 6492083B2 JP 2016536668 A JP2016536668 A JP 2016536668A JP 2016536668 A JP2016536668 A JP 2016536668A JP 6492083 B2 JP6492083 B2 JP 6492083B2
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JP2017501492A (ja
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アガーワル,ウッタム
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オラクル・インターナショナル・コーポレイション
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306Intercommunication techniques
    • G06F15/17331Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/2866Architectures; Arrangements
    • H04L67/2871Implementation details of single intermediate entities
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/064Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/067Bidirectional FIFO, i.e. system allowing data transfer in two directions

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP2016536668A 2013-12-04 2014-10-21 インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法 Active JP6492083B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US14/096,949 2013-12-04
US14/096,987 US8898353B1 (en) 2013-12-04 2013-12-04 System and method for supporting virtual host bus adaptor (VHBA) over infiniband (IB) using a single external memory interface
US14/096,987 2013-12-04
US14/096,949 US9104637B2 (en) 2013-12-04 2013-12-04 System and method for managing host bus adaptor (HBA) over infiniband (IB) using a single external memory interface
US14/097,009 2013-12-04
US14/097,009 US9311044B2 (en) 2013-12-04 2013-12-04 System and method for supporting efficient buffer usage with a single external memory interface
PCT/US2014/061640 WO2015084506A1 (en) 2013-12-04 2014-10-21 System and method for managing and supporting virtual host bus adaptor (vhba) over infiniband (ib) and for supporting efficient buffer usage with a single external memory interface

Related Child Applications (2)

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JP2019009655A Division JP6757808B2 (ja) 2013-12-04 2019-01-23 インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法
JP2019009654A Division JP6763984B2 (ja) 2013-12-04 2019-01-23 インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法

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JP2017501492A JP2017501492A (ja) 2017-01-12
JP2017501492A5 JP2017501492A5 (enExample) 2017-11-24
JP6492083B2 true JP6492083B2 (ja) 2019-03-27

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JP2019009654A Active JP6763984B2 (ja) 2013-12-04 2019-01-23 インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法
JP2019009655A Active JP6757808B2 (ja) 2013-12-04 2019-01-23 インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法

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JP2019009655A Active JP6757808B2 (ja) 2013-12-04 2019-01-23 インフィニバンド(IB)上で仮想ホストバスアダプタ(vHBA)を管理およびサポートするためのシステムおよび方法、ならびに単一の外部メモリインターフェイスを用いてバッファの効率的な使用をサポートするためのシステムおよび方法

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US (1) US9311044B2 (enExample)
EP (1) EP3077914B1 (enExample)
JP (3) JP6492083B2 (enExample)
CN (1) CN105793835B (enExample)
WO (1) WO2015084506A1 (enExample)

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CN109669788A (zh) * 2018-12-10 2019-04-23 西安微电子技术研究所 面向直接内存访问互连通信的多核芯片的mpi实现方法
EP3942422A4 (en) 2019-05-23 2022-11-16 Hewlett Packard Enterprise Development LP SYSTEM AND METHOD FOR ENABLING THE EFFICIENT MANAGEMENT OF NON-IDEMPOTENT OPERATIONS IN A NETWORK CARD (NIC)
CN112463654B (zh) * 2019-09-06 2025-11-21 华为技术有限公司 一种带预测机制的cache实现方法
CN110968530B (zh) * 2019-11-19 2021-12-03 华中科技大学 一种基于非易失性内存的键值存储系统和内存访问方法
CN113608686B (zh) * 2021-06-30 2023-05-26 苏州浪潮智能科技有限公司 一种远程内存直接访问方法及相关装置
CN117389733B (zh) * 2023-10-25 2024-04-26 无锡众星微系统技术有限公司 一种减少开关链开销的sas i/o调度方法和装置
CN117956054B (zh) * 2024-03-26 2024-06-11 上海云豹创芯智能科技有限公司 在rdma中实现定时器处理的方法、系统、芯片及存储介质

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Publication number Publication date
US9311044B2 (en) 2016-04-12
US20150154004A1 (en) 2015-06-04
JP2017501492A (ja) 2017-01-12
JP2019091483A (ja) 2019-06-13
CN105793835A (zh) 2016-07-20
JP6757808B2 (ja) 2020-09-23
JP2019091482A (ja) 2019-06-13
WO2015084506A1 (en) 2015-06-11
EP3077914A1 (en) 2016-10-12
CN105793835B (zh) 2018-09-07
JP6763984B2 (ja) 2020-09-30
EP3077914B1 (en) 2018-12-26

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