JP6487741B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device using a power transformer.

  FIG. 10 shows a conventional switching power supply device (for example, Patent Document 1). One terminal of the primary winding L1 of the power transformer T1 is connected to the positive input terminal IN +, and the other terminal is connected to the negative input terminal IN− via the power transistor MP2. The gate of the power transistor MP2 is connected to the output side of the drive circuit 110 composed of the PMOS transistor M11 and the NMOS transistor M12. The drive circuit 110 is controlled by the control circuit 120. A rectifying / smoothing circuit including a diode D1 and a capacitor C2 is connected to the secondary winding L2 of the power transformer T1. A series circuit of a Zener diode D2 and a photodiode PD is connected in parallel to the capacitor C2. The photodiode PD is coupled to the phototransistor PT, and a current flowing through the phototransistor PT is input to the control circuit 120.

  In this switching power supply device, the photodiode PD detects the output voltage VOUT generated between the positive output terminal OUT + and the negative output terminal OUT−, and the internal resistance of the phototransistor PT is controlled in accordance with the current flowing through the photodiode PD. Is done. Thereby, the transistors M11 and M12 of the drive circuit 110 are controlled by the control signal generated in the control circuit 120, and ON / OFF of the power transistor MP2 is controlled.

JP 2007-104759 A

  However, in the switching power supply device of FIG. 10, the drive circuit 110 controls the gate voltage VG2 of the power transistor MP2 with a rectangular wave. Therefore, when the power transistor MP2 is turned on, as shown in FIG. VG2 changes greatly from 0V to VDD. For this reason, since the surge current S1 flows in the drain current ID2 of the power transistor MP2, there is a problem that noise is generated by the surge current S1 and the conversion efficiency is lowered.

  An object of the present invention is to provide a switching power supply apparatus that suppresses a surge current when a power transistor is turned on, reduces switching noise, and improves conversion efficiency.

  In order to achieve the above object, an invention according to claim 1 is directed to an inductor or a power transformer, a power transistor that switches an input voltage of the inductor or the power transformer by turning ON / OFF, and an output of the inductor or the power transformer. In a switching power supply apparatus comprising: a rectifying / smoothing circuit that generates an output voltage from a side AC voltage; and a control circuit that controls ON / OFF of the power transistor, the control circuit includes a drive circuit, A power transistor OFF circuit that turns off the power transistor when the OFF voltage is valid; a level shift circuit that level-shifts the ON voltage that changes with a slope according to the level of the output voltage when the OFF voltage is invalid; The power transformer is controlled by the output of the level shift circuit. A buffer circuit for ON the power transistor after gradually closer to ON registers, characterized by having a.

  According to a second aspect of the present invention, in the switching power supply device according to the first aspect, the OFF voltage becomes effective every predetermined period.

  According to a third aspect of the present invention, there is provided a power transformer including a primary winding, a secondary winding, and an auxiliary winding, and a power transistor that is connected in series to the primary winding and switches an input voltage by turning on and off. And a rectifying / smoothing circuit that generates an output voltage from the AC voltage of the secondary winding, and ON / OFF control of the power transistor according to the output voltage of the rectifying / smoothing circuit and the voltage generated in the auxiliary winding The control circuit includes an OFF signal generation circuit, an ON timing signal generation circuit, and a drive circuit, and the OFF signal generation circuit has the power transistor ON. In response to the positive voltage generated in the auxiliary winding, and in response to the negative voltage generated in the auxiliary winding when the power transistor is turned off. A third capacitor to be electrified, and when the voltage of the third capacitor rises and reaches a first predetermined value, an effective OFF voltage is generated, and the ON timing signal generation circuit includes the rectifying and smoothing circuit The fourth capacitor is charged with a larger current as the output voltage is lower, an ON voltage is generated in the fourth capacitor, and the drive circuit turns off the power transistor when the OFF voltage is valid A power transistor OFF circuit, a level shift circuit for level shifting the ON voltage when the OFF voltage is invalid, and a buffer for turning on the power transistor after the power transistor is gradually brought close to ON by the output of the level shift circuit And a circuit.

  The invention according to claim 4 is the switching power supply device according to claim 3, wherein the fourth capacitor is charged according to the positive voltage generated in the auxiliary winding when the power transistor is turned on, The power transistor is discharged according to the negative voltage generated in the auxiliary winding when the power transistor is turned off.

  The invention according to claim 5 is the switching power supply device according to claim 1 or 3, wherein the power transistor OFF circuit of the drive circuit turns off the buffer circuit when the OFF voltage is valid, and the power transistor It is characterized by comprising a driver for turning on the twelfth transistor that turns off the transistor.

  According to a sixth aspect of the present invention, in the switching power supply device according to the first, third, or fifth aspect, the level shift circuit of the drive circuit is turned on when the OFF voltage is valid and turned off when the OFF voltage is invalid. 9, a PMOS or PNP tenth transistor generated between the voltage gate and source or between the base and emitter corresponding to the ON voltage when the ninth transistor is OFF, a current source, and the current A voltage source connected between the source and the source or emitter of the tenth transistor, and a common connection point between the current source and the voltage source is connected to the buffer circuit. .

According to a seventh aspect of the present invention, in the switching power supply device according to the third aspect, the control circuit further includes a voltage / current conversion circuit and a voltage clamp circuit, and the voltage / current conversion circuit includes the power transistor. A positive voltage generated in the auxiliary winding when turned on is converted into a positive current and output, and a negative voltage generated in the auxiliary winding when the power transistor is turned off is converted into a negative current and output. The voltage clamp circuit generates a first clamp voltage based on the positive current output from the voltage / current conversion circuit, and a second clamp voltage based on the negative current output from the voltage / current conversion circuit. And the third capacitor of the OFF signal generation circuit is charged with the first clamp voltage output from the voltage clamp circuit, and the second clamp voltage In is discharged, switching, characterized in that.

  The invention according to claim 8 is the switching power supply device according to claim 7, wherein the fourth capacitor of the ON timing signal generation circuit is charged with the first clamp voltage output from the voltage clamp circuit, Discharging with the second clamp voltage is characterized.

  According to a ninth aspect of the present invention, in the switching power supply device according to the seventh aspect, when the positive current is output from the voltage / current conversion circuit, the voltage clamp circuit supplies a base-emitter voltage to the first power source. A first transistor that generates a clamp voltage; a second transistor that generates a base-emitter voltage as the second clamp voltage when the negative current is output from the voltage / current conversion circuit; A first current mirror circuit group that outputs a current corresponding to the collector current of the second transistor as a charging current for the third capacitor; and a current corresponding to the collector current of the second transistor is discharged to the third capacitor. A second current mirror circuit group that outputs current and a collector current of the first transistor; Comprising the a third current mirror circuit group for outputting the current as a charging current to said fourth capacitor, and wherein the.

  According to a tenth aspect of the present invention, in the switching power supply device according to the ninth aspect, the voltage clamp circuit outputs a current corresponding to a collector current of the second transistor as a discharge current for the fourth capacitor. 4 current mirror circuit groups.

  The invention according to claim 11 is the switching power supply device according to claim 4, 8 or 10, characterized in that a second resistor is connected in series to the non-ground side of the fourth capacitor.

The invention according to claim 12 is the switching power supply device according to any one of claims 7 to 10, wherein the third resistor has one end connected to the gate of the power transistor and the other end of the third resistor. And a fifth capacitor connected between the input side of the voltage / current conversion circuit.

  According to the present invention, when the power transistor is turned on, the rise of the gate voltage is not abrupt. Therefore, the surge current immediately after the power transistor is turned on is greatly suppressed, and the transistor winding connected to the power transistor is used. Ringing due to the surge current can be suppressed and switching noise can be reduced. Further, the conversion efficiency can be increased by largely suppressing the surge current.

1 is a circuit diagram of a switching power supply device according to a first embodiment of the present invention. It is an operation | movement waveform diagram of the switching power supply device of a 1st Example. It is a circuit diagram of the switching power supply device of the 2nd Example of this invention. It is a circuit diagram of the switching power supply device of the 3rd Example of this invention. It is an operation | movement waveform diagram of the switching power supply device of a 3rd Example. It is a circuit diagram of the switching power supply device of the 4th Example of this invention. It is an operation | movement waveform diagram of the switching power supply device of a 4th Example. It is a circuit diagram of the switching power supply device of the 5th Example of this invention. It is an operation | movement waveform diagram of the switching apparatus of a 5th Example. It is a circuit diagram of the conventional switching power supply device. It is an operation | movement waveform diagram of the switching power supply device of FIG.

<First embodiment>
FIG. 1 shows a switching power supply device according to a first embodiment of the present invention. L0 is an inductor, and a series circuit of the inductor L0 and the power transistor MP1 is connected between the positive input terminal IN + and the negative input terminal IN−. An input voltage VIN is input between both input terminals IN + and IN−, and an input capacitor C1 is connected thereto. The diode D1 whose anode is connected to the common connection point of the inductor L0 and the power transistor MP1 and the output capacitor C2 connected to the cathode of the diode D1 constitute a rectifying and smoothing circuit. Both ends of the output capacitor C2 are connected to the positive output terminal OUT + and the negative output terminal IN−.

  When the power transistor MP1 is turned on, energy is accumulated in the inductor L0. When the power transistor MP1 is turned OFF, the diode D1 is turned on by the energy stored in the inductor L0 and the output capacitor C2 is charged with a voltage. Thereby, a voltage higher than the input voltage VIN can be obtained as the output voltage VOUT. Switching of the power transistor MP1 is driven by the drive circuit 10.

  The drive circuit 10 includes a level shift circuit 11, a buffer circuit 12, and a power transistor OFF circuit 13. Among them, the level shift circuit 11 includes an NMOS transistor M9 that inputs an OFF voltage to the gate, a PMOS transistor M10 that inputs an ON voltage to the gate, a shift voltage source Va, and a bias current source Ib. The power transistor OFF circuit 13 includes a driver 131 for inputting a voltage VOFF and an NMOS transistor M12 controlled by the driver 131. The buffer circuit 12 includes an NMOS transistor M11 that is controlled by the output voltage of the level shift circuit 11 and the control voltage of the driver 131. A common connection point between the transistors M11 and M12 is connected to the gate of the power transistor MP1.

  The ninth transistor in the claims is a transistor M9, the tenth transistor is a transistor M10, and the twelfth transistor is a transistor M12.

  Reference numeral 20 denotes an OFF signal generation circuit that periodically generates an “H” level voltage VOFF for turning off the power transistor MP1 at a predetermined period and inputs the voltage to the drive circuit 10. Reference numeral 30 denotes an output voltage feedback circuit that takes in the output voltage VOUT output to the positive output terminal OUT +. Reference numeral 40 denotes an ON timing signal generation circuit that generates a voltage VON for turning on the power transistor MP1 and inputs the voltage VON to the drive circuit 10.

  The ON timing signal generation circuit 40 takes in a voltage proportional to the output voltage VOUT output from the output voltage feedback circuit 30 and outputs a current Ic inversely proportional to the output voltage VOUT, and the current Ic is It is comprised with the capacitor | condenser C4 which produces | generates the voltage VON by being charged.

  Now, as shown in FIG. 2, when the voltage VOFF of the OFF signal generation circuit 20 is valid and is at the “H” level, the transistor M12 is turned on by the driver 131 of the power transistor OFF circuit 13, The power transistor MP1 is OFF because the gate voltage VG1 is "L". At this time, in the level shift circuit 11, since the transistor M9 is ON, the capacitor C4 of the ON timing signal generation circuit 40 is discharged, the voltage VON becomes the “L” level, and the transistor M10 is turned ON. ing. In the buffer circuit 12, since the gate of the transistor M11 is controlled to a low voltage by the driver 131, the transistor M11 is OFF.

  Next, when the voltage VOFF of the OFF signal generation circuit 20 becomes invalid and becomes “L” level, the driver 131 releases the control of turning off the transistor M12 and setting the gate of the transistor M11 to a low voltage. Further, the transistor M9 is turned off, charging of the capacitor C4 of the ON timing signal generation circuit 40 with the current Ic inversely proportional to the output voltage VOUT is started, and the voltage VON gradually increases.

  The transistor M10 is biased by the current of the current source Ib. When the transistor M9 is turned off, the voltage VON of the capacitor C4 is applied to the gate, and the source voltage increases in accordance with the increase in the voltage VON. The source voltage of the transistor M10 is shifted by the voltage source Va and applied to the gate of the transistor M11. As the voltage VON increases, the drain current of the transistor M11 gradually increases, and the gate voltage VG1 output from the drive circuit 10 gradually increases. Thereafter, when the gate voltage VG1 exceeds the threshold value Vth of the power transistor MP1, the power transistor MP1 is turned on and energy storage to the inductor L0 is started.

  As described above, in this embodiment, when the power transistor MP1 is turned on, the gate voltage VG1 gradually increases and then reaches the threshold value Vth to be completely turned on. That is, the gate voltage VG1 does not reach the threshold voltage Vth all at once from “L”. For this reason, the surge current generated when the power transistor MP1 is turned on can be greatly suppressed, the occurrence of ringing due to the surge current in the inductor L0 connected to the power transistor MP1 can be suppressed, and the switching noise can be reduced. Further, the conversion efficiency can be increased by largely suppressing the surge current.

<Second embodiment>
FIG. 3 shows a switching power supply device according to a second embodiment of the present invention. This embodiment is applied to an isolated flyback power supply apparatus in which the input side and the output side are electrically insulated by a power transformer T1. The primary winding L1 of the power transformer T1 and the power transistor MP1 are connected in series. This series circuit is connected between input terminals IN + and IN-. A rectifying / smoothing circuit including a diode D1 and an output capacitor C2 is connected to the secondary winding L2. The ● marks on the windings L1 and L2 indicate the beginning of winding.

  Also in this embodiment, when the power transistor MP1 is turned on, energy is stored in the power transformer T1. When the power transistor MP1 is turned off, the diode D1 is turned on by the energy stored in the power transformer T1 and the output capacitor C2 is charged with a voltage. Thereby, a voltage corresponding to the turn ratio between the primary side and the secondary side of the power transformer T1 can be obtained as the output voltage VOUT.

  Also in this embodiment, when the power transistor MP1 is turned on, the drive circuit 10 operates to reach the threshold value Vth after the gate voltage VG1 gradually increases. For this reason, the surge current generated when the power transistor MP1 is turned on can be greatly suppressed, and the occurrence of ringing due to the surge current in the windings L1 and L2 of the power transformer T1 connected to the power transistor MP1 can be suppressed. Noise can be reduced. Further, the conversion efficiency can be increased by largely suppressing the surge current.

<Third embodiment>
FIG. 4 shows a switching power supply device according to a third embodiment of the present invention. In this embodiment, a power transformer T2 having an auxiliary winding L3 is used in addition to the primary winding L1 and the secondary winding L2. The auxiliary winding L3 has a terminal opposite to the beginning of winding (marked with ●) connected to the negative input terminal IN− and the source of the power transistor MP1.

  In this embodiment, in order to control ON / OFF of the power transistor MP1, in addition to the configuration of the first and second embodiments, the voltage / current conversion circuit 50 and the voltage clamp circuit 60 are provided in addition to the power transformer T2. Prepare. The OFF signal generation circuit 20 includes a capacitor C3 and a comparator 21 that sets the output voltage VOFF to “H” when the capacitor C3 exceeds the voltage V1. The OFF signal generation circuit 20 described in the first and second embodiments is a circuit that periodically sets the voltage VOFF to “H”, but in the OFF signal generation circuit 20 of this embodiment, what is periodic? An unlimited voltage VOFF is output.

  The voltage / current conversion circuit 50 includes a resistor R1, one end of the resistor R1 is connected to the winding start (marked with ●) of the auxiliary winding L3 of the power transformer T2, and the other end is a node on the input side of the voltage clamp circuit 60. Connected to N1.

  The voltage clamp circuit 60 includes NPN transistors Q1, Q2, Q3, and Q4, PMOS transistors M1, M2, M3, M4, and M7, NMOS transistors M5, M6, and M8, and a constant current source Ia.

  The collector of the transistor Q1 and the emitter of the transistor Q2 are connected to the node N1 on the input side. The collector and base of the transistor Q1 are connected in common, and further connected to the base of the transistor Q3. Transistors Q1 and Q3 have a current mirror configuration with their emitters connected to ground.

  As a result, when a positive current flows from the node N1 into the voltage clamp circuit 60 (when the voltage VL3 generated in the auxiliary winding L3 is a positive voltage), the node N1 is a voltage between the base and emitter of the transistor Q1 ( Clamped to Vbe). This voltage is the “first clamp voltage”, and a current corresponding to this is output from the collector of the transistor Q3.

  The base of the transistor Q2 is commonly connected to the base and collector of the transistor Q4. The emitter of transistor Q4 is connected to the collector and base of transistor Q5, and the emitter of transistor Q5 is connected to ground. Since the current Ia flows from the constant current source Ia to the collector of the transistor Q4, the base-collector voltages of the transistors Q4 and Q5 are kept constant.

  Thereby, when a negative current flows out from the node N1 of the voltage clamp circuit 60 toward the voltage / current conversion circuit 50 (when the voltage VL3 generated in the auxiliary winding L3 is a negative voltage), the emitter voltage of the transistor Q2 is The transistor Q4 is clamped with a voltage (Vbe) that is lowered from the collector voltage (2Vbe) of the transistor Q2 by the base-emitter voltage (Vbe) of the transistor Q2. This voltage is the “second clamp voltage”, and a current corresponding thereto is taken out from the collector of the transistor Q2.

  The current flowing through the collector of the transistor Q3 is converted into a charging current flowing from the node N2 to the capacitor C3 by the current mirror circuit including the transistors M3 and M4. An OFF voltage VOFF is generated in the capacitor C3. Further, the current mirror circuit including the transistors M3 and M7 converts the current into a charging current flowing from the node N3 to the capacitor C4. A voltage VON is generated in the capacitor C4.

  On the other hand, the current flowing through the collector of the transistor Q2 is converted into a discharge current flowing through the capacitor C3 by the current mirror circuit including the transistors M1 and M2 and the current mirror circuit including the transistors M5 and M6. Further, the current is converted into a discharge current flowing in the capacitor C4 by the current mirror circuit including the transistors M1 and M2 and the current mirror circuit including the transistors M5 and M8.

  The first transistor described in the claims is composed of the transistor Q1, and the second transistor is composed of the transistor Q2. The first current mirror circuit group includes transistors Q1, Q3, M3, and M4. The second current mirror circuit group includes transistors Q2, M1, M2, M5, and M6. The third current mirror circuit group includes transistors Q1, Q3, M3, and M7. The fourth current mirror circuit group includes transistors Q2, M1, M2, M5, and M8. The third capacitor is constituted by a capacitor C3, and the fourth capacitor is constituted by a capacitor C4.

  Next, the operation will be described with reference to FIG. When the power transistor MP1 is ON, the voltage VL3 of the auxiliary winding L3 is a positive voltage, so that a positive current converted by the voltage / current conversion circuit 50 according to the positive voltage flows into the voltage clamp circuit 60. Then, a first clamp voltage is generated in the voltage clamp circuit 60. Thereby, in the voltage clamp circuit 60, currents corresponding to the first clamp voltage are individually output from the nodes N2 and N3 to charge the capacitors C3 and C4.

  When the voltage VOFF of the capacitor C3 increases to reach the reference voltage V1, the voltage output from the OFF signal generation circuit 20 becomes “H” indicating validity. For this reason, the transistor 131 is turned on by the driver 131, the gate voltage VG1 becomes "L", and the power transistor MP1 is turned off. Further, when the voltage VOFF becomes “H”, the transistor M9 is turned on, the capacitor C4 is instantaneously discharged, and the voltage VON becomes zero. Further, when the transistor M12 is ON, its gate is controlled to “L” by the driver 131 so that the transistor M11 is not ON.

  When the power transistor MP1 is turned off, a flyback voltage is generated in the secondary winding L2, the rectifier diode D1 is conducted, and the output capacitor C2 is charged. At this time, the voltage VL3 of the auxiliary winding L3 becomes a negative voltage. In response to the negative voltage, the negative current converted by the voltage / current conversion circuit 50 flows out from the voltage clamp circuit 60 to the voltage / current conversion circuit 50, and a second clamp voltage is generated in the voltage clamp circuit 60. As a result, in the voltage clamp circuit 60, currents corresponding to the second clamp voltage are individually drawn from the nodes N2 and N3, and the capacitors C3 and C4 are discharged.

  When the capacitor C3 is discharged and its voltage falls below the voltage V1, the output VOFF of the comparator 14 changes to “L” indicating invalidity. For this reason, the transistor 131 is turned off by the driver 131, and the operation of setting the gate of the transistor M11 to a low voltage is released.

  When the voltage VOFF changes to “L”, the transistor M9 is turned off, and the transistor M10 is controlled by the voltage VON of the capacitor C4. At this time, since the second clamp voltage is generated in the voltage clamp circuit 60, the node N3 draws current, but in the ON timing signal generation circuit 40, the current Ic is output from the timing current generation circuit 41. The capacitor C4 is charged by the difference between the two currents, and the voltage VON is input to the gate of the transistor M10 of the level shift circuit 11. The current Ic output from the timing current generation circuit 41 is a current that is inversely proportional to the output voltage VOUT. However, when the voltage VOUT is higher than a predetermined value (target value), the current Ic is small or 0A.

  Thereafter, when the voltage VON is increased by the current Ic, the source voltage of the transistor M10 biased by the current of the current source Ib is increased in conjunction with it. A voltage obtained by shifting the source voltage by the voltage source Va is applied to the gate of the transistor M11, the drain current of the transistor M11 gradually increases, and the gate voltage VG1 output from the drive circuit 10 becomes the voltage of the capacitor C4. It gradually increases as VOFF increases.

  When the gate voltage VG1 exceeds the threshold value Vth of the power transistor MP1, the power transistor MP1 is completely turned on.

  As described above, also in this embodiment, when the power transistor MP1 is turned on, the operation reaches the threshold value Vth after the gate voltage VG1 gradually increases, so that the surge current generated when the power transistor MP1 is turned on is greatly suppressed. can do. For this reason, it is possible to suppress ringing caused by a surge current in the windings L1, L2, and L3 of the power transformer T2 connected to the power transistor MP1, and to reduce switching noise. Further, the conversion efficiency can be increased by largely suppressing the surge current.

  In this embodiment, the node N3 of the voltage clamp circuit 60 is connected to the capacitor C4, but it is not always necessary to connect it. In this case, the capacitor C4 operates in the same manner as described with reference to FIGS.

<Fourth embodiment>
FIG. 6 shows a switching power supply apparatus according to a fourth embodiment of the present invention. In the present embodiment, in the switching power supply device of FIG. 4, a resistor R2 is further connected in series to the node N3 side (non-grounded side) of the capacitor C4. The resistor R2 constitutes the second resistor of the claims.

  The operation will be described with reference to FIG. When the power transistor MP1 is turned off and then the rectifier diode D1 is turned off, the drain voltage VD1 of the power transistor MP1 freely oscillates. Accordingly, the output voltage VL3 of the auxiliary winding L3 is proportionally centered on 0V. Vibrate. At this time, the free vibration charging / discharging current flows through the capacitor C4 and the resistor R2 connected in series therewith.

  At this time, when the voltage VL3 generated in the auxiliary winding L3 is positive, the charging current flows through the resistor R2 and the capacitor C4 due to the current flowing through the transistor M7. Therefore, the voltage VON generated at the node N3 By flowing from R2 to the capacitor C4, it becomes higher than the charging voltage of the capacitor C4 itself.

  On the other hand, when the voltage VL3 generated in the auxiliary winding L3 is negative, a discharge current flows through the resistor R2 and the capacitor C4 due to the current flowing through the transistor M8. Therefore, the voltage VON generated at the node N3 is the discharge current of the capacitor C4. To the resistor R2, the charging voltage of the capacitor C4 itself becomes lower.

  During such free oscillation, the voltage VON at the node N3 gradually increases while oscillating and is input to the gate of the transistor M10 to oscillate the source voltage of the transistor M10. Then, after the gate voltage of the transistor M11 gradually rises while oscillating, the gate voltage VG1 reaches the threshold value Vth and the power transistor MP1 is turned on.

  The timing at which the gate voltage VG1 of the power transistor MP1 reaches the threshold value Vth is when the output voltage VL3 of the auxiliary winding L3 is increasing. This time is when the drain voltage VD1 of the power transistor MP1 is low (see FIG. 7).

  As described above, even when free oscillation of the drain voltage VD1 of the power transistor MP1 occurs, a quasi-resonant switching operation in which the power transistor MP1 is turned on at the bottom timing of the drain voltage VD1 is realized. Further, noise generated at the ON timing of the power transistor MP1 can be further minimized.

<Fifth embodiment>
FIG. 8 shows a switching power supply device according to a fifth embodiment of the present invention. In the present embodiment, in the switching power supply device of FIG. 4, the resistor R3 is connected so that the resistor R3 is connected to the gate side of the power transistor MP1 and the capacitor C5 is connected to the input side of the voltage / current conversion circuit 50. A series circuit of a capacitor C5 was connected. The resistor R3 constitutes the third resistor of the claims, and the capacitor C5 constitutes the fifth capacitor of the claims.

  In the present embodiment, the voltage VON of the capacitor C4 gradually increases during the period in which the power transistor MP1 is OFF, and the gate voltage VG1 output from the drive circuit 10 also corresponds to the increase in voltage level shifted by the voltage source Va. Gradually rise. When free oscillation occurs in the discontinuous mode, the oscillation component of the voltage VL3 of the auxiliary winding L3 is superimposed on the gate voltage VG1 by the series circuit of the resistor R3 and the capacitor C5, so that the gate voltage VG1 rises while oscillating. The power transistor MP1 is completely turned on at a certain peak of the voltage.

  Thus, also in the present embodiment, quasi-resonant switching can be performed, and noise generated at the ON timing of the power transistor MP1 can be minimized.

10: drive circuit, 11: level shift circuit, 12: buffer circuit, 13: power transistor OFF circuit, 131: driver 20: OFF signal generation circuit, 21: converter 30: output voltage feedback circuit 40: ON timing signal generation circuit, 41: Timing current generation circuit 50: Voltage / current conversion circuit 60: Voltage clamp circuit 110: Drive circuit 120: Control circuit

Claims (12)

An inductor or a power transformer, a power transistor that switches an input voltage of the inductor or the power transformer by turning ON / OFF, a rectifying and smoothing circuit that generates an output voltage from an AC voltage on the output side of the inductor or the power transformer, and In a switching power supply device comprising a control circuit for controlling ON / OFF of a power transistor,
The control circuit includes a drive circuit;
The drive circuit includes a power transistor OFF circuit that turns off the power transistor when the OFF voltage is valid, and a level shift that level-shifts the ON voltage that changes with a slope corresponding to the level of the output voltage when the OFF voltage is invalid A switching power supply device comprising: a circuit; and a buffer circuit that turns on the power transistor after the power transistor is gradually brought close to ON by an output of the level shift circuit. The switching power supply device according to claim 1,
The switching power supply device, wherein the OFF voltage becomes effective every predetermined period. A power transformer including a primary winding, a secondary winding, and an auxiliary winding; a power transistor that is connected in series to the primary winding to switch an input voltage; and A rectifying / smoothing circuit for generating an output voltage from an AC voltage; and a control circuit for controlling ON / OFF of the power transistor in accordance with the output voltage of the rectifying / smoothing circuit and the voltage generated in the auxiliary winding. In switching power supply,
The control circuit includes an OFF signal generation circuit, an ON timing signal generation circuit, and a drive circuit,
The OFF signal generation circuit is charged in accordance with a positive voltage generated in the auxiliary winding when the power transistor is turned on, and in accordance with a negative voltage generated in the auxiliary winding when the power transistor is turned off. Having a third capacitor to be discharged, generating an effective OFF voltage when the voltage of the third capacitor rises and reaches a first predetermined value;
The ON timing signal generation circuit has a fourth capacitor that is charged with a larger current as the output voltage of the rectifying and smoothing circuit is lower, and an ON voltage is generated in the fourth capacitor,
The drive circuit includes a power transistor OFF circuit that turns off the power transistor when the OFF voltage is valid, a level shift circuit that level-shifts the ON voltage when the OFF voltage is invalid, and an output of the level shift circuit A buffer circuit for turning on the power transistor after gradually bringing the power transistor close to ON.
The switching power supply device characterized by the above-mentioned. In the switching power supply device according to claim 3,
The fourth capacitor is charged according to the positive voltage generated in the auxiliary winding when the power transistor is turned on, and is charged to the negative voltage generated in the auxiliary winding when the power transistor is turned off. A switching power supply device that is discharged in response. In the switching power supply device according to claim 1 or 3,
The power transistor OFF circuit of the drive circuit includes a driver that turns off the buffer circuit when the OFF voltage is valid and turns on a twelfth transistor that turns off the power transistor. Switching power supply device. In the switching power supply device according to claim 1, 3 or 5,
The level shift circuit of the drive circuit includes a ninth transistor that is turned on when the OFF voltage is valid and turned off when the OFF voltage is invalid, and a voltage gate corresponding to the ON voltage when the ninth transistor is off. A PMOS or PNP tenth transistor generated between the sources or between the base and the emitter, a current source, and a voltage source connected between the current source and the source or emitter of the tenth transistor A switching power supply device, wherein a common connection point between the current source and the voltage source is connected to the buffer circuit. In the switching power supply device according to claim 3 ,
The control circuit further includes a voltage / current conversion circuit and a voltage clamp circuit,
The voltage / current conversion circuit converts a positive voltage generated in the auxiliary winding into a positive current when the power transistor is turned on and outputs the positive current, and generates in the auxiliary winding when the power transistor is turned off. Convert negative voltage to negative current and output,
The voltage clamp circuit generates a first clamp voltage based on the positive current output from the voltage / current conversion circuit, and a second clamp voltage based on the negative current output from the voltage / current conversion circuit. Occur and
The third capacitor of the OFF signal generation circuit is charged with the first clamp voltage output from the voltage clamp circuit and discharged with the second clamp voltage.
The switching power supply device characterized by the above-mentioned.
The switch device according to claim 7,
The switch device, wherein the fourth capacitor of the ON timing signal generation circuit is charged with the first clamp voltage output from the voltage clamp circuit and discharged with the second clamp voltage. The switching power supply device according to claim 7,
The voltage clamp circuit includes a first transistor that generates a base-emitter voltage as the first clamp voltage when the positive current is output from the voltage / current conversion circuit, and the voltage / current conversion circuit A second transistor that generates a base-emitter voltage as the second clamp voltage when a negative current is output, and a current corresponding to the collector current of the first transistor as a charging current for the third capacitor A first current mirror circuit group for outputting, a second current mirror circuit group for outputting a current corresponding to the collector current of the second transistor as a discharge current for the third capacitor, A third capacitor that outputs a current corresponding to the collector current as a charging current for the fourth capacitor. Comprising a Ntomira circuit group, a
The switching power supply device characterized by the above-mentioned. In the switching power supply device according to claim 9,
The switching power supply device, wherein the voltage clamp circuit includes a fourth current mirror circuit group that outputs a current corresponding to a collector current of the second transistor as a discharge current for the fourth capacitor. The switching power supply device according to claim 4, 8 or 10,
A switching power supply device, wherein a second resistor is connected in series to the non-ground side of the fourth capacitor. The switching power supply device according to any one of claims 7 to 10,
A third resistor having one end connected to the gate of the power transistor, and a fifth capacitor connected between the other end of the third resistor and the input side of the voltage / current conversion circuit. Switching power supply device.

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