JP6485024B2 - Method for manufacturing thin film transistor substrate - Google Patents

Description

  The present disclosure relates to a method of manufacturing a thin film transistor substrate (TFT substrate) having a thin film transistor (TFT).

  In an active matrix display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device, a TFT substrate on which TFTs are formed as switching elements or driving elements is used. For example, Patent Document 1 discloses an active matrix organic EL display device using a TFT substrate. The TFT includes a gate electrode, a semiconductor layer (channel layer) formed to face the gate electrode, and a source electrode and a drain electrode connected to the semiconductor layer.

  An interlayer insulating film is formed on the TFT substrate. The interlayer insulating film is formed between conductive members (wirings and electrodes) formed in different layers, or formed between a conductive member formed in different layers and a semiconductor layer. For example, in a TFT, an interlayer insulating film is formed between a gate electrode and a semiconductor layer, and between a semiconductor layer and a source electrode and a drain electrode.

  In addition, an opening (contact hole) is formed in the interlayer insulating film in order to electrically connect conductive members of different layers or to electrically connect the conductive member and the semiconductor layer. The opening of the interlayer insulating film is formed using, for example, a photolithography method and an etching method.

JP 2010-27584 A

  When forming openings in the interlayer insulating film, a plurality of openings may be formed at the same time. In this case, if the exposed conductive member and semiconductor layer are formed in different layers, a plurality of openings having different depths are formed simultaneously.

  At this time, there may be a problem that a plurality of openings having different depths cannot be formed in a predetermined shape and size, and there is a problem that the yield of the TFT substrate is lowered.

  An object of the technology of the present disclosure is to provide a manufacturing method of a TFT substrate capable of forming a plurality of openings having different depths without reducing the yield.

In order to achieve the above object, one aspect of a method of manufacturing a thin film transistor substrate is a method of manufacturing a thin film transistor substrate in which a thin film transistor having a semiconductor layer having a predetermined shape and a conductive member having a predetermined shape are formed. Forming a first insulating film so as to cover one of the conductive members, and covering the semiconductor layer and the other member of the conductive member on the first insulating film. A step of forming two insulating films, and a first opening and a second opening in the laminated film including the first insulating film and the second insulating film so that each of the one member and the other member is exposed. Forming an opening, and the opening forming step includes:
A pre-etching step of forming an opening by etching the laminated film of at least the upper part of the one member halfway, and the laminated film of the upper part of the one member corresponding to the opening after the pre-etching step And the laminated film in the upper part of the other member are exposed to form the first opening by exposing the one member and the second opening by exposing the other member. And a subsequent etching step to be formed.

  A plurality of openings having different depths can be formed without reducing the yield.

It is a partially cutaway perspective view of an organic EL display device according to an embodiment. It is an electric circuit diagram which shows the structure of the pixel circuit in the organic electroluminescence display which concerns on embodiment. It is a fragmentary sectional view of a TFT substrate concerning an embodiment. It is sectional drawing for demonstrating the board | substrate preparation process in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the 1st electroconductive member formation process in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the 1st insulating film formation process in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the semiconductor layer formation process in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the 2nd insulating film formation process in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the 2nd conductive member formation process (conductive film formation process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the 2nd conductive member formation process (conductive film patterning process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (mask formation process) in the manufacturing method of the TFT substrate of a comparative example. It is sectional drawing for demonstrating the opening part formation process (etching process) in the manufacturing method of the TFT substrate of a comparative example. It is sectional drawing for demonstrating the opening part formation process (mask removal process) in the manufacturing method of the TFT substrate of a comparative example. It is sectional drawing for demonstrating the opening part formation process (1st mask formation process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (1st etching process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (1st mask removal process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (2nd mask formation process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (2nd etching process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (2nd mask removal process) in the manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (1st mask formation process) in the other manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (1st etching process) in the other manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (1st mask removal process) in the other manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (2nd mask formation process) in the other manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (2nd etching process) in the other manufacturing method of the TFT substrate which concerns on embodiment. It is sectional drawing for demonstrating the opening part formation process (2nd mask removal process) in the other manufacturing method of the TFT substrate which concerns on embodiment. It is a fragmentary sectional view of a TFT substrate concerning a modification. It is sectional drawing for demonstrating the opening part formation process (before 1st etching process) in the manufacturing method of the TFT substrate which concerns on a modification. It is sectional drawing for demonstrating the opening part formation process (1st etching process) in the manufacturing method of the TFT substrate which concerns on a modification. It is sectional drawing for demonstrating the opening part formation process (2nd etching process) in the manufacturing method of the TFT substrate which concerns on a modification. It is sectional drawing for demonstrating the opening part formation process (3rd etching process) in the manufacturing method of the TFT substrate which concerns on a modification. It is sectional drawing for demonstrating the opening part formation process (before a 1st etching process) in the other manufacturing method of the TFT substrate which concerns on a modification. It is sectional drawing for demonstrating the opening part formation process (1st etching process) in the other manufacturing method of the TFT substrate which concerns on a modification. It is sectional drawing for demonstrating the opening part formation process (2nd etching process) in the other manufacturing method of the TFT substrate which concerns on a modification.

  Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present disclosure. Accordingly, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present disclosure. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

(Embodiment)
First, a configuration of an organic EL display device will be described as an example of a display device using a thin film transistor substrate (TFT substrate).

[Organic EL display device]
FIG. 1 is a partially cutaway perspective view of an organic EL display device according to an embodiment. FIG. 2 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. Note that the pixel circuit illustrated in FIG. 2 is an example, and is not limited to the configuration illustrated in FIG.

  As shown in FIG. 1, the organic EL display device 100 includes a TFT substrate 110 on which a TFT is formed, and an organic EL element 130 (light emitting unit) formed on the TFT substrate 110.

  The organic EL element 130 has a laminated structure of an anode 131 as a lower electrode, an organic EL layer (light emitting layer) 132, and a cathode 133 as an upper electrode.

  The TFT substrate 110 in the present embodiment is a TFT array substrate having a plurality of TFTs. The organic EL element 130 is formed on an interlayer insulating film (planarization layer) formed so as to cover a plurality of TFTs.

  The organic EL display device 100 is a top emission type that emits light of the organic EL element 130 from the side opposite to the TFT substrate 110 side. In this case, the anode 131 as a lower electrode is a reflective electrode made of metal or the like, and the cathode 133 as an upper electrode is a transparent electrode made of ITO or the like. The organic EL display device 100 is not limited to the top emission type, but may be a bottom emission type that emits light from the organic EL element 130 from the TFT substrate 110 side.

  The TFT substrate 110 has a plurality of pixels 120 in a matrix form. Each of the plurality of pixels 120 is provided with a pixel circuit constituted by one or more circuit elements such as TFTs and capacitor elements. Each of the plurality of pixels 120 is driven and controlled by a pixel circuit provided for each pixel 120.

  The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 has a configuration in which an organic EL layer 132 is disposed between an anode 131 and a cathode 133. A hole transport layer is further provided between the anode 131 and the organic EL layer 132, and an electron transport layer is further provided between the organic EL layer 132 and the cathode 133. Note that another functional layer may be provided between the anode 131 and the cathode 133.

  The TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and a plurality of gate wirings 140 arranged along the column direction of the pixels 120 so as to intersect the gate wiring 140. Source wiring (signal wiring) 150 and a plurality of power supply wirings 160 (not shown in FIG. 1) arranged in parallel with the source wiring 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.

  The gate wiring 140 is connected to the gate electrode G2 of the switching transistor SwTr included in each pixel circuit for each row. The source line 150 is connected to the source electrode S2 of the switching transistor SwTr included in each pixel circuit for each column. The power supply wiring 160 is connected to the drain electrode D1 of the drive transistor DrTr included in each pixel circuit for each column.

  As shown in FIG. 2, each pixel 120 includes a TFT portion that is a region where a TFT is formed, and a storage capacitor portion that is a region where a capacitive element Cs including a pair of electrodes is formed. Specifically, the pixel circuit in each pixel 120 includes a TFT formed as a drive transistor DrTr, a TFT formed as a switching transistor SwTr, and a capacitive element formed as a storage capacitor (retention capacitor) that stores a data voltage. Cs (capacitor). In the present embodiment, the drive transistor DrTr is a TFT for driving the organic EL element 130, and the switching transistor SwTr is a TFT for selecting the pixel 120 to emit light.

  The switching transistor SwTr includes a gate electrode G2 connected to the gate wiring 140, a source electrode S2 connected to the source wiring 150, a drain electrode connected to one electrode of the capacitive element Cs and the gate electrode G1 of the driving transistor DrTr. D2 and a semiconductor layer (not shown) functioning as a channel layer. When a predetermined voltage is applied to the gate wiring 140 and the source wiring 150 connected to the switching transistor SwTr, the voltage applied to the source wiring 150 is held in the capacitor Cs as a data voltage.

  The drive transistor DrTr includes a gate electrode G1 connected to the drain electrode D2 of the switching transistor SwTr and the other electrode of the capacitor element Cs, a drain electrode D1 connected to the power supply wiring 160, an anode 131 of the organic EL element 130, and a capacitor. A source electrode S1 connected to the other electrode of the element Cs and a semiconductor layer (not shown) functioning as a channel layer are provided. The drive transistor DrTr supplies a current corresponding to the data voltage held by the capacitive element Cs from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S1. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the organic EL layer emits light.

  Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the switching transistor SwTr and the drive transistor DrTr in each pixel 120, and a desired image is displayed.

[TFT substrate]
Next, the TFT substrate 110 according to the embodiment will be described.

  The TFT substrate 110 includes a thin film transistor having a semiconductor layer with a predetermined shape and a conductive member with a predetermined shape. The conductive member is made of a conductive material, and is, for example, an electrode or a wiring.

  The TFT substrate 110 includes a first insulating film formed so as to cover one member of the semiconductor layer and the conductive member, and a first insulating film so as to cover the other member of the semiconductor layer and the conductive member. And a second insulating film formed thereon. The first insulating film and the second insulating film are interlayer insulating films in the TFT substrate 110.

  Hereinafter, a specific configuration of the TFT substrate 110 according to the present embodiment will be described with reference to FIG. FIG. 3 is a partial cross-sectional view of the TFT substrate 110 according to the embodiment. In FIG. 3, the drive transistor DrTr is shown as a TFT in the TFT portion.

  As shown in FIG. 3, the TFT substrate 110 includes a first conductive member 21 located above the substrate 10, a first insulating film 31 located above the first conductive member 21, and above the first insulating film 31. , The second insulating film 32 positioned above the semiconductor layer 40, and the second conductive member 22 positioned above the second insulating film 32. Note that an insulating film may be further formed on the second conductive member 22 as a passivation film or an interlayer insulating film.

  The TFT substrate 110 has a laminated structure of a wiring layer (conductive layer), a semiconductor layer, and an insulating layer. As shown in FIG. 3, in the present embodiment, the first wiring layer WL21, the first insulating layer IL31, and the semiconductor It has a layer 40, a second insulating layer IL32, and a second wiring layer WL22.

  In the first wiring layer WL21 and the second wiring layer WL22, conductive members such as an electrode of the drive transistor DrTr, an electrode of the capacitive element Cs, and various wirings are formed by patterning the same conductive film.

  In the present embodiment, the first wiring layer WL21 is a gate metal layer, and the first wiring layer WL21 includes a gate electrode 21T, a first capacitor electrode 21C, and a first wiring 21L as the first conductive member 21. Is formed. On the other hand, the second wiring layer WL22 is a source / drain metal layer. The second wiring layer WL22 includes a source electrode 22S, a drain electrode 22D, a second capacitor electrode 22C, and a second wiring as the second conductive member 22. 22L is formed.

  In addition, an insulating film is formed as an interlayer insulating film in the first insulating layer IL31 and the second insulating layer IL32.

  In the present embodiment, a first insulating film 31 is formed in the first insulating layer IL31. A second insulating film 32 is formed on the second insulating layer IL32. The first insulating film 31 and the second insulating film 32 have a laminated structure, and the first insulating film 31 and the second insulating film 32 constitute a laminated film (insulating laminated film) 30.

  The drive transistor DrTr is a TFT having a bottom gate structure, and includes a gate electrode 21T, a semiconductor layer 40 facing the gate electrode 21T, a source electrode 22S (S1 in FIG. 2) electrically connected to the semiconductor layer 40, and a drain. Electrode 22D (D1 in FIG. 2). Further, the first insulating film 31 between the gate electrode 21T and the semiconductor layer 40 functions as a gate insulating film in the driving transistor DrTr, and the semiconductor layer 40 functions as a channel layer in the driving transistor DrTr. In the present embodiment, the drive transistor DrTr is a channel protection type (channel etching stopper type) TFT. In the drive transistor DrTr, the source electrode 22S and the drain electrode 22D have a top contact structure.

  The capacitive element Cs has the first capacitive electrode 21C as one electrode and the second capacitive electrode 22C as the other electrode. The first capacitor electrode 21C and the second capacitor electrode 22C are arranged to face each other with the first insulating film 31 in a cross-sectional view. The first insulating film 31 between the first capacitor electrode 21C and the second capacitor electrode 22C functions as a dielectric (dielectric film) in the capacitor element Cs. The first capacitor electrode 21C and the second capacitor electrode 22C have an overlapping region (overlapping region) in plan view, and the overlapping region functions as a storage capacitor.

  A plurality of openings (contact holes) are formed in the laminated film 30 in the TFT substrate 110. Specifically, the stacked film 30 is formed with a first opening CH1, a second opening CH2, and a third opening CH3.

  The first opening CH1 is formed so as to penetrate both the second insulating film 32 and the first insulating film 31. The second conductive member 22 formed in the second wiring layer WL22 is connected to the first conductive member 21 formed in the first wiring layer WL21 through the first opening CH1. Specifically, the second wiring 22L is connected (gate contact) to the first wiring 21L of the gate metal layer through the first opening CH1. That is, the first opening CH1 is a through hole for connecting the first wiring 21L and the second wiring 22L.

  The second opening CH2 and the third opening CH3 are formed so as to penetrate only the second insulating film 32 in the stacked film 30. The second conductive member 22 formed in the second wiring layer WL22 is connected to the semiconductor layer 40 through the second opening CH2 and the third opening CH3. Specifically, the source electrode 22S and the drain electrode 22D are connected (ohmic contact) to the semiconductor layer 40 through the second opening CH2. The second capacitor electrode 22C is connected (ohmic contact) to the semiconductor layer 40 via the third opening CH3. That is, the second opening CH2 is a through hole for connecting the source electrode 22S and the drain electrode 22D and the semiconductor layer 40, and the third opening CH3 connects the second capacitor electrode 22C and the semiconductor layer 40. It is a through hole for doing.

  The semiconductor layer 40 is not limited to being directly connected to the source electrode 22S and the drain electrode 22D (or the second capacitor electrode 22C), but is indirectly connected through a conductive material or a semiconductor material. It may be.

  Hereinafter, the constituent members of each layer in the TFT substrate 110 will be described in detail.

[substrate]
The substrate 10 is, for example, a glass substrate, but is not limited to a glass substrate, and may be a resin substrate or the like. Further, the substrate 10 may be a flexible substrate instead of a rigid substrate. An undercoat layer made of silicon nitride or silicon oxide may be formed on the surface of the substrate 10.

[First wiring layer]
The first wiring layer WL <b> 21 is a lowermost wiring layer among the plurality of wiring layers, and is a layer located immediately above the substrate 10. In the first wiring layer WL21, a first conductive member 21 patterned in a predetermined shape is formed.

  The first conductive member 21 has a single-layer structure or a multi-layer structure of a conductive film made of a conductive material such as metal or an alloy thereof. For example, molybdenum (Mo), aluminum (Al), copper (Cu), tungsten ( W), titanium (Ti), manganese (Mn), chromium (Cr), tantalum (Ta), niobium (Nb), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), indium ( In), nickel (Ni), neodymium (Nd), or the like, or an alloy of metals selected from these metals (such as molybdenum tungsten (MoW)). In addition, the material of the 1st electrically-conductive member 21 is not restricted to these materials, You may be comprised by electroconductive metal oxides, such as indium tin oxide (ITO), or an electroconductive polymer material.

  As described above, the first conductive member 21 is, for example, the gate electrode 21T, the first capacitor electrode 21C, and the first wiring 21L. That is, the first capacitor electrode 21C and the first wiring 21L are formed in the same layer as the gate electrode 21T.

  As shown in FIG. 3, the gate electrode 21T, the first capacitor electrode 21C, and the first wiring 21L are formed continuously and integrally, but may be formed separately from each other. Further, the electrode or wiring formed in the first wiring layer WL21 is not limited to the gate electrode 21T, the first capacitance electrode 21C, and the first wiring 21L, and other electrodes and wirings are included in the first wiring layer WL21. May be formed.

[First insulating layer]
The first insulating layer IL31 is the lowermost insulating layer among the plurality of insulating layers. The first insulating layer IL31 is a layer between the first wiring layer WL21 and the semiconductor layer 40, and is located on the first wiring layer WL21.

  As described above, the first insulating film 31 is formed in the first insulating layer IL31. The first insulating film 31 is formed between the first conductive member 21 and the semiconductor layer 40. The first insulating film 31 is also formed in a region where the first conductive member 21 and the semiconductor layer 40 are not formed. For example, the first insulating film 31 is also formed between the first conductive member 21 and the second insulating film 32 and between the substrate 10 and the second insulating film 32.

  In the present embodiment, as shown in FIG. 3, the first insulating film 31 is formed on the entire surface of the substrate 10 so as to cover the first conductive member 21.

  The first insulating film 31 is made of a material having electrical insulating properties. As an example, the first insulating film 31 is a single layer such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a hafnium oxide film. The insulating film is a film or a laminated film in which a plurality of these films are stacked.

  In the present embodiment, the first insulating film 31 is made of a compound containing silicon, and is, for example, a stacked film of a silicon oxide film (90 nm) and a silicon nitride film (70 nm). In this case, the film immediately above the first conductive member 21 may be a silicon nitride film (SiN), and the film in contact with the semiconductor layer 40 may be a silicon oxide film (SiO). This is because when an oxide semiconductor is used as the material of the semiconductor layer 40, the silicon nitride film generates more hydrogen during film formation than the silicon oxide film, and the semiconductor layer is affected by the hydrogen contained in the silicon nitride film. This is because 40 characteristic fluctuations are likely to occur. Another reason is that the variation in TFT characteristics due to fixed charges at the interface between the oxide semiconductor and the insulating film is smaller in the silicon oxide film than in the silicon nitride film.

[Semiconductor layer]
The semiconductor layer 40 is formed in a predetermined shape on the first insulating film 31. For example, the semiconductor layer 40 is formed in an island shape on the first insulating film 31 that functions as a gate insulating film. The semiconductor layer 40 is formed to face the gate electrode 21T with the first insulating film 31 interposed therebetween.

The semiconductor layer 40 is an oxide semiconductor layer made of, for example, a transparent amorphous oxide semiconductor (TAOS) such as InGaZnO _x (IGZO). The material of the oxide semiconductor layer is not limited to IGZO, and may be InWZnO _X , InSiO _X, or the like. The semiconductor layer 40 is not limited to an oxide semiconductor layer, and may be a silicon semiconductor layer made of crystalline silicon or amorphous silicon.

  The semiconductor layer 40 in the TFT portion and the semiconductor layer 40 in the storage capacitor portion are integrally connected, but may be separated. Further, the semiconductor layer 40 may not be formed in the storage capacitor portion.

[Second insulating layer]
The second insulating layer IL32 is the second insulating layer from the bottom among the plurality of insulating layers. The second insulating layer IL32 is a layer between the semiconductor layer 40 and the second wiring layer WL22, and is located on the semiconductor layer 40.

  As described above, the second insulating film 32 is formed in the second insulating layer IL32. The second insulating film 32 is formed between the semiconductor layer 40 and the second conductive member 22. The second insulating film 32 is also formed in a region where the semiconductor layer 40 and the second conductive member 22 are not formed.

  In the present embodiment, the second insulating film 32 is formed on the entire surface of the first insulating film 31 so as to cover the semiconductor layer 40.

  The second insulating film 32 on the semiconductor layer 40 functions as a channel protective film (channel etching stopper) that protects the channel region of the semiconductor layer 40. Specifically, the second insulating film 32 on the semiconductor layer 40 prevents the semiconductor layer 40 from being etched when the source electrode 22S and the drain electrode 22D are patterned on the semiconductor layer 40 by etching.

  The second insulating film 32 is made of an electrically insulating material and can be formed using the same material as the first insulating film 31. The second insulating film 32 is a single layer film as an example, but may be a laminated film in which a plurality of films are laminated.

  In the present embodiment, the second insulating film 32 is made of a compound containing silicon, and is, for example, a single layer film of a silicon oxide film (200 nm). As described above, since an oxide semiconductor is easily damaged by hydrogen, when an oxide semiconductor is used as the material of the semiconductor layer 40, the second insulating film 32 generates hydrogen during film formation as compared with a silicon nitride film. A silicon oxide film with a small amount may be used.

  When the second insulating film 32 is a laminated film, an aluminum oxide film that can block hydrogen and oxygen is preferably used. For example, as the second insulating film 32, a laminated film having a three-layer structure of a silicon oxide film, an aluminum oxide film, and a silicon oxide film can be used.

[Second wiring layer]
The second wiring layer WL22 is the second wiring layer from the bottom among the plurality of wiring layers. The second wiring layer WL22 is located on the second insulating layer IL32. A second conductive member 22 patterned in a predetermined shape is formed on the second wiring layer WL22.

  The material of the second conductive member 22 is a single layer structure or a multilayer structure of a conductive film made of a conductive material such as metal or an alloy thereof, and the same material as the material of the first conductive member 21 can be used.

  As described above, the second conductive member 22 is, for example, the source electrode 22S, the drain electrode 22D, and the second wiring 22L. That is, the second wiring 22L is formed in the same layer as the source electrode 22S and the drain electrode 22D. Note that other electrodes and wirings may be formed in the second wiring layer WL22.

[TFT substrate manufacturing method]
Next, an outline of a method for manufacturing the TFT substrate 110 according to the embodiment will be described with reference to FIGS. 4A to 4H. 4A to 4H are cross-sectional views of each step in the manufacturing method of the TFT substrate 110 according to the embodiment.

  First, as shown to FIG. 4A, the board | substrate 10 is prepared (board | substrate preparation process). For example, a glass substrate is prepared as the substrate 10. If necessary, an undercoat layer such as a silicon nitride film or a silicon oxide film may be formed on the surface of the substrate 10.

  Next, as shown in FIG. 4B, a first conductive member 21 having a predetermined shape is formed above the substrate 10 (first conductive member forming step). For example, after a conductive film such as a metal film (gate metal film) is formed on the substrate 10 by a sputtering method, the conductive film is processed using a photolithography method and a wet etching method, whereby a predetermined shape of the first film is formed. 1 Conductive member 21 is formed.

  In the present embodiment, as the first conductive member 21, a gate electrode 21T, a first capacitor electrode 21C, and a first wiring 21L are formed. In the case where an undercoat layer is formed on the surface of the substrate 10, the first conductive member 21 is formed on the undercoat layer.

  Next, as shown in FIG. 4C, a first insulating film 31 is formed so as to cover the first conductive member 21 (first insulating film forming step). Specifically, the first insulating film 31 is formed on the entire surface of the substrate 10 so as to cover the gate electrode 21T, the first capacitor electrode 21C, and the first wiring 21L.

As a method of forming the first insulating film 31, for example, a plasma CVD (Chemical Vapor Deposition) method or the like can be used. For example, a silicon oxide film can be formed by a plasma CVD method using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as introduction gases. Further, a silicon nitride film can be formed by a plasma CVD method using silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) as an introduction gas.

  Next, as shown in FIG. 4D, a semiconductor layer 40 having a predetermined shape is formed on the first insulating film 31 so as to face at least the gate electrode 21T (semiconductor layer forming step). In the present embodiment, the semiconductor layer 40 made of IGZO is formed in an island shape on the first insulating film 31 above the gate electrode 21T and the first capacitor electrode 21C.

Specifically, first, an IGZO film is formed on the first insulating film 31 by a sputtering method or the like. For example, using a target material containing In, Ga, and Zn, argon (Ar) gas as an inert gas flows into the vacuum chamber and a gas containing oxygen (O ₂ ) as a reactive gas flows. A voltage having a power density of 1 is applied to the target material. Thereby, an IGZO film can be formed. Thereafter, the semiconductor layer 40 having a predetermined shape can be formed by processing the IGZO film using a photolithography method and a wet etching method.

  Next, as shown in FIG. 4E, the second insulating film 32 is formed on the semiconductor layer 40 (second insulating film forming step). Specifically, the second insulating film 32 is formed on the entire surface of the substrate 10 so as to cover the semiconductor layer 40 and the first insulating film 31. Thereby, the laminated film 30 in which the first insulating film 31 and the second insulating film 32 are laminated can be formed.

  The second insulating film 32 can be formed by the same method as the first insulating film 31. For example, a silicon oxide film can be formed as the second insulating film 32 by plasma CVD.

  Next, as shown in FIG. 4F, a plurality of openings (contact holes) are formed in the laminated film 30 so that a part of the first conductive member 21 and a part of the semiconductor layer 40 are exposed (opening part). Forming step). For example, a part of the laminated film 30 is removed by etching to form through holes in the laminated film 30 to form a plurality of openings.

  Specifically, the first opening CH1 is formed in the laminated film 30 so that the first wiring 21L (first conductive member 21) is exposed. In addition, two second openings CH2 are formed in the stacked film 30 so that the semiconductor layer 40 above the gate electrode 21T is exposed. The third opening CH3 is formed in the stacked film 30 so that the semiconductor layer 40 above the first capacitor electrode 21C is exposed.

  At this time, in the present embodiment, the first opening CH1 and the second opening CH2 (or the third opening CH3) having different depths are formed by two etching steps. A specific method for forming the first opening CH1, the second opening CH2, and the third opening CH3 will be described later.

  Next, as shown in FIG. 4G, a conductive film 22F such as a metal film (source / drain metal film) is formed on the second insulating film 32 by a sputtering method so as to cover a plurality of openings formed in the stacked film 30. A film is formed (conductive film forming step). At this time, the conductive film 22F is in contact with the first wiring 21L through the first opening CH1, and is in contact with the semiconductor layer 40 through the second opening CH2 and the third opening CH3.

  Next, as shown in FIG. 4H, the second conductive member 22 having a predetermined shape is formed by processing the conductive film 22F by photolithography and wet etching (conductive film patterning step).

  In the present embodiment, as the second conductive member 22, a source electrode 22S, a drain electrode 22D, and a second wiring 22L are formed.

  Although not shown, a passivation film made of silicon nitride or silicon oxide may be formed so as to cover the whole. The passivation film can be formed by plasma CVD or the like.

[Features of the present disclosure]
Hereinafter, characteristic contents in the manufacturing method of the TFT substrate 110 according to the present embodiment will be described including the background to the technology of the present disclosure.

  On the TFT substrate, a plurality of insulating films are formed as interlayer insulating films. An opening (contact hole) is formed in the interlayer insulating film in order to connect the conductive members of different layers or to electrically connect the conductive member and the semiconductor layer.

  For example, in the structure of the TFT substrate 110 as shown in FIG. 3, it is necessary to form a plurality of openings having different depths in the laminated film 30 in which the first insulating film 31 and the second insulating film 32 are laminated. is there. Specifically, the first opening CH1 for connecting the first wiring 21L and the second wiring 22L, and the second opening CH2 for connecting the source electrode 22S / drain electrode 22D and the semiconductor layer 40, The third opening CH3 for connecting the second capacitor electrode 22C and the semiconductor layer 40 needs to be formed, and the depth of the first opening CH1 is the second opening CH2 (or the third opening). It becomes deeper than the depth of CH3).

  In this case, for example, the first opening CH1, the second opening CH2, and the third opening CH3 can be formed by the method shown in FIGS. 5A to 5C. 5A to 5C are cross-sectional views for explaining an opening forming step in the manufacturing method of the TFT substrate of the comparative example.

  First, similarly to the method shown in FIGS. 4A to 4E, the first conductive member 21 is formed on the substrate 10, the first insulating film 31 is formed so as to cover the first conductive member 21, and the first A semiconductor layer 40 is formed on the insulating film 31, and a second insulating film 32 is formed so as to cover the semiconductor layer 40.

  Next, as illustrated in FIG. 5A, a resist mask 500 having mask openings 500 a, 500 b, and 500 c is formed on the stacked film 30.

  Next, as shown in FIG. 5B, dry etching is performed using the resist mask 500 as a mask. Accordingly, the first opening 300a, the second opening 300b, and the third opening 300c can be simultaneously formed in the laminated film 30 corresponding to each of the mask openings 500a, 500b, and 500c. At this time, the first opening 300a is formed so that the first wiring 21L (first conductive member 21) is exposed. The second opening 300b and the third opening 300c are formed so that the semiconductor layer 40 is exposed.

  Next, as shown in FIG. 5C, the resist mask 500 is removed. Thereby, the first opening CH1, the second opening CH2, and the third opening CH3 can be formed in the stacked film 30.

  However, in the method shown in FIGS. 5A to 5C, a plurality of openings having different depths are simultaneously formed in one etching process, so that the second opening CH2 and the third opening CH3 having the shallower depth are formed. The (second opening 300b and the third opening 300c) are etched as compared with the first opening CH1 (first opening 300a) having a deep depth because the portion of the stacked film 30 to be etched is only the second insulating film 32. The film thickness of the laminated film 30 is thin. Therefore, the shallower second opening 300b and third opening 300c reach the semiconductor layer 40 before the first opening 300a reaches the first wiring 21L.

  In this case, the opening diameters (contact diameters) of the second opening CH2 and the third opening CH3 are expanded by the receding of the resist mask during etching, and a plurality of openings having different depths are formed with predetermined shapes and dimensions. There is a problem that you can not.

  In addition, when the second opening 300b and the third opening 300c reach the semiconductor layer 40 first, if the semiconductor layer 40 has a defect, there is a possibility that a short-circuit defect may occur due to the penetration of the contact.

  Furthermore, when a plurality of openings having different depths are formed at the same time, the etching time is adjusted to the first opening 300a formed deeper. For this reason, since one etching time becomes long, problems, such as a throughput fall and the electrode temperature of a dry etching apparatus rise, also generate | occur | produce.

  As described above, in the method of simultaneously forming a plurality of openings having different depths, various problems occur, resulting in a problem that the yield of the TFT substrate is lowered.

  The manufacturing method of the TFT substrate 110 according to the present embodiment is based on such knowledge, and the step of forming the first insulating film so as to cover one member of the semiconductor layer and the conductive member. (First insulating film forming step), a step of forming a second insulating film on the first insulating film so as to cover the other member of the semiconductor layer and the conductive member (second insulating film forming step), Forming a first opening and a second opening in the laminated film including the first insulating film and the second insulating film so that each of the one member and the other member is exposed (opening forming step). Contains.

  Then, the opening forming process includes a pre-etching process in which the upper part of at least one member (a member on the lower layer side) is etched halfway to form an opening, a pre-etching process, and a pre-etching process. One member is exposed by etching the laminated film in the upper part of one member (lower layer side member) corresponding to the formed opening and the laminated film in the upper part of the other member (upper layer side member). Forming a first opening and exposing the other member to form a second opening.

  Here, a specific manufacturing method of the TFT substrate 110 according to the present embodiment will be described with reference to FIGS. 4C to 4E with reference to FIGS. 6A to 6F. 6A to 6F are cross-sectional views for explaining an opening forming step in the manufacturing method of the TFT substrate according to the embodiment.

  First, as shown in FIGS. 4C to 4E, a first insulating film 31 is formed so as to cover the first conductive member 21 (one member), and the semiconductor layer 40 (the other member) is formed on the first insulating film 31. The second insulating film 32 is formed so as to cover.

  Next, as shown in FIG. 6A, a first resist mask 51 (first mask) having a first mask opening 51 a is formed on the stacked film 30. The first resist mask 51 is, for example, a resist film made of a photosensitive coating material, and the first mask opening 51a can be formed by a photolithography method. The first mask opening 51a corresponds to the first opening CH1, and is formed above the first wiring 21L.

  Next, as shown in FIG. 6B, as the first etching process (pre-etching process) as the first etching process, the stacked film 30 in the upper part of the first wiring 21L is formed using the first resist mask 51 as a mask. Etch halfway. Thereby, the laminated film 30 in the upper part of the first wiring 21 </ b> L is etched to a predetermined depth, and a first opening 30 a is formed in the laminated film 30.

  In the present embodiment, in the first etching process, the laminated film 30 is etched until the remaining film thickness of the laminated film 30 in the upper part of the first wiring 21L becomes equal to the film thickness of the second insulating film 32. . Since the film thickness of the first insulating film 31 is larger than the film thickness of the second insulating film 32, in this etching process, etching is performed halfway through the first insulating film 31 through the second insulating film 32. .

  In addition, the stacked film 30 in the upper part of only the first wiring 21L of the first wiring 21L and the semiconductor layer 40 is etched. That is, the stacked film 30 in the upper part of the semiconductor layer 40 is not etched.

  As the etching, for example, dry etching by a reactive ion etching (RIE) method can be used. Specifically, part of the laminated film 30 is removed by dry etching using the first resist mask 51 as a mask. Thereby, the first opening 30 a can be formed in the laminated film 30.

In the case of dry etching, for example, a mixed gas containing carbon tetrafluoride gas (CF ₄ ), oxygen gas (O ₂ ), and helium gas (He) can be used as an etching gas. As an example, using a mixed gas of 4500 sccm for CF ₄ , 500 sccm for O _{2 and} 4000 sccm for He, the pressure of the apparatus in the RIE chamber may be 5 Pa, and the applied power may be 10000 W. In the case of this etching condition, the dry etching rate for the SiO film is about 80 nm / min.

  Note that the etching amount of the stacked film 30 (the depth of the first opening 30a) can be controlled by the etching time.

  Next, as shown in FIG. 6C, the first resist mask 51 is removed to expose the entire surface of the laminated film 30. The removal of the first resist mask 51 can be performed by a stripping solution or ashing.

  Next, as illustrated in FIG. 6D, a second resist mask 52 (second mask) having second mask openings 52 a, 52 b, and 52 c is formed on the stacked film 30. Similar to the first resist mask 51, the second resist mask 52 is, for example, a resist film made of a photosensitive coating material, and the second mask openings 52a, 52b and 52c can be formed by photolithography. .

  The second mask opening 52a corresponds to the first opening CH1 and is formed above the first wiring 21L. That is, the second mask opening 52a is formed so as to correspond to the first opening 30a formed in the first etching process.

  The second mask opening 52b corresponds to the second opening CH2 and is formed above the gate electrode 21T. The second mask opening 52c corresponds to the third opening CH3 and is formed above the first capacitor electrode 21C.

  In the present embodiment, the opening diameter of the second mask opening 52 a in the second resist mask 52 is equal to or smaller than the opening diameter of the first mask opening 51 a in the first resist mask 51. That is, as shown in FIG. 6D, the opening diameter of the second mask opening 52a in the vicinity of the laminated film 30 of the second resist mask 52 is equal to or smaller than the opening diameter of the bottom of the first opening 30a.

  Next, as shown in FIG. 6E, as a second etching process (second-stage etching process) as the second etching process, the first wiring 21L and the semiconductor layer 40 are exposed using the second resist mask 52 as a mask. Thus, the laminated film 30 is etched.

  In the present embodiment, in the second etching step, the stacked film 30 in the upper part of both the first wiring 21L and the semiconductor layer 40 is etched to expose both the first wiring 21L and the semiconductor layer 40. Yes.

  Specifically, the depth of the first opening 30a is further increased by etching the stacked film 30 in the upper part of the first wiring 21L corresponding to the first opening 30a through the second mask opening 52a. The wiring 21L is exposed. Furthermore, the second opening 30b is formed by etching the laminated film 30 in the upper part of the gate electrode 21T through the second mask opening 52b to expose the semiconductor layer 40. In addition, the third opening 30c is formed by etching the laminated film 30 in the upper part of the first capacitor electrode 21C through the second mask opening 52c to expose the semiconductor layer 40.

  In the second etching step, the laminated film 30 can be etched by a dry etching method using a reactive ion etching (RIE) method, as in the first etching step. Etching conditions may be the same conditions as in the first etching step. In the second etching process, the etching amount of the laminated film 30 can be controlled by the etching time.

  In the present embodiment, as described above, the opening diameter of the second mask opening 52a in the second resist mask 52 is equal to or smaller than the opening diameter of the first mask opening 51a in the first resist mask 51. A step is formed on the side surface of the one opening 30a. Specifically, in the first opening 30a, the inner diameter of the part formed in the second etching process is equal to or smaller than the inner diameter of the part formed in the first etching process. That is, the opening end formed in the second etching step is located inside the contact edge portion opened in the first etching step or coincides with the contact edge portion.

  3 and 4F show the case where the opening diameter of the second mask opening 52a and the opening diameter of the first mask opening 51a are matched (when no step is formed on the side surface of the first opening 30a). FIG. 6E shows a case where the opening diameter of the second mask opening 52a is smaller than the opening diameter of the first mask opening 51a (when a step is formed on the side surface of the first opening 30a).

  Next, as shown in FIG. 6F, the second resist mask 52 is removed to expose the entire surface of the laminated film 30. Thereby, the first opening CH1, the second opening CH2, and the third opening CH3 can be formed in the stacked film 30. The removal of the second resist mask 52 can be performed by a stripping solution or ashing.

  As described above, in the manufacturing method of the TFT substrate 110 shown in FIGS. 6A to 6F, the etching process is divided into two times when the plurality of openings having different depths are formed. That is, by performing the etching process (photolithography process) twice, the first opening CH1 and the second opening CH2 (third opening CH3) having different depths are formed.

  Specifically, in the first etching step, first, the laminated film 30 above the first wiring 21L (gate contact portion) is etched halfway. In the second etching step, both the stacked film 30 above the first wiring 21L (gate contact portion) and the stacked film 30 above the gate electrode 21T and the first capacitor electrode 21C (ohmic contact portion) are simultaneously formed. The first wiring 21L and the semiconductor layer 40 are exposed by etching.

  Thereby, the shallow second opening CH2 and the third opening CH3 reach the semiconductor layer 40 before the deep first opening CH1 reaches the first wiring 21L. Disappears.

  Therefore, the problem that the opening diameters (contact diameters) of the second opening CH2 and the third opening CH3 are increased by the receding of the resist mask during etching as in the case of FIGS. 5A to 5C can be solved. In addition, even when the semiconductor layer 40 has a defect, it is possible to suppress the occurrence of a short-circuit failure due to contact penetration.

  Furthermore, by dividing the etching process into two times, the etching time per time can be shortened as compared with the case of FIGS. 5A to 5C. Thereby, a decrease in throughput can be suppressed and an increase in the electrode temperature of the dry etching apparatus can be suppressed. For this reason, it is also possible to suppress the problem of misalignment of the electrode due to the thermal expansion of the electrode in the dry etching apparatus.

  Thus, according to the manufacturing method of TFT substrate 110 according to the present embodiment, a plurality of openings having different depths can be formed without reducing the yield.

  In the present embodiment, in the first etching process, the stacked film 30 is etched until the remaining film thickness of the stacked film 30 in the upper part of the first wiring 21L becomes equal to the film thickness of the second insulating film 32. ing. Specifically, in the first etching step, the laminated film 30 above the first wiring 21L is etched by the thickness of the lower first insulating film 31. Next, in the second etching step, both the stacked film 30 above the first wiring 21L and the stacked film 30 above the gate electrode 21T and the first capacitor electrode 21C are divided by the film thickness of the upper second insulating film 32. Only etching at the same time.

  Thereby, in the second etching process, the first opening 30a reaches the first wiring 21L and the first wiring 21L is exposed, and at the same time, the second opening 30b and the third opening 30c reach the semiconductor layer 40 and the semiconductor. Layer 40 is exposed. Therefore, damage to the semiconductor layer 40 during etching can be suppressed.

  In the present embodiment, the opening diameter of the second mask opening 52 a in the second resist mask 52 is equal to or smaller than the opening diameter of the first mask opening 51 a in the first resist mask 51.

  Thereby, it is possible to suppress an increase in the opening diameter of the first opening CH1 in the connection portion (gate contact portion) between the first wiring 21L and the second wiring 22L.

  In the method shown in FIGS. 6A to 6F, in the first etching process (pre-stage etching process), the upper portion of the stacked film 30 of only the first wiring 21 </ b> L of the first wiring 21 </ b> L and the semiconductor layer 40 is etched. In the second etching process (second-stage etching process), the laminated film 30 in the upper part of both the first wiring 21L and the semiconductor layer 40 is etched, but the present invention is not limited to this. For example, as shown in FIGS. 7A to 7F, contrary to the method shown in FIGS. 6A to 6F, in the first etching process (pre-etching process), above both the first wiring 21 </ b> L and the semiconductor layer 40. The laminated film 30 in the part may be etched, and the laminated film 30 in the upper part of only the first wiring 21L of the first wiring 21L and the semiconductor layer 40 may be etched in the second etching process (second-stage etching process). .

  7A to 7F are cross-sectional views for explaining an opening forming step in another method for manufacturing a TFT substrate according to the embodiment.

  Specifically, first, as shown in FIG. 7A, a first resist mask 51A having first mask openings 51a, 51b and 51c is formed on the laminated film 30. Like the first resist mask 51, the first resist mask 51A is made of, for example, a photosensitive coating material, and the first mask openings 51a, 51b, and 51c can be formed by photolithography.

  The first resist mask 51A is formed in a pattern shape similar to that of the second resist mask 52, the first mask opening 51a corresponds to the first opening CH1, and the first mask opening 51b is the second opening. Corresponding to CH2, the first mask opening 51c corresponds to the third opening CH3.

  Next, as shown in FIG. 7B, as the first etching step (pre-stage etching step), the first resist mask 51A is used as a mask to etch the laminated film 30 in the upper part of the first wiring 21L halfway, The stacked film 30 above the gate electrode 21T and the first capacitor electrode 21C is etched so that the semiconductor layer 40 is exposed. As an example, only the second insulating film 32 corresponding to each of the first mask openings 51a, 51b, and 51c is removed by etching, and the first opening 30a and the second opening are formed in the stacked film 30 (second insulating film 32). An opening 30b and a third opening 30c are formed.

  As the etching, a dry etching method by a reactive ion etching (RIE) method can be used.

  Next, as shown in FIG. 7C, the first resist mask 51 </ b> A is removed to expose the entire surface of the laminated film 30.

  Next, as illustrated in FIG. 7D, a second resist mask 52 </ b> A having a second mask opening 52 a is formed on the stacked film 30. Similarly to the first resist mask 51, the second resist mask 52A is, for example, a resist film made of a photosensitive coating material, and the second mask opening 52a can be formed by a photolithography method.

  The second mask opening 52a corresponds to the first opening CH1 and is formed above the first wiring 21L. That is, the second mask opening 52a is formed so as to correspond to the first opening 30a formed in the first etching process.

  Also in this embodiment, the opening diameter of the second mask opening 52a in the second resist mask 52A is equal to or smaller than the opening diameter of the first mask opening 51a in the first resist mask 51A.

  Next, as shown in FIG. 7E, as a second etching process (post-stage etching process), the laminated film 30 is etched using the second resist mask 52A as a mask so that the first wiring 21L is exposed.

  Specifically, the first opening 30a is further deepened by etching the laminated film 30 in the upper part of the first wiring 21L corresponding to the first opening 30a through the second mask opening 52a, thereby forming the first wiring 21L. It is exposed.

  Also in the second etching step, the dry etching method by the reactive ion etching (RIE) method is used, as in the first etching step.

  Next, as shown in FIG. 7F, the second resist mask 52A is removed, and the entire surface of the laminated film 30 is exposed. Thereby, the first opening CH1, the second opening CH2, and the third opening CH3 can be formed in the stacked film 30.

  As described above, in the manufacturing method of the TFT substrate 110 shown in FIGS. 7A to 7F, as in the method shown in FIGS. 6A to 6F, the etching process is performed when forming a plurality of openings having different depths. Divided into times.

  Thereby, the effect similar to the method shown by FIG. 6A-FIG. 6F can be acquired. That is, it is possible to suppress the opening diameters of the second opening CH2 and the third opening CH3 from being enlarged due to the receding of the resist mask during etching. In addition, even when the semiconductor layer 40 has a defect, it is possible to suppress the occurrence of a short-circuit failure due to contact penetration. Furthermore, since the etching time per time can be shortened, a decrease in throughput can be suppressed and an increase in the electrode temperature of the dry etching apparatus can be suppressed.

  Therefore, a plurality of openings having different depths can be formed without reducing the yield.

  In the method shown in FIGS. 7A to 7F, unlike the method shown in FIGS. 6A to 6F, the second opening CH2 and the third opening CH3 are completed in the first etching step. The semiconductor layer 40 is exposed in the second etching process. For this reason, as shown in FIGS. 7D and 7E, the surface of the semiconductor layer 40 comes into contact with the second resist mask 52A in the second photolithography. Moreover, as shown in FIGS. 7C and 7F, the surface of the semiconductor layer 40 is affected by two removal steps (such as a stripping solution or ashing) of removing the first resist mask 51A and removing the second resist mask 52A. Will receive. Therefore, in the method shown in FIGS. 7A to 7F, the surface of the semiconductor layer 40 may be damaged by the contact of the second resist mask 52A and the influence of the two removal steps. Therefore, it is better to use the method shown in FIGS. 6A to 6F than the method shown in FIGS. 7C and 7F.

(Modification)
Next, a description will be given of a TFT substrate 110A according to a modification and a manufacturing method thereof. FIG. 8 is a partial cross-sectional view of a TFT substrate 110A according to a modification.

  As shown in FIG. 8, in the TFT substrate 110 </ b> A, the third insulating film 33 is formed between the first insulating film 31 and the second insulating film 32, and the stacked film 30 is formed between the first insulating film 31 and the first insulating film 31. The three-insulating film 33 and the second insulating film 32 have a three-layer structure.

  The TFT substrate 110 </ b> A is located above the substrate 10, the first conductive member 21 located above the substrate 10, the first insulating film 31 located above the first conductive member 21, and the first insulating film 31. The third conductive member 23, the third insulating film 33 located above the third conductive member 23, the semiconductor layer 40 located above the third insulating film 33, and the second insulation located above the semiconductor layer 40 The film 32 and the second conductive member 22 positioned above the second insulating film 32 are included.

  In addition, the TFT substrate 110A has a first wiring layer WL21, a first insulating layer IL31, a third wiring layer WL23, a third insulating layer IL33, a semiconductor layer 40, a second insulating layer IL32, and a second wiring layer WL22. .

  In the present modification, the first conductive member 21 is formed in the first wiring layer WL21 as one electrode (first capacitor electrode) of the capacitor element Cs. In the third wiring layer WL23, the third conductive member 23 is formed as the other electrode (second capacitor electrode) of the capacitor element Cs and as the gate electrode of the drive transistor DrTr. That is, the third conductive member 23 serves as both the electrode of the capacitive element Cs and the gate electrode of the drive transistor DrTr. In the second wiring layer WL22, a source electrode 22S, a drain electrode 22D, and wirings 22L1 and 22L2 are formed as the second conductive member 22.

  In addition, the material of the 1st conductive member 21, the 3rd conductive member 23, and the 2nd conductive member 22 can use the material of the 1st conductive member 21 and the 2nd conductive member 22 in the TFT substrate 110 of the said embodiment. .

  A first insulating film 31 is formed on the first insulating layer IL31. A third insulating film 33 is formed on the third insulating layer IL33, and a second insulating film 32 is formed on the second insulating layer IL32.

  In addition, the material of the 1st insulating film 31, the 3rd insulating film 33, and the 2nd insulating film 32 can use the material of the 1st insulating film 31 and the 2nd insulating film 32 in the TFT substrate 110 of the said embodiment. .

  A plurality of openings (contact holes) are formed in the laminated film 30 in the TFT substrate 110A. Specifically, a first opening CH1A, a second opening CH2A, and a third opening CH3A are formed in the stacked film 30 in the present modification.

  The first opening CH1A is a through hole for connecting the first conductive member 21 and the second conductive member 22 (wiring 22L1), and the second insulating film 32, the third insulating film 33, and the first insulating film 31. It is formed so as to penetrate all of the above. The second conductive member 22 (wiring 22L1) formed in the second wiring layer WL22 is connected to the first conductive member 21 formed in the first wiring layer WL21 through the first opening CH1A.

  The second opening CH2A is a through hole for connecting the third conductive member 23 and the second conductive member 22 (wiring 22L2), and only the second insulating film 32 and the third insulating film 33 in the laminated film 30 are provided. It is formed so as to penetrate. The second conductive member 22 (wiring 22L2) formed in the second wiring layer WL22 is connected to the third conductive member 23 through the second opening CH2A.

  The third opening CH3A is a through hole for connecting the semiconductor layer 40 and the second conductive member 22 (source electrode 22S, drain electrode 22D), and penetrates only the second insulating film 32 in the stacked film 30. It is formed as follows. The second conductive member 22 (source electrode 22S, drain electrode 22D) formed in the second wiring layer WL22 is connected to the semiconductor layer 40 through the third opening CH3A.

  Next, a manufacturing method of the TFT substrate 110A according to this modification will be described with reference to FIGS. 9A to 9D. 9A to 9D are cross-sectional views for explaining an opening forming step in the manufacturing method of the TFT substrate 110A according to the modification.

  The manufacturing method of the TFT substrate 110A according to this modification is the same as the manufacturing method of the TFT substrate 110 according to the above-described embodiment, and further includes a third insulating film 33 between the first insulating film 31 and the second insulating film 32. Forming an opening in the laminated film 30 including the first insulating film 31, the third insulating film 33, and the second insulating film 32. The opening forming process includes forming a first opening in the laminated film 30. A portion CH1A, a second opening CH2A, and a third opening CH3A are formed.

  The opening forming process in this modification further includes a middle etching process between the former etching process and the latter etching in the manufacturing method of the TFT substrate 110 according to the above embodiment. In the middle etching process, the laminated film 30 in the upper part of the first conductive member corresponding to the first opening 30a formed in the previous etching process is further etched.

  A specific manufacturing method of the TFT substrate 110A according to the present modification can be performed in accordance with the manufacturing method of the TFT substrate 110 of the above-described embodiment. As shown in FIG. The member 21 is formed, the first insulating film 31 is formed so as to cover the first conductive member 21, the third conductive member 23 is formed on the first insulating film 31, and the third conductive member 23 is covered. The third insulating film 33 is formed, the semiconductor layer 40 is formed on the third insulating film 33, and the second insulating film 32 is formed so as to cover the semiconductor layer 40.

  Next, as shown in FIG. 9B, as a first etching process (first etching process), a first resist mask (not shown) having a first mask opening corresponding to the first opening CH1A is used. The laminated film 30 in the upper part of the member 21 is etched halfway. Thereby, the laminated film 30 in the upper part of the first conductive member 21 is etched to a predetermined depth, and a first opening 30 a is formed in the laminated film 30.

  Next, as shown in FIG. 9C, as a middle etching process (second etching process), a second resist mask (not shown) having a second mask opening corresponding to the first opening CH1A and the second opening CH2A. Then, the laminated film 30 in the upper part of the first conductive member 21 corresponding to the first opening 30a is further etched, and the laminated film 30 in the upper part of the third conductive member 23 is etched halfway. As a result, the first opening 30 a is etched to a deeper depth, and the laminated film 30 in the upper part of the third conductive member 23 is etched to a predetermined depth to form the second opening 30 b in the laminated film 30.

  Next, as shown in FIG. 9D, as a subsequent etching process (third etching process), a third mask opening having a third mask opening corresponding to the first opening CH1A, the second opening CH2A, and the third opening CH3 is used. Using a resist mask (not shown), the laminated film 30 in the upper part of the first conductive member 21 corresponding to the first opening 30a and the laminated film 30 in the upper part of the third conductive member 23 corresponding to the second opening 30b Is further etched, and the laminated film 30 in the upper part of the semiconductor layer 40 is etched. Thus, the first opening 30a and the second opening 30b are further deepened to expose the first conductive member 21 and the third conductive member 23, and are formed in the stacked film 30 in the upper portion of the semiconductor layer 40. The semiconductor layer 40 is exposed through the third opening 30c.

  Thus, the first opening CH1A, the second opening CH2A, and the third opening CH3A can be formed in the stacked film 30.

  9D and thereafter, as in the above-described embodiment shown in FIGS. 4G and 4H, the source electrode 22S, the drain electrode 22D, and the wirings 22L1 and 22L2 are formed as the second conductive member 22 having a predetermined shape.

  Thus, in this modification, the etching process is divided into three times when a plurality of openings having different depths are formed. That is, by performing the photolithography process three times, the first opening CH1A, the second opening CH2A, and the third opening CH3A having different depths are formed.

  Thereby, the effect similar to the method shown by FIG. 6A-FIG. 6F can be acquired. That is, it is possible to suppress the opening diameters of the second opening CH2 and the third opening CH3 from being enlarged due to the receding of the resist mask during etching. In addition, even when the semiconductor layer 40 has a defect, it is possible to suppress the occurrence of a short-circuit failure due to contact penetration. Furthermore, since the etching time per time can be shortened, a decrease in throughput can be suppressed and an increase in the electrode temperature of the dry etching apparatus can be suppressed.

  Therefore, a plurality of openings having different depths can be formed without reducing the yield.

  In this modification, the three openings having different depths (first opening CH1A, second opening CH2A, and third opening CH3A) are formed by three etching steps (photolithography process). As shown in FIGS. 10A to 10C, the etching process (a photolithography process) may be performed twice.

  10A to 10C are cross-sectional views for explaining an opening forming step in another method for manufacturing a TFT substrate according to a modification.

  Specifically, as shown in FIG. 10A, as in FIG. 9A, the first conductive member 21 is formed on the substrate 10, and the first insulating film 31 is formed so as to cover the first conductive member 21, Forming the third conductive member 23 on the first insulating film 31, forming the third insulating film 33 so as to cover the third conductive member 23, and forming the semiconductor layer 40 on the third insulating film 33; A second insulating film 32 is formed so as to cover the semiconductor layer 40.

  Next, as shown in FIG. 10B, as a pre-etching step (first etching step), a first resist mask (not shown) having a first mask opening corresponding to the first opening CH1A and the second opening CH2A. Is used to etch the laminated film 30 in the upper part of the first conductive member 21 halfway to form the first opening 30a, and etch the laminated film 30 in the upper part of the third conductive member 23 to obtain the second opening. 30b is formed.

  At this time, in FIG. 10B, the third conductive member 23 is exposed by the second opening 30b, but the third conductive member 23 may not be exposed.

  Next, as shown in FIG. 10C, as a subsequent etching process (second etching process), a second resist mask (not shown) having a second mask opening corresponding to the first opening CH1A and the third opening CH3A. Then, the laminated film 30 in the upper part of the first conductive member 21 corresponding to the first opening 30a is further etched, and the laminated film 30 in the upper part of the semiconductor layer 40 is etched. As a result, the first opening 30a becomes deeper and the first conductive member 21 is exposed, and the semiconductor layer 40 is exposed by the third opening 30c formed in the stacked film 30 in the upper part of the semiconductor layer 40. .

  In FIG. 10B, when the third conductive member 23 is not exposed, a second resist mask having a second mask opening corresponding to the second opening CH2A may be used. Accordingly, the stacked film 30 in the upper part of the third conductive member 23 corresponding to the second opening 30b can be further etched to further increase the depth of the second opening 30b, and the third conductive member 23 is exposed. .

(Other)
As described above, the method for manufacturing the thin film transistor substrate has been described based on the embodiment and the modification. However, the technology of the present disclosure is not limited to the embodiment and the modification.

  For example, in the above-described embodiment, one member of the laminated film 30 covered with the lower first insulating film 31 is a conductive member (such as the gate electrode 21T) formed in the first wiring layer WL21. Of these, the other member covered by the upper second insulating film 32 is the semiconductor layer 40, but is not limited thereto. For example, one member covered by the first insulating film 31 may be the semiconductor layer 40 and the other member covered by the second insulating film 32 may be the conductive member.

  In the embodiment and the modification, the opening for exposing the conductive member and the opening for exposing the semiconductor layer are described as the two openings having different depths. However, the present invention is not limited to this. is not. For example, the two openings having different depths may be openings for exposing the conductive member. In other words, one member covered by the lower first insulating film may be a conductive member, and the other member covered by the upper second insulating film may also be a conductive member.

  Moreover, in the said embodiment and modification, as the 1st mask and 2nd mask for forming several opening part in the laminated film 30, the resist film (1st resist mask and 1st mask comprised with the photosensitive coating material) is used. However, the present invention is not limited to this, and other masks such as a metal mask may be used.

  In the above-described embodiment and modification, the number of insulating films in the laminated film 30 is two or three. However, the number of insulating films is not limited to this, and the laminated film 30 is configured by four or more insulating films. It may be.

  Further, in the above-described embodiment and modification, the dry etching method is used as the method for removing the stacked film 30 (etching method) when the opening is formed in the stacked film 30, but the wet etching method may be used. .

  In the above-described embodiments and modifications, the TFT formed in the TFT portion is the drive transistor DrTr. However, the TFT formed in the TFT portion may be the switching transistor SwTr. Note that the configuration of the switching transistor SwTr is the same as that of the drive transistor DrTr.

  In the above-described embodiments and modifications, the drive transistor DrTr and the switching transistor SwTr are channel etching stopper types (channel protection types), but may be channel etching types.

  In the embodiment and the modification described above, the pixel circuit in one pixel has a configuration of 2Tr1C including two TFTs (drive transistor DrTr, switching transistor SwTr) and one capacitor element Cs. Not exclusively. For example, three or more TFTs may be provided in one pixel, and two or more capacitor elements may be formed.

  In the embodiment and the modification, the organic EL display device is described as the display device using the thin film transistor substrate. However, the thin film transistor substrate in the above embodiment is a liquid crystal display device or other active matrix substrate. The present invention can also be applied to a display device.

  The display device (display panel) such as the organic EL display device described above can be applied to any electronic device having a display panel such as a television set, a personal computer, a mobile phone, or a mobile terminal.

  Note that the thin film transistor substrate in this embodiment and the modification may be applied to other panels such as a solar battery panel.

  Other configurations and functions in the embodiment and the modification may be arbitrarily obtained without departing from the gist of the present disclosure, and the forms obtained by making various modifications conceived by those skilled in the art with respect to the embodiment and the modification described above. A form realized by combination is also included in the present disclosure.

  The technology of the present disclosure can be widely used in electronic devices using a TFT substrate.

100 Organic EL Display Device 10 Substrate 21 First Conductive Member 21T, G1, G2 Gate Electrode 21C First Capacitance Electrode 21L First Wiring 22 Second Conductive Member 22S, S1, S2 Source Electrode 22D, D1, D2 Drain Electrode 22L Second Wiring 22L1, 22L2 wiring 22F conductive film 23 third conductive member 30 laminated film 30a, 300a first opening 30b, 300b second opening 30c, 300c third opening 31 first insulating film 32 second insulating film 33 third insulating film 40 Semiconductor layer 51, 51A First resist mask 51a, 51b, 51c First mask opening 52, 52A Second resist mask 52a, 52b, 52c Second mask opening 110, 110A TFT substrate 120 Pixel 130 Organic EL element 131 Anode 132 Organic EL Layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring 500 Resist mask 500a, 500b, 500c Mask opening DrTr Drive transistor SwTr Switching transistor Cs Capacitor element WL21 First wiring layer WL22 Second wiring layer IL31 First insulating layer IL32 Second insulating layer IL33 Third insulating layer CH1 , CH1A first opening CH2, CH2A second opening CH3, CH3A third opening

Claims (11)

A method of manufacturing a thin film transistor substrate in which a thin film transistor having a semiconductor layer having a predetermined shape and a conductive member having a predetermined shape are formed,
Forming a first insulating film so as to cover one member of the semiconductor layer and the conductive member;
Forming a second insulating film on the first insulating film so as to cover the other member of the semiconductor layer and the conductive member;
An opening forming step of forming a first opening and a second opening in a laminated film including the first insulating film and the second insulating film so that each of the one member and the other member is exposed; Including
The opening forming step includes
A pre-etching step of etching the laminated film of the upper part of only the one member out of the one member and the other member halfway to form an opening;
After the pre-etching step, the one member is exposed by etching both the laminated film in the upper part of the one member corresponding to the opening and the laminated film in the upper part of the other member. And a post-etching step of forming the first opening and exposing the other member to form the second opening.
In the pre-etching step, using the first mask having the first mask opening, the opening is formed by etching the stacked film in the upper part of the one member,
In the post-etching step , using the second mask having the second mask opening corresponding to the opening, the stacked film in the upper part of the one member is further etched to form the first opening,
The method of manufacturing a thin film transistor substrate, wherein an opening diameter of the second mask opening is equal to or smaller than an opening diameter of the first mask opening. 2. The thin film transistor substrate according to claim 1, wherein in the pre-etching step, the stacked film is etched until a remaining film thickness of the stacked film in an upper portion of the one member becomes equal to a film thickness of the second insulating film. Production method. The film thickness of the first insulating film is larger than the film thickness of the second insulating film,
3. The method of manufacturing a thin film transistor substrate according to claim 1, wherein in the pre-stage etching step, etching is performed halfway through the first insulating film. The method of manufacturing a thin film transistor substrate according to claim 1, wherein an etching amount of the stacked film in the pre-stage etching step and the post-stage etching step is controlled by an etching time. The one member is the conductive member,
The method for manufacturing a thin film transistor substrate according to claim 1, wherein the other member is the semiconductor layer. A method of manufacturing a thin film transistor substrate in which a thin film transistor having a semiconductor layer having a predetermined shape and a conductive member having a predetermined shape are formed,
Forming a first insulating film so as to cover one member of the semiconductor layer and the conductive member;
Forming a second insulating film on the first insulating film so as to cover the other member of the semiconductor layer and the conductive member;
An opening forming step of forming a first opening and a second opening in a laminated film including the first insulating film and the second insulating film so that each of the one member and the other member is exposed; Including
The opening forming step includes
A pre-etching step of forming the second opening by exposing the other member by etching the laminated film on the upper part of both the one member and the other member;
After the pre-etching process, the first opening is formed by exposing the one member by etching the laminated film in the upper part of only the one member among the one member and the other member. And a subsequent etching step,
The film thickness of the first insulating film is larger than the film thickness of the second insulating film,
In the pre-etching step, the thin film transistor substrate is manufactured by etching halfway through the first insulating film. A method of manufacturing a thin film transistor substrate in which a thin film transistor having a semiconductor layer having a predetermined shape and a conductive member having a predetermined shape are formed,
Forming a first insulating film so as to cover one member of the semiconductor layer and the conductive member;
Forming a second insulating film on the first insulating film so as to cover the other member of the semiconductor layer and the conductive member;
An opening forming step of forming a first opening and a second opening in a laminated film including the first insulating film and the second insulating film so that each of the one member and the other member is exposed; Including
The opening forming step includes
A pre-etching step of forming the second opening by exposing the other member by etching the laminated film on the upper part of both the one member and the other member;
After the pre-etching process, the first opening is formed by exposing the one member by etching the laminated film in the upper part of only the one member among the one member and the other member. And a subsequent etching step,
The method of manufacturing a thin film transistor substrate, wherein an etching amount of the stacked film in the pre-stage etching step and the post-stage etching step is controlled by an etching time. A method of manufacturing a thin film transistor substrate in which a thin film transistor having a semiconductor layer having a predetermined shape and a conductive member having a predetermined shape are formed,
Forming a first insulating film so as to cover one member of the semiconductor layer and the conductive member;
Forming a second insulating film on the first insulating film so as to cover the other member of the semiconductor layer and the conductive member;
An opening forming step of forming a first opening and a second opening in a laminated film including the first insulating film and the second insulating film so that each of the one member and the other member is exposed; Including
The opening forming step includes
A pre-etching step of forming the second opening by exposing the other member by etching the laminated film on the upper part of both the one member and the other member;
After the pre-etching process, the first opening is formed by exposing the one member by etching the laminated film in the upper part of only the one member among the one member and the other member. And a subsequent etching step,
The one member is the conductive member,
The other member is the semiconductor layer. A method of manufacturing a thin film transistor substrate. Wherein in the front etching process using a first mask having a first mask opening, the laminated film of the upper portion of the one member to form an etching to open the mouth,
In the post-etching step , using the second mask having the second mask opening corresponding to the opening, the stacked film in the upper part of the one member is further etched to form the first opening,
The method of manufacturing a thin film transistor substrate according to claim 6, wherein an opening diameter of the second mask opening is equal to or smaller than an opening diameter of the first mask opening. The first insulating film and the second insulating film are made of a compound containing silicon,
The method for manufacturing a thin film transistor substrate according to claim 1, wherein the etching in the pre-stage etching step and the post-stage etching step is dry etching. Forming a third insulating film between the first insulating film and the second insulating film;
In the opening forming step, the first opening and the second opening are formed in the stacked film including the first insulating film, the third insulating film, and the second insulating film,
The opening forming step further includes a middle etching step between the former etching step and the latter etching step ,
2. The method of manufacturing a thin film transistor substrate according to claim 1, wherein in the middle etching process, the stacked film in an upper part of the one member corresponding to the opening formed in the previous etching process is further etched.

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