JP6483411B2 - Display device - Google Patents

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JP6483411B2
JP6483411B2 JP2014234689A JP2014234689A JP6483411B2 JP 6483411 B2 JP6483411 B2 JP 6483411B2 JP 2014234689 A JP2014234689 A JP 2014234689A JP 2014234689 A JP2014234689 A JP 2014234689A JP 6483411 B2 JP6483411 B2 JP 6483411B2
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insulating film
subpixel
pixel
drain electrode
display device
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JP2016099423A (en
Inventor
光隆 沖田
光隆 沖田
康克 觀田
康克 觀田
敏行 日向野
敏行 日向野
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Japan Display Inc
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Japan Display Inc
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Priority to JP2014234689A priority Critical patent/JP6483411B2/en
Priority to CN201510794982.0A priority patent/CN105607364B/en
Priority to US14/944,536 priority patent/US9946130B2/en
Publication of JP2016099423A publication Critical patent/JP2016099423A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Description

本開示は表示装置に関し、例えば画素電極とソース／ドレイン電極とを接続するコンタクトホールを有する表示装置に適用可能である。   The present disclosure relates to a display device, and is applicable to a display device having a contact hole that connects a pixel electrode and a source / drain electrode, for example.

近年、スマートフォンやタブレット向けの液晶表示装置では高解像度化が進み、液晶表示装置の画素サイズは微細化され４００ｐｐｉ以上のパネルが製品化されおり、６００ｐｐｉクラスの液晶表示装置も開発されている。
本開示に関連する先行技術として特開２０１３−００３２００号公報またはこれに対応する米国特許出願公開２０１２／０３１４１６９号明細書がある。 In recent years, liquid crystal display devices for smartphones and tablets have been improved in resolution, the pixel size of the liquid crystal display device has been reduced, and a panel of 400 ppi or more has been commercialized, and a 600 ppi class liquid crystal display device has also been developed.
As prior art related to the present disclosure, there is JP 2013-003200 A or US Patent Application Publication No. 2012/0314169 corresponding thereto.

特開２０１３−００３２００号公報JP 2013-003200 A 米国特許出願公開２０１２／０３１４１６９号明細書US Patent Application Publication No. 2012/0314169

画素サイズが小さくなると画素面積に対するブラックマトリクス（ゲート配線、信号配線、および画素電極と薄膜トランジスタ（ＴＦＴ）のドレイン電極とを接続するためのコンタクトホール部等を覆う遮光層）の面積比率が高くなり開口率が低くなる。このため、高精細の液晶表示装置では透過率が低くなるためバックライトを明るくする必要があり消費電力が大きくなる。なお、画素電極と接続されるＴＦＴの電極をソース電極と呼ぶ場合もあるが、本明細書では、ドレイン電極と呼ぶこととする。
その他の課題と新規な特徴は、本開示の記述および添付図面から明らかになるであろう。 When the pixel size is reduced, the area ratio of the black matrix (the light shielding layer covering the gate wiring, the signal wiring, and the contact hole portion for connecting the pixel electrode and the drain electrode of the thin film transistor (TFT)) to the pixel area is increased and the opening is increased. The rate is lowered. For this reason, in a high-definition liquid crystal display device, since the transmittance is low, it is necessary to brighten the backlight, resulting in an increase in power consumption. Note that an electrode of a TFT connected to the pixel electrode is sometimes referred to as a source electrode, but in this specification, it is referred to as a drain electrode.
Other problems and novel features will become apparent from the description of the present disclosure and the accompanying drawings.

本開示のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
すなわち、表示装置はアレイ基板と対向基板とを備える。前記アレイ基板は、第１および第２のドレイン電極と、信号線と、前記信号線上に形成された有機絶縁膜と、前記有機絶縁膜上に形成された無機絶縁膜と、前記無機絶縁膜上に形成された第１および第２の画素電極と、を備える。前記有機絶縁膜は前記第１のドレイン電極と前記第２のドレイン電極とに跨る有機絶縁膜開口部を備える。前記有機絶縁膜開口部を覆う前記無機絶縁膜は第１および第２の無機絶縁膜開口部を備える。前記第１の画素電極は前記第１の無機絶縁膜開口部を介して前記第１のドレイン電極に接続される。前記第２の画素電極は前記第２の無機絶縁膜開口部を介して前記第２のドレイン電極に接続される。 The outline of a representative one of the present disclosure will be briefly described as follows.
That is, the display device includes an array substrate and a counter substrate. The array substrate includes first and second drain electrodes, a signal line, an organic insulating film formed on the signal line, an inorganic insulating film formed on the organic insulating film, and the inorganic insulating film And first and second pixel electrodes formed on the substrate. The organic insulating film includes an organic insulating film opening extending over the first drain electrode and the second drain electrode. The inorganic insulating film covering the organic insulating film opening includes first and second inorganic insulating film openings. The first pixel electrode is connected to the first drain electrode through the first inorganic insulating film opening. The second pixel electrode is connected to the second drain electrode through the second inorganic insulating film opening.

比較例１に係る表示装置を説明するための平面図である。10 is a plan view for explaining a display device according to comparative example 1. FIG. 比較例１に係る表示装置を説明するための断面図である。10 is a cross-sectional view for explaining a display device according to comparative example 1. FIG. 実施形態に係る表示装置を説明するための平面図である。It is a top view for demonstrating the display apparatus which concerns on embodiment. 実施形態に係る表示装置を説明するための断面図である。It is sectional drawing for demonstrating the display apparatus which concerns on embodiment. 実施例１に係る表示装置を説明するための平面図である。FIG. 3 is a plan view for explaining the display device according to the first embodiment. 実施例１に係る表示装置を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining the display device according to the first embodiment. 実施例１に係る表示装置を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining the display device according to the first embodiment. 実施例１に係る表示装置を説明するための平面図である。FIG. 3 is a plan view for explaining the display device according to the first embodiment. 実施例１に係る表示装置を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining the display device according to the first embodiment. 実施例２に係る表示装置を説明するための平面図である。6 is a plan view for explaining a display device according to a second embodiment; FIG. 比較例２に係る表示装置を説明するための平面図である。10 is a plan view for explaining a display device according to comparative example 2. FIG. 実施例２に係る表示装置を説明するための平面図である。6 is a plan view for explaining a display device according to a second embodiment; FIG. 実施例２に係る表示装置を説明するための断面図である。6 is a cross-sectional view for explaining a display device according to Example 2. FIG.

以下に、実施形態、実施例および比較例について、図面を参照しつつ説明する。なお、開示はあくまで一例にすぎず、当業者において、発明の主旨を保っての適宜変更について容易に想到し得るものについては、当然に本発明の範囲に含有されるものである。また、図面は説明をより明確にするため、実際の態様に比べ、各部の幅、厚さ、形状等について模式的に表される場合があるが、あくまで一例であって、本発明の解釈を限定するものではない。また、本明細書と各図において、既出の図に関して前述したものと同様の要素には、同一の符号を付して、詳細な説明を適宜省略することがある。   Embodiments, examples, and comparative examples will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the sake of clarity, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part as compared to the actual embodiment, but are merely examples, and the interpretation of the present invention is not limited. It is not limited. In addition, in the present specification and each drawing, elements similar to those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description may be omitted as appropriate.

＜比較例１＞
まず、本願発明者らが検討した技術（以下、比較例１という。）について図１および図２を用いて説明する。図１は比較例１に係る表示装置の構成を示す平面図であり、１画素（３副画素）分が示されている。図２は図１のＡ−Ａ’線における断面図である。
比較例１に係る表示装置１００Ｒは、信号線１２−１，１２−２，１２−３と、ドレイン電極１３−１，１３−２，１３−３と、信号線１２−１，１２−２，１２−３およびドレイン電極１３−１，１３−２，１３−３の上に形成された有機絶縁膜１４と、を備える。表示装置１００Ｒは、さらに、有機絶縁膜１４の開口部（コンタクトホール）１４Ｃ−１，１４Ｃ−２，１４Ｃ−３および有機絶縁膜１４の上に形成された無機絶縁膜１６と、無機絶縁膜１６の開口部（コンタクトホール）１６Ｃ−１，１６Ｃ−２，１６Ｃ−３および無機絶縁膜１６の上に形成された画素電極１８−１，１８−２，１８−３と、を備える。すなわち、表示装置１００Ｒでは、副画素毎に有機絶縁膜の開口部を設けて、画素電極とドレイン電極を接続させている。なお、有機絶縁膜は平坦化膜として機能するため、無機絶縁膜に比べて厚く形成されている。この画素構造では、画素サイズが微細化されて画素サイズが小さくなると有機絶縁膜の開口部も小さくする必要がある。しかし、有機絶縁膜の最小開口幅は無機絶縁膜の最小開口幅のように小さくすることができず、ドレイン電極は有機絶縁膜の最小開口幅よりも大きくする必要があるために開口率が低くなり、高精細画素では画素レイアウトが困難になる。 <Comparative Example 1>
First, a technique studied by the inventors of the present application (hereinafter referred to as Comparative Example 1) will be described with reference to FIGS. FIG. 1 is a plan view showing a configuration of a display device according to Comparative Example 1, and shows one pixel (three sub-pixels). 2 is a cross-sectional view taken along line AA ′ of FIG.
A display device 100R according to Comparative Example 1 includes signal lines 12-1, 12-2, and 12-3, drain electrodes 13-1, 13-2, and 13-3, and signal lines 12-1, 12-2, 12-3 and the drain electrode 13-1, 13-2, 13-3, and the organic insulating film 14 formed. The display device 100R further includes an inorganic insulating film 16 formed on the openings (contact holes) 14C-1, 14C-2, 14C-3 of the organic insulating film 14 and the organic insulating film 14, and the inorganic insulating film 16 Pixel electrodes 18-1, 18-2, 18-3 formed on the openings (contact holes) 16C-1, 16C-2, 16C-3 and the inorganic insulating film 16. That is, in the display device 100R, an opening of the organic insulating film is provided for each subpixel, and the pixel electrode and the drain electrode are connected. Note that the organic insulating film functions as a planarization film and thus is thicker than the inorganic insulating film. In this pixel structure, when the pixel size is reduced and the pixel size is reduced, it is also necessary to reduce the opening of the organic insulating film. However, the minimum opening width of the organic insulating film cannot be made as small as the minimum opening width of the inorganic insulating film, and the drain electrode needs to be larger than the minimum opening width of the organic insulating film. Therefore, pixel layout becomes difficult with high-definition pixels.

＜実施形態＞
実施形態に係る表示装置について図３および図４を用いて説明する。図３は実施形態に係る表示装置の構成を示す平面図である。図４は図１のＡ−Ａ’線における断面図である。
実施形態に係る表示装置１００は、ドレイン電極１３−１，１３−２と、ドレイン電極１３−１，１３−２の上に形成された有機絶縁膜１４と、有機絶縁膜１４の開口部１４Ｃおよび有機絶縁膜１４の上に形成された無機絶縁膜１６と、無機絶縁膜１６の開口部１６Ｃ−１，１６Ｃ−２および無機絶縁膜１６の上に形成された画素電極１８−１，１８−２と、を備える。
すなわち、表示装置１００では、複数の副画素に跨るように有機絶縁膜の開口部を設けて、画素電極とドレイン電極を接続させている。この画素構造では、画素サイズが微細化されて画素サイズが小さくなっても有機絶縁膜の開口部を小さくする必要がない。ドレイン電極の大きさは、無機絶縁膜の最小開口幅よりも大きければよい。ドレイン電極のＹ方向の幅は有機絶縁膜の開口部１４ＣのＹ方向の幅よりも広くしているが、有機絶縁膜の開口部１４ＣのＹ方向の幅よりも狭くしてもよい。上述したように無機絶縁膜の最小開口幅は有機絶縁膜の最小開口幅よりも小さくすることができるので、ドレイン電極の大きさを小さくすることができる。よって、開口率を大きくすることができ、また、画素ピッチが小さくなる高精細画素でも画素レイアウトが可能になる。 <Embodiment>
The display device according to the embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view showing the configuration of the display device according to the embodiment. 4 is a cross-sectional view taken along line AA ′ of FIG.
The display device 100 according to the embodiment includes a drain electrode 13-1, 13-2, an organic insulating film 14 formed on the drain electrode 13-1, 13-2, an opening 14C of the organic insulating film 14, and The inorganic insulating film 16 formed on the organic insulating film 14, the openings 16C-1 and 16C-2 of the inorganic insulating film 16, and the pixel electrodes 18-1 and 18-2 formed on the inorganic insulating film 16 And comprising.
That is, in the display device 100, an opening of the organic insulating film is provided so as to extend over a plurality of subpixels, and the pixel electrode and the drain electrode are connected. In this pixel structure, even if the pixel size is reduced and the pixel size is reduced, it is not necessary to reduce the opening of the organic insulating film. The size of the drain electrode may be larger than the minimum opening width of the inorganic insulating film. The width of the drain electrode in the Y direction is wider than the width in the Y direction of the opening 14C of the organic insulating film, but may be narrower than the width of the opening 14C in the organic insulating film in the Y direction. As described above, since the minimum opening width of the inorganic insulating film can be made smaller than the minimum opening width of the organic insulating film, the size of the drain electrode can be reduced. Therefore, the aperture ratio can be increased, and pixel layout is possible even for high-definition pixels with a small pixel pitch.

実施例１に係る表示装置について図５から図９を用いて説明する。図５は実施例１に係る表示装置の全体平面図である。図６は図５のＡ−Ａ’線における断面図である。図７は実施例１に係る表示装置の画素、走査線および信号線の配置を説明するための平面図である。図８は図７のＡの部分の画素コンタクトを示す平面図であり、１画素（３副画素）分が示されている。図９は図８のＡ−Ａ線’における断面図である。
図５および図６に示すように、実施例１に係る表示装置１００Ａは表示パネル１とドライバＩＣ２とバックライト３とを備える。表示パネル１は、アレイ基板１０Ａと、対向基板２０Ａと、アレイ基板１０Ａと対向基板２０Ａとの間に封入される液晶材料３０と、を備える。アレイ基板１０Ａと対向基板２０Ａとは、表示領域ＤＡを囲む環状のシール材４０で接着されており、液晶材料３０は、アレイ基板１０Ａ、対向基板２０Ａ、およびシール材４０で囲まれた空間に密封されている。また、アレイ基板１０Ａおよび対向基板２０Ａの外側を向いた面、すなわち、液晶材料３０と対向する面の裏面には、それぞれ、下偏光板５０Ａおよび上偏光板５０Ｂが設けられている。また、表示領域ＤＡは、例えば、マトリクス状に配置された複数個の画素の集合で構成されている。アレイ基板１０Ａは、後述するＹ方向に延在する信号線やＸ方向に延在する走査線、画素電極、および図示しないＴＦＴで形成された走査線を駆動する走査回路等を備える。対向基板２０Ａは、図示しないブラックマトリクスやカラーフィルタ等を備える。ドライバＩＣ２は、図示しない信号線を駆動する回路等を備える。 A display device according to Example 1 will be described with reference to FIGS. FIG. 5 is an overall plan view of the display device according to the first embodiment. 6 is a cross-sectional view taken along line AA ′ of FIG. FIG. 7 is a plan view for explaining the arrangement of pixels, scanning lines, and signal lines of the display device according to the first embodiment. FIG. 8 is a plan view showing the pixel contact in the portion A of FIG. 7 and shows one pixel (three sub-pixels). 9 is a cross-sectional view taken along line AA ′ of FIG.
As illustrated in FIGS. 5 and 6, the display device 100 </ b> A according to the first embodiment includes a display panel 1, a driver IC 2, and a backlight 3. The display panel 1 includes an array substrate 10A, a counter substrate 20A, and a liquid crystal material 30 sealed between the array substrate 10A and the counter substrate 20A. The array substrate 10A and the counter substrate 20A are bonded by an annular sealing material 40 surrounding the display area DA, and the liquid crystal material 30 is sealed in a space surrounded by the array substrate 10A, the counter substrate 20A, and the sealing material 40. Has been. Further, a lower polarizing plate 50A and an upper polarizing plate 50B are provided on the surfaces facing the outside of the array substrate 10A and the counter substrate 20A, that is, the back surfaces of the surfaces facing the liquid crystal material 30, respectively. Further, the display area DA is constituted by a set of a plurality of pixels arranged in a matrix, for example. The array substrate 10A includes a signal line extending in the Y direction, which will be described later, a scanning line extending in the X direction, a pixel electrode, a scanning circuit for driving a scanning line formed by a TFT (not shown), and the like. The counter substrate 20A includes a black matrix, a color filter, etc. (not shown). The driver IC 2 includes a circuit for driving a signal line (not shown).

図７に示すように、表示装置１００Ａは、赤（Ｒ）の副画素、緑（Ｇ）の副画素および白（Ｗ）の副画素で構成される第１の画素と、Ｒの副画素、Ｇの副画素および青（Ｂ）の副画素で構成される第２の画素と、が存在する。表示装置１００はＷの副画素の追加によって透過率を向上させるため、Ｂの副画素数の１／２をＷの副画素に置き換えている。第１の画素はＸ方向にＲの副画素およびＧの副画素とＷの副画素とが隣接配置されている。第２の画素はＸ方向にＲの副画素およびＧの副画素とＢの副画素とが隣接配置されている。Ｘ方向に第１の画素と第２の画素とが交互に配置され、Ｙ方向に第１の画素と第２の画素とが交互に配置されている。
Ｒの副画素、Ｇの副画素、Ｂの副画素およびＷの副画素は、それぞれ走査線（ゲート線）および信号線（ソース線）に接続される薄膜トランジスタ（ＴＦＴ）を備えている。走査線はＴＦＴのゲート電極に接続され、信号線はＴＦＴのソース電極に接続される。なお、信号線をドレイン線ということもあり、ドレイン線に接続されるＴＦＴの電極をドレイン電極という。Ｒの副画素は信号線ＳＬ１に接続され、Ｇの副画素は信号線ＳＬ２に接続され、Ｗの副画素およびＢの副画素は信号線ＳＬ３に接続される。 As illustrated in FIG. 7, the display device 100A includes a first pixel including a red (R) subpixel, a green (G) subpixel, and a white (W) subpixel, an R subpixel, And a second pixel composed of a G subpixel and a blue (B) subpixel. In order to improve the transmittance by adding the W subpixel, the display device 100 replaces ½ of the number of B subpixels with the W subpixel. In the first pixel, an R subpixel, a G subpixel, and a W subpixel are arranged adjacent to each other in the X direction. In the second pixel, an R subpixel, a G subpixel, and a B subpixel are adjacently arranged in the X direction. The first pixel and the second pixel are alternately arranged in the X direction, and the first pixel and the second pixel are alternately arranged in the Y direction.
Each of the R subpixel, the G subpixel, the B subpixel, and the W subpixel includes a thin film transistor (TFT) connected to a scanning line (gate line) and a signal line (source line). The scanning line is connected to the gate electrode of the TFT, and the signal line is connected to the source electrode of the TFT. The signal line is sometimes referred to as a drain line, and the TFT electrode connected to the drain line is referred to as a drain electrode. The R subpixel is connected to the signal line SL1, the G subpixel is connected to the signal line SL2, and the W subpixel and the B subpixel are connected to the signal line SL3.

図８および図９に示すように、表示装置１００Ａのアレイ基板１０Ａは、信号線１２−１（ＳＬ１），１２−２（ＳＬ２），１２−３（ＳＬ３）と、ドレイン電極１３−１，１３−２，１３−３と、信号線１２−１，１２−２，１２−３およびドレイン電極１３−１，１３−２，１３−３の上に形成された有機絶縁膜１４と、を備える。アレイ基板１０Ａは、さらに、有機絶縁膜１４の開口部（コンタクトホール）１４Ｃおよび有機絶縁膜１４の上に形成された無機絶縁膜１６と、無機絶縁膜１６の開口部（コンタクトホール）１６Ｃ−１，１６Ｃ−２，１６Ｃ−３および無機絶縁膜１６の上に形成された画素電極１８−１，１８−２，１８−３と、を備える。なお、アレイ基板１０Ａは、図示しないガラス基板やドレイン電極に接続されるＴＦＴ、ＴＦＴのゲート電極に接続される走査線、有機絶縁膜１４と、無機絶縁膜１６との間に配置される共通電極等も備える。有機絶縁膜１４は平坦化膜と機能するため、無機絶縁膜１６よりも厚く形成されている。信号線は、図示しないＴＦＴのソース電極に接続される。
すなわち、表示装置１００Ａでは、３副画素（１画素）に跨るように有機絶縁膜の開口部１４Ｃを設けて、画素電極１３−１，１３−２，１３−３とドレイン電極１８−１，１８−２，１８−３を接続させている。この画素構造では、画素サイズが微細化されて画素サイズが小さくなっても有機絶縁膜の開口部を小さくする必要がない。ドレイン電極の大きさは、絶縁膜の最小開口幅よりも大きければよい。上述したように無機絶縁膜の最小開口幅は有機絶縁膜の最小開口幅よりも小さくすることができるので、ドレイン電極の大きさを小さくすることができる。 As shown in FIGS. 8 and 9, the array substrate 10A of the display device 100A includes signal lines 12-1 (SL1), 12-2 (SL2), 12-3 (SL3) and drain electrodes 13-1, 13. -2, 13-3, and the organic insulating film 14 formed on the signal lines 12-1, 12-2, 12-3 and the drain electrodes 13-1, 13-2, 13-3. The array substrate 10A further includes an opening (contact hole) 14C of the organic insulating film 14 and an inorganic insulating film 16 formed on the organic insulating film 14, and an opening (contact hole) 16C-1 of the inorganic insulating film 16. , 16C-2, 16C-3, and pixel electrodes 18-1, 18-2, 18-3 formed on the inorganic insulating film 16. The array substrate 10A includes a TFT connected to a glass substrate (not shown) and a drain electrode, a scanning line connected to the gate electrode of the TFT, a common electrode disposed between the organic insulating film 14 and the inorganic insulating film 16. Etc. Since the organic insulating film 14 functions as a planarizing film, the organic insulating film 14 is formed thicker than the inorganic insulating film 16. The signal line is connected to a source electrode of a TFT (not shown).
That is, in the display device 100A, an opening 14C of an organic insulating film is provided so as to straddle three subpixels (one pixel), and the pixel electrodes 13-1, 13-2, 13-3 and the drain electrodes 18-1, 18 are provided. -2, 18-3 are connected. In this pixel structure, even if the pixel size is reduced and the pixel size is reduced, it is not necessary to reduce the opening of the organic insulating film. The drain electrode may be larger than the minimum opening width of the insulating film. As described above, since the minimum opening width of the inorganic insulating film can be made smaller than the minimum opening width of the organic insulating film, the size of the drain electrode can be reduced.

３副画素（１画素）に跨るように有機絶縁膜の開口部１４Ｃを設けたが、複数画素やＸ方向のすべての画素に跨るように有機絶縁膜の開口部１４Ｃを設けてもよい。ドレイン電極のＹ方向の幅は有機絶縁膜の開口部１４ＣのＹ方向の幅よりも広くしているが、有機絶縁膜の開口部１４ＣのＹ方向の幅よりも狭くしてもよい。   Although the organic insulating film opening 14C is provided so as to straddle three subpixels (one pixel), the organic insulating film opening 14C may be provided so as to straddle a plurality of pixels or all pixels in the X direction. The width of the drain electrode in the Y direction is wider than the width in the Y direction of the opening 14C of the organic insulating film, but may be narrower than the width of the opening 14C in the organic insulating film in the Y direction.

実施例２に係る表示装置について図１０、図１２および図１３を用いて説明する。図１０は実施例２に係る表示装置の画素、走査線および信号線の配置を説明するための平面図である。図１２は図７のＡの部分の画素コンタクトを示す平面図であり、１画素（３副画素）分が示されている。図１３は図１２のＡ−Ａ線’における断面図である。
実施例２に係る表示装置１００Ｂは実施例１に係る表示装置１００Ａと画素および信号線の配置が異なるが、これら以外は基本的に表示装置１００Ａと同様な構成である。図１０に示すように、表示装置１００Ｂは、Ｒの副画素、Ｇの副画素およびＷの副画素で構成される第１の画素と、Ｒの副画素、Ｇの副画素およびＢの副画素で構成される第２の画素と、が存在する。表示装置１００ＢはＷの副画素の追加によって透過率を向上させるため、Ｂの副画素数の１／２をＷの副画素に置き換えている。Ｇの副画素およびＲの副画素のそれぞれの開口面積は、Ｂの副画素およびＷの副画素のそれぞれの開口面積の約１／２にしている。第１の画素はＹ方向にＲの副画素とＧの副画素とが隣接配置され、Ｘ方向にＲの副画素およびＧの副画素とＷの副画素とが隣接配置されている。第２の画素はＹ方向にＲの副画素とＧの副画素とが隣接配置され、Ｘ方向にＲの副画素およびＧの副画素とＢの副画素とが隣接配置されている。Ｘ方向に第１の画素と第２の画素とが交互に配置され、Ｙ方向に第１の画素と第２の画素とが交互に配置されている。 A display device according to Example 2 will be described with reference to FIGS. 10, 12, and 13. FIG. 10 is a plan view for explaining the arrangement of pixels, scanning lines, and signal lines of the display device according to the second embodiment. FIG. 12 is a plan view showing a pixel contact in a portion A in FIG. 7, and shows one pixel (three subpixels). 13 is a cross-sectional view taken along line AA ′ of FIG.
The display device 100B according to the second embodiment differs from the display device 100A according to the first embodiment in the arrangement of pixels and signal lines, but basically has the same configuration as the display device 100A except for these. As illustrated in FIG. 10, the display device 100B includes a first pixel including an R subpixel, a G subpixel, and a W subpixel, an R subpixel, a G subpixel, and a B subpixel. There is a second pixel comprised of In order to improve the transmittance by adding the W subpixel, the display device 100B replaces ½ of the number of B subpixels with the W subpixel. The opening area of each of the G subpixel and the R subpixel is approximately ½ of the opening area of each of the B subpixel and the W subpixel. In the first pixel, an R subpixel and a G subpixel are arranged adjacent to each other in the Y direction, and an R subpixel, a G subpixel, and a W subpixel are arranged adjacent to each other in the X direction. In the second pixel, an R subpixel and a G subpixel are arranged adjacent to each other in the Y direction, and an R subpixel, a G subpixel, and a B subpixel are arranged adjacent to each other in the X direction. The first pixel and the second pixel are alternately arranged in the X direction, and the first pixel and the second pixel are alternately arranged in the Y direction.

Ｒの副画素、Ｇの副画素、Ｂの副画素およびＷの副画素は、それぞれ走査線（ゲート線）および信号線（ソース線）に接続される薄膜トランジスタ（ＴＦＴ）を備えている。走査線はＴＦＴのゲート電極に接続され、信号線はＴＦＴのソース電極に接続される。なお、信号線をドレイン線ということもあり、ドレイン線に接続されるＴＦＴの電極をドレイン電極という。   Each of the R subpixel, the G subpixel, the B subpixel, and the W subpixel includes a thin film transistor (TFT) connected to a scanning line (gate line) and a signal line (source line). The scanning line is connected to the gate electrode of the TFT, and the signal line is connected to the source electrode of the TFT. The signal line is sometimes referred to as a drain line, and the TFT electrode connected to the drain line is referred to as a drain electrode.

走査線ＧＬ１と走査線ＧＬ２との間に配置された第１の画素のＲの副画素およびＷの副画素は走査線ＧＬ１に接続され、Ｇの副画素は走査線ＧＬ２に接続される。また、走査線ＧＬ１と走査線ＧＬ２との間に配置された第２の画素のＲの副画素およびＢの副画素は走査線ＧＬ１に接続され、Ｇの副画素は走査線ＧＬ２に接続される。言い換えると、走査線ＧＬ２を挟んで隣接する第１の画素のＧの副画素および第２の画素のＲの副画素は走査線ＧＬ２に接続される。また、走査線ＧＬ２を挟んで隣接する第２の画素のＧの副画素および第１の画素のＲの副画素は走査線ＧＬ２に接続される。走査線ＧＬ２を挟んで隣接する第１の画素のＷの副画素は走査線ＧＬ１に接続され、第２の画素のＢの副画素は走査線ＧＬ２に接続される。すなわち、Ｙ方向に隣接するＧの副画素とＲの副画素とは同一の走査線に接続され、Ｙ方向に隣接するＷの副画素とＢの副画素とは異なる走査線に接続される。   The R subpixel and the W subpixel of the first pixel arranged between the scanning line GL1 and the scanning line GL2 are connected to the scanning line GL1, and the G subpixel is connected to the scanning line GL2. In addition, the R subpixel and the B subpixel of the second pixel arranged between the scan line GL1 and the scan line GL2 are connected to the scan line GL1, and the G subpixel is connected to the scan line GL2. . In other words, the G subpixel of the first pixel and the R subpixel of the second pixel which are adjacent to each other across the scanning line GL2 are connected to the scanning line GL2. Further, the G sub-pixel of the second pixel and the R sub-pixel of the first pixel which are adjacent to each other across the scanning line GL2 are connected to the scanning line GL2. The W subpixel of the first pixel adjacent to the scan line GL2 is connected to the scan line GL1, and the B subpixel of the second pixel is connected to the scan line GL2. That is, the G subpixel and the R subpixel adjacent in the Y direction are connected to the same scanning line, and the W subpixel and the B subpixel adjacent in the Y direction are connected to different scanning lines.

Ｒの副画素は信号線ＳＬ１に接続され、Ｇの副画素は信号線ＳＬ２に接続され、Ｗの副画素およびＢの副画素は信号線ＳＬ３に接続される。Ｒの副画素およびＧの副画素は信号線ＳＬ１と信号線ＳＬ２との間に配置され、Ｗの副画素およびＢの副画素は信号線ＳＬ３と信号線ＳＬ４との間に配置される。言い換えると、信号線ＳＬ１と信号線ＳＬ２との間に配置されたＲの副画素は信号線ＳＬ１に接続され、信号線ＳＬ１と信号線ＳＬ２との間に配置されたＧの副画素は信号線ＳＬ２に接続される。また、信号線ＳＬ３と信号線ＳＬ４との間に配置されたＷの副画素およびＢの副画素は信号線ＳＬ３に接続される。なお、信号線ＳＬ２と信号線ＳＬ３との間には副画素は配置されない。すなわち、副画素間に信号線が１本配置されるものと、副画素間に２本の信号線が配置されるものとがある。   The R subpixel is connected to the signal line SL1, the G subpixel is connected to the signal line SL2, and the W subpixel and the B subpixel are connected to the signal line SL3. The R subpixel and the G subpixel are arranged between the signal line SL1 and the signal line SL2, and the W subpixel and the B subpixel are arranged between the signal line SL3 and the signal line SL4. In other words, the R subpixel arranged between the signal line SL1 and the signal line SL2 is connected to the signal line SL1, and the G subpixel arranged between the signal line SL1 and the signal line SL2 is connected to the signal line SL1. Connected to SL2. The W subpixel and the B subpixel arranged between the signal line SL3 and the signal line SL4 are connected to the signal line SL3. Note that no sub-pixel is disposed between the signal line SL2 and the signal line SL3. That is, there are one in which one signal line is arranged between subpixels and one in which two signal lines are arranged between subpixels.

＜比較例２＞
実施例２に係る表示装置の画素配列において比較例１と同様に有絶縁膜の開口部を設けた例（以下、比較例２という。）ついて図１１を用いて説明する。図１１は比較例２に係る表示装置の構成を示す平面図であり、１画素（３副画素）分が示されている。
比較例２に係る表示装置１００Ｓは、信号線１２−１，１２−２，１２−３，１２−４と、ドレイン電極１３−１，１３−２，１３−３と、信号線１２−１，１２−２，１２−３およびドレイン電極１３−１，１３−２，１３−３の上に形成された有機絶縁膜１４と、を備える。表示装置１００Ｓは、さらに、有機絶縁膜１４の開口部１４Ｃ−１，１４Ｃ−２，１４Ｃ−３および有機絶縁膜１４の上に形成された無機絶縁膜１６と、無機絶縁膜１６の開口部１６Ｃ−１，１６Ｃ−２，１６Ｃ−３および無機絶縁膜１６の上に形成された画素電極１８−１，１８−２，１８−３と、を備える。信号線１２−１と信号線１２−２との間（SUBPIXCEL(1)）に、ドレイン電極１３−１，１３−２と、有機絶縁膜１４の開口部１４Ｃ−１，１４Ｃ−２と、無機絶縁膜１６の開口部１６Ｃ−１，１６Ｃ−２と、画素電極１８−１，１８−２と、を備える。信号線１２−３と信号線１２−４との間（SUBPIXCEL(2)）に、ドレイン電極１３−３と、有機絶縁膜１４の開口部１４Ｃ−３と、無機絶縁膜１６の開口部１６Ｃ−３と、画素電極１８−３と、を備える。表示装置１００ＳのＲの副画素およびＧの副画素部（SUBPIXCEL(1)）では、１画素幅の約１／２の幅に有機絶縁膜の開口部１４Ｃ−１，１４Ｃ−２を２つ設ける必要があることから比較例１よりも高精細画素では画素レイアウトが困難である。 <Comparative example 2>
An example in which an opening portion of an insulating film is provided in the pixel array of the display device according to Example 2 as in Comparative Example 1 (hereinafter referred to as Comparative Example 2) will be described with reference to FIG. FIG. 11 is a plan view showing a configuration of a display device according to Comparative Example 2, and shows one pixel (three subpixels).
A display device 100S according to Comparative Example 2 includes signal lines 12-1, 12-2, 12-3, and 12-4, drain electrodes 13-1, 13-2, and 13-3, and signal lines 12-1, 12-2, 12-3 and the organic insulating film 14 formed on the drain electrodes 13-1, 13-2, 13-3. The display device 100S further includes an inorganic insulating film 16 formed on the openings 14C-1, 14C-2, 14C-3 and the organic insulating film 14 of the organic insulating film 14, and an opening 16C of the inorganic insulating film 16. -1, 16C-2, 16C-3 and pixel electrodes 18-1, 18-2, 18-3 formed on the inorganic insulating film 16. Between the signal line 12-1 and the signal line 12-2 (SUBPIXCEL (1)), the drain electrodes 13-1, 13-2, the openings 14C-1, 14C-2 of the organic insulating film 14, and the inorganic Openings 16C-1 and 16C-2 of the insulating film 16 and pixel electrodes 18-1 and 18-2 are provided. Between the signal line 12-3 and the signal line 12-4 (SUBPIXCEL (2)), the drain electrode 13-3, the opening 14C-3 of the organic insulating film 14, and the opening 16C- of the inorganic insulating film 16 are provided. 3 and the pixel electrode 18-3. In the R subpixel and the G subpixel portion (SUBPIXCEL (1)) of the display device 100S, two openings 14C-1 and 14C-2 of the organic insulating film are provided in about a half of one pixel width. Since it is necessary, the pixel layout is difficult for a high-definition pixel as compared with Comparative Example 1.

図１２および図１３に示すように、実施例２に係る表示装置１００Ｂのアレイ基板は、信号線１２−１（ＳＬ１），１２−２（ＳＬ２），１２−３（ＳＬ３）と、ドレイン電極１３−１，１３−２，１３−３と、信号線１２−１，１２−２，１２−３およびドレイン電極１３−１，１３−２，１３−３の上に形成された有機絶縁膜１４と、をそなえる。表示装置１００Ｂのアレイ基板は、さらに、有機絶縁膜１４の開口部１４Ｃ、有機絶縁膜１４の開口部（コンタクトホール）１４Ｃ−３および有機絶縁膜１４の上に形成された無機絶縁膜１６と、無機絶縁膜１６の開口部１６Ｃ−１，１６Ｃ−２，１６Ｃ−３および無機絶縁膜１６の上に形成された画素電極１８−１，１８−２，１８−３と、を備える。信号線１２−１と信号線１２−２との間（SUBPIXCEL(1)）に、ドレイン電極１３−１，１３−２と、有機絶縁膜１４の開口部１４Ｃと、無機絶縁膜１６の開口部１６Ｃ−１，１６Ｃ−２と、画素電極１８−１，１８−２と、を備える。信号線１２−３と信号線１２−４との間（SUBPIXCEL(2)）に、ドレイン電極１３−３と、有機絶縁膜１４の開口部１４Ｃ−３と、無機絶縁膜１６の開口部１６Ｃ−３と、画素電極１８−３と、を備える。なお、表示装置１００Ｂのアレイ基板は、表示装置１００Ａと同様に、図示しないガラス基板やドレイン電極に接続されるＴＦＴ、ＴＦＴのゲート電極に接続される走査線、有機絶縁膜１４と無機絶縁膜１６との間に配置される共通電極等を備える。信号線は、図示しないＴＦＴのソース電極に接続される。表示装置１００Ｂの対向基板は、表示装置１００Ａと同様に、図示しないブラックマトリクスやカラーフィルタ等を備える。
すなわち、表示装置１００Ｂでは、２副画素に跨るように有機絶縁膜の開口部１４Ｃを設けて、画素電極１３−１，１３−２とドレイン電極１８−１，１８−２をそれぞれ接続させている。この画素構造では、画素サイズが微細化されて画素サイズが小さくなっても有機絶縁膜の開口部を小さくする必要がない。ドレイン電極の大きさは、無機絶縁膜の最小開口幅よりも大きければよい。上述したように無機絶縁膜の最小開口幅は有機絶縁膜の最小開口幅よりも小さくすることができるので、ドレイン電極の大きさを小さくすることができる。 As illustrated in FIGS. 12 and 13, the array substrate of the display device 100 </ b> B according to the second embodiment includes signal lines 12-1 (SL <b> 1), 12-2 (SL <b> 2), and 12-3 (SL <b> 3), and the drain electrode 13. -1, 13-2, 13-3, and the organic insulating film 14 formed on the signal lines 12-1, 12-2, 12-3 and the drain electrodes 13-1, 13-2, 13-3, . The array substrate of the display device 100B further includes an opening 14C of the organic insulating film 14, an opening (contact hole) 14C-3 of the organic insulating film 14, and an inorganic insulating film 16 formed on the organic insulating film 14. And openings 16C-1, 16C-2, 16C-3 of the inorganic insulating film 16 and pixel electrodes 18-1, 18-2, 18-3 formed on the inorganic insulating film 16. Between the signal line 12-1 and the signal line 12-2 (SUBPIXCEL (1)), the drain electrodes 13-1, 13-2, the opening 14C of the organic insulating film 14, and the opening of the inorganic insulating film 16 are provided. 16C-1 and 16C-2 and pixel electrodes 18-1 and 18-2. Between the signal line 12-3 and the signal line 12-4 (SUBPIXCEL (2)), the drain electrode 13-3, the opening 14C-3 of the organic insulating film 14, and the opening 16C- of the inorganic insulating film 16 are provided. 3 and the pixel electrode 18-3. Note that the array substrate of the display device 100B is similar to the display device 100A in that the TFT is connected to a glass substrate or drain electrode (not shown), the scanning line connected to the gate electrode of the TFT, the organic insulating film 14 and the inorganic insulating film 16. And a common electrode disposed between the two. The signal line is connected to a source electrode of a TFT (not shown). Similar to the display device 100A, the counter substrate of the display device 100B includes a black matrix, a color filter, and the like (not shown).
That is, in the display device 100B, an opening 14C of an organic insulating film is provided so as to straddle two subpixels, and the pixel electrodes 13-1 and 13-2 and the drain electrodes 18-1 and 18-2 are connected to each other. . In this pixel structure, even if the pixel size is reduced and the pixel size is reduced, it is not necessary to reduce the opening of the organic insulating film. The size of the drain electrode may be larger than the minimum opening width of the inorganic insulating film. As described above, since the minimum opening width of the inorganic insulating film can be made smaller than the minimum opening width of the organic insulating film, the size of the drain electrode can be reduced.

２副画素（１画素）に跨るように有機絶縁膜の開口部１４Ｃを設けたが、３副画素（１画素）や複数画素、Ｘ方向のすべての画素に跨るように有機絶縁膜の開口部１４Ｃを設けてもよい。ドレイン電極のＹ方向の幅は有機絶縁膜の開口部１４ＣのＹ方向の幅よりも広くしているが、有機絶縁膜の開口部１４ＣのＹ方向の幅よりも狭くしてもよい。   Although the opening 14C of the organic insulating film is provided so as to straddle two subpixels (one pixel), the opening of the organic insulating film so as to straddle three subpixels (one pixel), a plurality of pixels, and all pixels in the X direction. 14C may be provided. The width of the drain electrode in the Y direction is wider than the width in the Y direction of the opening 14C of the organic insulating film, but may be narrower than the width of the opening 14C in the organic insulating film in the Y direction.

１・・・表示パネル
２・・・ドライバＩＣ
３・・・バックライト
１０Ａ・・・アレイ基板
１２−１，１２−２，１２−３，１２−４・・・信号線
１３−１，１３−２，１３−３・・・ドレイン電極
１４・・・有機絶縁膜
１４Ｃ−１，１４Ｃ−２，１４Ｃ−３・・・有機絶縁膜の開口部
１６・・・無機絶縁膜
１６Ｃ−１，１６Ｃ−２，１６Ｃ−３・・・無機絶縁膜の開口部
１８・・・画素電極
２０Ａ・・・対向基板
３０・・・液晶層
４０・・・シール
５０Ａ，５０Ｂ・・・偏光板
１００・・・表示装置
ＧＬ１，ＧＬ２，ＧＬ３・・・走査線
ＳＬ１，ＳＬ２，ＳＬ３，ＳＬ４，ＳＬ５，ＳＬ６，ＳＬ７，ＳＬ８，ＳＬ９・・・信号線 1 ... Display panel 2 ... Driver IC
3 ... Backlight 10A ... Array substrates 12-1, 12-2, 12-3, 12-4 ... Signal lines 13-1, 13-2, 13-3 ... Drain electrode 14 ..Organic insulating films 14C-1, 14C-2, 14C-3... Organic insulating film openings 16... Inorganic insulating films 16C-1, 16C-2, 16C-3. Opening 18 ... Pixel electrode 20A ... Counter substrate 30 ... Liquid crystal layer 40 ... Seals 50A, 50B ... Polarizing plate 100 ... Display devices GL1, GL2, GL3 ... Scanning line SL1 , SL2, SL3, SL4, SL5, SL6, SL7, SL8, SL9 ... signal lines

Claims (9)

アレイ基板と対向基板とを備えた表示装置であって、
前記アレイ基板は、
第１および第２のドレイン電極と、
信号線と、
前記信号線が延在する方向とは異なる方向に延在する走査線と、
前記信号線上に形成された有機絶縁膜と、
前記有機絶縁膜上に形成された無機絶縁膜と、
前記無機絶縁膜上に形成された第１および第２の画素電極と、
を備え、
前記第１のドレイン電極は第１の副画素のＴＦＴの電極であり、
前記第２のドレイン電極は第２の副画素のＴＦＴの電極であり、
前記第２の副画素は前記第１の副画素と前記走査線が延在する方向に隣接し、
前記有機絶縁膜の形成された層は前記走査線が延在する方向に沿って前記第１のドレイン電極と前記第２のドレイン電極とに跨る前記有機絶縁膜が除去された有機絶縁膜開口部を備え、
前記無機絶縁膜は前記有機絶縁膜開口部を覆って形成され、前記有機絶縁膜開口部を覆う前記無機絶縁膜の形成された層は、前記第１の副画素に形成された第１の無機絶縁膜開口部および前記第２の副画素に形成された第２の無機絶縁膜開口部を備え、
前記第１の画素電極は前記第１の無機絶縁膜開口部を介して前記第１のドレイン電極に接続され、
前記第２の画素電極は前記第２の無機絶縁膜開口部を介して前記第２のドレイン電極に接続されることを特徴とする表示装置。 A display device comprising an array substrate and a counter direction board,
The array substrate is
First and second drain electrodes;
A signal line;
A scanning line extending in a direction different from a direction in which the signal line extends;
An organic insulating film formed on the signal line;
An inorganic insulating film formed on the organic insulating film;
First and second pixel electrodes formed on the inorganic insulating film;
With
The first drain electrode is a TFT electrode of the first subpixel,
The second drain electrode is a TFT electrode of the second subpixel,
The second subpixel is adjacent to the first subpixel in the direction in which the scanning line extends,
The layer where the organic insulating film is formed is an organic insulating film opening in which the organic insulating film straddling the first drain electrode and the second drain electrode along the direction in which the scanning line extends is removed. With
The inorganic insulating film is formed to cover the organic insulating film opening, the layer formed of the inorganic insulating layer covering the organic insulating film opening, a first inorganic formed in the first subpixel An insulating film opening and a second inorganic insulating film opening formed in the second subpixel ;
The first pixel electrode is connected to the first drain electrode through the first inorganic insulating film opening,
The display device, wherein the second pixel electrode is connected to the second drain electrode through the second inorganic insulating film opening. 前記信号線は前記第１のドレイン電極と前記第２のドレイン電極との間に配置されることを特徴とする請求項１記載の表示装置。 Before SL signal line display apparatus according to claim 1, characterized in that it is disposed between the second drain electrode and the first drain electrode. 前記第１および第２の画素電極のそれぞれは、前記信号線が延在する方向に沿うように、前記第１および第２の無機絶縁膜開口部から同一方向に延在することを特徴とする請求項１記載の表示装置。 Each of the previous SL first and second pixel electrodes, and wherein the signal line is along a direction extending, extending in the same direction from said first and second inorganic insulating film opening The display device according to claim 1 . 第３のドレイン電極と前記無機絶縁膜上に形成された第３の画素電極とを備え、
前記有機絶縁膜開口部は前記第１のドレイン電極と前記第２のドレイン電極と前記第３のドレイン電極に跨るようにされ、
前記有機絶縁膜開口部を覆う前記無機絶縁膜は第３の無機絶縁膜開口部を備え、
前記第１の画素電極は前記第１の無機絶縁膜開口部を介して前記第１のドレイン電極に接続され、
前記第２の画素電極は前記第２の無機絶縁膜開口部を介して前記第２のドレイン電極に接続され、
前記第３の画素電極は前記第３の無機絶縁膜開口部を介して前記第３のドレイン電極に接続されることを特徴とする請求項１記載の表示装置。 A third drain electrode and a third pixel electrode formed on the inorganic insulating film,
The organic insulating film opening extends over the first drain electrode, the second drain electrode, and the third drain electrode,
The inorganic insulating film covering the organic insulating film opening includes a third inorganic insulating film opening;
The first pixel electrode is connected to the first drain electrode through the first inorganic insulating film opening,
The second pixel electrode is connected to the second drain electrode through the second inorganic insulating film opening,
The display device according to claim 1, wherein the third pixel electrode is connected to the third drain electrode through the third inorganic insulating film opening. 前記第３のドレイン電極は第３の副画素のＴＦＴの電極であり、
前記第３のドレイン電極は前記第２の副画素に隣接する第３の副画素のＴＦＴの電極であることを特徴とする請求項４記載の表示装置。 Before Symbol third drain electrode is an electrode of the third sub-pixel TFT,
5. The display device according to claim 4, wherein the third drain electrode is a TFT electrode of a third subpixel adjacent to the second subpixel. 前記第３の副画素は前記第２の副画素と前記信号線が延在する方向とは異なる方向に隣接することを特徴とする請求項５記載の表示装置。 Before Symbol display device according to claim 5, wherein the adjacent in a direction different from the third sub-pixel of the direction in which the signal line and the second sub-pixel extends. 前記アレイ基板と前記対向基板とに挟持される液晶層を備えることを特徴とする請求項１記載の表示装置。 Before Symbol display apparatus according to claim 1, further comprising a liquid crystal layer sandwiched between the array substrate and the counter substrate. 前記対向基板はブラックマトリクスとカラーフィルタとを備えることを特徴とする請求項１記載の表示装置。 Before Symbol counter substrate display device according to claim 1, characterized in that it comprises a black matrix and a color filter. 前記アレイ基板は前記有機絶縁膜と前記無機絶縁膜の間に共通電極を備えることを特徴とする請求項１記載の表示装置。 Display device according to claim 1, characterized in that it comprises a common electrode between the front SL array substrate wherein the organic insulating film and the inorganic insulating film.
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