JP6482453B2 - Impulse UWB receiver circuit - Google Patents

Description

  The present invention relates to an impulse UWB receiving circuit.

  Conventionally, a distance measurement / positioning system (for example, refer to Patent Document 1) for receiving a UWB (Ultra Wide Band) signal and detecting the distance to the measurement object and its position, and data communication using the UWB signal There is a system.

JP 2014-65566 A

However, in addition to the original received signal to be detected (hereinafter sometimes referred to as the main signal), if there is a reflected wave reflected by another object such as a building or an unnecessary signal such as noise, it will be erroneously detected. If an unnecessary signal exists at a timing close to the main signal, the waveform of the main signal is affected and becomes a temporal error factor.
That is, there is a problem that an unnecessary signal other than the main signal is received to cause a data detection error or a distance measurement error.

Accordingly, an object of the present invention is to provide an impulse UWB receiving circuit that reliably removes unnecessary signals and receives only a main signal with high accuracy with a relatively simple circuit configuration.
In particular, the object is to reliably reduce the error rate in receiving the impulse UWB.

  In order to achieve the above object, an impulse UWB reception circuit according to the present invention includes a PLL circuit unit that outputs a lock signal indicating synchronization with an impulse UWB signal, a clock signal from the PLL circuit unit, A timing signal generator that outputs a timing signal when both of the lock signals are input, a blocking signal generator that outputs a blocking signal based on the timing signal, and an on / off control of the UWB signal based on the blocking signal And a reception signal switch unit configured to block unnecessary signals between waveforms of UWB signals to be detected.

  According to the present invention, even if an unnecessary signal such as a reflected wave or noise reflected from another object exists between the waveforms of UWB signals to be detected, the unnecessary signal is blocked and detected. A power UWB signal (main signal) can be extracted with high accuracy and reliability. That is, it is possible to reduce the occurrence of errors such as data detection errors and distance measurement errors (error rate), and to obtain an accurate UWB ranging / positioning system and UWB data communication system that are excellent in stability.

It is a block diagram which shows embodiment of the impulse UWB receiving circuit of this invention. It is a circuit diagram. It is an action explanatory view, (a) is an action explanatory view showing an example of a received waveform, (b) is an action explanatory view showing an example of a conventional detection waveform, and (c) is a conventional pulse signal. It is an operation explanatory view showing an example, (d) is an operation explanatory view showing an output of a blocking signal, and (e) is an operation explanatory view showing a pulse signal of an example.

The impulse UWB reception circuit of the present invention will be described in detail below based on the illustrated embodiment.
As shown in FIG. 1, an antenna unit 11 for receiving an impulse UWB signal S, a first amplifying unit 12 for amplifying the received UWB signal S, provided in a circuit on the receiver side, are received. An envelope detection unit 14 for detecting the UWB signal S as an (envelope) detection waveform, and a UWB signal from the first amplification unit 12 interposed between the first amplification unit 12 and the envelope detection unit 14 The reception signal switch unit 13 for switching on / off the UWB signal S by switching whether or not to transmit S to the envelope detection unit 14 and the UWB signal S ′ (main signal detection waveform S ′) subjected to the envelope detection are amplified. The second amplifying unit 15, an automatic gain control unit 16 for adjusting (feedback control) so that the gain is in an appropriate range, and a pulse converting unit 17 for converting the UWB signal S from a detected waveform into a pulse signal. And the pulse-converted UWB signal S ″ (main A PLL circuit section (phase synchronization circuit section) 18 for extracting data from the signal pulse S ″), and a digital processing section 19 for digitally processing the main signal pulse S ″ extracted by the PLL circuit section 18. I have. Based on the data processed by the digital processing unit 19, the distance and position to the measurement object are calculated by an arithmetic processor such as a CPU or an integrated circuit (not shown).

  In FIG. 2, an antenna unit 11 is an antenna member 11 having an antenna element, a first amplifier unit 12 is a high frequency amplifier (LNA: Low Noise Amplifier) 12, and a received signal switch unit 13 is an ON-OFF switch. Unit 13, envelope detector 14 is detector (envelope detector circuit) 14, second amplifier 15 is amplifier (AMP) 15, and automatic gain controller 16 is AGC (Automatic Gain Control). ) A circuit unit 16, a pulse conversion unit 17 is a comparator (comparator) 17 set to a predetermined threshold value (threshold value), and a digital processing unit 19 is a baseband circuit unit 19.

The PLL (Phase Locked Loop) circuit unit 18 can output the clock signal Ia and start and synchronize (locked) when it recognizes the preamble (initial signal for synchronization) of the impulse UWB signal S. Is a circuit that can output a lock signal Ib.
The PLL circuit unit 18 inputs the output of the (internal) variable frequency oscillator and the input from the pulse conversion unit 17 to the (internal) phase comparator, and automatically automatically eliminates the phase difference between the two signals. The frequency of the variable frequency oscillator is controlled, and the lock signal Ib is output in a state where the phase difference is eliminated.

  Further, as shown in FIG. 1, when both the clock signal Ia and the lock signal Ib from the PLL circuit unit 18 are input, the timing signal generating unit 20 that outputs the timing signal Ic and blocking based on the timing signal Ic. And a blocking signal creation unit 21 that outputs the signal Id to the reception signal switch unit 13.

In FIG. 2, the timing signal generation unit 20 is an AND circuit unit 20.
The AND circuit unit 20 outputs the timing signal Ic when both the clock signal Ia and the lock signal Ib from the PLL circuit unit 18 are input. That is, the timing signal Ic is obtained when the correct reception system is in place (when synchronization is established).
This timing signal Ic is synchronized with the UWB signal S (detection output) to be detected.

  When the timing signal Ic is input as a trigger signal to an integrated circuit that can be configured by a circuit designer, for example, a PLD (programmable logic device) or an FPGA (field-programmable gate array), the blocking signal creation unit 21 The programmable one-shot multi-circuit unit 21 is programmed to output a signal having a predetermined pulse width (one-shot pulse) as a blocking signal Id.

  The ON-OFF switch unit 13 disables the signal transmission function between the LNA 12 and the detector 14 while receiving the blocking signal Id. When the blocking signal Id is not received, the LNA 12 And the detector 14 are controlled in two states so that the signal transmission function is in an effective state (ON).

Next, the operation (action) of the impulse UWB receiving circuit of the present invention will be described.
Until the antenna unit 11 receives various signals and the PLL circuit unit 18 confirms the preamble (synchronization initial signal), the locked state is not generated and the lock signal Ib is not output. The clock signal Ia is output in both the locked state and the unlocked state.

  When the antenna member 11 receives the preamble (initial signal for synchronization) of the UWB signal S and the PLL circuit unit 18 recognizes (synchronization confirmation), a lock (information) signal Ib is output from the PLL circuit unit 18.

The AND circuit unit 20 outputs a timing signal Ic when both the lock signal Ib and the clock signal Ia are input.
When the timing signal Ic is input, the programmable one-shot multicircuit unit 21 outputs a blocking signal Id.

  While the blocking signal Id is being input, the ON-OFF switch unit 13 invalidates (cuts or cuts off) the signal transmission function between the LNA 12 and the detector 14, and with respect to the signal received by the antenna unit 11. The reception signal detection (detection) cannot be performed.

Here, as shown in FIG. 3A, the received waveform received by the antenna unit 11 is reflected by a UWB signal S to be detected (hereinafter also referred to as a main signal S) and other objects. There are unnecessary signals Z such as reflected waves and noise.
As shown in FIG. 3B, in the prior art, the UWB signal S and the unnecessary signal Z to be detected are converted into a detection waveform by the envelope detection unit 14.
Hereinafter, for ease of explanation, the UWB signal S ′ converted to the detected waveform is called a main signal detected waveform S ′, and the unnecessary signal Z ′ converted to the detected waveform is called an unnecessary detected waveform Z ′. There is a case.

Then, as in the prior art shown in FIGS. 3B and 3C, the pulse conversion unit 17 causes the detection waveform (main signal detection waveform S ′ and unnecessary detection waveform Z ′) to be a predetermined threshold value (predetermined voltage value). Is converted into a pulse.
Although the UWB signal S to be detected can be detected as a pulse signal, if the unnecessary detection waveform Z ′ (detection waveform of the unnecessary signal Z) exceeds a predetermined threshold, it is detected as a pulse signal.
That is, a pulse signal S ″ obtained by pulse conversion of the UWB signal S (hereinafter also referred to as a main signal pulse S ″) and a pulse signal Z ″ obtained by pulse conversion of the unnecessary signal Z (hereinafter referred to as unnecessary pulse Z ′). May be called ').

  If such an unnecessary pulse Z ″ is taken in, it causes a data communication error and a measurement error. In addition, if the unnecessary signal Z is present near the main signal S to be detected, the detection waveform and the detected pulse signal are affected, which causes a temporal error.

  However, in the present invention, as shown in FIG. 3 (d), the main signal S (in other words, the data signal after the preamble) received after the synchronization confirmation in the PLL circuit unit 18 is subjected to pulse conversion (pulse detection). Immediately after that, output of the blocking signal Id is started, and the blocking signal Id having a predetermined pulse width Ta is output. In other words, the blocking signal Id is output only for the programmed time, so that the ON-OFF switch unit 13 is turned OFF for the predetermined time and the UWB signal S to be detected comes immediately after the pulse conversion (Δta). Even if the antenna unit 11 receives the unnecessary signal Z immediately before pulse conversion of the main signal S (Δtb), the unnecessary signal Z between the waveforms of the main signal S is not transmitted to the envelope detection unit 14. Thus, the detection of the received signal is blocked (controlled) so that the envelope detection and pulse conversion of the unnecessary signal Z are not performed (the unnecessary detection waveform Z ′ and the unnecessary pulse Z ″ are not detected). That is, the unnecessary signal Z between the waveforms of the UWB signal S to be detected is blocked.

  The unnecessary signal Z between the waveforms of the UWB signal S to be detected as shown in FIG. 3A is not detected as an unnecessary pulse Z ″ as in the embodiment shown in FIG. Only the pulse S ″ is present. Errors are reduced in data analysis, distance calculation, and the like in the digital processing unit 19 and arithmetic processing unit in the next process.

The predetermined pulse width Ta of the blocking signal Id is the period W1 of the main signal S (main signal detection waveform S ′), the detection width W2, the predetermined threshold detection end position of the main signal detection waveform S ′, and the next main signal detection waveform. Based on the interval length (time) W3 between the predetermined threshold value detection start positions of S ′, it is set in advance by a program.
The programmable one-shot multi-circuit unit 21 digitally sets a delay value via a CPU (not shown) and performs timing control (pulse control) of the blocking signal Id to realize extremely accurate time setting.

The term “immediately” immediately after the pulse conversion (Δta) includes the same time and includes a range within 2 nanoseconds (0 ns ≦ Δta ≦ 2 ns) from the time of pulse conversion (simultaneous). For example, from the time of pulse conversion It is preferable to set the blocking signal Id to rise in the range of 1 nanosecond to 2 nanoseconds (1 ns ≦ Δta ≦ 2 ns).
Further, “immediately before” immediately before pulse conversion includes the simultaneous and includes the range from 2 nanoseconds before pulse conversion to the time of pulse conversion (simultaneous) (0 ns ≦ Δta ≦ 2 ns). For example, the next UWB It is preferable to set so that the blocking signal Id falls in a range between 2 nanoseconds and 1 nanosecond before the signal S is subjected to pulse conversion.

  The present invention can be applied to a receiver for receiving the UWB signal S in various systems such as a data communication system and a ranging / positioning system. For example, a fixed transceiver provided in a warehouse, a forklift, It can be incorporated in a receiving circuit such as a moving tag with a transmitter / receiver provided on a moving body such as a transported object. It can also be used in a receiver of a data communication system.

  In the present invention, the design can be changed, and the timing signal creation unit 20, the blocking signal creation unit 21, and the reception signal switch unit 13 are not limited to the circuit configuration shown in FIG.

  As described above, according to the present invention, the PLL circuit unit 18 that outputs the lock signal Ib indicating that it is synchronized with the impulse UWB signal S, and both the clock signal Ia and the lock signal Ib from the PLL circuit unit 18 are provided. ON / OFF control of the UWB signal S based on the blocking signal Id, the timing signal generating unit 20 that outputs the timing signal Ic when the signal is input, the blocking signal generating unit 21 that outputs the blocking signal Id based on the timing signal Ic And a reception signal switch unit 13 that blocks the unnecessary signal Z between the waveforms of the UWB signal S to be detected, and therefore exists between the waveforms of the UWB signal (main signal) S to be detected. The unnecessary signal Z to be blocked can be blocked, and the main signal S can be extracted with high accuracy and reliability. That is, it is possible to reduce the occurrence of errors such as data detection errors and distance measurement errors (error rate), and to obtain an accurate UWB ranging / positioning system and UWB data communication system that are excellent in stability.

13 Receive signal switch
18 PLL circuit
20 Timing signal generator
21 Blocking signal generator
Ia clock signal Ib lock signal Ic timing signal Id blocking signal S UWB signal Z unnecessary signal

Claims (1)

A PLL circuit unit (18) that outputs a lock signal (Ib) indicating that it is synchronized with the impulse UWB signal (S), a clock signal (Ia) from the PLL circuit unit (18), and the lock signal (Ib) when both are input, a timing signal generator (20) that outputs a timing signal (Ic) and a blocking signal generator (Id) that outputs a blocking signal (Id) based on the timing signal (Ic) 21) and a reception signal switch unit (13) for controlling on / off of the UWB signal (S) based on the blocking signal (Id),
An impulse UWB reception circuit configured to block an unnecessary signal (Z) between waveforms of the UWB signal (S) to be detected.

Images