JP6478819B2 - Thin film transistor substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a TFT active matrix substrate (hereinafter referred to as “TFT substrate (thin film transistor substrate)”) using a thin film transistor (TFT) as a switching device and a method for manufacturing the same.

  Generally, the display modes of a liquid crystal display (LCD) are roughly classified into a TN (Twisted Nematic) method, an IPS (In-Plane Switching) method (“IPS” is a registered trademark), and an FFS method (Fringe Field Switching: It is divided into a horizontal electric field system represented by fringe electric field driving. A horizontal electric field type liquid crystal display device has a feature that a wide viewing angle and a high contrast can be obtained. The IPS method is a display method in which display is performed by applying a horizontal electric field to liquid crystal sandwiched between opposing substrates, but since the pixel electrode and the common electrode for applying the horizontal electric field are provided in the same layer, The liquid crystal molecules located immediately above the pixel electrode cannot be driven sufficiently, and the transmittance is lowered.

  In order to improve this problem, for example, an FFS type LCD as disclosed in Patent Document 1 has been proposed.

  In the FFS method, since the common electrode and the pixel electrode are arranged to face each other with an interlayer insulating film interposed therebetween, an oblique electric field (fringe electric field) is generated, and the liquid crystal molecules located above the pixel electrode are also laterally aligned. Thus, the liquid crystal molecules can be sufficiently driven. As a result, it is possible to obtain a wider viewing angle and higher transmittance than the IPS system.

  Until now, amorphous silicon has been used for a semiconductor film serving as an active layer (channel layer) in a switching device of a TFT substrate for a liquid crystal display device. However, in recent years, demands for narrower frames, lower costs, higher performance, higher definition, etc. are increasing. To meet these demands, TFTs are miniaturized using high-mobility semiconductor materials. In addition, by forming the source drive circuit and the gate drive circuit on the same substrate, it is necessary to reduce the drive circuit and the mounting area in the outer edge region (frame region) of the image display region.

In recent years, TFTs using an oxide semiconductor have been actively developed as high mobility TFTs. As an oxide semiconductor, a zinc oxide (ZnO) -based material, an amorphous InGaZnO-based material obtained by adding gallium oxide (Ga ₂ O ₃ ) and indium oxide (In ₂ O ₃ ) to zinc oxide is mainly used. This technique is disclosed in Patent Documents 2 and 3, for example. In order to realize a high-performance (high mobility) liquid crystal display device with a wide viewing angle and high transmittance, it is desirable to use an FFS-type LCD panel using a TFT using an oxide semiconductor as a switching device.

Generally, amorphous ITO (Indium Tin Oxide: indium oxide (In ₂ O ₃ ) + tin oxide (SnO ₂ )) is used for the pixel electrode of the TFT substrate of the liquid crystal display device. This amorphous ITO can be etched with a weakly acidic solution such as oxalic acid or carboxylic acid. However, amorphous ITO crystallizes when heat of 150 ° C. or higher is applied. Although the crystallized ITO film is difficult to etch with the above weak acid solution, the post-baking treatment after resist patterning in the photolithography process is usually 90 ° C. to 130 ° C., so the amorphous ITO film is partially May crystallize.

  Then, an etching residue of the ITO film is generated, and there is a possibility that a display abnormality due to current leakage between adjacent pixels due to the residue occurs. In order to suppress the residue, there is a method of increasing the distance between the pixels. However, the pixel electrode area is reduced, and the aperture ratio is greatly reduced. There is also a method of removing the residue by lengthening the etching time, but the manufacturing time becomes long, so the cost becomes high. Moreover, since the side etching amount increases when the etching time is lengthened, there is a possibility that the pixel electrode is disconnected at a stepped portion such as the source and drain electrodes.

  For example, Patent Document 4 proposes a method for reducing residues by adding ZnO (zinc oxide) to ITO and raising the crystallization temperature. However, the generation of ITO film residue is difficult to optimize because it depends on the type and surface state of the underlying insulating film. In particular, when the distance between adjacent pixels becomes narrower with higher definition, the countermeasure becomes more difficult. Further, when ZnO is added, the transmittance and the conductivity are likely to be lowered, and the luminance of the liquid crystal panel may be lowered.

  Patent Document 5 proposes a method for forming a semiconductor channel layer and a pixel electrode in the same layer using amorphous InGaZnO. Amorphous InGaZnO is easily etched with a weakly acidic solution such as oxalic acid or carboxylic acid, and no residue is generated. In addition, in order to use both in the semiconductor channel layer and the pixel electrode, it is necessary to control the conductivity for each application, and Patent Document 5 proposes a method of increasing the conductivity by performing plasma treatment on the pixel electrode portion. However, when amorphous InGaZnO is plasma-treated, it is possible to increase the conductivity, but it is difficult to control it. Even if plasma treatment is performed, the conductivity is lower by 2 to 3 digits than that of amorphous ITO, and the performance as a transparent conductive film is inferior.

JP 2001-56474 A JP-A-2005-77822 JP 2007-281409 A JP 2008-010342 A International Publication No. 2011/010415

  Amorphous ITO and amorphous oxide semiconductor film to be pixel electrodes are soluble in oxalic acid and carboxylic acid. Therefore, when using an oxide semiconductor for the channel layer of the switching device of the FFS TFT substrate, the number of masks must be Need to increase. For example, an FFS TFT substrate disclosed in FIG. 3 of Patent Document 1 includes (1) a gate electrode formation process, (2) a gate insulating film and semiconductor film formation process, and (3) source / drain electrode formation. It is formed through six photoengraving steps: (4) pixel electrode formation step, (5) contact hole formation step to the protective insulating film, and (6) common electrode formation step. In this manufacturing flow, there is a high possibility that the channel layer (oxide semiconductor) is exposed to the etching solution when the pixel electrode is patterned, and the channel layer disappears. In order to prevent disappearance, it is necessary to form a channel protective film (etching stopper film). As a result, the photolithography process is increased by one time, and the manufacturing cost is increased.

  The present invention has been made to solve the above-described problems, and even when an oxide semiconductor is used for the channel layer of the switching device of the FFS type TFT substrate, the etching residue of the pixel electrode is prevented. An object of the present invention is to provide a manufacturing method that reduces the manufacturing cost by providing a configuration and reducing the photolithography process.

  An aspect of a thin film transistor substrate according to the present invention is a thin film transistor substrate in which a plurality of pixels are arranged in a matrix, and each of the pixels includes a gate electrode and a common electrode wiring selectively disposed on the substrate, A first insulating film covering a gate electrode and the common electrode wiring; an oxide semiconductor film selectively disposed on the first insulating film; and the first insulating film and the oxide semiconductor film A portion of the second insulating film disposed on the drain electrode, a source electrode, a drain electrode and a source wiring disposed on the second insulating film, and a portion of the second insulating film being in contact with an end of the drain electrode; A pixel electrode electrically connected to the drain electrode; a source electrode; the drain electrode; the source wiring; a third insulating film disposed on the pixel electrode; and the pixel electrode facing the pixel electrode. And a counter electrode disposed on the third insulating film, wherein the counter electrode is connected to the common electrode via a common electrode contact hole that penetrates the third insulating film and the first insulating film. Electrically connected to the electrode wiring, the oxide semiconductor film is provided at least above the gate electrode and below the pixel electrode, the pixel electrode has a portion in direct contact with the oxide semiconductor film; The source electrode and the drain electrode are electrically connected to the oxide semiconductor film through a source electrode contact hole and a drain electrode contact hole that penetrate the second insulating film, respectively.

  According to the thin film transistor substrate of the present invention, since the oxide semiconductor film is present below the pixel electrode, no etching residue is generated during patterning of the pixel electrode. In other words, even when the pixel electrode is partially crystallized by heat treatment during the manufacturing process, the oxide semiconductor layer is etched, so that the crystallized pixel electrode is lifted off and removed. For this reason, display anomalies due to current leakage between adjacent pixels due to residue are prevented. In addition, since oxygen is supplied from the oxide semiconductor film to the pixel electrode, the transmittance of the pixel electrode is improved. In addition, since the end portion of the drain electrode is sandwiched between the oxide semiconductor film and the pixel electrode, the adhesion between the drain electrode and the pixel electrode is improved and the mechanical strength is also improved. Disconnection from the electrode is suppressed.

It is a top view which shows the structure of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the structure of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is a top view which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is a top view which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is a top view which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 1 which concerns on this invention. It is a top view which shows the structure of the TFT substrate of the modification of Embodiment 1 which concerns on this invention. It is sectional drawing which shows the structure of the TFT substrate of the modification of Embodiment 1 which concerns on this invention. It is a top view which shows the structure of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the structure of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is a top view which shows the structure of the TFT substrate of Embodiment 3 which concerns on this invention. It is sectional drawing which shows the structure of the TFT substrate of Embodiment 3 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 2 which concerns on this invention. It is a top view which shows the manufacturing method of the TFT substrate of Embodiment 3 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 3 which concerns on this invention. It is sectional drawing which shows the manufacturing method of the TFT substrate of Embodiment 3 which concerns on this invention.

<Embodiment 1>
<TFT substrate pixel configuration>
First, the configuration of the TFT substrate 100 according to the first embodiment will be described with reference to FIG. 1 and FIG. Although the present invention relates to a TFT substrate, since it is particularly characterized by the configuration of the pixel, the configuration of the pixel will be described below. FIG. 1 is a plan view showing a planar configuration of a pixel of the TFT substrate 100 according to the first embodiment, and FIG. 2 is a sectional configuration taken along line XX, a sectional configuration taken along line YY in FIG. It is sectional drawing which shows the cross-sectional structure in a ZZ line.

  Note that the cross-sectional configuration along the line XX includes a “TFT portion” that is a TFT formation region, a “transmission pixel portion” that is a formation region of the pixel electrode 13 and the counter electrode 18, a counter electrode 18, and a common electrode. 4 and an “electrode connecting portion” to which the terminal 4 is connected. The cross-sectional configuration along the Y-Y line corresponds to the cross-sectional configuration of the “gate terminal portion”, which is the formation region of the gate terminal 3 and the gate terminal pad 19 for supplying a gate signal to the gate wiring 22, and Z− The cross-sectional configuration along the Z line corresponds to the cross-sectional configuration of the “source terminal portion”, which is the formation region of the source terminal 12 and the source terminal pad 20 for applying a display signal to the source wiring 21.

  In the following description, it is assumed that the TFT substrate 100 is used for a light transmission type FFS liquid crystal display device.

  As shown in FIG. 1, the TFT substrate 100 is arranged such that a plurality of gate wirings 22 (scanning signal lines) and a plurality of source wirings 21 (display signal lines) intersect at right angles, and the intersections of both wirings. A TFT is disposed in the vicinity, a part of the gate wiring 22 becomes the TFT gate electrode 2, the TFT source electrode 11 is connected to the source wiring 21, and the TFT drain electrode 10 is a light-transmissive pixel electrode 13. It is connected to the. Further, the common electrode 4 is disposed so as to extend in a direction parallel to the gate wiring 22.

  That is, the gate wiring 22 arranged so as to extend from the gate terminal 3 in the horizontal direction (X direction) with a constant line width is formed with a wide line width in the TFT formation region (TFT portion). However, the line width between the gate electrodes 2 of adjacent pixels is constant, and the gate electrodes are connected to each other. Further, the source electrode 11 branches from the source wiring 21 arranged so as to extend from the source terminal 12 in the vertical direction (Y direction) with a certain line width, and is provided above the gate electrode 2 in the TFT portion. The upper part of the formed oxide semiconductor film 6 is covered. Then, it is connected to the oxide semiconductor film 6 through the source electrode contact hole 9. In addition, the drain electrode 10 provided to face the source electrode 11 in plan view has one end connected to the oxide semiconductor film 6 through the drain electrode contact hole 8 and the other end connected to the pixel electrode 13. ing.

  Since the region surrounded by the adjacent source wiring 21, gate wiring 22, and common electrode 4 is a pixel region, the TFT substrate 100 has a configuration in which the pixel regions are arranged in a matrix.

  A gate terminal pad 19 connected to the gate terminal 3 through the gate terminal contact hole 15 is formed on the gate terminal 3. A source terminal pad 20 connected to the source terminal 12 through the source terminal contact hole 16 is formed on the source terminal 12.

  As shown in FIG. 2, the TFT substrate 100 is formed on a transparent insulating substrate 1 such as glass, for example. On the transparent insulating substrate 1, a gate terminal 3, a gate wiring 22 (FIG. 1), a gate electrode 2, and A common electrode wiring 4 is formed. An insulating film 5 (first insulating film) is formed so as to cover them.

  Oxide semiconductor films 6, 23 and 24 are formed on the insulating film 5, and an insulating film 7 (second insulating film) is formed thereon. The oxide semiconductor films 6, 23 and 24 are formed in the same layer, and the oxide semiconductor film 6 is provided above the gate electrode 2 in the TFT portion, functions as a channel layer, and is formed on the gate electrode 2. The film 5 functions as a gate insulating film. The oxide semiconductor film 23 is provided below the source wiring 21 and the source terminal 12, and the oxide semiconductor film 24 is provided below the pixel electrode 13.

  Note that the planar pattern of the oxide semiconductor film 6 is formed smaller than the planar pattern of the gate electrode 2, and the oxide semiconductor film 6 is accommodated in the formation region of the gate electrode 2.

  The insulating film 7 covers the oxide semiconductor film 6 in the TFT portion, but a drain electrode contact hole 8 and a source electrode contact hole 9 are provided so as to penetrate the insulating film 7, and each is formed on the insulating film 7. The drain electrode 10 and the source electrode 11 are embedded and electrically connected to the oxide semiconductor film 6. Further, most of the insulating film 7 is removed over the oxide semiconductor film 24, and the pixel electrode 13 is provided over the oxide semiconductor film 24. A source wiring 21 (FIG. 1) and a source terminal 12 are also formed on the insulating film 7.

  The pixel electrode 13 is electrically connected to the drain electrode 10 and the oxide semiconductor film 24. As shown in FIG. 1, the pixel electrode 13 and the oxide semiconductor film 24 are rectangular in plan view, and the pixel electrode 13 is formed slightly smaller than the oxide semiconductor film 24, and the outer edge of the pixel electrode 13. The portion is inside the outer edge portion of the oxide semiconductor film 24.

  An insulating film 14 (third insulating film) is provided so as to cover the pixel electrode 13, drain electrode 10, source electrode 11, insulating film 7, source wiring 21 (FIG. 1), source terminal 12 and insulating film 5. A gate terminal contact hole 15, a source terminal contact hole 16 and a common electrode contact hole 17 are formed so as to penetrate the insulating film 14.

  A comb-like counter electrode 18 having a plurality of slit openings SL, a gate terminal pad 19 and a source terminal pad 20 are formed on the insulating film 14 using the same conductive film. A terminal pad 19 is embedded and electrically connected to the gate terminal 3, a source terminal contact hole 16 is embedded and electrically connected to the source terminal 12, and the common electrode contact hole 17 is opposed to the common terminal contact hole 17. The electrode 18 is embedded and is electrically connected to the common electrode 4. The gate terminal contact hole 15 and the common electrode contact hole 17 are provided so as to penetrate not only the insulating film 14 but also the insulating film 5.

  Further, as shown in FIG. 1, the counter electrode 18 is provided in a continuous pattern so as to cover most of the TFT substrate 100 as well as on the pixel electrode 13 as a lower electrode. The slit opening SL is provided only in a portion facing the pixel electrode 13.

Note that in this embodiment 1, an oxide semiconductor is used as the oxide semiconductor film 6. For example, a ZnO-based oxide semiconductor, an InZnSnO-based oxide semiconductor obtained by adding indium oxide (In ₂ O ₃ ) and tin oxide (SnO ₂ ) to zinc oxide (ZnO), or a zinc oxide (ZnO) -based semiconductor Alternatively, an oxide semiconductor of InGaZnO in which gallium oxide (Ga ₂ O ₃ ) and indium oxide (In ₂ O ₃ ) are added to zinc oxide (ZnO) can be used.

<Manufacturing method>
Hereinafter, a method for manufacturing the TFT substrate 100 of the first embodiment will be described with reference to FIGS. A plan view and a cross-sectional view showing the final process correspond to FIGS. 1 and 2, respectively.

  First, in the step shown in FIG. 3, a conductive film 27 (first conductive film) is formed on the entire upper surface of the transparent insulating substrate 1 such as glass. Here, an aluminum (Al) alloy film, such as an Al—Ni—Nd film, is formed as the conductive film 27 to a thickness of 200 to 300 nm by a DC magnetron sputtering method.

  Next, a resist material is applied onto the conductive film 27, a photoresist pattern is formed in the first photolithography process, and the conductive film 27 is patterned by etching using the photoresist pattern as a mask. Thereby, the gate terminal 3, the gate wiring 22 (FIG. 1), the gate electrode 2 and the common electrode wiring 4 are formed on the transparent insulating substrate 1.

  Here, an Al—Ni—Nd alloy is used for the conductive film 27, but other materials may be used as long as the wiring resistance can be equal to or lower than that of the Al—Ni—Nd alloy. An Al—Ni—Nd alloy is a material whose main component is Al, and thus has high conductivity, and can be electrically joined to a transparent conductive film such as ITO by the added Ni. For the etching of the conductive film 27, wet etching using a generally known PAN solution (mixed acid including phosphoric acid, acetic acid, and nitric acid) as an etchant can be used. .

  Next, in the step shown in FIG. 4, the insulating film 5 is formed on the entire upper surface of the transparent insulating substrate 1. In the first embodiment, a silicon nitride (SiN) film having a thickness of 400 nm and a silicon oxide (SiO) film having a thickness of 50 nm are formed in this order by using a chemical vapor deposition (CVD) method. It was set to 5.

Since the silicon oxide film has a weak barrier property against impurity elements that affect TFT characteristics such as moisture (H ₂ O), hydrogen (H ₂ ), sodium (Na), and potassium (K), the insulating film 5 A laminated structure in which a SiN film having excellent barrier properties is provided under the SiO film. After that, as illustrated in FIG. 4, an oxide semiconductor film 28 is formed on the entire upper surface of the insulating film 5.

More specifically, first, an InGaZnO target [In ₂ O _3. (Ga ₂ O ₃ ). (ZnO) ₂ ] in which the atomic composition ratio of In: Ga: Zn: O is 1: 1: 1: 4 is set. An InGaZnO film is formed by the sputtering method used. At this time, when a sputtering method using a known argon (Ar) gas or krypton (Kr) gas is used, the oxygen atomic composition ratio is usually smaller than the stoichiometric composition, and the oxygen ion deficient state (the above-mentioned In the example, the oxide film has an O composition ratio of less than 4). Therefore, it is desirable to mix Ar gas with oxygen (O ₂ ) gas and perform sputtering. Here, sputtering was performed using a mixed gas obtained by adding 10% O ₂ gas at a partial pressure ratio to Ar gas, and an InGaZnO film was formed with a thickness of 50 nm. This InGaZnO film has an amorphous structure. In addition, an InGaZnO film having an amorphous structure generally has a crystallization temperature of 500 ° C. or higher, and most of the film is stable with an amorphous structure at room temperature.

  Next, a resist material is applied onto the oxide semiconductor film 28, a photoresist pattern is formed in the second photolithography process, and the oxide semiconductor film 28 is patterned by etching using the photoresist pattern as a mask.

  For the etching of the oxide semiconductor film 28, wet etching using a solution containing oxalic acid can be used. As the solution containing oxalic acid, a solution containing oxalic acid in the range of 1 to 10 wt% is preferable. In the first embodiment, an aqueous solution containing 5 wt% oxalic acid is used.

  Thereafter, the photoresist pattern is removed, and the entire substrate is annealed at 350 ° C. for 60 minutes in the air atmosphere. By annealing in a state containing oxygen, oxygen can be further supplied to the oxide semiconductor film, so that the oxygen ion deficiency state is more surely eliminated. At the same time, structural relaxation also occurs, so that structural defects are reduced and a high-quality semiconductor film is obtained.

  Through the above steps, oxide semiconductor films 6, 23 and 24 are formed on the insulating film 5 as shown in FIG. A plan view of this state is shown in FIG. As shown in FIG. 6, the oxide semiconductor film 6 is disposed above the gate electrode 2, and the oxide semiconductor film 23 is disposed in a region below the source wiring 21 and the source terminal 12 to be formed later. The oxide semiconductor film 24 is disposed in a region below the pixel electrode 13 to be formed later.

  In addition, although the example which anneals in air | atmosphere above was shown above, you may anneal in water vapor | steam atmosphere. Further, annealing may be performed in an atmosphere in which oxygen gas and nitrogen gas are mixed at a certain ratio. Further, the substrate surface may be annealed while generating ozone having high oxidizing power by irradiating the substrate surface with UV (ultraviolet) light.

  Next, the insulating film 7 is formed on the entire upper surface of the transparent insulating substrate 1, thereby covering the oxide semiconductor films 6, 23, and 24 with the insulating film 7. In the first embodiment, the insulating film 7 is formed by forming a 100 nm-thickness SiO film using the CVD method.

  Next, a resist material is applied on the insulating film 7, a photoresist pattern is formed in the third photolithography process, and the insulating film 7 is patterned by etching using the photoresist pattern as a mask.

For the etching of the insulating film 7, dry etching using a gas obtained by adding oxygen (O ₂ ) to sulfur hexafluoride (SF ₆ ) was used. By adding O ₂ to the etching gas, it is possible to suppress carrier concentration fluctuations due to the reduction reaction of the lower oxide semiconductor film 6 during etching.

  After that, by removing the photoresist pattern, the insulating film 7 completely covers the oxide semiconductor film 6 and the oxide semiconductor film 23 and partially covers the oxide semiconductor film 24 as shown in FIG. Formed. Note that a drain electrode contact hole 8 and a source electrode contact hole 9 are provided in the insulating film 7 on the oxide semiconductor film 6, and these portions are not covered with the insulating film 7.

  Next, in a step shown in FIG. 8, a conductive film 29 (second conductive film) is formed on the entire upper surface of the transparent insulating substrate 1. Here, a molybdenum (Mo) alloy film, a chromium (Cr) alloy film, an Al alloy film (for example, an Al—Ni—Nd film) or the like is formed as the conductive film 29 by a DC magnetron sputtering method. In the first embodiment, a MoNb alloy film and an Al—Ni—Nd alloy film each having a thickness of 100 nm are formed in this order to form the conductive film 29.

  Next, a resist material is applied on the conductive film 29, a photoresist pattern is formed in the fourth photolithography process, and the conductive film 29 is patterned by etching using the photoresist pattern as a mask.

  For etching the conductive film 29, a wet etching method using a PAN solution (mixed acid containing phosphoric acid, acetic acid, and nitric acid) as an etchant can be used. Here, an aqueous solution containing 70 wt% phosphoric acid, 7 wt% acetic acid, and 5 wt% nitric acid was used.

  In general, an oxide semiconductor film is used for etching processing of not only oxalic acid but also general metal films (Cr, Ti, Mo, Ta, Al, Cu, and alloys thereof) used for a source electrode and a drain electrode of a TFT. The acid-based solution may be damaged by etching to deteriorate the characteristics. In Embodiment 1, at this stage, the oxide semiconductor film 6 serving as a channel layer is protected by the insulating film 7 and thus is not damaged by the etching solution.

  Thereafter, by removing the photoresist pattern, the drain electrode 10, the source electrode 11, the source terminal 12, and the source wiring 21 (not shown) are formed as shown in FIG. Note that the drain electrode 10 is electrically connected to the oxide semiconductor film 6 through the drain electrode contact hole 8 and is also electrically connected to the oxide semiconductor film 24. The source electrode 11 is electrically connected to the oxide semiconductor film 6 through the source electrode contact hole 9. Note that the oxide semiconductor film between the drain electrode contact hole 8 and the source electrode contact hole 9 serves as a channel region.

  A plan view of this state is shown in FIG. As shown in FIG. 10, the drain electrode 10 and the source electrode 11 are disposed on the oxide semiconductor film 6, and the source wiring 21 and the source terminal 12 are disposed on the oxide semiconductor film 23. The insulating film 7 completely covers the oxide semiconductor film 6 and completely covers the oxide semiconductor film 23 below the source wiring 21 and the source terminal 12. Note that the insulating film 7 also covers part of the oxide semiconductor film 24.

  Next, in the step shown in FIG. 11, a transparent oxide conductive film 30 (first transparent oxide conductive film) is formed on the entire upper surface of the transparent insulating substrate 1.

Here, as the transparent oxide conductive film 30, an ITO film having a mixing ratio of indium oxide (In ₂ O ₃ ) and tin oxide (SnO ₂ ) of, for example, 90:10 (% by weight) was used.

In general, an ITO film has a stable crystalline (polycrystalline) structure at room temperature. Here, a gas containing hydrogen (H), for example, hydrogen (H ₂ ) gas or water vapor (H ₂ O) is used. An ITO film having a thickness of 80 nm is formed in an amorphous state by sputtering in a gas atmosphere in which is mixed with argon (Ar).

  Next, a resist material is applied onto the transparent oxide conductive film 30, a photoresist pattern is formed in the fifth photolithography process, and the transparent oxide conductive film 30 is patterned by etching using the photoresist pattern as a mask. Here, the photoresist pattern is formed so that the outer edge portion of the pixel electrode 13 is disposed inside the outer edge portion of the oxide semiconductor film 24 in plan view.

  For etching the transparent oxide conductive film 30, a wet etching method using an aqueous solution containing oxalic acid at 5 wt% can be used.

  In the first embodiment, even when the transparent oxide conductive film 30 is partially crystallized, for example, in an island shape by the heat of the photoengraving process, the oxide semiconductor is formed below the transparent oxide conductive film 30 in the pixel region. Since the film 24 exists, the crystallized transparent oxide conductive film 30 (ITO film) is lifted off and removed as etching progresses in the oxide semiconductor film 24. For this reason, the ITO film residue is not generated between adjacent pixels, and display abnormality due to current leakage between adjacent pixels due to the residue is prevented. Note that the crystallized transparent oxide conductive film 30 in a region other than the pixel region can be removed without residue by setting a longer etching time.

  After that, by removing the photoresist pattern, the pixel electrode 13 electrically connected to the drain electrode 10 and the oxide semiconductor film 24 is formed as shown in FIG.

  A plan view of this state is shown in FIG. As shown in FIG. 13, the oxide semiconductor film 24 is formed larger in plan paper than the pixel electrode 13. This is because the photoresist pattern on the transparent oxide conductive film 30 was formed as such, and the oxide semiconductor film generally has a lower etching rate with oxalic acid than the amorphous ITO film. This is because the edge portion of the oxide semiconductor film 24 remains without being removed even if it is not covered with the photoresist pattern.

  Next, an insulating film 14 (third insulating film) is formed on the entire upper surface of the transparent insulating substrate 1. In the first embodiment, a silicon oxide (SiO) film having a thickness of 200 nm and a silicon nitride (SiN) film having a thickness of 150 nm are formed in this order using the CVD method to form the insulating film 14.

Next, a resist material is applied on the insulating film 14, a photoresist pattern is formed in the sixth photolithography process, and the insulating film 14 and the insulating film 5 are etched using the photoresist pattern as a mask. For etching the insulating film 14 and the insulating film 5, dry etching using a gas obtained by adding oxygen (O ₂ ) to sulfur hexafluoride (SF ₆ ) was used.

  Thereafter, by removing the photoresist pattern, a gate terminal contact hole 15 reaching the gate terminal 3, a source terminal contact hole 16 reaching the source terminal 12, and a common electrode contact hole 17 reaching the common electrode 4 are obtained at the same time.

  Thereafter, as shown in FIG. 14, a transparent oxide conductive film 31 (second transparent oxide conductive film) is formed on the insulating film 14. In the first embodiment, the transparent oxide conductive film 31 is formed by forming an amorphous ITO film having the same composition by the same method as the transparent oxide conductive film 30. The transparent oxide conductive film 31 is embedded in the gate terminal contact hole 15, the source terminal contact hole 16 and the common electrode contact hole 17.

  Next, a resist material is applied on the transparent oxide conductive film 31, a photoresist pattern is formed in the seventh photolithography process, and the transparent oxide conductive film 31 is etched using the photoresist pattern as a mask.

  For the etching of the transparent oxide conductive film 31, a wet etching method using an aqueous solution containing oxalic acid at 5 wt% can be used.

  Thereafter, by removing the photoresist pattern, as shown in FIG. 1 and FIG. 2, the gate terminal pad 19 electrically connected to the gate terminal 3 through the gate terminal contact hole 15 and the source terminal contact hole 16 through the source terminal contact hole 16 are used. A source terminal pad 20 electrically connected to the terminal 12 and a counter electrode 18 electrically connected to the common electrode 4 through the common electrode contact hole 17 are obtained. The counter electrode 18 is also formed with a plurality of slit openings SL at the same time and has a comb shape.

  Thereafter, heat treatment (annealing) is performed for 60 minutes at a temperature of 230 ° C. in an air atmosphere in order to eliminate plasma damage and the like generated on the substrate during the manufacturing process. Thereby, the amorphous ITO is completely crystallized. Further, along with crystallization, oxygen is supplied from the oxide semiconductor film 24 toward the pixel electrode 13 during the heat treatment, and the transmittance of the pixel electrode 13 is increased. By this annealing, the FFS TFT substrate 100 is completed.

  An alignment film and a spacer are formed on the surface of the completed TFT substrate 100. The alignment film is a film for aligning liquid crystals and is made of polyimide or the like. In addition, a counter substrate including a color filter and an alignment film is prepared, and the TFT substrate 100 and the counter substrate are bonded to each other.

  The TFT substrate 100 and the counter substrate are bonded together with a certain gap by the spacer, and liquid crystal is injected into this gap and sealed. That is, the liquid crystal layer is sandwiched between the TFT substrate 100 and the counter substrate. Furthermore, a polarizing plate, a retardation plate, a backlight unit, and the like are provided on the outer surfaces of the TFT substrate 100 and the counter substrate, whereby an FFS liquid crystal display device can be obtained.

  As described above, in the first embodiment, a high mobility TFT is obtained by using the oxide semiconductor film 6 in the TFT channel layer, and the oxide semiconductor film 24 is disposed under the pixel electrode 13. Thus, when the pixel electrode 13 is patterned by etching with oxalic acid, no ITO film residue is generated between adjacent pixels, and display abnormality due to current leakage between adjacent pixels due to the residue is prevented. Is done.

  Further, by supplying oxygen from the oxide semiconductor film 24 containing a large amount of oxygen, the transmittance of the pixel electrode 13 is improved, and the luminance of the liquid crystal panel can be increased. Further, since the drain electrode 10 is sandwiched between the oxide semiconductor film 24 that is a metal oxide and the pixel electrode 13 that is an amorphous ITO film, the adhesion between the drain electrode 10 and the pixel electrode 13 is improved. In addition, since the mechanical strength is improved, disconnection of the pixel electrode 13 at the step portion of the drain electrode 10 is suppressed.

  In Embodiment 1, a stacked film of the oxide semiconductor film 23 and the insulating film 7 is formed under the source wiring 21. For this reason, an effect of preventing the occurrence of a defect due to an electrical short between the source wiring 21, the gate wiring 22 and the common electrode wiring 4 can be expected.

<Modification>
Next, the configuration of a TFT substrate according to a modification of the first embodiment will be described with reference to FIGS. 15 and 16. 15 is a plan view showing a planar configuration of a pixel in an FFS TFT substrate 100A according to a modification of the first embodiment. FIG. 16 is a sectional configuration taken along line XX in FIG. It is sectional drawing which shows the cross-sectional structure in BB, and the cross-sectional structure in a ZZ line. In addition, the same code | symbol is attached | subjected about the structure same as the TFT substrate 100 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

  As shown in FIGS. 15 and 16, in the TFT substrate 100A, instead of the drain electrode, the pixel electrode extending portion 131 of the pixel electrode 13A provided to extend above the oxide semiconductor film 6 includes: The oxide semiconductor film 6A is directly electrically connected through the drain electrode contact hole 8. In order to prevent the drain electrode from being formed above the oxide semiconductor film 6, the conductive film 29 is formed on the entire upper surface of the transparent insulating substrate 1 in the process described with reference to FIG. This can be realized by changing the photoresist pattern formed in the plate making process to a pattern that does not form a drain electrode above the oxide semiconductor film 6 and performing etching using a PAN solution.

  The drain electrode is generally formed of metal and does not transmit light. However, according to the above configuration, the drain electrode is not provided, and the pixel electrode 13A formed of a transparent oxide conductive film is directly connected to the oxide semiconductor film 6. Therefore, the light transmission area increases. As a result, the pixel area is widened, the aperture ratio is improved, and an FFS mode liquid crystal display panel with high luminance can be realized.

<Embodiment 2>
In the first embodiment described above, the TFT substrate 100 is formed through seven photolithography processes. In the second embodiment described below, a manufacturing method in which the number of photolithography processes is reduced will be described.

  FIG. 17 is a plan view showing a planar configuration of a pixel in the FFS TFT substrate 200 according to the second embodiment. FIG. 18 is a sectional configuration taken along line XX in FIG. It is sectional drawing which shows a cross-sectional structure and a cross-sectional structure in a ZZ line. In addition, the same code | symbol is attached | subjected about the structure same as the TFT substrate 100 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 18, in the TFT substrate 200, an oxide semiconductor film 6A is formed on the insulating film 5 so as to extend from the TFT portion to the transmissive pixel portion (pixel portion). An oxide semiconductor film 23 is formed on the insulating film 5 below the wiring 21 (FIG. 17) and the source terminal 12, and an insulating film 7A (second insulating film) is formed thereon. The oxide semiconductor films 6A and 23 are formed of the same layer, and a portion of the oxide semiconductor film 6A provided above the gate electrode 2 of the TFT portion functions as a channel layer and is formed on the gate electrode 2. The insulating film 5 functions as a gate insulating film. Further, a portion of the oxide semiconductor film 6 </ b> A provided in the pixel portion is provided so as to face the pixel electrode 13.

  In addition, the planar pattern of the portion provided in the TFT portion of the oxide semiconductor film 6A is formed larger than the planar pattern of the gate electrode 2, and the whole is covered with the insulating film 7A.

  The insulating film 7A covers the entire portion of the oxide semiconductor film 6A provided in the TFT portion, but the drain electrode contact hole 8 and the source electrode contact hole 9 are provided so as to penetrate the insulating film 7A. The drain electrode 10 and the source electrode 11 formed on the insulating film 7A are buried and electrically connected to the oxide semiconductor film 6A. Further, most of the insulating film 7A is removed on the oxide semiconductor film 6A provided in the pixel portion, and the pixel electrode 13 is provided on the oxide semiconductor film 6A. The insulating film 7A does not cover the side surface of the oxide semiconductor film 23 and covers only the oxide semiconductor film 23. In FIG. 17, the oxide semiconductor film 23 is hidden by the insulating film 7A and is not illustrated. ing. A source wiring 21 (FIG. 1) and a source terminal 12 are also formed on the insulating film 7A.

  The pixel electrode 13 is electrically connected to the drain electrode 10 and the oxide semiconductor film 6A. As shown in FIG. 17, the pixel electrode 13 and the oxide semiconductor film 6A in the pixel portion are rectangular in plan view, and the pixel electrode 13 is formed slightly smaller than the oxide semiconductor film 6A in the pixel portion. The outer edge portion of the pixel electrode 13 is inside the outer edge portion of the oxide semiconductor film 6A in the pixel portion.

<Manufacturing method>
Hereinafter, a method for manufacturing the TFT substrate 200 of the second embodiment will be described with reference to FIGS. Further, description will be made with reference to the process diagram of Embodiment 1 as appropriate. A plan view and a cross-sectional view showing the final process correspond to FIGS. 17 and 18, respectively.

  First, in the step shown in FIG. 3, a conductive film 27 (first conductive film) is formed on the entire upper surface of the transparent insulating substrate 1 such as glass. Here, an aluminum (Al) alloy film, such as an Al—Ni—Nd film, is formed as the conductive film 27 to a thickness of 200 to 300 nm by a DC magnetron sputtering method.

  Next, a resist material is applied onto the conductive film 27, a photoresist pattern is formed in the first photolithography process, and the conductive film 27 is patterned by etching using the photoresist pattern as a mask. Thereby, as shown in FIG. 19, the gate terminal 3, the gate wiring 22 (FIG. 17), the gate electrode 2, and the common electrode wiring 4 are formed on the transparent insulating substrate 1.

  For the etching of the conductive film 27, wet etching using a generally known PAN solution as an etchant can be used.

  Next, in the step shown in FIG. 4, the insulating film 5 is formed on the entire upper surface of the transparent insulating substrate 1. In the second embodiment, a SiN film having a thickness of 400 nm and a SiO film having a thickness of 50 nm are formed in this order by using the CVD method to form the insulating film 5.

Since the silicon oxide film has a weak barrier property against impurity elements that affect TFT characteristics such as moisture (H ₂ O), hydrogen (H ₂ ), sodium (Na), and potassium (K), the insulating film 5 A laminated structure in which a SiN film having excellent barrier properties is provided under the SiO film. After that, as illustrated in FIG. 4, an oxide semiconductor film 28 is formed on the entire upper surface of the insulating film 5.

Here, an InZnSnO-based oxide semiconductor film in which indium oxide (In ₂ O ₃ ) and tin oxide (SnO ₂ ) were added to zinc oxide (ZnO) by a sputtering method was formed to a thickness of 50 nm. While an InZnSnO-based oxide semiconductor film is soluble in an etching solution containing a carboxylic acid such as oxalic acid, the InZnSnO-based oxide semiconductor film is used as an etching solution for a metal film generally used as an electrode material of Al, Mo, Ag, and Cu. It is an oxide semiconductor film that is insoluble or hardly soluble in a wide composition range and cannot be etched by a known PAN solution.

  Next, the entire substrate is annealed at 350 ° C. for 60 minutes in an air atmosphere. Annealing in a state containing oxygen induces structural relaxation of the oxide semiconductor film, and further supplies oxygen to reduce structural defects in the film.

  Next, the insulating film 7A is formed so as to cover the entire surface of the oxide semiconductor film 28. In the second embodiment, an insulating film 7A is formed by forming a SiO film having a thickness of 100 nm using a CVD method.

  Next, a resist material is applied on the insulating film 7A, a photoresist pattern is formed in the second photolithography process, and the insulating film 7A is patterned by etching using the photoresist pattern as a mask.

For the etching of the insulating film 7A, dry etching using a gas obtained by adding oxygen (O ₂ ) to sulfur hexafluoride (SF ₆ ) was used. By adding O ₂ to the etching gas, it is possible to suppress carrier concentration fluctuations due to the reduction reaction of the lower oxide semiconductor film 28 during etching.

  Thereafter, by removing the photoresist pattern, as shown in FIG. 20, the insulating film 7A covers the entire portion of the oxide semiconductor film 28 provided in the TFT portion and is oxidized in the source terminal portion. The physical semiconductor film 28 is formed so as to partially cover it. Although not shown, the oxide semiconductor film 28 is also provided in a region below the source wiring 21 to be formed later, and the insulating film 7A is formed so as to partially cover it. The

  Note that the drain electrode contact hole 8 and the source electrode contact hole 9 are provided in the insulating film 7A on the oxide semiconductor film 28 provided in the TFT portion, and these portions are not covered with the insulating film 7A. .

  Next, a MoNb alloy film and an Al—Ni—Nd alloy film each having a thickness of 100 nm are formed in this order as a second conductive film on the entire upper surface of the transparent insulating substrate 1 by DC magnetron sputtering.

  Next, a resist material is applied onto the second conductive film, a photoresist pattern is formed in the third photolithography process, and the second conductive film is patterned by etching using the photoresist pattern as a mask.

  For etching the second conductive film, a wet etching method using a PAN solution (mixed acid containing phosphoric acid, acetic acid, and nitric acid) as an etchant can be used. Here, an aqueous solution containing 70 wt% phosphoric acid, 7 wt% acetic acid, and 5 wt% nitric acid was used. Since the oxide semiconductor film 28 is insoluble or hardly soluble in the PAN solution, the oxide semiconductor film 28 is not removed when the second conductive film is etched.

  Thereafter, by removing the photoresist pattern, the drain electrode 10, the source electrode 11, the source terminal 12, and the source wiring 21 (not shown) are formed as shown in FIG. Note that the drain electrode 10 is electrically connected to the oxide semiconductor film 28 in the TFT portion through the drain electrode contact hole 8 and is also electrically connected to the oxide semiconductor film 28 in the pixel portion. The source electrode 11 is electrically connected to the oxide semiconductor film 28 in the TFT portion through the source electrode contact hole 9. Note that the oxide semiconductor film between the drain electrode contact hole 8 and the source electrode contact hole 9 serves as a channel region.

Next, in a step shown in FIG. 22, a transparent oxide conductive film 30 (first transparent oxide conductive film) is formed on the entire upper surface of the transparent insulating substrate 1. Here, as the transparent oxide conductive film 30, an ITO film having a mixing ratio of indium oxide (In ₂ O ₃ ) and tin oxide (SnO ₂ ) of, for example, 90:10 (% by weight) was used.

In general, an ITO film has a stable crystalline (polycrystalline) structure at room temperature. Here, a gas containing hydrogen (H), for example, hydrogen (H ₂ ) gas or water vapor (H ₂ O) is used. An ITO film having a thickness of 80 nm is formed in an amorphous state by sputtering in a gas atmosphere in which is mixed with argon (Ar).

  Next, a resist material is applied onto the transparent oxide conductive film 30, a photoresist pattern 40 is formed in the fourth photolithography process, and the transparent oxide conductive film 30 and the oxide semiconductor film are formed using the photoresist pattern 40 as a mask. 28 is etched at once. For the etching of the transparent oxide conductive film 30 and the oxide semiconductor film 28, a wet etching method using an aqueous solution containing oxalic acid at 5 wt% can be used.

  As a result of this etching, as shown in FIG. 23, the pixel electrode 13 is formed and unnecessary portions of the oxide semiconductor film 28 are removed, and an oxide semiconductor film 6A extending from the TFT portion to the pixel portion is formed. The Note that the oxide semiconductor film 6A below the pixel electrode 13 is slightly larger in plan view. This is because an oxide semiconductor film generally has a lower etching rate with oxalic acid than an amorphous ITO film.

  Thereafter, by removing the photoresist pattern 40, the pixel electrode 13 electrically connected to the drain electrode 10 and the oxide semiconductor film 6A of the TFT portion is formed.

  Next, an insulating film 14 (third insulating film) is formed on the entire upper surface of the transparent insulating substrate 1. In the second embodiment, a silicon oxide (SiO) film having a thickness of 200 nm and a silicon nitride (SiN) film having a thickness of 150 nm are formed in this order using the CVD method to form the insulating film 14.

Next, a resist material is applied on the insulating film 14, a photoresist pattern is formed in the fifth photolithography process, and the insulating film 14 and the insulating film 5 are etched using the photoresist pattern as a mask. For etching the insulating film 14 and the insulating film 5, dry etching using a gas obtained by adding oxygen (O ₂ ) to sulfur hexafluoride (SF ₆ ) was used.

  Thereafter, by removing the photoresist pattern, as shown in FIG. 24, the gate terminal contact hole 15 reaching the gate terminal 3, the source terminal contact hole 16 reaching the source terminal 12, and the common electrode contact hole 17 reaching the common electrode 4. Are obtained at the same time.

  Thereafter, a second transparent oxide conductive film is formed on the insulating film 14. In the second embodiment, the second transparent oxide conductive film is formed by forming an amorphous ITO film having the same composition by the same method as the transparent oxide conductive film 30.

  Next, a resist material is applied onto the second transparent oxide conductive film, a photoresist pattern is formed in the sixth photolithography process, and the second transparent oxide conductive film is etched using the photoresist pattern as a mask. To do.

  For the etching of the second transparent oxide conductive film, a wet etching method using an aqueous solution containing oxalic acid at 5 wt% can be used.

  Thereafter, by removing the photoresist pattern, as shown in FIG. 17 and FIG. 18, the source through the gate terminal pad 19 and the source terminal contact hole 16 which are electrically connected to the gate terminal 3 through the gate terminal contact hole 15. A source terminal pad 20 electrically connected to the terminal 12 and a counter electrode 18 electrically connected to the common electrode 4 through the common electrode contact hole 17 are obtained. The counter electrode 18 is also formed with a plurality of slit openings SL at the same time and has a comb shape.

  Thereafter, heat treatment (annealing) is performed for 60 minutes at a temperature of 230 ° C. in an air atmosphere in order to eliminate plasma damage and the like generated on the substrate during the manufacturing process. Thereby, the amorphous ITO is completely crystallized. Further, along with crystallization, oxygen is supplied from the oxide semiconductor 6A toward the pixel electrode 13 during the heat treatment, and the transmittance of the pixel electrode 13 is increased. By this annealing, the FFS type TFT substrate 200 is completed.

  As described above, in the second embodiment, it is possible to manufacture a TFT substrate having a high mobility TFT in six photolithography processes by using the oxide semiconductor film 6A for the TFT channel layer. Become.

  Further, in the manufacturing method of the second embodiment, in addition to the effects obtained in the first embodiment, the pixel electrode 13 can be further enlarged. That is, in the manufacturing method of the first embodiment, since the pixel electrode is formed in the second photolithography process and the fifth photolithography process, an overlap margin of photolithography is necessary, and the pixel electrode is equivalent to the margin. 13 becomes smaller. However, in the manufacturing method of the second embodiment, since the size and shape of the pixel electrode are determined in the fourth photolithography process, it is not necessary to provide an overlay margin, and the area of the pixel electrode is increased and the aperture ratio is improved. It will be.

<Embodiment 3>
In the second embodiment described above, the TFT substrate 200 is formed through six photolithography processes. In the third embodiment described below, a manufacturing method in which the number of photolithography processes is further reduced will be described. .

  FIG. 25 is a plan view showing a planar configuration of a pixel in the FFS TFT substrate 300 according to the third embodiment. FIG. 26 is a sectional configuration taken along line XX in FIG. It is sectional drawing which shows a cross-sectional structure and a cross-sectional structure in a ZZ line. In addition, the same code | symbol is attached | subjected about the structure same as the TFT substrate 200 demonstrated using FIG. 17 and FIG. 18, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 26, in the TFT substrate 300, an oxide semiconductor film 6A is formed on the insulating film 5 so as to extend from the TFT portion to the pixel portion, and the source wiring 21 (FIG. 17). The oxide semiconductor film 23 is formed on the insulating film 5 below the source terminal 12, and the insulating film 7A (second insulating film) is formed thereon. The oxide semiconductor films 6A and 23 are formed of the same layer, and a portion of the oxide semiconductor film 6A provided above the gate electrode 2 of the TFT portion functions as a channel layer and is formed on the gate electrode 2. The insulating film 5 functions as a gate insulating film. Further, a portion of the oxide semiconductor film 6A provided in the pixel portion is provided so as to face the pixel electrode 13A.

  In addition, the planar pattern of the portion provided in the TFT portion of the oxide semiconductor film 6A is formed larger than the planar pattern of the gate electrode 2, and the whole is covered with the insulating film 7A.

  The insulating film 7A covers the entire portion of the oxide semiconductor film 6A provided in the TFT portion, but the drain electrode contact hole 8 and the source electrode contact hole 9 are provided so as to penetrate the insulating film 7A.

  The insulating film 7A is mostly removed on the oxide semiconductor film 6A provided in the pixel portion, and the pixel electrode 13A is provided on the oxide semiconductor film 6A. The insulating film 7A does not cover the side surface of the oxide semiconductor film 23 and covers only the oxide semiconductor film 23. In FIG. 25, the oxide semiconductor film 23 is hidden by the insulating film 7A and is not illustrated. ing.

  A redundant source wiring 133 formed of the same material and in the same layer as the pixel electrode 13A is formed on the insulating film 7A, and the source wiring 21 (FIG. 1) and the source terminal 12 are formed on the redundant source wiring 133. Is formed.

  In the TFT substrate 300, the pixel electrode extension 131 of the pixel electrode 13A provided so as to extend above the oxide semiconductor film 6A is directly connected to the oxide semiconductor film 6A via the drain electrode contact hole 8. The drain electrode 10 is provided on the pixel electrode extension 131.

  The source electrode contact hole 9 has a redundant source electrode 132 formed of the same material in the same layer as the pixel electrode 13A and is electrically connected to the oxide semiconductor film 6A. The source electrode 11 is provided on the redundant source electrode 132.

  As shown in FIG. 25, the pixel electrode 13A and the oxide semiconductor film 6A in the pixel portion are rectangular in plan view, and the pixel electrode 13A is formed to be slightly smaller than the oxide semiconductor film 6A in the pixel portion. The outer edge portion of the pixel electrode 13A is inside the outer edge portion of the oxide semiconductor film 6A in the pixel portion.

  Thus, in the TFT substrate 300, the pixel electrode extension 131 of the pixel electrode 13A provided so as to extend above the oxide semiconductor film 6A is electrically connected to the oxide semiconductor film 6A. The drain electrode 10 is provided on the pixel electrode extension 131. Further, the redundant source electrode 132 is electrically connected to the oxide semiconductor film 6A, the source electrode 11 is formed on the redundant source electrode 132, and the source wiring 21 and the source terminal 12 are formed on the redundant source wiring 133. ing. For this reason, the drain electrode 10, the source electrode 11, and the source wiring 21 become a redundant structure, and disconnection can be reduced significantly.

  In the third embodiment, a stacked film of the oxide semiconductor film 23 and the insulating film 7A is formed under the redundant source wiring 133. For this reason, an effect of preventing the occurrence of a defect due to an electrical short between the source wiring 21, the gate wiring 22 and the common electrode wiring 4 can be expected.

<Manufacturing method>
Hereinafter, a manufacturing method of the TFT substrate 300 according to the third embodiment will be described with reference to FIGS. A plan view and a cross-sectional view showing the final process correspond to FIGS. 25 and 26, respectively.

  Note that the process up to the patterning of the insulating film 7A described with reference to FIG. 20 in the second embodiment is the same in the third embodiment, and thus the description thereof is omitted. The processes after the patterning of the insulating film 7A are described. To do.

  As shown in FIG. 27, a transparent oxide conductive film 30 (first transparent oxide conductive film) and a conductive material are formed on the entire upper surface of the transparent insulating substrate 1 on which the insulating film 7A has been patterned through two photolithography processes. A film 29 (second conductive film) is formed in this order. Here, an amorphous ITO film having a thickness of 80 nm is formed as the transparent oxide conductive film 30, and a MoNb alloy film and an Al—Ni—Nd alloy film each having a thickness of 100 nm are formed in this order as the conductive film 29. Formed. The formation method and composition of the transparent oxide conductive film 30 and the conductive film 29 are the same as those in the first and second embodiments.

  Next, a resist material is applied onto the conductive film 29, and as shown in FIG. 28, a photoresist pattern 41 is formed in the third photolithography process using the halftone mask 26.

  That is, a resist material composed of a novolac positive photosensitive resin is applied onto the conductive film 29 by a coating method to form a photoresist having a thickness of about 1.5 μm. Then, the photoresist is exposed using a halftone mask 26 prepared in advance. The halftone mask 26 includes a light shielding film pattern 26b for forming the drain electrode 10 and the pixel electrode extension 131, a light shielding film pattern 26c for forming the source electrode 11 and the redundant source electrode 132, the source wiring 21, and the source. A light shielding film pattern 26 d for forming the terminal 12 and the redundant source wiring 133 is provided. A region where exposure light is blocked by these light shielding film patterns becomes a light shielding region. Further, the halftone mask 26 is provided with a semi-transmissive semi-transmissive pattern 26a for reducing the light intensity of exposure at a portion to be a pattern for forming the pixel electrode 13A, and the semi-transmissive pattern 26a is used for exposure. A region where light is attenuated becomes a semi-transmissive region.

  After exposing the photoresist using the halftone mask 26, development is performed using an organic alkaline developer containing tetramethylammonium hydroxide (TMAH) to obtain a photoresist pattern 41 shown in FIG. It is done. The photoresist pattern 41 remains as the first film thickness portion while maintaining the initial thickness in the unexposed areas corresponding to the light shielding film patterns 26b, 26c, and 26d, but the semi-exposed area under the semi-transmissive pattern 26a. Then, it remains as a second film thickness portion having a thickness smaller than that of the first film thickness portion, and is completely removed in the exposure region. In the third embodiment, the minimum film thickness is set to about 0.2 μm. The photoresist pattern 41 has an opening OP above the insulating film 7A on the channel region.

  Next, the conductive film 29 and the transparent oxide conductive film 30 are etched using the photoresist pattern 41 as a mask. For etching the conductive film 29 which is a laminated film of the MoNb alloy film and the Al—Ni—Nd alloy film, a wet etching method using a PAN solution as an etchant can be used, and it is an amorphous ITO film. Since the transparent oxide conductive film 30 is also soluble in the PAN solution, the conductive film 29 and the transparent oxide conductive film 30 can be etched together.

  When the conductive film 29 and the transparent oxide conductive film 30 are etched together, the transparent oxide conductive film 30 that is an amorphous ITO film has a lower etching rate. The pixel electrode 13A obtained by etching the conductive film 30 is slightly larger in area in plan view than the conductive film 29 on the pixel electrode 13A. Since the etching with the PAN solution proceeds through the opening OP of the photoresist pattern 41, the conductive film 29 and the transparent oxide conductive film 30 above the channel region are also removed, and the insulating film 7A is exposed above the channel region. .

  Subsequently, the oxide semiconductor film 28 is etched using the photoresist pattern 41 as a mask. For the etching of the oxide semiconductor film 28 which is an amorphous InZnSnO film, wet etching using a solution containing oxalic acid is used. However, since the amorphous ITO film is also etched again by etching with oxalic acid, a transparent oxidation is performed. The physical conductive film 30 is also etched, and as shown in FIG. 30, the area of the pixel electrode 13A becomes smaller than that of FIG. In addition, since the InZnSnO film, which is the oxide semiconductor film 28, has a lower etching rate with oxalic acid than the amorphous ITO film, the oxide semiconductor film 28 is slightly larger in area in plan view than the pixel electrode 13A. The oxide semiconductor film 6A is formed.

Next, in the step shown in FIG. 31, the film thickness of the photoresist pattern 41 is entirely reduced by using O ₂ ashing, and the photoresist pattern 41 in the pixel portion having the minimum film thickness is completely removed. As a result, photoresist patterns 411, 412 and 413 with reduced film thickness are obtained. Thereafter, annealing was performed in an air atmosphere at 150 ° C. for 30 minutes in order to crystallize the amorphous ITO film. At this time, if the crystallization temperature is higher than 150 ° C., the photoresist is hardened and difficult to remove.

  Next, using the photoresist patterns 411, 412 and 413 as a mask, the conductive film 29 in the pixel portion is etched with a PAN solution, and the photoresist patterns 411, 412 and 413 are removed, as shown in FIG. The pixel electrode 13A, the drain electrode 10, the source electrode 11, the source wiring 21 (not shown), the source terminal 12, the pixel electrode extension 131, the redundant source electrode 132, and the redundant source wiring 133 are formed.

  Next, a third insulating film is formed on the entire upper surface of the transparent insulating substrate 1. In Embodiment Mode 3, a silicon oxide (SiO) film having a thickness of 200 nm and a silicon nitride (SiN) film having a thickness of 150 nm are formed in this order by using a CVD method to form a third insulating film.

Next, a resist material is applied on the third insulating film, a photoresist pattern is formed in the fourth photolithography process, and the third insulating film and the insulating film 5 are etched using the photoresist pattern as a mask. For etching the third insulating film and the insulating film 5, dry etching using a gas in which oxygen (O ₂ ) is added to sulfur hexafluoride (SF ₆ ) was used.

  Thereafter, by removing the photoresist pattern, as shown in FIG. 26, the gate terminal contact hole 15 reaching the gate terminal 3, the source terminal contact hole 16 reaching the source terminal 12, and the common electrode contact hole reaching the common electrode 4. 17 is obtained simultaneously.

  Thereafter, a second transparent oxide conductive film is formed on the insulating film 14. In the third embodiment, an amorphous ITO film having the same composition is formed as the second transparent oxide conductive film by the same method as that of the transparent oxide conductive film 30.

  Next, a resist material is applied onto the second transparent oxide conductive film, a photoresist pattern is formed in the fifth photolithography process, and the second transparent oxide conductive film is etched using the photoresist pattern as a mask. To do.

  For the etching of the second transparent oxide conductive film, a wet etching method using an aqueous solution containing oxalic acid at 5 wt% can be used.

  Thereafter, by removing the photoresist pattern, as shown in FIG. 25 and FIG. 26, the source through the gate terminal pad 19 and the source terminal contact hole 16 electrically connected to the gate terminal 3 through the gate terminal contact hole 15. A source terminal pad 20 electrically connected to the terminal 12 and a counter electrode 18 electrically connected to the common electrode 4 through the common electrode contact hole 17 are obtained. The counter electrode 18 is also formed with a plurality of slit openings SL at the same time and has a comb shape.

  Thereafter, heat treatment (annealing) is performed for 60 minutes at a temperature of 230 ° C. in an air atmosphere in order to eliminate plasma damage and the like generated on the substrate during the manufacturing process. Thereby, the amorphous ITO is completely crystallized. Further, along with crystallization, oxygen is supplied from the oxide semiconductor 6A toward the pixel electrode 13A during the heat treatment, and the transmittance of the pixel electrode 13A increases. By this annealing, the FFS type TFT substrate 300 is completed.

  As described above, in the third embodiment, by using the oxide semiconductor film 6A for the TFT channel layer, a TFT substrate having a high mobility TFT can be manufactured in five photolithography processes. Become.

  In addition to these, the present invention can be freely combined with each other within the scope of the present invention, and each embodiment can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate, 2 Gate electrode, 3 Gate terminal, 4 Common electrode wiring, 5, 7 Insulating film, 6, 6A, 23, 24 Oxide semiconductor film, 8 Drain contact hole, 9 Source contact hole, 10 Drain electrode , 11 source electrode, 12 source terminal, 13, 13A pixel electrode, 18 counter electrode, 21 source wiring, 22 gate wiring.

Claims (9)

A thin film transistor substrate in which a plurality of pixels are arranged in a matrix,
Each of the pixels
A gate electrode and a common electrode wiring selectively disposed on the substrate;
A first insulating film covering the gate electrode and the common electrode wiring;
An oxide semiconductor film selectively disposed on the first insulating film;
A second insulating film disposed on the first insulating film and the oxide semiconductor film;
A source electrode, a drain electrode and a source wiring disposed on the second insulating film;
A pixel electrode electrically connected to the drain electrode by contacting a part of the drain electrode on an end of the drain electrode;
A third insulating film disposed on the source electrode, the drain electrode, the source wiring, and the pixel electrode;
A counter electrode disposed on the third insulating film so as to face the pixel electrode,
The counter electrode is
Electrically connected to the common electrode wiring through a common electrode contact hole penetrating the third insulating film and the first insulating film;
The oxide semiconductor film is provided at least above the gate electrode and below the pixel electrode,
The pixel electrode has a portion in direct contact with the oxide semiconductor film,
The thin film transistor substrate, wherein the source electrode and the drain electrode are electrically connected to the oxide semiconductor film through a source electrode contact hole and a drain electrode contact hole penetrating the second insulating film, respectively. Instead of the drain electrode, a pixel electrode extending portion provided so as to extend from the pixel electrode to above the oxide semiconductor film,
The pixel electrode extending portion is
The thin film transistor substrate according to claim 1, wherein the thin film transistor substrate is electrically connected to the oxide semiconductor film through the drain electrode contact hole.   The thin film transistor substrate according to claim 1, wherein the oxide semiconductor film and the second insulating film are disposed as a laminated film below the source wiring. A thin film transistor substrate in which a plurality of pixels are arranged in a matrix,
Each of the pixels
A gate electrode and a common electrode wiring selectively disposed on the substrate;
A first insulating film covering the gate electrode and the common electrode wiring;
An oxide semiconductor film selectively disposed on the first insulating film;
A second insulating film disposed on the first insulating film and the oxide semiconductor film;
A pixel electrode having a pixel electrode extending portion provided so as to extend above the oxide semiconductor film with the second insulating film interposed therebetween;
A redundant source electrode and a redundant source wiring provided as the same layer as the pixel electrode on the second insulating film;
A source electrode, a drain electrode, and a source wiring provided on the redundant source electrode, the pixel electrode extension portion, and the redundant source wiring, respectively;
A third insulating film disposed on the source electrode, the drain electrode, the source wiring, and the pixel electrode;
A counter electrode disposed on the third insulating film so as to face the pixel electrode,
The counter electrode is
Electrically connected to the common electrode wiring through a common electrode contact hole penetrating the third insulating film and the first insulating film;
The oxide semiconductor film is provided at least above the gate electrode and below the pixel electrode,
The pixel electrode has a portion in direct contact with the oxide semiconductor film,
The thin film transistor substrate, wherein the redundant source electrode and the pixel electrode extending portion are electrically connected to the oxide semiconductor film through a source electrode contact hole and a drain electrode contact hole that penetrate the second insulating film, respectively. .   5. The thin film transistor substrate according to claim 4, wherein the oxide semiconductor film, the second insulating film, and the redundant source wiring are disposed as a laminated film below the source wiring. 6. A method of manufacturing a thin film transistor substrate in which a plurality of pixels are arranged in a matrix,
(A) forming a first conductive film on the entire upper surface of the substrate;
(B) patterning the first conductive film by a first photolithography process and an etching process to form a gate electrode and a common electrode wiring;
(C) after the step (b), forming a first insulating film on the entire upper surface of the substrate;
(D) forming an oxide semiconductor film over the entire upper surface of the first insulating film;
(E) forming a second insulating film on the entire upper surface of the oxide semiconductor film;
(F) The second insulating film is patterned by the second photolithography process and the etching process, and the second insulating film is left so as to cover the oxide semiconductor film in the upper part of the gate electrode. And forming a source electrode contact hole and a drain electrode contact hole penetrating the second insulating film above the gate electrode;
(G) after (f), forming a second conductive film on the entire upper surface of the substrate;
(H) patterning the second conductive film by a third photolithography process and etching process to form a source electrode, a drain electrode and a source wiring;
(I) After the step (h), forming a first transparent oxide conductive film on the entire upper surface of the substrate;
(J) forming a pixel electrode by simultaneously patterning the first transparent oxide conductive film and the oxide semiconductor film by a fourth photolithography process and an etching process;
(K) After the step (j), forming a third insulating film on the entire upper surface of the substrate;
(L) forming a common electrode contact hole penetrating the third insulating film and the first insulating film by a fifth photolithography process and an etching process;
(M) after (l), forming a second transparent oxide conductive film on the entire upper surface of the substrate;
And (n) patterning the second transparent oxide conductive film by a sixth photolithography process and an etching process to form a counter electrode facing the pixel electrode. Method. A method of manufacturing a thin film transistor substrate in which a plurality of pixels are arranged in a matrix,
(A) forming a first conductive film on the entire upper surface of the substrate;
(B) patterning the first conductive film by a first photolithography process and an etching process to form a gate electrode and a common electrode wiring;
(C) after the step (b), forming a first insulating film on the entire upper surface of the substrate;
(D) forming an oxide semiconductor film over the entire upper surface of the first insulating film;
(E) forming a second insulating film on the entire upper surface of the oxide semiconductor film;
(F) The second insulating film is patterned by the second photolithography process and the etching process, and the second insulating film is left so as to cover the oxide semiconductor film in the upper part of the gate electrode. And forming a source electrode contact hole and a drain electrode contact hole penetrating the second insulating film above the gate electrode;
(G) after (f), forming a first transparent oxide conductive film on the entire upper surface of the substrate;
(H) forming a second conductive film on the entire upper surface of the first transparent oxide conductive film;
(I) A resist pattern having a first film thickness portion and a second film thickness portion thinner than the first film thickness portion on the second conductive film by the third photolithography process. Forming a step;
(J) Using the resist pattern, the second conductive film and the first transparent oxide conductive film are patterned by an etching process to form a source electrode, a redundant source electrode thereunder, a source wiring, and a lower part thereof Forming a redundant source wiring, a drain electrode, and a pixel electrode having a pixel electrode extension under the redundant source wiring,
(K) After the step (j),
Reducing the thickness of the resist pattern so that the second thickness portion of the resist pattern disappears;
(L) After the step (k), using the resist pattern having a reduced film thickness, removing the second conductive film not covered with the resist pattern by an etching step;
(M) after (j), forming a third insulating film over the entire upper surface of the substrate;
(N) forming a common electrode contact hole penetrating the third insulating film and the first insulating film by a fourth photolithography process and an etching process;
(O) After (n), forming a second transparent oxide conductive film on the entire upper surface of the substrate;
(P) patterning the second transparent oxide conductive film by a fifth photolithography process and etching process to form a counter electrode facing the pixel electrode, and manufacturing a thin film transistor substrate Method. The step (d)
The method for manufacturing a thin film transistor substrate according to claim 6, further comprising a step of forming the oxide semiconductor film with a material that is insoluble or hardly soluble in etching the second conductive film. The step (g)
The method of manufacturing a thin film transistor substrate according to claim 7, comprising a step of forming the first transparent oxide conductive film with a material that is soluble in etching of the second conductive film.

Images