JP6477185B2 - Arithmetic processing apparatus and control method of arithmetic processing apparatus - Google Patents

Description

  The embodiments referred to herein relate to an arithmetic processing unit and a control method of the arithmetic processing unit.

  In recent years, for example, parallel processing by a single instruction multiple data (SIMD) type arithmetic processing unit (processor) has been used to execute processing in an image recognition or analysis method of big data.

  In such a SIMD processor, for example, an instruction (command) is transmitted from a PE (processor element) control unit to each processor element (PE: Processor Element) through a common command bus (common bus).

  In addition, each PE (each core in a multi-core processor) accesses the memory (common resource) via, for example, an arbitration circuit (Arbiter) to perform parallel processing of data stored in the memory. Run.

  By the way, conventionally, various methods have been proposed as SIMD type arithmetic processing devices including a plurality of processor elements and control methods of the arithmetic processing devices.

JP, 2005-148899, A Japanese Patent Application Laid-Open No. 08-030577 Japanese Patent Application Publication No. 06-036060

  As described above, for example, in the SIMD processor, a command from the PE control unit is input to each PE via the common bus. Furthermore, each PE accesses the memory through, for example, a complex arbiter provided on the memory side, and a memory read request and an acknowledge mechanism are implemented on the PE side.

  Therefore, for example, there is a problem that the next command can not be executed until all the PEs finish executing the command, and the number of processing cycles increases, which makes it difficult to execute data processing at high speed. In addition, depending on the circuit size, the decrease in the operating frequency of the arbiter may be delayed, again making it difficult to execute data processing at high speed.

  According to one embodiment, there is provided an arithmetic processing unit including a plurality of processor elements simultaneously accessible to a common resource, the arithmetic processing unit having a first bus and a second bus. .

  The first bus is connected in parallel to the plurality of processor elements to give a common first instruction to each of the processor elements, and the second bus is connected in series to the plurality of processor elements Be done.

  The second bus is connected in series to the first processor element in the second cycle following the first cycle, for the second instruction given to the first processor element in the first cycle in the plurality of processor elements. Tell the second processor element.

  The disclosed arithmetic processing device and the control method of the arithmetic processing device have an effect that processing speed for a common resource by a plurality of processor elements can be improved while suppressing an increase in circuit scale.

FIG. 1 is a block diagram showing an example of an arithmetic processing unit as a related art. FIG. 2 is a block diagram showing an example of processor elements in the arithmetic processing unit shown in FIG. FIG. 3 is a view for explaining an example in the case where graphics processing is performed by the arithmetic processing unit shown in FIG. FIG. 4 is a diagram for explaining an example of the binary tree search process. FIG. 5 is a timing chart for explaining an example of the operation when the binary tree search process shown in FIG. 4 is executed by the arithmetic processing unit shown in FIG. FIG. 6 is a block diagram showing the processing unit of the first embodiment. FIG. 7 is a block diagram showing an example of processor elements in the arithmetic processing unit shown in FIG. FIG. 8 is a diagram for describing a selector in the processor element shown in FIG. FIG. 9 is a timing chart for explaining an example of the operation of the processing unit of the first embodiment. FIG. 10 is a block diagram showing an arithmetic processing unit of the second embodiment. FIG. 11 is a block diagram showing an example of processor elements in the arithmetic processing unit shown in FIG. FIG. 12 is a diagram for describing a selector in the processor element shown in FIG. FIG. 13 is a timing chart for explaining an example of the operation of the processing unit of the second embodiment. FIG. 14 is a block diagram showing an arithmetic processing unit of the third embodiment. FIG. 15 is a block diagram showing an example of processor elements in the arithmetic processing unit shown in FIG. FIG. 16 is a diagram (part 1) for describing a selector in the processor element shown in FIG. FIG. 17 is a second diagram to explain a selector in a processor element shown in FIG. 15; FIG. 18 is a timing chart for explaining an example of the operation of the processing unit of the third embodiment. FIG. 19 is a block diagram showing an example of a semiconductor integrated circuit to which the processing unit of this embodiment is applied.

  First, before describing the arithmetic processing device and the control method of the arithmetic processing device according to the present embodiment in detail, an example of a control method of the arithmetic processing device and the problems thereof will be described with reference to FIGS. .

  FIG. 1 is a block diagram showing an example of an arithmetic processing unit as a related art, and shows, for example, an example of a SIMD type arithmetic processing unit (SIMD type processor) that executes processing in an image recognition and analysis method of big data. It is.

  In FIG. 1, reference numerals 101a to 101n denote processor elements (PE), 102 denotes a PE control unit, 103 denotes a memory (memory for tree), 104 denotes a common command bus (common bus), 105 denotes a comparison target data bus, Reference numeral 106 denotes an arbitration circuit (arbiter).

  In FIG. 1, the tree memory 103 is shown as a common resource that can be simultaneously accessed by the plurality of PEs 101 a to 101 n, but, for example, an arbiter that performs arbitration is also provided to an image memory (not shown). It will be.

  The PE control unit 102 includes a fetch unit 121 which temporarily holds an instruction (command), and a program memory 122 which stores a program. Here, each of the PEs 101a to 101n receives a common command from the PE control unit 102 through the common bus 104, and accesses the memory 103 through the buses 110a to 110n with the arbiter 106, respectively.

  Although the buses 110a to 110n between the PEs 101a to 101n and the arbiter 106 in FIG. 1 are drawn as one line, for example, an address bus and data of a plurality of bits (for example, 32 or 64 bits) in both directions Including the bus.

  Also, for example, when a binary tree search is performed by the SIMD processor shown in FIG. 1, data of each tree data (nodes 0 to k in trees 0 to n) of the binary tree is, for example, , And stored in one memory (tree data storage memory).

  Furthermore, the comparison target data may be supplied from, for example, another memory (RAM: Random Access Memory). Also, the number of PEs may be variously set to a few to a few hundred according to the specification, but, for example, about one hundred and several tens to execute processing in an image recognition or analysis method of big data. It is conceivable to

  FIG. 2 is a block diagram showing an example of processor elements in the arithmetic processing unit shown in FIG. As shown in FIG. 2, each of the PEs 101 (101a to 101n) includes a command buffer 111 that receives and holds commands from the common bus 104, and a processor core 112 that executes commands held in the command buffer 111.

  Then, the PE 101 outputs a RAM (memory) address and a RAM read request to the memory 103 via the bus 110 and the arbiter 106, and a RAM read ACK (acknowledgement) from the memory 103 via the arbiter 106 and the bus 110. And receive RAM read data.

  FIG. 3 is a view for explaining an example in the case where graphics processing is performed by the arithmetic processing unit shown in FIG. Here, FIG. 3 is for explaining the case where graphics processing is performed as an example in which a plurality of data processing is performed with the same program by a SIMD type processor including a plurality of PEs 101a to 101n.

  As shown in FIG. 3, when graphics processing is performed, for example, pixel data (A 1, A 2, A 3,... To N 1, N 2, N 3,...) Of pixels handled by each of the PEs 101 a to 101 n. Send in a fixed order.

  Each of the PEs 101a to 101n performs a simple operation (for example, A1 * A2 + A3 to N1 * N2 + N3) on input data and outputs the result. That is, when performing graphics processing, data can be supplied from outside (external memory) by DMA (Direct Memory Access) or the like regardless of the internal state of each of the PEs 101a to 101n.

  FIG. 4 is a diagram for explaining an example of the binary tree search process, and FIG. 4 (a) shows nodes of the binary tree, and FIG. 4 (b) shows binary tree search process (bifurcation) Tree processing) is a flowchart for explaining an example.

  As shown in FIG. 4A, in a tree structure which is a kind of data structure, a binary tree has a parent node having two or less child nodes and has a root without a parent (root node: node 0), and in order are arranged as node 1, node 2,.

  This binary tree is used, for example, in a method called random forest used in machine learning such as image recognition. A SIMD-type processor is then applied to process multiple binary tree searches in parallel. In the following description, for the sake of simplicity, the SIMD processor shown in FIG. 6 is used to set the luminance of a certain pixel as a threshold at each node (node 1, 2, 3,...) Of binary tree search. I will compare.

  As shown in FIG. 4B, when binary tree processing is started (START), i = 0, ie, the root node (node 0) is set in step ST1, and the process proceeds to step ST2. In step ST2, in node i, the determination pixel coordinates for determination, the determination threshold, the branch destination information for each of the determination results true / false, and the determination result in the case of the final node are read out from the tree memory (32) Lead). The branch destination information indicates a tree memory address (in the case of the final node, NULL (null)) in which information of the next node is stored.

  Further, the process proceeds to step ST3, the luminance data corresponding to the determination pixel coordinates is read from the image memory (31), and the process proceeds to step ST4. Here, the memory for tree (32) is a memory for storing information of each node of the binary tree, and the memory for image (31) is a memory for storing the luminance of each pixel.

  In step ST4, determination is performed, that is, it is determined whether the luminance read in step ST3 is larger than the threshold (luminance> threshold?), And in step ST5, it is the final node, ie, the branch destination is null. It is determined whether or not (branch destination == Null).

  If it is determined in step ST5 that the node is not the final node, the process proceeds to step ST6 to determine a branch destination node according to the determination result, and returns to step ST2 to repeat the same processing. On the other hand, when it is determined in step ST5 that the node is the final node, the process proceeds to step ST7, the determination result is output, and the process is ended (END).

  By the way, assuming that one binary tree is allocated to each of the PEs 101a to 101n, for example, data of the root node node 0 is uniquely determined because there is no option. That is, although the data of node 0 can be supplied from the outside, it is the information that only the corresponding PE recognizes as to which of node 1 or node 2 is to be selected in the next step. It is difficult to supply corresponding data from

  That is, when the binary tree search is applied to the SIMD processor, individual accesses to the image memory (31) and the tree memory (32) are required from each of the PEs 101a to 101n at least after the second step. become.

  Therefore, simultaneous accesses to the memory from multiple PEs 101a to 101n occur, and the implementation of a complex arbiter (arbitration circuit) is required on the memory side. As a result, the operating frequency of the arbiter becomes slower depending on the circuit size. There is a problem that it becomes difficult to execute

  Furthermore, in the SIMD type processor, it is difficult to execute the next instruction until all the PEs 101a to 101n complete the instruction. Therefore, while the arbitration of the individual PEs 101a to 101n is performed by the above-described memory access, It becomes difficult to move on to the next instruction. Therefore, there is a problem that the number of processing cycles increases and it is difficult to execute data processing at high speed.

  FIG. 5 is a timing chart for explaining an example of the operation when the binary tree search process shown in FIG. 4 is executed by the arithmetic processing unit shown in FIG. The memory is a general single port RAM.

  As shown in FIG. 5, first, a read command cmd1 for the tree memory (32) is issued to the common bus 104. Each of the PEs 101a to 101n tries to execute a read command of the tree memory (32) all at once, but the tree memory only receives an access from one PE in one cycle.

  Here, it is assumed that the arbiter of the tree memory (32) receives an access such as PE 0 → PE 1 → ... → PE 15 when the number of PEs (processor elements) is 16, for example. At this time, since the PE 0 can receive a memory access in the first cycle, it then enters a wait state until the other PE's access is completed.

  Also, after being accepted for memory access in the cycle next to PE0, PE1 enters a wait state. Thus, a total of 16 cycles are spent until the memory access of the PE 15 is accepted.

  Similarly, a read command (read command) to the next image memory (31), cmd2, will consume a total of 16 cycles, and a total of 32 cycles will be spent by these two instructions.

  As described above, according to the processing device of the related art, it is difficult to shorten the access time from each of the PEs 101a to 101n to the memory, and it is difficult to improve, for example, the image recognition speed in image processing.

  Hereinafter, an embodiment of an arithmetic processing unit and a control method of the arithmetic processing unit will be described in detail with reference to the attached drawings. FIG. 6 is a block diagram showing an arithmetic processing unit according to the first embodiment. For example, a first embodiment of a SIMD type arithmetic processing unit (SIMD processor) which executes processing in image recognition and analysis method of big data is described. It is shown.

  In FIG. 6, reference numerals 1a to 1n denote processor elements (PE), 2 denotes a PE (processor element) control unit, 31 denotes an image memory, 32 denotes a tree memory, and 4 denotes a common command bus (common bus: first bus) And 5 indicate a cascade bus (second bus).

  Here, the cascade bus 5 is a bus for passing (bucket relaying) a command (second instruction) to the PEs serially connected in series based on each cycle, and in the present specification, the command is bucket relayed. This bus will be called a cascade bus for convenience.

  In addition, information (for example, luminance) of each pixel to be compared in binary tree search (binary tree processing) is stored in the image memory 31, and binary tree processing is performed in the tree memory 32. The node information used in is stored.

  One binary tree process is assigned to each of the PEs 1a to 1n. The common bus 4 is connected in parallel to the plurality of PEs 1a to 1n, and is configured to give a common command (first instruction) common to the respective PEs 1a to 1n.

  Furthermore, the cascade bus 5 is connected in series to the plurality of PEs 1a to 1n, and in the plurality of PEs 1a to 1n, for example, the cascade command (second instruction) given to the PE 1a in the first cycle is It is designed to transmit to PE1b in a cycle.

  The PE control unit 2 includes a fetch unit 21 that temporarily holds an instruction (command), and a program memory 22 that stores a program. Here, each of the PEs 1 a to 1 n receives a common command from the PE control unit 2 through the common bus 4, and further receives a cascade command through the cascade bus 5.

  As shown in FIG. 6, the PEs 1a to 1n and the image memory 31 are connected by buses 18a to 18n, respectively, and the PEs 1a to 1n and the tree memory 32 are connected by buses 19a to 19n, respectively. There is.

  Although these buses 18a to 18n and 19a to 19n are drawn as one line, they include, for example, an address bus and a data bus of multiple bits (for example, 32 or 64 bits) in both directions. .

  In FIG. 6, a common command (first instruction) sent through the common bus 4 from the PE control unit 2 and a cascade command (second instruction) sent through the cascade bus 5 have 1 bit bit field (cascade bit) Field is set.

An example of the instruction format is shown in Table 1 below. Here, the instruction length is 33 bits, the most significant bit is assigned to a cascade bit field CBF (Cascade Bit Field: instruction type information), and the lower 32 bits are used as an instruction field for a normal 32-bit processor.

  As shown in Table 1, the cascade bit field CBF indicates, for example, that it is an instruction (cascade command) to be transmitted through the cascade bus 5 when "1". When it is "0", it indicates that it is an instruction (common command) transmitted through the common bus 4.

  As described above, the PE control unit 2 and each of the PEs 1 a to 1 n are connected by two buses, the common bus 4 and the cascade bus 5. Then, the PE control unit 2 issues a command (common command) in which each of the PEs 1 a to 1 n does not perform memory access to the common bus 4 and issues a command (cascade command) to perform memory access to the cascade bus 5.

  At this time, when the cascade bit field CBF is provided as a control signal (instruction type information) on the bus and a command is issued to the cascade bus 5, for example, the cascade bit field CBF is “1” (high level “H” Set to).

  The CBF can be softly incorporated into a command, for example, by a programmer who creates a program or a compiler which converts the source code of a program written in a programming language.

  Alternatively, without embedding CBF in the command, for example, the type of command is determined to determine whether it is a common command to be transmitted to each PE 1 a to 1 n through common bus 4 or a cascade command to be transmitted to each PE 1 a to 1 n through cascade bus 5 It is also possible to perform processing.

  FIG. 7 is a block diagram showing an example of processor elements in the arithmetic processing unit shown in FIG. As shown in FIG. 7, each processor element 1 (1 a to 1 n) includes a command buffer 11, a processor core 12 and a selector (first selector) 13.

  The selector 13 selects the common command of the common bus 4 or the cascade command of the cascade bus 5 by the cascade bit field (instruction type information) CBF, and the command selected by the selector 13 is held in the command buffer 11.

  That is, selector 13 selects the cascade command of cascade bus 5 when CBF is "1", and selects the common command of common bus 4 when CBF is "0", and the selected command is a command buffer. 11 is held.

  The processor core 12 executes the command held in the command buffer 11. Then, when the command output from the command buffer 11 is a memory access, the PE1 outputs an address (RAM address) and a read enable (RAM read enable) to the memory from the PE1, and the corresponding read data (RAM read) Receive data).

  The command bit buffer 11 observes a cascade bit field CBF which is a control signal on the cascade bus 5, and when the CBF is "1", a cascade command by the cascade bus 5 selected by the selector 5 is taken. When the CBF is “0”, the command buffer 11 receives a common command from the common bus 4 selected by the selector 5.

  The command buffer 11 buffers the fetched command, and outputs the buffered command to the processor core 12 of its own PE (for example, PE1a). Furthermore, the command buffered in the command buffer 11 is transmitted through the cascade bus 5 to the serially connected (next stage) PEs (e.g., the PE 1 b) in the next cycle.

  Thereby, for example, since the CBR is set to “1”, the command (cascade command) for performing memory access is sequentially processed from the processor element closer to the PE control unit 2 (1a → 1b → 1c →...) It will be transmitted off the cycle.

  As described above, the PE1 executes the command output from the PE control unit 2. When the command is a memory access, the PE1 outputs an address (RAM address) and a read enable to the memory (RAM read enable) Do.

  Here, the address has a significant value only in the cycle in which the read enable is asserted, and outputs "0" in the other cycles. Also, since memory access commands are input through the cascade bus 5, it is guaranteed that cycles do not overlap.

  Therefore, the address and the read enable input to the memory can be made simple by taking the logical sum of the address and the read enable output from the respective PEs 1 (1a to 1n). Also, on the PE 1 side, since the read enable can be issued and then read data can be received after a determined cycle (for example, after one cycle), the acknowledgment mechanism becomes unnecessary.

  The PE control unit 2 can recognize that the memory access of all the processor elements 1a to 1n is completed, for example, by observing CBF (CTS) output from the final processor element 1n, and the common bus 4 It is possible to issue commands for

  That is, as shown in FIG. 6 described above, for example, the cascade bit field CBF of the final processor element 1 n may be input to the PE control unit 2 via the predetermined wiring L1 as the cascade end signal CTS. Become.

  As described above, according to the processing unit of the first embodiment, for example, the memory read request and the acknowledge mechanism are implemented on the processor element (PE) side without providing a complex arbiter on the memory side. Instead, it becomes possible to perform predetermined processing.

  FIG. 8 is a diagram for explaining the selectors in the processor element shown in FIG. 7. FIG. 8 (a) shows the selector 13 paying attention to it, and FIG. 8 (b) shows the truth table of the selector 13. Show.

  As shown in FIG. 8 (a), the cascade command (A) via the cascade bus 5 and the common command (B) via the common bus 4 are input to the selector 13, and the cascade bit field CBF ( One is selected according to the value of S).

  Here, the cascade command (A), the common command (B) and the selection command (Y) are, for example, 33 bits ([32: 0]), and CBF is the most significant 1 bit (33 bits) [32]). Incidentally, this is merely an example, and it is needless to say that the configuration of the command may be variously changed.

  As shown in FIG. 8B, for example, when the cascade bit field (S) is "1", the selection command (Y [32: 0]) selected by the selector 13 is a cascade command (A [32]. : 0]). When the cascade bit field (S) is “0”, the selection command (Y [32: 0]) is a common command (B [32: 0]).

  FIG. 9 is a timing chart for explaining an example of the operation of the processing unit of the first embodiment, wherein 16 (PE0 to PE15) processor elements are used and the tree memory 32 and the image memory 31 are used. The waveform in the case of continuous memory access is shown. The memory is a general single port RAM.

  As apparent from the comparison between FIG. 9 and FIG. 5 described above, for example, although it takes 32 cycles to execute the read commands cmd1 and cmd2 to the image memory 31, the first embodiment According to, it can be seen that it is reduced to 17 cycles.

  That is, the command (instruction) cmd1 which is an access to the memory for tree 32 and the command cmd2 which is an access to the image memory are issued in a continuous cycle to the cascade bus 5 because they are accesses to different memories. be able to.

  As a result, although the end of the command cmd1 consumes 16 cycles as in the case of FIG. 5, the command cmd2 can substantially finish the processing in one cycle, and the execution time of the command is It can be seen that it can be shortened significantly.

  As for the read command for the tree memory 32 and the image memory 31, for example, CBF is set to “1” and stored in the program memory 22 of the PE control unit 2 in the operation of FIG. 9.

  Also, the fetch unit 21 of the PE control unit 2 sees the CBF and outputs these commands to the cascade bus 5. Here, it is assumed that the setting of CBF in the command is set in advance by a compiler or a programmer, but for example, logic for analyzing the command is added to the fetch unit 21 of the PE control unit 2 to automatically CBF may be added.

  Also, in the present embodiment, accesses to different memories (for example, the image memory 31 and the tree memory 32 in FIG. 6) can be issued as continuous cascade commands, which are for image and tree. It is not limited to two memories.

  Furthermore, accesses (instructions) that can be issued as continuous cascade commands are not limited to memory accesses, but, for example, are for common resources that can be accessed by multiple processor elements (1a to 1n). It may be.

  Here, the memory (image memory 31 and tree memory 32) is merely an example of a common resource. That is, as a common resource, for example, various things such as an operation unit including a multiplier which is expensive to be implemented in an input / output interface or individual processor elements are applicable.

  As described above, according to the first embodiment, for example, the number of instruction execution cycles is significantly reduced as compared to a method of performing arbitration for each memory access and waiting for access of all processor elements to be completed. It will be possible to

  That is, since the complicated arbitration circuit connected between the processor element and the memory becomes unnecessary and it is not necessary to wait for the next execution until the read access at the time of memory access is completed, Processing speed can be greatly improved. This effect is similarly exhibited in the second and third embodiments described below, and is also exhibited similarly in the access to common resources other than the memory.

  FIG. 10 is a block diagram showing an arithmetic processing unit according to the second embodiment, which corresponds to the case where one of the plurality of processor elements is terminated prematurely. As apparent from the comparison between FIG. 10 and FIG. 6 described above, in the second embodiment, the case where the terminal node NN is reached in the binary tree processing given to the second processor element 1b will be described as an example.

  That is, as shown in FIG. 10, for example, when the processor element 1 b reaches the terminal node NN, the given binary tree processing ends early. In the second embodiment, for the processing for which the determination result is determined early, the processor element 1b connected by the cascade bus 5 is skipped by setting the determination end flag, and the processing speed is further improved. It has become.

  As shown in FIG. 10, in the binary tree processing assigned to each of the PEs 1a to 1n, it is not always the case that the number of nodes is the same for all binary tree processing (binary tree). Furthermore, not all PEs 1a to 1n can be assigned binary trees to be processed.

  Therefore, for PEs for which the determination result was decided earlier (data processing has been completed) and PEs for which binary tree processing was not allocated (data processing is not required), the determination completion or invalid flag is set. , Skip their PE.

  That is, by skipping PEs for which data processing is unnecessary or completed from the plurality of PEs 1a to 1n connected in series by the cascade bus 5, the processing speed can be further improved.

  FIG. 11 is a block diagram showing an example of a processor element in the arithmetic processing unit shown in FIG. 10, and FIG. 12 is a diagram for explaining a selector in the processor element shown in FIG.

  Here, FIG. 12A shows the selector (second selector) 14 paying attention, and FIG. 12B shows a truth table of the selector 14. The selector (first selector) 13 is the same as that described with reference to FIGS. 7 and 8.

  As shown in FIGS. 11 and 12A, the selector 14 receives the output of the selector 13 and the output of the command buffer 11, selects one of them according to the output (CS0) of the OR gate 153, and outputs it. .

  Here, the processor core 12 does not operate when the invalidation flag is "1". Although it is assumed that setting / releasing of the invalidation flag is performed using a dedicated control signal not shown, for example, a dedicated logic circuit is added to the common bus 4 and an instruction for setting the invalidation flag is It is possible to set / cancel the invalid flag when issued.

  Also, the command buffer 11 replaces the cascade command with a NOP (No-OPeration) command when the determination end flag or the invalid flag is "1". Further, the setting of the determination end flag is performed from the processor core 12 using a command via the common bus 4 or the cascade bus 5. The determination end flag can be released from the processor core 12 using a command via the common bus 4.

  That is, the OR gate 153 takes the logical sum of the determination end flag (151) and the invalid flag (152), and outputs the control signal CS0 of "1" to the selector 14 when at least one becomes "1". Do.

  As shown in FIG. 12B, the selector 14 receives the control signal CS0 (S is “1”) of “1” from the OR gate 153, and the command (B [32: 0] selected by the selector 13 Choose).

  Then, the command (B [32: 0], the command of the cycle) selected by the selector 13 is serially connected through the cascade bus 5 as a selection command (Y [32: 0]) by the selector 14 (next Transferred to the (stage) processor element. At this time, the control signal CS0 of "1" from the OR gate 153 is also input to the command buffer 11, and the above-mentioned replacement process with the NOP command is performed.

  Specifically, as shown in FIG. 10, for example, when the binary tree processing by the PE 1b ends early, the determination end flag (151) is set (set to “1”) to allow the OR gate 153 to The control signal CS0 to be output becomes "1".

  Thereby, the command (B [32: 0]) of the cycle selected by the selector 13 is transmitted to PE1 c next to PE1 b as a selection command (Y [32: 0]), and the command by the cascade bus 5 is It is possible to reduce the transmission time of

  Also, for example, when binary tree processing is not assigned to PE 1 b, the invalidation flag (152) is set (set to “1”), whereby the control signal CS0 output from the OR gate 153 is “1”. "become.

  Thereby, the command (B [32: 0], the command of the cycle) selected by the selector 13 is transmitted to PE1 c next to PE1 b as a selection command (Y [32: 0]), and the cascade bus 5 It becomes possible to shorten the transmission time of the command.

  When the determination completion flag (151) and the invalid flag (152) are not set and the control signal CS0 output from the OR gate 153 is “0”, the selector 14 outputs the command buffer 11 (A [32: 0]. ] Is selected, and the same processing as in the first embodiment described above is performed.

  That is, as shown in FIG. 12 (b), the selector 14 receives the control signal CS 0 (S is “0”) of “0” from the OR gate 153, and the command (A [32 : 0]) is selected.

  Then, a processor in which a command (A [32: 0], a command of the previous cycle) output from the command buffer 11 is serially connected through the cascade bus 5 as a selection command (Y [32: 0]) by the selector 14 It is transmitted to the element. That is, when the control signal CS0 is "0", processing similar to that of the first embodiment is performed.

  FIG. 13 is a timing chart for explaining an example of the operation of the arithmetic processing unit of the second embodiment, which is for explaining the case where the processor element PE1 has already finished the determination processing. The reference code cmd1 indicates an access command to the tree memory 32, and cmd2 indicates an access command to the image memory 31. Also, the memory is a general single-port RAM.

  As apparent from the comparison between FIG. 13 and FIG. 9 described above, according to the second embodiment, the control signal CS0 of the selector (second selector) 14 is “1” in PE1 which has finished the determination process. "become.

  Therefore, the command (B [32: 0]) selected by the selector (first selector) 13 is output from the second selector 14 as the selection command (Y [32: 0]), and the next through PE1. It is transmitted to PE2 of the stage.

  That is, since the determination end flag is set (S is "1"), the command (cmd1, cmd2) received from PE0 through the cascade bus 5 is not buffered by the command buffer 11, and PE1 is passed through. And it is transmitted to PE2.

  That is, PE2 originally receives a command in a cycle in which PE1 receives a command (when the determination processing of PE1 has not ended), and therefore PE3 to PE15 also receive a command one cycle earlier than the case shown in FIG. Will be processed.

  This makes it possible to reduce the process required for 17 cycles in the first embodiment described with reference to FIG. 9 by 1 cycle and skip to 16 cycles by skipping PE1. It goes without saying that the effect of shortening the processing cycle becomes more pronounced, for example, as the number of processor elements for which the determination processing has been completed or which is invalidated is larger.

  FIG. 14 is a block diagram showing an arithmetic processing unit according to a third embodiment, in which execution cycles are further shortened by operating a plurality of processor elements in parallel using paths capable of independent operation. is there.

  Specifically, for example, when processing the respective images by two cameras provided on the left and right, the image memory 3 becomes two independent image memories 311 and 312. Here, the image memories 311 and 312 can be identified, for example, by the most significant bit (MSB) of the address (RAM address).

  In FIG. 14, for example, the MSB of the RAM address is already set in the route selector register 16 shown in FIG. 15, and the image memory to which each PE accesses is already designated.

  That is, in FIG. 14, the first-stage PE 1a accesses the first image memory 311, reads two data (data to be compared), performs comparison (determination) processing, and the second-stage PE 1b performs the second image memory A case where access is made to 312 and two data are read and comparison processing is performed is shown.

  In the third embodiment described below, although two independent image memories 311 and 312 are taken as an example, the number of image memories is not limited to two. For example, in the case of application to four independent image memories, the upper two bits of the RAM address can be used to designate an image memory to be accessed by each PE.

  Furthermore, the image memory is merely an example of a common resource, and it is not limited to the memory as long as it is a common resource that can be accessed simultaneously by a plurality of processor elements. That is, the common resource may be, for example, various elements such as an arithmetic unit including a multiplier which is expensive to be implemented in an input / output interface or an individual processor element. The third embodiment can also be applied to the plurality of independent computing units and the like.

  As shown in FIG. 14, in the processing unit of the third embodiment, two cascade buses connecting the PE control unit 2 and the PEs 1a to 1n are the same as the number of independent image memories 311 and 312 (51 , 52) provided.

  Further, from each of the PEs 1a to 1n, buses 19a to 19n for accessing the tree memory 32 and buses for accessing the two image memories 311 and 312 are provided independently.

  However, as described above, FIG. 14 shows that the PE 1a reads two data from the first image memory 311 already designated via the bus 181a, and the PE 1b for the second image already designated via the bus 181b. It shows that two pieces of data are read from the memory 312 and comparison processing is performed.

  Each of the PEs 1a to 1n is assigned for each data processing (for example, for each image) stored as tree information, and the PEs 1a to 1n are independently connected by selecting a cascade connection (cascade bus) with which paths can be operated. The processing time is reduced by operating 1 to 1 n in parallel.

  As shown in FIG. 14, when there are two image memories (311, 312) that can be accessed independently, for example, the upper first bit (most significant bit: MSB: Most Significant Bit) of the RAM address It can be used to select the image memories 311 and 312.

  That is, each of the PEs 1a to 1n can identify whether the RAM to be accessed is the first image memory 311 or the second image memory 312 based on the MSB of the RAM address.

  At this time, associated two cascade buses 51 and 52 are provided for two image memories (RAMs) 311 and 312 to be accessed. Note that selecting the first and second image memories 311 and 312 using the MSB of the RAM address is merely an example, and the present invention is not limited to this.

  Here, when the MSB (CS1) of the RAM address is “0”, the even-numbered PEs 1a, 1c,... (PE0, PE2,..., PE14) are selected by the first cascade command transmitted through the first cascade bus 51. It is assumed that one image memory 311 is accessed.

  In addition, when CS1 is “1”, odd-numbered PEs 1b, 1d,... (PE1, PE3,..., PE15) access the second image memory 312 by the second cascade command transmitted through the second cascade bus 52. It shall be.

  Each of the PEs 1a to 1n (PE0 to PE15) executes only a command (instruction) from the cascade bus 51 or 52 corresponding to the image memory 311 or 312 accessed by itself. Then, commands from other cascade buses are passed through as they are without buffering by the command buffer 11, and are transmitted to PEs connected in series (next stage).

  In addition, although an access command to the memory for tree 32 may be transmitted through the first cascade bus 51 or the second cascade bus 52, a third cascade bus different from the first and second cascade buses is provided, and the third It can also be transmitted through the cascade bus.

  In FIG. 14, a route selection bit field for selecting one route of the cascade bus separately from CBF in the instruction (cascade command) sent from the PE control unit 2 through the first and second cascade buses 51 and 52. (RSBF) is set.

  An example of the instruction format of the cascade command is shown in Table 2 below. Here, the instruction length is 34 bits, and the most significant bit is assigned to RSBF (Route Select Bit Field: route selection information). The lower 33 bits are the same as in Table 1 described above, the upper 2 bits are assigned to CBF (instruction type information), and the lower 32 bits from the upper 3 bits are used as an instruction field for a normal 32-bit processor. There is.

Here, for example, when the RSBF is set to “1”, the CBF is also set to “1”.

  The RSBF can be incorporated into commands in a soft manner by, for example, a programmer who creates a program or a compiler which converts the source code of a program written in a programming language.

  Alternatively, it is also possible to add an RSBF automatically in the conduit by adding a logic circuit for analyzing an instruction (command) and a memory access destination to the fetch unit 21 of the PE control unit 2.

  In the case of access to the tree memory 32, for example, RSBF is "0" and CBF is "1". At this time, in the third embodiment, commands are fetched from the first cascade bus 51. Do.

  FIG. 15 is a block diagram showing an example of a processor element in the arithmetic processing unit shown in FIG. 14. FIGS. 16 and 17 are diagrams for explaining selectors in the processor element shown in FIG.

  Here, FIG. 16 is shown paying attention to two selectors (the first selector 13 and the second selector 14), and FIG. 17 (a) shows a truth table of the first selector 13, and FIG. 17 (b) Shows a truth table of the second selector 14. In addition, in FIG. 17A and FIG. 17B, the symbol “x” indicates “don't care” that may not be taken into consideration.

  As shown in FIG. 15, each PE 1 (1 a to 1 n) includes a route selector register 16. The root selector register 16 holds, for example, the most significant bit (MSB of the RAM address) of the address for accessing the image memory (311, 312), and selects the cascade bus 51, 52 (control signal (route select signal) ) Output CS1 to selectors 13 and 14.

  That is, each PE 1 (1 a to 1 n) sets the MSB (CS 1) of the RAM address in the route selector register 16 before the cycle of executing the access to the image memory (311, 312).

  Further, as shown in FIGS. 15 and 16, the first selector 13 receives the first cascade command (A) via the first cascade bus 51 and the second cascade command via the second cascade bus 52. (B) is input.

  Here, as described with reference to Table 2, the most significant bit MSB of each cascade command (for example, 34 bits) is used as route selection information (RSBF), and the upper second bit is the instruction type information ( Used as CBF).

  That is, RSBF and CBF of the first cascade command are input as S1 and S2 of the first selector 13, and RSBF and CBF of the second cascade command are input as S3 and S4 of the first selector 13. The common command via the common bus 4 is input as C of the first selector 13.

  The first and second cascade buses 51 and 52 output from the PE control unit 2 are connected as they are to the processor element 1a of the first stage. A common command is issued from the PE control unit 2 to the first and second cascade buses 51 and 52. Here, the first selector 13 selects one of the first and second cascade commands and the common command based on S0 to S4.

  Specifically, as shown in FIG. 17A, when the first cascade command (A) satisfies S1 = S2 = “1” and S0 = “1”, as shown in FIG. 1) Select a cascade command (A) as Y and output it to the command buffer 11.

  When the second cascade command (B) matches S3 = S4 = “1” and S0 = “0”, the first selector 13 selects the second cascade command (B) as Y, and the command Output to buffer 11.

  Furthermore, the first selector 13 selects the common command (C) from the common bus 4 when S2 = “0” of the first cascade command (A) and S4 = “0” of the second cascade command (B). It is selected as Y and output to the command buffer 11.

  Then, as shown in FIG. 17B, in the second selector 14, both RSBF and CBF are “1” (S1 = S2 = “1”, S3 = S4 = “1”), and S0 (S1 = S2 = “1”). Cascade commands A and B which do not match CS1) are transmitted to the PE of the next stage as they are as Y1 and Y0.

  That is, when the cascade command (B) of S3 = S4 = “1” is input to the second cascade bus 52 when S0 is “1”, the cascade command (B) is input to the next stage. Output (Y0) as it is to the second cascade bus 52 of PE.

  When the cascade command (A) of S1 = S2 = “1” is input to the first cascade bus 51 when S0 is “0”, the cascade command (A) is input to the next stage. Output (Y1) to the first cascade bus 51 of the PE of FIG.

  In other cases, the output (C) from the command buffer 11 is output (Y1, Y0) as it is to the first and second cascade buses 51, 52 of the next-stage PE.

  FIG. 18 is a timing chart for explaining an example of the operation of the processing unit of the third embodiment, and two paths (first and second cascade buses 51 and 52) capable of independent operation are used. It shows how the independent image memories 311 and 312 are accessed.

  18, even-numbered processor elements (PE0, PE2,..., PE14) are, for example, memory for the first image for the first address of the RAM address “0” by the first cascade command transmitted through the first cascade bus 51. Suppose that 311 is accessed.

  In addition, odd-numbered processor elements (PE1, PE3,..., PE15) are controlled, for example, by the second cascade command transmitted through the second cascade bus 52 to store the first image memory 312 whose MSB of the RAM address is "1". It shall be accessed.

  As a result, as shown in FIG. 18, PEs accessing the same image memory form a group using the same cascade bus, and processing can be performed simultaneously with access to groups belonging to different cascade buses. Further shortening is possible.

  The number of independent image memories is not limited to two, and is not limited to image memories as long as it is a common resource that multiple PEs can simultaneously access, as described above. is there.

  FIG. 19 is a block diagram showing an example of a semiconductor integrated circuit to which the arithmetic processing unit of the present embodiment is applied, and schematically showing an SoC (System On a Chip) for digital cameras. As shown in FIG. 19, a SoC (semiconductor integrated circuit) 200 includes a SIMD block 201, an embedded memory 202, a memory IF (interface) 203, an image sensor IF 204, an image processing unit 205, a CPU 206, and a bus matrix 207.

  Here, the SIMD block 201, the built-in memory 202, the memory IF 203, the image sensor IF 204, the image processing unit 205, and the CPU 206 are mutually connected by a bus matrix 207. The image sensor IF 204 receives, for example, a signal obtained by converting an image by an optical system such as a lens provided outside into an electrical signal by the image sensor. The arithmetic processing unit of each of the embodiments described above corresponds to the SIMD block 201.

  That is, the PE control unit 2 in the SIMD block 201 shown in FIG. 19 is controlled, for example, by an instruction from the CPU 206. Also, the image memory 31 (311, 312) and the tree memory 32 in the SIMD block 201 are, for example, from the built-in memory 202 that stores data fetched from an external large capacity memory (not shown) via the memory IF 203. It will read data.

  In the above, the application of the arithmetic processing unit of the present embodiment is not limited to the SoC that performs image processing, and it can be widely applied as a semiconductor integrated circuit used for various electronic devices. Absent.

  Although the embodiments have been described above, all the examples and conditions described herein are for the purpose of assisting the understanding of the concept of the invention applied to the invention and the technology, and the examples and conditions described are particularly It is not intended to limit the scope of the invention. Also, such descriptions in the specification do not show the advantages and disadvantages of the invention. While the embodiments of the invention have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the invention.

Further, the following appendices will be disclosed regarding the embodiment including the above-described example.
(Supplementary Note 1)
An arithmetic processing unit including a plurality of processor elements that can simultaneously access a common resource,
A first bus connected in parallel to the plurality of processor elements and providing a common first instruction to each of the processor elements;
A second instruction, which is serially connected to the plurality of processor elements, and which is given to the first processor element in the first cycle in the plurality of processor elements, is said first in the second cycle following the first cycle. And a second bus for communicating to a second processor element serially connected to the processor element.
Arithmetic processing apparatus characterized in that.

(Supplementary Note 2)
Each said processor element is
A processor core that executes instructions,
A first selector for selecting one of the first bus and the second bus according to instruction type information indicating one of the first instruction and the second instruction;
The arithmetic processing unit according to appendix 1, characterized in that:

(Supplementary Note 3)
The first instruction and the second instruction include bit fields of the instruction type information indicating whether each instruction is a first instruction or a second instruction,
The first selector is
When the bit field of the instruction type information indicates the second instruction, the second bus is selected to output the second instruction;
When the bit field of the instruction type information indicates the first instruction, the first bus is selected to output the first instruction.
The arithmetic processing unit according to appendix 2, characterized in that

(Supplementary Note 4)
Each said processor element is further
A command buffer for holding an instruction selected by the first selector;
The arithmetic processing unit according to appendix 2 or appendix 3, characterized in that

(Supplementary Note 5)
The first processor element is
In the first cycle, the instruction selected by the first selector is held in the command buffer,
The second cycle transmits the instruction held in the command buffer to the second processor element through the second bus.
The arithmetic processing unit according to appendix 4, characterized in that

(Supplementary Note 6)
Each said processor element is further
And a second selector that selects one of the instruction selected by the first selector and the instruction held in the command buffer.
The arithmetic processing unit according to appendix 4, characterized in that

(Appendix 7)
When the first processor element does not need or complete data processing by the first processor element,
The second selector selects the instruction selected by the first selector by skipping the first processor element, and transmits the selected instruction to the second processor element.
The arithmetic processing unit according to appendix 6, characterized in that

(Supplementary Note 8)
The common resource includes a plurality of common resources that can operate independently,
The second bus includes a plurality of second buses corresponding in number to the plurality of common resources.
The arithmetic processing unit according to Supplementary Note 6 or 7, characterized in that

(Appendix 9)
Each said processor element is further
Among the plurality of common resources, including a route selector register specifying a common resource accessed by its own processor element
The arithmetic processing unit according to appendix 8, characterized in that

(Supplementary Note 10)
The second instruction includes a bit field of route selection information that selects through which route on the plurality of second buses that instruction is transmitted.
The arithmetic processing unit according to appendix 9, characterized in that

(Supplementary Note 11)
The arithmetic processing unit is a SIMD type arithmetic processing unit,
The common resource is memory,
The arithmetic processing unit according to any one of Appendixes 1 to 10, which is characterized in that:

(Supplementary Note 12)
The memory includes an image memory for storing image data, and a tree memory for storing node information used when executing a binary tree search on the image data.
The first instruction accesses the tree memory,
The second instruction accesses the image memory.
The arithmetic processing unit according to appendix 11, characterized in that

(Supplementary Note 13)
The plurality of processor elements simultaneously perform parallel data processing by accessing the tree memory by the first instruction and accessing the image memory by the second instruction.
The arithmetic processing unit according to appendix 12, characterized in that

(Supplementary Note 14)
An arithmetic processing unit according to any one of Appendixes 1 to 13
A semiconductor integrated circuit characterized by

(Supplementary Note 15)
A control method of an arithmetic processing unit including a plurality of processor elements simultaneously accessible to a common resource, the control method comprising:
Providing a common first instruction to each of the processor elements through a first bus connected in parallel to the plurality of processor elements;
The second instruction given to the first processor element in the first cycle in the plurality of processor elements through the second bus serially connected to the plurality of processor elements is the second following the first cycle Transferring to a second processor element serially connected to the first processor element in a cycle
A control method of an arithmetic processing unit characterized in that.

1, 1a-1n, PE0-PE15 Processor Element (PE)
2, 102 PE control unit 4, 104 common command bus (common bus: first bus)
5, 51, 52 Cascade bus (second bus)
11, 111 command buffer 12 processor core 13 selector (first selector)
14 second selector 16 root selector register 21, 121 fetch unit 22, 122 program memory 31, 311, 312 image memory 32, 103 tree memory
106 Arbiter

Claims (11)

An arithmetic processing unit including a plurality of processor elements that can simultaneously access a common resource,
A first bus connected in parallel to the plurality of processor elements and providing a common first instruction to each of the processor elements;
A second instruction, which is serially connected to the plurality of processor elements, and which is given to the first processor element in the first cycle in the plurality of processor elements, is said first in the second cycle following the first cycle. And a second bus for communicating to a second processor element serially connected to the processor element.
Arithmetic processing apparatus characterized in that. Each said processor element is
A processor core that executes instructions,
A first selector for selecting one of the first bus and the second bus according to instruction type information indicating one of the first instruction and the second instruction;
The arithmetic processing unit according to claim 1, characterized in that: The first instruction and the second instruction include bit fields of the instruction type information indicating whether each instruction is a first instruction or a second instruction,
The first selector is
When the bit field of the instruction type information indicates the second instruction, the second bus is selected to output the second instruction;
When the bit field of the instruction type information indicates the first instruction, the first bus is selected to output the first instruction.
The arithmetic processing unit according to claim 2, characterized in that: Each said processor element is further
A command buffer for holding an instruction selected by the first selector;
The arithmetic processing unit according to claim 2 or 3 characterized by things. The first processor element is
In the first cycle, the instruction selected by the first selector is held in the command buffer,
The second cycle transmits the instruction held in the command buffer to the second processor element through the second bus.
The arithmetic processing unit according to claim 4, characterized in that: Each said processor element is further
And a second selector that selects one of the instruction selected by the first selector and the instruction held in the command buffer.
The arithmetic processing unit according to claim 4, characterized in that: When the first processor element does not need or complete data processing by the first processor element,
The second selector selects the instruction selected by the first selector by skipping the first processor element, and transmits the selected instruction to the second processor element.
The arithmetic processing unit according to claim 6, characterized in that: The common resource includes a plurality of common resources that can operate independently,
The second bus includes a plurality of second buses corresponding in number to the plurality of common resources.
The arithmetic processing unit according to claim 6 or 7 characterized by things. Each said processor element is further
Among the plurality of common resources, including a route selector register specifying a common resource accessed by its own processor element
The arithmetic processing unit according to claim 8, characterized in that: The second instruction includes a bit field (RSBF) of route selection information which selects through which route in the plurality of second buses that instruction of its own is transmitted.
The arithmetic processing unit according to claim 9, characterized in that: A control method of an arithmetic processing unit including a plurality of processor elements simultaneously accessible to a common resource, the control method comprising:
Providing a common first instruction to each of the processor elements through a first bus connected in parallel to the plurality of processor elements;
The second instruction given to the first processor element in the first cycle in the plurality of processor elements through the second bus serially connected to the plurality of processor elements is the second following the first cycle Transferring to a second processor element serially connected to the first processor element in a cycle
A control method of an arithmetic processing unit characterized in that.

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