JP6467871B2 - Circuit device and electronic device - Google Patents

Description

  The present invention relates to a circuit device, an electronic device, and the like.

The printer controls a plurality of motors to perform paper feeding and head feeding. For example, when paper feeding is assumed, the paper is moved by the motor, and the position information is fed back to the control unit of the motor by the position detection sensor (encoder). Then, the motor is controlled based on the fed back information.

At this time, the control unit generates a motor control signal to control the motor. For example, a reset signal may be erroneously input to the control unit due to noise or the like. If a reset signal is erroneously input to the control unit, the control unit cannot correctly generate a motor control signal, and the motor cannot be normally controlled.

For this reason, conventionally, measures have been taken such as taking a sufficient substrate potential inside the IC and providing a dead time at the on-off timing of the pre-driver in order to reduce the short-circuit current. In addition, the voltage-sensitive detection circuit and the circuit that receives the output are sensitive to noise, such as away from the noise source as much as possible, or surrounded by a guard ring, etc.
It was less affected by noise.

In addition, there are conventional techniques described in Patent Document 1 and Patent Document 2 as inventions related to noise removal. For example, Patent Document 1 discloses a noise cancellation circuit having both a delay circuit using an inverter and a shift register.
This is for noise characteristics that vary depending on the use conditions. Patent Document 2 discloses an invention in which a noise cancellation circuit is configured in a two-stage series connection.

JP 2011-66547 A JP 2009-55470 A

In the prior art, a circuit configuration that makes it difficult for noise to occur has been adopted. However, when noise actually occurs, the control unit of the motor and the motor have malfunctioned without being able to cope with it.

In addition, in the prior art, the area occupied by the circuit was increased by increasing the distance between the noise source and the noise sensitive part, or surrounding the noise source with a guard ring.
The effect is small, and there is a limit to increasing the distance and area in consideration of the effect and cost.

According to some embodiments of the present invention, it is possible to provide a circuit device, an electronic device, and the like that can reduce malfunction due to noise while suppressing an increase in circuit scale.

According to one embodiment of the present invention, a bridge circuit including a high-side transistor and a low-side transistor, and an on / off control of the high-side transistor and the low-side transistor are performed to flow through the bridge circuit. A control unit that switches between a charge period for increasing current and a decay period for decreasing the current, a signal generation unit that generates an input signal input to the control unit based on an analog signal, the charge period, and the A storage unit that stores delay time information corresponding to a noise width of the analog signal when the decay period is switched; and a noise cancellation circuit that performs noise cancellation on the input signal based on the delay time information. Related to the circuit device including.

In one embodiment of the present invention, a noise cancellation circuit is provided, and the noise cancellation circuit is input to the control unit based on delay time information corresponding to the noise width of the analog signal when the charge period and the decay period are switched. Noise cancellation is performed for digital input signals. Therefore, it is possible to reduce malfunction due to noise while suppressing an increase in circuit scale.

One embodiment of the present invention may include a noise detection circuit that detects the noise width when the charge period and the decay period are switched.

This makes it possible to set a delay value in the noise cancellation circuit so that noise generated at the time of mode switching can be canceled.

One embodiment of the present invention may include a noise detection circuit that detects the noise width of the analog signal when power is turned on.

This makes it possible to set a delay value in the noise cancellation circuit so that noise generated when the power is turned on can be canceled.

In the aspect of the invention, the storage unit stores first delay time information and second delay time information, and the noise cancellation circuit performs the second delay before detecting the noise width. The noise cancellation may be performed based on the delay time information, and after the noise width is detected, the noise cancellation may be performed based on the first delay time information.

As a result, it becomes unnecessary to set a long delay value unnecessarily, and detection of a normally output signal can be accelerated.

In the aspect of the invention, the first delay time information may be the delay time information corresponding to the noise width.

Thereby, after detecting the noise width, it becomes possible to set a delay value based on the delay time information corresponding to the noise width.

In the aspect of the invention, the second delay time information may be the delay time information corresponding to a maximum delay time that can be set in the noise cancellation circuit.

Accordingly, it is possible to set a maximum delay value that can be set before detecting the noise width so that the correct noise width can be detected.

In the aspect of the invention, the input signal may be a digital reset signal input to the control unit.

Thereby, it becomes possible to reset the drive of the control unit (to an inactive state) or to make it active.

In the aspect of the invention, the analog signal may be an output signal of a voltage drop detection circuit that detects a drop in voltage input to the control unit.

Thus, when the signal generation unit determines that the voltage input to the control unit has decreased based on the analog signal, it is possible to output a reset signal to the control unit.

In the aspect of the invention, the signal generation unit includes a comparator, and the comparator has a voltage of the analog signal input to the first input terminal and a reference voltage input to the second input terminal. And the input signal may be output.

Accordingly, the signal generation unit resets the drive of the control unit (inactive state) when the voltage of the analog signal input to the first input terminal is smaller than the reference voltage input to the second input terminal. An inactive level input signal can be output.

In one embodiment of the present invention, the noise cancellation circuit includes N pieces (N
Is an integer greater than or equal to 2), a NAND circuit, an OR circuit, and a flip-flop circuit, and the first shift register circuit among the N shift register circuits receives the input Based on the input signal, clock signal, and external reset signal,
A first shift output signal obtained by shifting the input signal is output, and an i-th (i is an integer of 2 ≦ i ≦ N) shift register circuit among the N shift register circuits is input (i
-1) i-th shift output obtained by shifting the (i-1) -th shift output signal based on the (i-1) -th shift output signal from the shift register circuit, the clock signal, and the external reset signal The NAND circuit outputs the input signal and the first signal
A NAND signal is output based on the shift output signal to the Nth shift output signal, and the OR circuit is based on the input signal that is input and the first shift output signal to the Nth shift output signal. An OR signal may be output, and the flip-flop circuit may output a reset signal of the control unit based on the input NAND signal and the OR signal.

This makes it possible to cancel noise having a noise width corresponding to the number of clocks shorter than the number of shift register circuits.

In one embodiment of the present invention, the noise cancellation circuit outputs the N shift output signals from the N shift register circuits to the flip-flop circuit based on the detected noise width. The shift output signal used to determine the NAND signal and the OR signal may be selected.

As a result, it is possible to cancel noise that may occur and to suppress detection delay of a signal that does not carry noise.

In one embodiment of the present invention, the noise cancellation circuit includes N pieces (N
Is an integer greater than or equal to 2), N shift circuits, N NAND circuits, N OR circuits, a first selector section, a second selector section, and a flip-flop circuit,
A first shift register circuit among the shift register circuits is a first shift register circuit that shifts the input signal based on the input signal, a clock signal, and an external reset signal.
A shift output signal is output, and the k-th of the N shift register circuits (k is 2 ≦ k
≦ N integer) The shift register circuit is based on the input (k−1) th shift output signal from the (k−1) th shift register circuit, the clock signal, and the external reset signal. A k-th shift output signal obtained by shifting the (k−1) -th shift output signal is output, and the first NAND circuit among the N NAND circuits receives the input signal and the first shift output signal. And outputting a first NAND signal to the first selector unit,
The kth NAND circuit among the N NAND circuits receives the kth NAND signal based on the input signal and the first shift output signal to the kth shift output signal. The first OR circuit out of the N OR circuits outputs the first OR signal to the second selector based on the input signal and the first shift output signal. A k-th OR circuit among the N OR circuits, wherein the k-th OR circuit is based on the input signal and the first to k-th shift output signals. A signal is output to the second selector unit, and the first selector unit selects one of the input first NAND signal to Nth NAND signal based on the detected noise width. N
An AND signal is selected and output to the flip-flop circuit, and the second selector unit includes:
Based on the detected noise width, one of the input OR signals to the N-th OR signal is selected and output to the flip-flop circuit, and the flip-flop The circuit may output a reset signal of the control unit based on the input NAND signal and the OR signal.

This makes it possible to select a shift register circuit to be used from a plurality of shift register circuits according to the noise width.

In one embodiment of the present invention, the number of the noise cancellation circuits is M (M
Is an integer greater than or equal to 2) cancellation block, decoder unit, and selector unit,
The first cancellation block among the M cancellation blocks includes a first delay circuit that outputs a first delay signal based on the input signal that is input, and the input signal and the first delay signal that are input. A first NAND that outputs a first NAND signal based on
A jth (j is an integer of 2 ≦ j ≦ M) cancellation block among the M cancellation blocks, based on the input (j−1) delay signal, A decoder having a j-th delay circuit for outputting a j-th delay signal; and a j-th NAND circuit for outputting a j-th NAND signal based on the input signal and the j-th delay signal. The unit outputs a decode signal based on the input first NAND signal to the Mth NAND signal, and the selector unit inputs the first NAND signal to the Mth NAND signal. And a reset signal of the control unit may be output based on the decode signal.

As a result, it becomes possible to set an appropriate delay value and cancel noise.

  Another aspect of the present invention relates to an electronic apparatus including the circuit device.

The system configuration example of this embodiment. 2A and 2B are explanatory diagrams of connection positions of the noise cancellation circuit. 2 is a detailed system configuration example of the present embodiment. 4A to 4C are explanatory diagrams of a charge period and a decay period. The timing chart explaining the charge and decay repetitive operation. The timing chart explaining the detailed operation | movement at the time of mode switching. Explanatory drawing of the noise generation timing at the time of mode switching. 6 is a configuration example of a noise cancellation circuit having a two-stage shift register circuit. The timing chart explaining the detailed operation | movement at the time of noise cancellation. Explanatory drawing of the truth table of a flip-flop circuit. 6 is a configuration example of a noise cancellation circuit having an 8-stage shift register circuit. Configuration example of an analog noise cancellation circuit. An example of the configuration of a noise cancellation circuit capable of adjusting the delay value. Explanatory drawing of the relationship between the test | inspection timing by a voltage detection circuit, and noise. An example of the configuration of a noise cancellation circuit capable of adjusting the delay value. 16A to 16D are explanatory diagrams of simulation results of noise cancellation. Configuration example of an electronic device.

Hereinafter, this embodiment will be described. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. In addition, all the configurations described in the present embodiment are not necessarily essential configuration requirements of the present invention.

1. Overview As described above, in a device using a motor such as a printer, a control unit (motor driver IC) generates a motor control signal to control the motor. However, at this time, for example, if a reset signal is erroneously input to the control unit due to noise or the like, there is a problem that the control unit cannot control the motor normally.

Therefore, in this embodiment, for example, for a malfunction in which the control unit malfunctions due to noise included in the output of the voltage drop detection circuit, a noise cancellation circuit is inserted between the voltage drop detection circuit and the circuit that receives the output. To prevent malfunction.

Specifically, FIG. 1 shows a configuration example of the circuit device 100 of the present embodiment. The circuit device 100 according to this embodiment performs on / off control of a bridge circuit 210 having a high-side transistor and a low-side transistor, and a high-side transistor and a low-side transistor, and A control unit 240 that switches between a charge period for increasing the flowing current and a decay period for decreasing the current, a signal generation unit 110 that generates a digital input signal input to the control unit 240 based on an analog signal, and a charge A storage unit 120 that stores delay time information corresponding to the noise width of the analog signal when the period and the decay period are switched; a noise cancellation circuit 130 that performs noise cancellation on the input signal based on the delay time information; including.

For example, as illustrated in FIG. 1, the circuit device 100 is a circuit (motor driver) that drives the motor 280, and drives the motor 280 by a current flowing through the bridge circuit 210. However, the circuit device 100 is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of these components or adding other components are possible.

In the present embodiment, for example, a voltage drop detection circuit (not shown) is connected to the signal generation unit 110, and the signal generation unit 110 is connected to the control unit 240 based on an output signal (analog signal) from the voltage drop detection circuit. A reset signal (input signal) that resets the operation is output. More specifically, if the output signal of the voltage drop detection circuit indicates a voltage drop, an H (High) level reset signal that resets (inactivates) the operation of the control unit 240 is output and the voltage drop occurs. If the output signal of the detection circuit indicates that the voltage has not dropped, an L (Low) level reset signal that activates the operation of the control unit 240 is output. At this time, if no measures are taken against noise included in the output signal (analog signal) from the voltage drop detection circuit, it is erroneously determined that the output signal indicates a voltage drop due to the noise. In some cases, the signal generation unit 110 may output an H level reset signal to erroneously reset the operation of the control unit 240.

As shown in FIG. 2A, the other circuit device does not include a noise cancellation circuit between the signal generation unit and the control unit (the flip-flop circuit FF in the control unit). As shown in FIG. 2B, 100 includes a noise cancellation circuit 130 between the signal generation unit 110 and the control unit 240 (a flip-flop circuit FF in the control unit).

When the circuit device 100 includes the noise cancellation circuit 130 between the signal generation unit 110 and the control unit 240 as in the present embodiment, the delay required for the noise cancellation circuit 130 to detect noise included in the input signal. The operation start time of the detection circuit 220 (described in FIG. 3 described later) for detecting the current flowing through the bridge circuit 210 is delayed by the time. Therefore, in the present embodiment, the delay value used in the noise cancellation circuit 130 is set to a value corresponding to the period corresponding to the actual noise width, so that the current detection start timing in the detection circuit 220 is advanced as much as possible.

Specifically, the circuit device 100 further includes a noise detection circuit 140. The noise detection circuit 140 detects the noise width at the switching timing of the first charge period and the decay period after the power is turned on, and after the power is turned on. Select the delay value corresponding to the noise width at the first switching. Specifically, the selection of the delay value is performed by connecting a plurality of delay circuits (shift register circuits) in series and examining the presence or absence of noise at the connection point. Then, the optimum delay value setting data is stored in the storage unit 120 (register), and thereafter, the noise cancellation circuit 130 outputs an input signal based on the stored delay value setting data. Thereby, the start timing of current detection can be advanced as much as possible.

As described above, in the present embodiment, not only noise is hardly generated, but also noise can be canceled even when noise is generated. At this time, it is not necessary to increase the distance between the noise-sensitive part and the noise generation source, or to surround with a guard ring, so that an increase in circuit scale can be suppressed.

Therefore, according to the present embodiment, it is possible to reduce malfunction due to noise while suppressing an increase in circuit scale. That is, the noise of the input signal input to the control unit 240 can be canceled. As a result, it is possible to prevent malfunction of the control unit 240 to which an input signal is input. Also, by setting the delay value, you can cancel noise optimally and reliably.
A stable operation of the control unit 240 can be maintained. Furthermore, since it is not necessary to provide a dead time at the on-off timing of the pre-driver 260 described later, the responsiveness of the motor control can be improved.

Further, as described above, Patent Document 1 discloses a noise cancellation circuit having both a delay circuit using an inverter and a shift register. This is for noise characteristics that differ depending on the use conditions, but two types of delay circuits complement each other, and the delay value is not adjusted by the noise width itself as in this embodiment. Patent Document 2 described above discloses an invention in which the noise cancellation circuit 130 has a two-stage series connection configuration. Unlike this embodiment, this also does not adjust the delay value of the cancel circuit by the noise width.

2. System Configuration Example Next, FIG. 3 shows a detailed configuration example of the circuit device 100 of the present embodiment. The circuit device 100 according to the present embodiment includes a bridge circuit 210 that supplies a drive current to a motor 280 (for example, a DC motor or a stepping motor), a control unit 240 that outputs a PWM signal to the bridge circuit 210, and buffering the PWM signal. The pre-driver 260, the detection circuit 220 for detecting the charge current, the clock generation circuit 270, the register unit 250, the signal generation unit 110, the storage unit 120, the noise cancellation circuit 130, and the noise detection circuit 140. And including. However, the circuit device 100 is not limited to the configuration of FIG. 3, and various modifications such as omitting some of these components or adding other components are possible.

The circuit device 100 is composed of, for example, an IC chip (integrated circuit device), and the circuit device 1
The 00 terminal corresponds to the IC chip package terminal or the pad on the silicon substrate. The IC chip constituting the circuit device 100 is mounted on a printed board. The sense resistor 290 is mounted on the printed board as a circuit component.

The bridge circuit 210 includes high-side transistors TR1 and TR2 and low-side transistors TR3 and TR4. The transistors TR1 to TR4 are CMOS transistors configured in an H bridge. High-side transistor TR
1, TR2 is, for example, a P-type transistor, and a low-side transistor TR3
, TR4 is connected to a higher potential power supply side than TR4. Low side transistors TR3, TR
4 is, for example, an N-type transistor, and high-side transistors TR1 and TR2
It is connected to the lower potential power supply side.

Specifically, the source nodes of the high-side transistors TR1 and TR2 are connected to the node of the power supply voltage VCC, and the source nodes of the low-side transistors TR3 and TR4 are connected to the node N1 connected to the terminal RNF. . The terminal RNF has a sense resistor 2
One end of 90 is connected. The other end of the sense resistor 290 is connected to a ground voltage node. The drain nodes of the transistors TR1 and TR3 are connected to a terminal OUT1 to which one end of the motor 280 is connected. The drain nodes of the transistors TR2 and TR4 are connected to a terminal OUT2 to which the other end of the motor 280 is connected.

The transistors TR1 to TR4 include parasitic diodes D1 to D4 having a CMOS structure, and these are connected in parallel to the transistors TR1 to TR4.

Here, all of the transistors TR1 to TR4 may be composed of N-type CMOS transistors. Alternatively, the transistors TR1 to TR4 may be composed of bipolar transistors. In this case, the diodes D1 to D4 are not parasitic diodes but circuit elements.

In addition, the control unit 240 includes a drive signal generation unit 241 that generates the drive signals S1 to S4 as PWM signals.

Then, the detection circuit 220 generates a reference voltage VR based on the input voltage Vref, outputs a D / A conversion circuit (D / A converter) 222, the reference voltage VR, and a voltage VS at one end of the sense resistor 290. And a comparator 221 for comparing. Here, the reference voltage VR is
The output voltage of the D / A conversion circuit 222, and the voltage VS is a detection voltage corresponding to the current flowing through the bridge circuit 210.

The comparator 221 outputs a signal CQ1 based on the comparison result between the reference voltage VR and the voltage VS at one end of the sense resistor 290. The signal CQ1 is a signal instructing switching from the charge period to the decay period when it is at the active level.

Then, the drive signal generation unit 241 generates drive signals S1 to S4 that drive the bridge circuit 210 based on the signal CQ1 input via the detection circuit 220. On the other hand, the input signal SW_UVLO is input from the noise cancellation circuit 130 to the control unit 240. This input signal SW_UVLO is not a signal directly used to generate the drive signals S1 to S4, but a reset signal that indicates whether the drive state of the flip-flop in the control unit 240 is to be active or inactive. It is.

In the present embodiment, as shown in FIG. 2B, the signal generation unit 110 outputs the input signal FBSW before noise cancellation to the noise cancellation circuit 130, and the noise cancellation circuit 13.
0 outputs the input signal SW_UVLO after noise cancellation to the control unit 240. And
The control unit 240 does not generate the drive signals S1 to S4 when the transition to the inactive state based on the input signal SW_UVLO or when the inactive state is continued, and the input signal SW
When transitioning to the active state based on _UVLO or continuing the active state, the drive signals S1 to S4 are generated based on the signal CQ1.

Here, when arranging various signals in order, the analog signal (V _{ana in} FIG. 3) first detects, for example, a voltage drop detection circuit (not shown) that detects a drop in the voltage input to the control unit 240. Output signal.

The power source of the control unit 240 (logic circuit) is outside (or inside) the circuit device 100.
Is generated by a power supply circuit (not shown). When the voltage of the power supply decreases, the control unit 240 may not operate normally, and the bridge circuit 210 controlled by the control unit 240 may operate abnormally (for example, lead to heat generation of the motor 280).
Therefore, a voltage drop detection circuit is provided so that the control unit 240 can be reset when the power supply voltage drops. The voltage drop detection circuit outputs an analog voltage (analog signal) V _ana based on the power supply voltage of the control unit 240, and is configured such that, for example, the analog voltage decreases when the power supply voltage decreases.

Accordingly, when the signal generation unit 110 determines that the voltage input to the control unit 240 has decreased based on the analog signal _Vana , the reset signal (FIG. 3) is transmitted to the control unit 240.
FBSW) can be output. However, the analog signal is not limited to this.

Specifically, the signal generation unit 110 includes a comparator 111. The comparator 111 compares the analog signal voltage V _ana inputted to the first input terminal (+ terminal) with the reference voltage Vref2 inputted to the second input terminal (− terminal), and compares the input signal. FBSW is output. The input signal FBSW is input to the noise cancellation circuit 130.

As a result, the signal generation unit 110 receives the voltage V _{a of the} analog signal input to the first input terminal.
_{When na} is smaller than the reference voltage Vref2 input to the second input terminal, the controller 240
It is possible to output an inactive level (L level) input signal FBSW that resets the driving of (inactive state). That is, when the voltage drop detection circuit determines that the voltage supplied to the control unit 240 has dropped, the voltage V smaller than the reference voltage Vred2
The signal of _ana is output and the control part 240 is reset.

Further, when the voltage V _{ana of the} analog signal is equal to or higher than the reference voltage Vref2, the control unit 2
For example, it is possible to output an input signal FBSW of an active level (H level) that activates the driving of 40. That is, when the voltage the voltage drop detection circuit is supplied to the control unit 240 determines that is stable, and outputs a signal of the reference voltage Vred2 more voltage V _ana, the control unit 240 to the active state .

As described above, the input signal FBSW is a reset signal that resets the drive of the control unit 240 (into an inactive state). Since the input signal FBSW is a digital signal, VDD or V
The signal level of either one of SS is taken.

The input signal SW_UVLO is a signal after the noise cancellation circuit 130 performs noise cancellation processing on the input signal FBSW. Similarly to the input signal FBSW, the input signal SW_UVLO can also be said to be a reset signal instructing reset of driving of the control unit 240, and the reset signal actually input to the control unit 240 is the SW_UVLO.

Then, by inputting the input signal SW_UVLO to the control unit 240, as described above, the drive of the control unit 240 can be reset (inactive) or activated. Even when the original reset signal (input signal) FBSW includes noise, as described above, the noise canceling circuit 130 removes (or suppresses) the noise, so that the control unit 240 is erroneously reset. Can be prevented.

3. Details of Processing in Acceleration Period and Deceleration Period Before describing the noise cancellation processing of this embodiment, FIG. 4 (A), FIG. 4 (B) and FIG.
The operation of the circuit device 100 during the acceleration period (charge period) and the deceleration period (decay period) will be described with reference to FIG.

In the charge period TC, as shown in FIG. 4A, the transistors TR1 and TR4 of the bridge circuit 210 are turned on and the transistors TR2 and TR3 are turned off. And
As shown in FIG. 4A, the charge current Id ₁ flows through the bridge circuit 210. At this time, since the charge current Id ₁ flowing through the motor 280 increases, the voltage VS increases as shown in FIG. The comparator 221 detects that the voltage VS has reached the reference voltage VR and activates the signal CQ1, and the controller 240 activates the signal CQ1 that has become active.
In response, the charge period TC is switched to the decay period TD. The voltage VS is the reference voltage V
The current when R is reached is called a chopping current IL.

On the other hand, in the decay period TD, as shown in FIG. 4B, the transistors TR2 and TR3 of the bridge circuit 210 are turned on and the transistors TR1 and TR4 are turned off. Then, as shown in FIG. 4B, a decay current Id ₂ flows through the bridge circuit 210. At this time, decay current Id ₂ flowing through the motor 280 decreases.

In this way, the current flowing through the motor 280 rises and falls with the chopping current IL as the upper limit, and the average becomes the drive current of the motor 280. In the register unit 250, the setting value (setting value of the reference voltage VR) of the D / A conversion circuit 222 can be variably set. Since the chopping current is determined by the reference voltage VR, the drive current is set by changing the set value of the D / A conversion circuit 222, and the rotation speed and torque of the motor 280 can be controlled.

FIG. 6 shows a more detailed timing chart of the above operation. First, the operation when switching from the charge period to the decay period will be described.

As indicated by A1 in FIG. 6, the control unit 240 generates the signal C at the rising edge of the clock signal CLK.
Q1 is sampled, and period switching is controlled based on the sampled signal CQ1.

Specifically, it is assumed that the signal CQ1 is at the H level at the first rise of the clock signal CLK. When the current Id exceeds the set value from the bottom to the top until the next second rise (when the voltage VS exceeds the reference voltage VR from the bottom to the top), the output signal CQ1 of the comparator 221 is H It changes from level (inactive) to L level (active). Then, the signal CQ1 changes to the L level at the second rise. Further, when the signal CQ1 is maintained at the L level at the next third rise, the control unit 240 switches from the charge period to the decay period. The switching timing is the next fourth rise after confirming the L level twice.

In this way, the output signal CQ1 of the comparator 221 becomes L in at least two clocks.
The process of confirming the level (active) and switching the period is called a mask process. By this masking process, inversion of the signal CQ1 due to noise can be eliminated, and the charge period can be switched to the decay period only when the chopping current truly exceeds the set value.

When switching to the decay period, the control unit 240 causes a counter (not shown) to start counting. When the control unit 240 confirms that the predetermined count value (“1F” in the example of FIG. 6) has been reached, the control unit 240 switches from the decay period to the charge period.

Further, the decay period in the examples of FIG. 4B, FIG. 5 and FIG. 6 described above is a first decay period, and in the decay period, as shown in FIG. The transistors TR3 and TR4 of the bridge circuit 210 are turned on and the transistor T
There is also a slow decay period in which R1 and TR2 are off. In this case, a decay current Id ₃ flows through the bridge circuit 210 as shown in FIG. In the following example, a case where the H bridge 210 is controlled by repeating three periods of a charge period, a first decay period, and a slow decay period will be described as an example.

4). Details of Noise Canceling Process Next, details of the noise canceling process will be described. First, FIG. 7 shows a timing chart relating to the control of the H-bridge 210 in order to explain the noise generation timing. As shown in FIG. 3, S1 to S4 are drive signals output by the drive signal generation unit 241, and OUT1 and OUT2 are signals at connection terminals OUT1 and OUT2 between the circuit device 100 and the motor 280, respectively. Represents. VCC and GND represent power supply voltage signals of the bridge circuit, and FBSW represents an input signal (reset signal) input to the control unit 240.

In this example, when the control unit 240 drives the motor 280, as shown in FIG. 7, “CHG (charge)” → “FD (Fast Decay)” → “
Three periods (modes) are repeated: “SD (Slow Decay)” → “CHG” → “FD” → “SD” .Hereafter, the modes are changed to CHG → FD, FD → SD, SD → CHG, respectively. Switching is called mode switching.

Here, when the mode is switched, the high-side and low-side transistors are turned on-of.
Due to the timing deviation, a large short-circuit current flows instantaneously, and noise resulting from the short-circuit current may ride on various signal lines via the substrate. For example, as shown in FIG. 7, at the timing T1 when the mode is switched from CHG to FD, or at the timing T2 when the mode is switched from SD to CHG, the power supply line (VCC, GND shown in FIG. 3) or the input signal FB
Noise gets on the SW. As described above, in particular, when noise is applied to the input signal FBSW, that is, when a glitch GR as shown in FIG. 7 occurs, an inactive level (L level) reset signal is generated at the reset terminal of the flip-flop in the control unit 240. The operation of the control unit 240 may be reset (inactivated) in some cases.

In the present embodiment, the noise cancel circuit 130 is connected to the reset terminal of the flip-flop in the control unit 240 that is particularly important in operation, thereby preventing the control unit 240 from malfunctioning. That is,
A noise cancellation circuit 130 is inserted between a signal line typified by the input signal FBSW and an input terminal such as a reset.

FIG. 8 shows a specific configuration example of the noise cancellation circuit 130. The noise cancellation circuit 130 of FIG. 8 includes two shift register circuits (SR1, SR2) connected in series,
A NAND circuit (3in_NAND), an OR circuit (3in_OR), and a flip-flop circuit FF are included. Here, for the sake of easy understanding, a minimum circuit configuration is shown.

Of the two shift register circuits, the first shift register circuit SR1 includes an input signal FBSW input to the D terminal, a clock signal CLK input to the C terminal, and an external reset signal RST input to the R terminal. The first shift output signal Q1 obtained by shifting the input signal FBSW is output based on.

Next, of the two shift register circuits, the second shift register circuit SR2 includes a first shift output signal Q1 from the first shift register circuit SR1 input to the D terminal and a clock signal input to the C terminal. Based on CLK and the external reset signal RST input to the R terminal, a second shift output signal Q2 obtained by shifting the first shift output signal Q1 is output.

The NAND circuit (3in_NAND) receives the input signal FBSW and the first input signal FBSW.
A NAND signal NDS is output based on the shift output signal Q1 and the second shift output signal Q2. The OR circuit (3in_OR) outputs an OR signal ORS based on the input signal FBSW, the first shift output signal Q1, and the second shift output signal Q2.

Then, the flip-flop circuit FF receives the input NAND signal NDS and the OR signal ODS.
Based on RS, the reset signal SW_UVLO of the control unit 240 is output.

Next, using the timing chart shown in FIG. 9, the noise cancellation circuit 13 shown in FIG.
An example of 0 operation will be described in detail.

First, an active level (H level) external reset signal RST is input to each shift register circuit, and each shift register circuit is activated (T0). Immediately after the timing T0, an L-level input signal FBSW is input to each shift register circuit.

Then, the H level input signal FBSW for one clock is input to the first shift register circuit SR1 at the fall of the middle of one clock (T1). The H level input signal for one clock is a glitch generated by the mode switching described above. Next, the first shift register circuit SR1 to which the input signal FBSW corresponding to the glitch is input shifts the output timing by half a clock while maintaining the signal level (H level) of the input signal FBSW. When the clock signal CLK rises, the first shift output signal Q1 is output (T2 to T4). Similarly, the second shift register circuit SR2 shifts the output timing by one clock while maintaining the signal level (H level) of the first shift output signal Q1, and the second shift register circuit SR2 A 2-shift output signal Q2 is output (T3 to T6).

Between timing T1 and timing T6, the input signal FBSW and the first shift output signal Q1
Among the second shift output signal Q2, the signal level of at least one of the three inputs is H level. The input signal FBSW, the first shift output signal Q1, and the second
There is no period during which all the shift output signals Q2 are at the H level. Therefore, during the period from timing T1 to timing T6, the NAND signal NDS is always at the H level, and the OR signal ORS is always at the H level.

Here, the flip-flop circuit FF in FIG. 8 (and FIG. 11 described later) is a D-type flip-flop circuit, and FIG. 10 shows a truth table of the flip-flop circuit FF. Note that ↑ in the column of input to the C terminal indicates the rising edge of the clock signal CLK, and x indicates that it does not depend on the input (don't care). In the flip-flop circuit FF, since the C terminal and the D terminal are connected to the ground, the input of the C terminal and the D terminal is always 0V. That is, in the present embodiment, the flip-flop circuit FF operates in the third to sixth rows of the truth table in FIG.

Since the input to the SB terminal is always H level (1) and the input to the RB terminal is always H level (1) during the period from timing T1 to timing T6, the truth table of FIG. According to the third row, the reset signal SW_UVLO that is the output from the Q terminal holds the output at the previous timing. In addition, at timing before timing T1, SB
Since the input to the terminal is H level (1) and the input to the RB terminal is L level (0),
According to the fifth row of the truth table of FIG. 10, an L level (0) reset signal SW_UVLO is output. Therefore, the reset signal SW_U is also used during the period from the timing T1 to the timing T6.
The signal level of VLO remains L level (0). That is, it is possible to cancel the glitch (noise) for one clock and continue to output the reset signal SW_UVLO at the same level as when no glitch is input.

Next, in the example of FIG. 9, the H level input signal FBSW is again input to the noise cancellation circuit 130.
Is input (T7). However, this time, the input signal FBSW does not temporarily become H level due to noise, but the signal level of the input signal FBSW is normally changed. Therefore, an L level reset signal SW_UVLO is output during a period of 1.5 clocks (substantially 1 clock) from timing T7 to timing T8.
After timing T8, an H level reset signal SW_UVLO is output. Thereby, the control part 240 can be reset at the timing T8.

Further, after the timing T8, during a period in which the H level input signal FBSW is input,
The L level input signal FBSW may be erroneously input due to noise (T9). Here, it is assumed that the input signal has become L level only for a period of one clock. In this case, the noise can be canceled in the same manner as when noise is applied during the period from timing T1 to timing T3, and the H level reset signal SW_UVLO is continuously output during the period from timing T9 to timing T10. be able to. Accordingly, the control unit 240
Can be prevented from being accidentally reset.

However, in the noise cancellation circuit shown in FIG. 8, if noise gets on the input signal FBSW for a period of 2 clocks or more, the noise cannot be canceled. Therefore, in the present embodiment, when it is necessary to deal with noise having a larger noise width, a noise cancellation circuit 130 having an increased number of shift register circuits is used as shown in FIG.

The noise cancellation circuit 130 shown in FIG. 11 includes N shift register circuits (SR1 to SRN) connected in series (N is an integer of 2 or more), a NAND circuit, an OR circuit, a flip-flop circuit FF, Have

The first shift register circuit SR1 among the N shift register circuits is a first shift obtained by shifting the input signal FBSW based on the input signal FBSW, the clock signal CLK, and the external reset signal RST. Output signal Q1 is output.

Of the N shift register circuits, the i-th (i is an integer of 2 ≦ i ≦ N) shift register circuit SRi is input from the (i−1) -th shift register circuit SR (i−1). The (i-1) th shift output signal Q (i-1) is shifted based on the (i-1) th shift output signal Q (i-1), the clock signal CLK, and the external reset signal RST. The i-th shift output signal Qi is output.

The NAND circuit receives the input signal FBSW and the first shift output signals Q1 to Q1.
The NAND signal NDS is output based on the Nth shift output signal QN, and the OR circuit generates an OR signal based on the input signal FBSW that is input and the first shift output signal Q1 to the Nth shift output signal QN. Output ORS.

The flip-flop circuit FF outputs the reset signal SW_UVLO of the control unit 240 based on the input NAND signal NDS and the OR signal ORS.

This corresponds to a clock number shorter than the number M of shift register circuits (that is, N
It is possible to cancel noise with a noise width (below the clock). For example, as shown in FIG. 8, when there are two shift register circuits, noise up to 2 clocks can be canceled, and when there are 8 shift register circuits, noise up to 8 clocks can be canceled. Can be canceled.

Further, the noise cancellation circuit 130 can be expected to have a sufficient noise cancellation effect even in the circuit configured by C and R shown in FIG. Even if the noise cancellation circuit 130 has a digital configuration, the L
An analog configuration such as PF may be used.

Here, as described above, the noise cancellation circuit 130 has a signal (Q1, Q2, etc. in the example of FIG. 9) having a delay that can cope with noise and an input without delay (FBS in the example of FIG. 9).
Noise is canceled by comparing with (W). However, the noise (noise width) varies depending on the use environment and use situation of the circuit device 100, and the noise width may be small or large. Therefore, it must be able to cope with the maximum width of noise that can occur.

In these noise cancellation circuits 130, the length of the delay value determines how much noise can be rejected. The larger the delay value, the longer the noise can be canceled. However, the delay value need not be increased unnecessarily. This is because the larger the delay value, the longer the detection of a normally output signal is delayed.

Therefore, in the present embodiment, the width of the noise is detected, and a delay value optimum for the length is set in the delay circuit. For example, the noise cancellation circuit 130 is used to determine a NAND signal and an OR signal to be output to the flip-flop circuit among N shift output signals from the N shift register circuits based on the detected noise width. The shift output signal to be selected may be selected.

As a result, it is possible to cancel noise that may occur and to suppress detection delay of a signal that does not carry noise.

Specifically, FIG. 13 shows a configuration example of the noise cancellation circuit 130 in which the shift output signal to be used among the N shift output signals can be changed according to the noise width.

The noise cancellation circuit 130 shown in FIG. 13 is the same as the noise cancellation circuit 13 shown in FIG.
N is a modification of 0, and N shift registers connected in series (N is an integer of 2 or more), N NAND circuits, N OR circuits, a first selector unit SL1, Second
It has a selector unit SL2 and a flip-flop circuit FF. In the example of FIG. 13, N =
In the following, a specific operation will be described in the case of N = 8, but the present embodiment is not limited to this.

First, the operation of the eight shift register circuits (SR1 to SR8) is as described with reference to FIG.

Next, of the eight NAND circuits, the first NAND circuit ND1 sends the first NAND signal NDS1 to the first selector unit SL1 based on the input signal FBSW and the first shift output signal Q1. Output. Similarly, of the eight NAND circuits, the kth NAND circuit NDk (k is an integer satisfying 2 ≦ k ≦ 8) includes the input signal FBSW and the first shift output signal Q1 to the kth shift output. Based on the signal Qk, the kth NAND signal NDSk is output to the first selector SL1.

In addition, the first OR circuit OR1 of the eight OR circuits receives the input signal FBSW.
And the first shift output signal Q1, the first OR signal ORS1 is converted to the second selector unit S.
Output to L2. Similarly, the kth OR circuit ORk among the eight OR circuits is based on the input signal FBSW and the first shift output signal Q1 to the kth shift output signal Qk.
The k-th OR signal ORSk is output to the second selector unit SL2.

Then, the first selector SL1 receives the first input based on the detected noise width.
NAND signal NDS1 to eighth NAND signal NDS8, any one NAN
The D signal is selected and output to the flip-flop circuit FF. In FIG. 13, the selected NA
The ND signal is called NDS. For example, the SEL signal shown in FIG.
When “001” is input as the selection signal), the first selector SL1 sets the first
NAND signal NDS1 is selected. When the first NAND signal NDS1 is selected, the noise width is small, and it can be sufficiently handled only by the first shift register circuit SR1,
Only the first shift register circuit SR1 is used. For example, the first selector unit S
When “111” is input as the SEL signal to L1 and the eighth NAND signal NDS8 is selected, the noise width is large, and all of the first shift register circuit SR1 to the eighth shift register circuit SR8 are used.

On the other hand, the second selector unit SL2 selects any one OR signal from the input first OR signal ORS1 to ORS8 based on the detected noise width, and performs flip-flop operation. Output to the circuit FF. In FIG. 13, the selected OR signal is referred to as ORS. When the first NAND signal NDS1 is selected by the first selector unit SL1, “001” is input to the second selector unit SL2 as the SEL signal, and the first OR
Signal ORS1 is selected. That is, in this example, the same number of shift register circuits are selected as the shift register circuits to be used in the first selector unit SL1 and the second selector unit SL2.

The flip-flop circuit FF receives the input NAND signal NDS and the OR signal ODS.
A reset signal SW_UVLO is output based on RS.

This makes it possible to select a shift register circuit to be used from a plurality of shift register circuits according to the noise width.

In order to perform such processing, the circuit device 100 according to the present embodiment includes a noise detection circuit 140 that detects a noise width when the charge period and the decay period are switched. For example, the noise detection circuit 140 detects noise at the timing of switching from the first SD to CHG, the timing of switching from CHG to FD, etc. from the time when the circuit device 100 is turned on and enters stable driving. Based on the detected noise, the optimal delay value (
Delay time information) is set, stored in the storage unit 120, and a delay value is set in the noise cancellation circuit 130 based on the stored information.

This makes it possible to set a delay value in the noise cancellation circuit 130 so that noise generated at the time of mode switching can be canceled.

The noise detection circuit 140 may detect the noise width of the analog signal when the power is turned on.

This makes it possible to set a delay value in the noise cancellation circuit 130 so that noise generated when the power is turned on can be canceled.

In the first detection of noise, the noise detection circuit 140 detects the noise width,
There will be a delay of at least the noise width. Therefore, at first, the noise cancellation circuit 1
The delay value of 30 is set to a sufficiently large value. Then, when the noise width is detected to some extent, the optimum delay value is set based on the delay time information stored in the storage unit 120 thereafter.

That is, the storage unit 120 stores the first delay time information and the second delay time information. The noise cancellation circuit 130 performs noise cancellation based on the second delay time information before detecting the noise width, and after detecting the noise width, the noise cancellation circuit 130 performs noise cancellation based on the first delay time information. I do.

As a result, it becomes unnecessary to set a long delay value unnecessarily, and detection of a normally output signal can be accelerated.

In this case, the first delay time information is, for example, delay time information corresponding to the actually detected noise width, and the second delay time information is, for example, the maximum delay time that can be set in the noise cancellation circuit 130. Is delay time information corresponding to.

Thereby, after detecting the noise width, it becomes possible to set a delay value based on the delay time information corresponding to the noise width. In addition, before detecting the noise width, it is possible to set a maximum delay value that can be set so that the correct noise width can be detected.

Further, the circuit device 100 includes a current detection circuit 220, and verifies whether or not the mode switching has been normally performed or the mode switching end period. It is desirable to follow this test as soon as possible when the mode is switched. However, since a normal result cannot be obtained even if this test is performed during a period in which noise may occur, the test is started after a delay necessary for noise cancellation.

Therefore, the first noise width immediately after the motor driving is started is monitored, the optimum delay value is set in the storage unit 120, and the noise generation timing after that is stored in the storage unit 12.
The noise cancellation circuit 130 is controlled based on the set data of 0.

In this way, the detection start timing of the detection circuit 220 can be made as early as possible.

Specifically, FIG. 14 shows an explanatory diagram about this. When noise having a width tn as shown in FIG. 11 is applied to the power supply VSS, the same noise is also applied to a node (terminal to be tested) for current detection, and after a while, the result of mode switching is actually expected. Changes to a value. In order to remove this noise, the delay value is set to tc, and the test enable signal for starting the current detection is set to the H level (active level) after a predetermined period td with some margin from the delay value tc. Therefore, if the noise width tn is large, the delay value tc is also increased, and the predetermined period td is also increased. Conversely, if the noise width tn is small, the predetermined period td can be reduced.

5. Modified Example of Noise Canceling Circuit Next, a modified example of the noise canceling circuit 130 capable of setting an appropriate delay value according to the detected noise width in the present embodiment is shown in FIG.

The noise cancellation circuit 130 of the present embodiment includes M (M is an integer of 2 or more) cancellation blocks (CNC1 to CNC4) connected in series, a decoder unit DC, and a selector unit SC. In the example of FIG. 15, M = 4, but is not limited thereto.

The first cancel block CNC1 among the M cancel blocks is based on the input signal FBSW that is input, the first delay circuit DL1 that outputs the first delay signal DLS1, the input signal FBSW that is input, The first NAND circuit ND1 that outputs the first NAND signal NDS1 based on the one delay signal DLS1 is provided.

Furthermore, the j-th (j is an integer of 2 ≦ j ≦ M) cancellation block CNCj among the M cancellation blocks is based on the inputted (j−1) th delay signal DLS (j−1). A j-th delay circuit DLj that outputs the j-th delay signal DLSj and a j-th NAND circuit NDj that outputs the j-th NAND signal NDSj based on the input signal FBSW and the j-th delay signal DLSj are provided.

The decoder unit DC receives the input first NAND signal NDS1 to Mth NAN.
Based on the D signal NDSM, the decode signal DCS is output (to the register RS), and the selector unit SC performs control based on the input first NAND signal NDS1 to Mth NAND signal NDSM and the decode signal DCS. The reset signal SW_UVLO of the unit 240 is output.

As a result, the noise width that can be canceled increases in order from the lower side of the cancel block in FIG. That is, the noise width that can be canceled by the cancel block CNC2 is larger than the noise width that can be canceled by the cancel block CNC1, and the noise width that can be canceled by the cancel block CNC3 than the noise width that can be canceled by the cancel block CNC2. Is bigger.

Specifically, FIGS. 16A to 16D show simulation results when noise cancellation is performed on noise of various noise widths that ride on the input signal FBSW. FIG.
6A represents the noise cancellation result by the cancel block CNC1 in FIG. 14, the waveform in FIG. 16B represents the noise cancellation result by the cancel block CNC2 in FIG. 14, and the waveform in FIG. The noise cancellation result by the cancellation block CNC3 in FIG. 14 is shown, and the waveform in FIG. 16D shows the noise cancellation result by the cancellation block CNC4 in FIG. In addition, the vertical axis of each graph in FIGS. 16A to 16D represents the intensity of noise, and indicates that the noise has been completely canceled when it reaches 0V. The horizontal axis of each graph represents time, and FIG. 16 (A) to FIG. 16 (D).
In the example, 50 nsec, 40 nsec, 30 nsec, 20 nsec, 10 nsec,
The result of having performed noise cancellation in order with respect to the noise of a noise width of 8 nsec and 6 nsec is shown.

First, according to the simulation result of FIG. 16A, it can be seen that in the cancel block CNC1, noise having a width of 6 nsec can be almost eliminated, but noise having a width of 8 nsec or more cannot be eliminated.

Next, according to the simulation result of FIG. 16B, it can be seen that in the cancel block CNC2, noise up to 8 nsec width can be almost eliminated, but noise of 10 nsec width or more cannot be eliminated.

Then, according to the simulation result of FIG. 16C, the cancel block CNC3
Then, it can be seen that noise up to 10 nsec width can be almost eliminated, but noise of 20 nsec width or more cannot be eliminated.

Further, according to the simulation result of FIG. 16D, the cancel block CNC4
Then, it can be seen that noise up to a width of 20 nsec can be almost eliminated, but noise over a width of 30 nsec cannot be eliminated.

By monitoring each output of this cancel block in this way, in this example 4
Two delay values can be selected. This makes it possible to set an appropriate delay value.

6). Electronic Device FIG. 17 shows a configuration example of an electronic device to which the circuit device 100 (motor driver) of this embodiment is applied. The electronic device includes a processing unit 300, a storage unit 310, an operation unit 320, and an input / output unit 3.
30, a circuit device 100, a bus 340 connecting these units, and a motor 280. In the following, we will explain using a printer that controls the head and paper feed by motor drive as an example.
The present embodiment is not limited to this, and can be applied to various electronic devices.

The input / output unit 330 is configured by an interface such as a USB connector or a wireless LAN, and receives image data and document data. The input data is stored in the storage unit 310 which is an internal storage device such as a DRAM. When the printing instruction is received by the operation unit 320, the processing unit 300 starts a printing operation of data stored in the storage unit 310. Processing unit 3
00 sends an instruction to the circuit device 100 (motor driver) according to the print layout of the data, and the circuit device 100 rotates the motor 280 based on the instruction to move the head and feed the paper.

Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

100 circuit device, 110 signal generation unit, 111 comparator, 120 storage unit,
130 noise cancellation circuit, 140 noise detection circuit,
210 bridge circuit (H bridge), 220 detection circuit, 221 comparator,
222 conversion circuit (DAC), 240 control unit, 241 drive signal generation unit,
250 register section, 260 pre-driver, 270 clock generation circuit,
280 motor, 290 sense resistor

Claims (13)

A bridge circuit having a high-side transistor and a low-side transistor;
A controller that performs on / off control of the high-side transistor and the low-side transistor to switch between a charge period for increasing the current flowing through the bridge circuit and a decay period for decreasing the current;
A signal generation unit that generates an input signal that is a digital reset signal input to the control unit based on an analog signal;
A storage unit that stores delay time information corresponding to a noise width of the analog signal when the charge period and the decay period are switched;
A noise cancellation circuit that performs noise cancellation on the input signal based on the delay time information;
A circuit device comprising: In claim 1,
A circuit device comprising: a noise detection circuit that detects the noise width when the charge period and the decay period are switched. In claim 1 or 2,
A circuit device comprising a noise detection circuit for detecting the noise width of the analog signal when power is turned on. In any one of Claims 1 thru | or 3,
The storage unit
Storing first delay time information and second delay time information;
The noise cancellation circuit is
Before the detection of the noise width, based on the second delay time information, the noise cancellation,
After detecting the noise width, the noise cancellation is performed based on the first delay time information. In claim 4,
The first delay time information is:
The circuit device according to claim 1, wherein the delay time information corresponds to the noise width. In claim 4 or 5,
The second delay time information is:
The circuit device characterized by the delay time information corresponding to the maximum delay time that can be set in the noise cancellation circuit. In any one of Claims 1 thru | or 6 .
The analog signal is
A circuit device comprising: an output signal of a voltage drop detection circuit for detecting a voltage drop input to the control unit. In any one of Claims 1 thru | or 7 ,
The signal generator is
Including a comparator,
The comparator is
A circuit device that compares the voltage of the analog signal input to the first input terminal with a reference voltage input to the second input terminal and outputs the input signal. In any one of Claims 1 thru | or 8 .
The noise cancellation circuit is
N shift register circuits (N is an integer of 2 or more) connected in series;
A NAND circuit;
An OR circuit;
A flip-flop circuit;
Have
The first shift register circuit among the N shift register circuits is:
Based on the input signal, the clock signal, and the external reset signal that are input, a first shift output signal that is a shift of the input signal is output,
Of the N shift register circuits, the i-th (i is an integer of 2 ≦ i ≦ N) shift register circuit is:
Based on the input (i-1) shift output signal from the (i-1) shift register circuit, the clock signal, and the external reset signal, the (i-1) shift output signal is obtained. The shifted i-th shift output signal is output,
The NAND circuit is
Based on the input signal and the first shift output signal to the Nth shift output signal, a NAND signal is output,
The OR circuit
Based on the input signal and the first shift output signal to the Nth shift output signal, an OR signal is output,
The flip-flop circuit is
A circuit device that outputs a reset signal of the control unit based on the input NAND signal and the OR signal. In claim 9 ,
The noise cancellation circuit is
A shift output used to determine the NAND signal and the OR signal to be output to the flip-flop circuit among N shift output signals by the N shift register circuits based on the detected noise width. A circuit device for selecting a signal. In any one of Claims 1 thru | or 8 .
The noise cancellation circuit is
N shift register circuits (N is an integer of 2 or more) connected in series;
N NAND circuits;
N OR circuits;
A first selector section;
A second selector section;
A flip-flop circuit;
Have
The first shift register circuit among the N shift register circuits is:
Based on the input signal, the clock signal, and the external reset signal that are input, a first shift output signal that is a shift of the input signal is output,
Of the N shift register circuits, the k-th (k is an integer satisfying 2 ≦ k ≦ N) shift register circuit,
Based on the (k-1) th shift output signal from the (k-1) th shift register circuit, the clock signal, and the external reset signal, the (k-1) th shift output signal is inputted. Outputs the shifted k-th shift output signal,
The first NAND circuit among the N NAND circuits is:
Based on the input signal and the first shift output signal that are input, the first NAND signal is output to the first selector unit,
The kth NAND circuit among the N NAND circuits is:
Based on the input signal and the first to k-th shift output signals, the k-th NAND signal is output to the first selector unit,
The first OR circuit among the N OR circuits is:
Based on the input signal and the first shift output signal that are input, the first OR signal is output to the second selector unit,
The kth OR circuit among the N OR circuits is:
Based on the input signal that is input and the first to k-th shift output signals, the k-th OR signal is output to the second selector unit,
The first selector unit includes:
Based on the detected noise width, any one NAND signal is selected from the input first NAND signal to Nth NAND signal, and is output to the flip-flop circuit,
The second selector unit is
Based on the detected noise width, one of the input OR signals to the Nth OR signal is selected and output to the flip-flop circuit,
The flip-flop circuit is
A circuit device that outputs a reset signal of the control unit based on the input NAND signal and the OR signal. In any one of Claims 1 thru | or 8 .
The noise cancellation circuit is
M (M is an integer of 2 or more) cancel blocks connected in series;
A decoder section;
A selector section;
Have
The first cancellation block among the M cancellation blocks is:
A first delay circuit for outputting a first delay signal based on the input signal;
A first NAND circuit that outputs a first NAND signal based on the input signal and the first delay signal;
Have
Of the M cancellation blocks, the jth cancellation block (j is an integer satisfying 2 ≦ j ≦ M) is:
A j-th delay circuit for outputting a j-th delay signal based on the inputted (j-1) delay signal;
A jth NAND circuit that outputs a jth NAND signal based on the input signal and the jth delay signal;
Have
The decoder unit
Based on the input first NAND signal to the Mth NAND signal, a decode signal is output,
The selector section is
A circuit device that outputs a reset signal of the control unit based on the inputted first NAND signal to the Mth NAND signal and the decode signal. An electronic apparatus comprising the circuit arrangement as claimed in any one of claims 1 to 12.

Images