JP6465384B2 - Image forming apparatus, parallel processing control program, and parallel processing control method - Google Patents

Description

  The present invention relates to an image forming apparatus, a parallel processing control program, and a parallel processing control method, and more particularly to an image forming apparatus including a multi-core processor, a parallel processing control program for controlling parallel processing in the image forming apparatus, and a parallel processing control method.

  Since it is difficult to improve the performance of the processor by increasing the operating frequency from the viewpoint of power consumption and cooling, multi-core processors are widely used as a method for improving processing performance while suppressing power consumption. A multi-core processor can improve processing performance by performing parallel processing using a plurality of processor cores, and can reduce power consumption by lowering the operating frequency per processor core. .

  Regarding a system that performs parallel processing using a multi-core processor, for example, Patent Document 1 below is a multi-core system that includes a plurality of multi-core processors having a plurality of cores and a shared resource that shares the resources of each multi-core processor. Load information collecting means for obtaining load information of each multi-core processor and load information at the time of accessing the shared resource, load information of each multi-core processor obtained by the load information collecting means, and at the time of access Load distribution determining means for determining whether or not to perform load distribution based on the condition of the load information, and when the load distribution determining means determines that the load distribution is to be performed, the load is distributed A configuration having load balancing means is disclosed.

JP 2008-191949 A

  The multi-core processor can be employed in various devices, but can be particularly effective when employed in a device having a plurality of functions. For example, by adopting a multi-core processor in an image forming apparatus such as an MFP (Multi Function Peripheral), a plurality of functions such as copy / print / scan / FAX can be processed in parallel.

  Here, when a plurality of functions are processed in parallel by a plurality of processor cores, each processor core needs to access the main memory to acquire instructions (programs) and data necessary for processing the target function. is there. For this reason, accesses to the main memory are concentrated, and the load on the memory bus connecting each processor core and the main memory becomes large. This load may become a bottleneck and cause a decrease in processing performance. As a result, the processing of each function cannot be completed within the time limit, and there is a problem that it is difficult to ensure real-time processing.

  The present invention has been made in view of the above problems, and a main object thereof is an image forming apparatus capable of improving processing performance while ensuring real-time processing in a configuration employing a multi-core processor. And a parallel processing control program and a parallel processing control method.

One aspect of the present invention is an image forming apparatus including a plurality of processor cores that hold a cache memory, the multi-core processor in which the plurality of processor cores share one main memory, and the operation of the image forming apparatus A control unit that controls a load calculation unit that calculates a memory access load to the main memory for each period defined in accordance with an overlap of processing steps of a plurality of jobs, and a memory access load for each period A period predicting unit that predicts a first period in which the memory access load to the main memory is maximized, and any one of a plurality of processing steps scheduled to be executed in the first period. , Dummy execution is performed on a processor core that is not performing processing of the plurality of jobs in a period before the first period, and the dummy execution is completed , The process steps, characterized in that and a processing control unit for the actual executed in the processor core subjected to the dummy execution.

One aspect of the present invention is a parallel processing control program that operates in an image forming apparatus that includes a plurality of processor cores that hold cache memory, and the plurality of processor cores share a single main memory. The image forming apparatus has a first process for calculating a memory access load to the main memory for each period defined in accordance with an overlap of processing steps of a plurality of jobs, based on the memory access load for each period. , A second process for predicting a first period in which the memory access load to the main memory is maximized, and any one of a plurality of process steps scheduled to be executed in the first period, During a period prior to the first period, dummy execution is performed on a processor core that is not processing the plurality of jobs, and the dummy execution is completed. After, the processing steps, characterized in that to execute the third process, the actual executed in the processor core subjected to the dummy execution.

One aspect of the present invention is a parallel processing control method in an image forming apparatus that includes a plurality of processor cores that hold a cache memory, and the plurality of processor cores includes a multi-core processor that shares one main memory. A first process for calculating a memory access load to the main memory for each period defined in accordance with an overlap of processing steps of the job, and a memory for the main memory based on the memory access load for each period The second process for predicting the first period in which the access load is maximized, and any one of the plurality of process steps scheduled to be executed in the first period is more than the first period. the previous period, the dummy run with multiple processor cores process is not performed in the job, after completion the dummy execution, the process steps And executes a third process that the actual executed in the processor core subjected to the dummy execution.

  According to the image forming apparatus, the parallel processing control program, and the parallel processing control method of the present invention, it is possible to distribute the memory access load in the configuration employing the multi-core processor, and the bottleneck of the memory access is eliminated. Processing performance can be improved while ensuring real-time performance.

1 is a block diagram illustrating a configuration of an image forming apparatus according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of a control unit of the image forming apparatus according to an embodiment of the present invention. FIG. 4 is a block diagram illustrating functions executed by a control unit of the image forming apparatus according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating the operation of the image forming apparatus according to the embodiment of the present invention. FIG. 7 is a diagram illustrating a configuration of a copy processing step in the image forming apparatus according to an embodiment of the present invention. 6 is a table showing a memory access load at each processing step of copying in the image forming apparatus according to the embodiment of the present invention. FIG. 6 is a diagram illustrating a configuration of a print processing step in the image forming apparatus according to an embodiment of the present invention. 6 is a table showing a memory access load at each processing step of printing in the image forming apparatus according to the embodiment of the present invention. FIG. 7 is a diagram illustrating a period of parallel copy / print processing in the image forming apparatus according to an embodiment of the present invention. 6 is a table showing a memory access load in each period of parallel copy / print processing in the image forming apparatus according to an embodiment of the present invention. It is a schematic diagram showing an example of parallel processing control in copy / print parallel processing in the image forming apparatus according to an embodiment of the present invention. It is a schematic diagram which shows the other example of the parallel processing control in the copy / print parallel processing in the image forming apparatus which concerns on one Example of this invention. FIG. 6 is a diagram illustrating a period of copy / print 1, 2 parallel processing in the image forming apparatus according to the embodiment of the present invention. 7 is a table showing memory access loads in each period of parallel processing of copy / print 1 and 2 in the image forming apparatus according to an embodiment of the present invention. FIG. 5 is a schematic diagram illustrating an example of processing control in parallel processing of copy / print 1 and 2 in the image forming apparatus according to an embodiment of the present invention. FIG. 10 is a schematic diagram illustrating another example of processing control in parallel processing of copy / print 1 and 2 in the image forming apparatus according to an embodiment of the present invention.

  As shown in the background art, a multi-core processor is widely used as a method for improving processing performance while suppressing power consumption, and is used in various apparatuses. In particular, in an image forming apparatus such as an MFP having a plurality of functions such as copy / print / scan / FAX, it is necessary to perform processing of a plurality of functions at the same time.

  When performing parallel processing using a multi-core processor, each processor core accesses the main memory to obtain necessary instructions and data, so that memory access is concentrated and processing performance may be reduced. . If each process cannot be completed within the time limit due to a decrease in processing performance, the real-time property of the process cannot be ensured.

  With respect to this problem, in Patent Document 1, load information of each processor core and load information at the time of memory access are acquired at regular intervals during program execution, and the load imbalance in the system is determined. A method is proposed in which it is determined that load distribution is necessary, a thread to be moved is determined, and the thread is moved to another processor core. However, with this method, when processing with a large memory access load continues, the memory access load cannot be reduced even if the thread is moved, and real-time processing is ensured by moving the thread. become unable.

  Therefore, in an embodiment of the present invention, a memory access load is large in an image forming apparatus that includes a plurality of processor cores that hold a cache memory and that includes a multi-core processor in which the plurality of processor cores share one main memory. The processing steps executed in the period are the first stage (referred to as dummy execution) in which only instructions are read from the main memory and stored in the cache memory, and the instructions stored in the cache memory are executed by reading data from the main memory. It is divided into the second stage (referred to as actual execution) and executed.

  Specifically, at the start of receiving a new job, the memory access load for each period defined according to the overlap of the processing steps of a plurality of jobs is calculated from the memory access load information of each processing step prepared in advance. A period (first period) in which access to the memory is concentrated is predicted. Then, one of the processing steps scheduled to be executed in a period in which access to the main memory is concentrated is dummy-executed in another processor core in the second period before the first period, and then the processing is performed. The step is actually executed by the dummy processor core.

  In this way, in dummy execution, by accessing the main memory and reading instructions, the number of accesses to the main memory during actual execution can be reduced, so the memory access load can be distributed and the processing performance Can be prevented. In addition, because dummy execution is performed before the period when access to the main memory is concentrated, processing delay due to division into two stages, dummy execution and actual execution, is suppressed, and real-time processing is ensured can do.

  In order to describe the above-described embodiment of the present invention in more detail, an image forming apparatus, a parallel processing control program, and a parallel processing control method according to an embodiment of the present invention will be described with reference to FIGS. To do. FIG. 1 is a block diagram illustrating the configuration of the image forming apparatus according to the present exemplary embodiment, and FIG. 2 is a block diagram illustrating the configuration of the control unit. FIG. 3 is a block diagram illustrating functions executed by the control unit, and FIG. 4 is a flowchart illustrating the operation of the image forming apparatus according to the present exemplary embodiment. 5 and 7 are diagrams showing the configuration of the copy / print processing steps of the image forming apparatus, and FIGS. 6 and 8 are tables showing the memory access load of each copy / print processing step. . 9 and 13 are diagrams showing periods of parallel processing, and FIGS. 10 and 14 are tables showing memory access loads in each period of parallel processing. FIG. 11, FIG. 12, FIG. 15 and FIG. These are schematic diagrams showing an example of parallel processing control in parallel processing.

  An image forming apparatus 10 according to the present exemplary embodiment is an image forming apparatus such as an MFP, and includes a multi-core processor 12 and a main memory 13 as illustrated in FIG. 1. The control unit 11 controls the operation of the image forming apparatus 10. And an HDD (Hard Disk Drive) 15, a network I / F unit 16, a scanner unit 17, a FAX control unit 18, an image forming unit 19, an operation display unit 20, and the like.

  As shown in FIG. 2, the multi-core processor 12 includes a plurality of processor cores 12a (N processor cores of 0 to N-1 here) and a cache memory 12b connected to each of the processor cores 12a. Is done. Each set of the processor cores 12 a and the cache memory 12 b is configured to share the main memory 13 connected via the memory bus 14.

  In the main memory 13, an instruction (program code) for executing processing of each function of the image forming apparatus 10 and data for executing processing of each function are recorded. When the control unit 11 controls functions such as copying, printing, and FAX, the processor core 12a assigned to the function reads instructions and data from the main memory 13, stores them in the cache memory 12b, and executes them. To process the function.

  Specifically, the control unit 11 performs edge enhancement processing and smoothing processing on image data (copy data) read from a document by the scanner unit 17 and image data (FAX data) transmitted and received by the FAX control unit 18. Image processing such as color conversion processing is performed. Also, a print job (PDL (Page Description Language) data described in a page description language such as PJL (Printer Job Language), PS (PostScript), PCL (Printer Control Language), or PDF acquired from an external computer device or PDF (Portable Document Format) data), each page included in the print job is rasterized to generate image data for each page, and the image processing is performed on the generated image data (print data). Then, the image data after image processing is VIDEO output to the image forming unit 19.

  The multi-core processor 12 may be operated by AMP (Asymmetric Multiprocessing) that assigns a specific function to each processor core 12a, or each processor core 12a may share the main memory 13 under equal conditions. It may be operated by Symmetric Multiprocessing) or may be operated by BMP (Bound Multiprocessing) in which AMP and SMP are merged. When operated by AMP, the parallel processing control program of this embodiment (such as an OS (Operating System) if necessary) is executed by a specific processor core 12a, and when operated by SMP, the processing control of this embodiment is performed. A program (such as an OS if necessary) is executed by all the processor cores 12a.

  Further, the number of processor cores 12a in the multi-core processor 12 is not particularly limited. Further, the plurality of processor cores 12a may be the same type (same in scale, configuration, and processing capability), or may be different in scale, configuration, and processing capability.

  The HDD 15 includes a print job acquired from an external computer device, intermediate data generated from the print job (display list), image data generated from the display list (print data), and image data (copy data) read from the document by the scanner unit 17. ), Image data (FAX data) transmitted and received by the FAX control unit 18 is stored.

  The network I / F unit 16 is a modem for connecting to a telephone line, a NIC (Network Interface Card) for connecting to a local communication network such as a LAN (Local Area Network), etc., and is connected via a telephone line. Communication with a computer apparatus connected via a FAX communication with a FAX apparatus or a local communication network.

  The scanner unit 17 is a part that optically reads image data from a document placed on a document table, and a light source that scans the document and a CCD (Charge Coupled Devices) that converts light reflected by the document into an electrical signal. ) And an A / D converter for A / D converting electrical signals, and outputs image data (copy data) read from the document to the control unit 11.

  The FAX control unit 18 controls the network I / F unit 16, transmits FAX data to an external FAX device, receives FAX data from the external FAX device, and sends the received FAX data to the control unit 11. Or output.

  The image forming unit 19 (engine) performs printing processing on paper based on the image data output from the control unit 11 as VIDEO. Specifically, in the case of an electrophotographic system, an electrostatic latent image is formed by irradiating light corresponding to an image from an exposure device onto a photosensitive drum charged by a charging device, and toner charged by a developing device is used. The toner image is attached and developed, and the toner image is primarily transferred to the transfer belt, secondarily transferred from the transfer belt to the paper, and further, the fixing device fixes the toner image on the paper.

  The operation display unit 20 includes a touch panel in which an operation unit such as a touch sensor including a grid-like transparent electrode is disposed on a display unit such as an LCD (Liquid Crystal Display), a hard key, and the like. A screen is presented, an operation from the user is accepted, and a signal corresponding to the operation is output to the control unit 11.

  In FIG. 1, the image forming apparatus 10 includes the scanner unit 17, the FAX control unit 18, and the image forming unit 19. However, the image forming apparatus 10 according to the present exemplary embodiment includes a plurality of functions for parallel processing. For example, when only copying and printing are performed, the FAX control unit 18 can be omitted. The image forming unit 19 (engine) is not necessarily built in the image forming apparatus 10, and the image forming unit 19 may be separated as a separate device. In this embodiment, the multicore processor 12 itself executes a program for controlling parallel processing by the multicore processor 12 (parallel processing control program). However, a processor other than the multicore processor 12 may execute the program. In this case, a configuration including a processor (such as a CPU (Central Processing Unit)) that manages the multi-core processor 12 may be employed.

  In the image forming apparatus 10 having the above configuration, when copying, the scanner unit 17 scans an original, performs data conversion for converting the scan data into the input format of the next step, edge enhancement processing, smoothing processing, color conversion processing. After performing image processing such as this, the video is output to the image forming unit 19. When printing is performed, print job data described in PDL or the like is received, and each page included in the print job is rasterized to generate image data for each page (RIP (Raster Image Processing) processing). After the above image processing is performed on the generated image data, the video data is output to the image forming unit 19. Also, when performing FAX reception, after receiving FAX data from the FAX control unit 18, performing data conversion for converting the FAX data into the input format of the next step, and performing the above image processing on the converted image data VIDEO is output to the image forming unit 19.

  The processor core 12a reads instructions and data from the main memory 13 via the memory bus 14 when executing each processing step in the above copy, print, and FAX. Overlap, the memory access load to the main memory 13 increases, and the processing capability decreases. In this case, it is possible to reduce the memory access load to the memory bus 14 by shifting the overlapping processing steps (moving the thread as in Patent Document 1), but in this method, the memory access load is reduced. When a large process continues, the process step cannot be shifted, and the process execution timing is delayed by shifting the process step, and the real time property of the process cannot be ensured.

  Therefore, in this embodiment, in order to improve the processing capability while ensuring real-time processing, as shown in FIG. 3, the control unit 11 includes a load calculation unit 11a, a period prediction unit 11b, and a processing control unit 11c. Give the function as. That is, any one processor core 12a is caused to execute a parallel processing control program that causes the control unit 11 to function as the load calculation unit 11a, the period prediction unit 11b, and the processing control unit 11c.

  The load calculation unit 11a performs memory access to the main memory 13 for each period defined in accordance with the overlap of the processing steps of a plurality of jobs in parallel processing (that is, divided by the start timing or end timing of each processing step). Calculate the load. The period prediction unit 11b predicts a period (referred to as a first period) in which memory accesses to the main memory 13 are concentrated (maximum) based on the calculated memory access load for each period. The process control unit 11c performs a plurality of process steps scheduled to be executed in the predicted first period in a period before the first period (hereinafter referred to as a second period). Dummy execution is performed by the idle processor core 12a not performing job processing, and then the processing step is actually executed by the processor core 12a that has performed dummy execution.

  The dummy execution is an execution form in which only instructions necessary for executing a processing step are read from the main memory 13 and stored in the cache memory, and the actual execution is necessary for executing the processing step. In this embodiment, data is read from the main memory 13 and an instruction stored in advance in the cache memory is executed with reference to the read data.

  As described above, in the dummy execution and the actual execution, the memory access to the main memory 13 is less than that in the case where the processing steps are executed as usual (when the instruction and data are read together). The increase in load can be suppressed, and by executing dummy execution before the period when the memory access load becomes maximum, processing delay can be suppressed and real-time processing can be ensured. it can.

  Hereinafter, the operation of the image forming apparatus 10 of this embodiment will be described. The multi-core processor 12 executes the process shown in the flowchart of FIG. 4 by executing the parallel processing control program. FIG. 4 is a control flow in the case where parallel processing of copying and printing is performed (when a print job is received during copying).

  First, when receiving a new print job, the control unit 11 (load calculation unit 11a) calculates a memory access load in each period (S101).

  Specifically, as shown in FIG. 5, a copy is composed of four processing steps of scan / data conversion / image processing / VIDEO output, so that as shown in FIG. A memory access load is set in advance. Also, as shown in FIG. 7, printing is composed of four processing steps of data reception / RIP processing / image processing / VIDEO output, so that as shown in FIG. A memory access load is set in advance.

  The memory access load for each processing step may be an actually measured value or a calculated value. Also, it may be an absolute value or a relative value. In addition, since the memory access load varies depending on conditions such as paper size, resolution, and color / monochrome in copying and printing, the memory access load may be an average value of various conditions, or a representative of frequently used conditions. A memory access load for each condition may be prepared.

  When a new print job is received in the middle of copying, the load calculation unit 11a sets a period defined according to the overlap of processing steps as shown in FIG. The memory access load for each period is calculated by adding the memory access load for each processing step in each period. FIG. 10 is an example of a table describing the memory access load for each period.

  For example, period 1 is a period during which print data is being received, and during that time, data conversion is performed during copying, so the memory access load during that period is 35 + 15 = 50. Period 2 is a period from the start of print RIP processing to the end of copy data conversion, and the memory access load in that period is 35 + 40 = 75. Period 3 is a period during which image processing for copying is performed, and during that time, since RIP processing is performed for printing, the memory access load during that period is 25 + 40 = 65. Period 4 is a period from the start of copy VIDEO output to the end of print RIP processing, and the memory access load during that period is 20 + 40 = 60. Period 5 is a period from the start of print image processing to the end of copy VIDEO output, and the memory access load during that period is 20 + 25 = 45.

  Returning to the flowchart of FIG. 4, the control unit 11 (period prediction unit 11b) determines whether or not there is a period in which the copy data conversion and the print RIP process overlap (S102). This determination is performed because the image forming apparatus 10 is a function that is often used for copying and printing, and both data conversion for copying and RIP processing for printing frequently access the main memory 13. . If the copy data conversion and the print RIP process overlap, the control unit 11 (process control unit 11c) performs a later job processing step (in this case, the print RIP process) as a dummy execution target. (S103).

  On the other hand, if the copy data conversion and the print RIP processing do not overlap, the control unit 11 (period prediction unit 11b) compares the calculated memory access loads for each period, and the period during which the memory access load is maximized. (First period) is predicted (S104). And the control part 11 (process control part 11c) determines the process step used as the object of dummy execution from the several process steps scheduled to be performed in a 1st period (S105). Here, from the table in FIG. 10, the period during which the memory access load is maximum is period 2, and from FIG. 9, the processing steps performed in period 2 are copy data conversion and print RIP processing. The RIP processing of the job (print) is determined as a processing step to be subjected to dummy execution.

  Next, the control part 11 (process control part 11c) determines the timing which starts dummy execution (S106). As the dummy execution start timing, a period (second period) in which the memory access load is minimum in a period before the period in which the memory access load is maximum (first period) is selected. Here, since the first period is period 2, period 1 is determined as the second period.

  Next, the control unit 11 (processing control unit 11c) determines the processor core 12a used for dummy execution (S107). The processor core 12a for dummy execution is selected from the processor cores 12a in the idle state. For example, when copying is performed by processor core 0 and printing is performed by processor core 1, processor core 2 is allocated for dummy execution.

  Next, the control unit 11 (process control unit 11c) starts dummy execution of the target process step (S108). In this dummy execution, one instruction is executed (only an instruction is executed without referring to data) in order to read an instruction necessary for actual execution into the cache memory 12b. Here, if another process is executed by the processor core 12a (here, the processor core 2) that performed the dummy execution between the dummy execution and the actual execution, the instruction read into the cache memory 12b is lost. After completing the dummy execution, the control unit 11 (process control unit 11c) prohibits the assignment of the process to the dummy execution processor core 12a (for example, sets a flag) (S109).

  Next, the control unit 11 (processing control unit 11c) determines whether or not actual execution can be started for the processing process for which dummy execution has been performed (S110). This determination is performed because the dummy execution is performed in a period before the period during which the processing step is performed. Therefore, the processing step before the processing step may not be completed at the stage where the dummy execution is completed. Because. Specifically, when the RIP process for printing is executed in a dummy manner, the actual execution of the RIP process cannot be performed unless the data reception as the previous processing step is completed. It is determined whether or not actual execution can be started depending on whether or not.

  When the actual execution cannot be started (that is, when the processing process before the processing process that performed the dummy execution has not ended), the process waits until the actual execution can be started. When the actual execution can be started, the control unit 11 (process control unit 11c) cancels the prohibition of the process assignment to the dummy execution processor core (for example, cancels the flag) (S111), and sets the dummy execution processor core. The target processing step is assigned and actual execution is performed (S112), and the processing steps subsequent to the processing step are also executed by the dummy execution processor core. For example, when the processor core 2 performs the RIP process as a dummy, the processor core 2 performs the actual execution of the RIP process, and the processor core 2 also performs image processing and VIDEO output.

  Hereinafter, dummy execution and actual execution of the above flow will be specifically described with reference to the drawings.

  FIG. 11 is an example of parallel processing control when a print job is received while copying is performed by the processor core 0. In this case, the memory access load in each period is as shown in the table of FIG. 10, and the memory access load in period 2 is maximized. Control processing. Specifically, in the period 1 which is a period before the period 2, the processor core 2 is used to perform dummy execution of the print RIP process (indicated by a one-dot chain line). Here, the reception of the print data is not completed at the stage where the dummy execution of the RIP process is completed, and the actual execution of the RIP process cannot be performed unless the data reception is completed. (Denoted by a two-dot chain line). In actual execution, there is no need to read an instruction from the main memory 13 (already read in dummy execution), so that the process can be completed in a shorter time than a normal RIP process (indicated by a broken line). Thereafter, the processor core 2 that has performed dummy execution and actual execution performs image processing and VIDEO output.

  By performing such parallel processing control, it is possible to reduce the memory access load to the main memory 13 and improve the processing capability while ensuring the real-time processing. In addition, the actual execution processing time is shorter than the normal processing time, and further, the processing time of jobs other than the job to be controlled is shortened by reducing the memory access load. And a plurality of processes can be executed efficiently.

  In the above description, when the processing steps overlap, the processing step of the subsequent job is set as the control target. However, the processing step of the previous job can be set as the control target. FIG. 12 shows another example of parallel processing control when a print job is received while copying is performed by the processor core 0. If the memory access load for copy image processing is a large value (for example, “40” larger than data conversion), the memory access load in period 3 is the maximum (40 + 40 = 80). It is also possible to perform parallel processing control on the scheduled copy image processing. Specifically, dummy execution of copy image processing is performed using the processor core 2 in a period before the period 3 (here, period 1). Again, since the copy data conversion has not been completed at the stage where the dummy execution of the image processing has been completed, the actual execution of the image processing cannot be performed unless the data conversion is completed. I do. By performing such parallel processing control, it is possible to reduce the memory access load and improve the processing capability, and to ensure real-time processing.

  The case where two processes of copying and printing are processed in parallel has been described above, but the same control can be performed when three or more processes are processed in parallel. For example, when a print 1 job is received during the copy job processing and a print 2 job is received during the copy and print 1 job processing, the period defined according to the overlap of the processing steps is as follows. As shown in FIG. When the memory access load for each processing step of copying and printing is set as shown in FIGS. 6 and 8, the memory access load for each period is as shown in the table of FIG.

  In this case, since the memory access load in period 3 is the largest, parallel processing control is performed for the processing steps scheduled to be executed in period 3. For example, as shown in FIG. 15, the processor core 3 is used in a period that is a period before the period 3 (here, the memory access load is smaller in the period 1 than in the period 2). Dummy execution of RIP processing 2 for print 2 is performed. Since the data reception 2 of the print 2 is not completed when the dummy execution of the RIP process 2 is completed, the RIP process 2 is actually executed simultaneously with the start of the period 3. Thereafter, image processing 2 and VIDEO output 2 are performed by the processor core 3 that has performed dummy execution and actual execution. In this way, even when three or more jobs are processed in parallel, by performing parallel processing control on the processing steps of any job, the memory access load can be reduced and the processing capability can be improved. Real-time processing can be ensured.

  In FIG. 15, the parallel processing control of this embodiment is performed for the last job (print 2 in this case), but for the previous job (copy job or print 1 job), as in FIG. The parallel processing control of this embodiment can also be performed.

  In FIG. 15, the parallel processing control of this embodiment is performed for one job processing step. However, the parallel processing control of this embodiment may be performed for a plurality of job processing steps. For example, as shown in FIG. 16, dummy execution of the RIP process 1 for print 1 is performed using the processor core 3 in a period (period 1 in this case) before the period 3, and the processor core 4 Is used to perform a dummy execution of the RIP process 2 for print 2. Here, since the data reception 1 of the print 1 is completed when the dummy execution of the RIP process 1 is completed, the actual execution of the RIP process 1 is immediately performed. Further, since the data reception 2 of the print 2 is not completed at the stage where the dummy execution of the RIP process 2 is completed, the actual execution of the RIP process 2 is performed simultaneously with the start of the period 3. Thereafter, the processor core 3 that has performed dummy execution and actual execution performs image processing 1 and VIDEO output 1 of the print 1, and the processor core 4 performs image processing 2 and VIDEO output 2 of the print 2. In this way, when three or more jobs are processed in parallel, the parallel processing control of this embodiment is performed for the processing steps of a plurality of jobs, thereby reducing the memory access load and improving the processing capability. And real-time processing can be secured.

  In addition, this invention is not limited to the said Example, The structure and control can be changed suitably, unless it deviates from the meaning of this invention.

  For example, in the above-described embodiment, the case where copy and print are processed in parallel has been described. However, the parallel processing control of the present invention is also applied to the case where copy and FAX, print and FAX, and copy, print and FAX are processed in parallel. The same can be applied. The parallel processing control of the present invention can be similarly applied to parallel processing including processing (for example, scanning) other than copy / print / FAX.

  In the above-described embodiment, the case where the subsequent job is received during the processing of the previous job is described. However, the parallel processing control of the present invention is similarly applied to the case where a plurality of jobs are received simultaneously. be able to. In the above embodiment, copying and printing are each divided into four processing steps, but the number of divisions of processing steps is arbitrary.

  Moreover, in the said Example, although the case where the 2nd period before the 1st period existed was described, in the case where the 1st period is the earliest period, the process which becomes object in the 1st period A dummy execution of the step is performed. In this case, the timing at which the actual execution of the processing step ends is slower than when the processing step is normally executed, but the memory access load on the main memory 13 can be reduced.

  The present invention relates to an image forming apparatus including a multi-core processor composed of a plurality of processor cores, a parallel processing control program for controlling parallel processing in the image forming apparatus, a recording medium on which the parallel processing control program is recorded, and the The present invention can be used for a parallel processing control method in an image forming apparatus.

DESCRIPTION OF SYMBOLS 10 Image forming apparatus 11 Control part 11a Load calculation part 11b Period estimation part 11c Processing control part 12 Multi-core processor 12a Processor core 12b Cache memory 13 Main memory 14 Memory bus 15 HDD
16 Network I / F unit 17 Scanner unit 18 FAX control unit 19 Image forming unit 20 Operation display unit

Claims (11)

An image forming apparatus including a plurality of processor cores that hold a cache memory, and a multi-core processor in which the plurality of processor cores share one main memory,
The control unit that controls the operation of the image forming apparatus includes:
A load calculating unit that calculates a memory access load to the main memory for each period defined in accordance with an overlap of processing steps of a plurality of jobs;
A period prediction unit that predicts a first period in which the memory access load on the main memory is maximized based on the memory access load for each period;
Any one of the plurality of processing steps scheduled to be executed in the first period is performed by a processor core that has not processed the plurality of jobs in a period before the first period. A dummy execution, and after completion of the dummy execution, a processing control unit that actually executes the processing step on the processor core that performed the dummy execution ,
An image forming apparatus. The process control unit performs the dummy execution and the actual execution for a process step of a job after the plurality of process steps scheduled to be executed in the first period.
The image forming apparatus according to claim 1. The load calculation unit calculates a memory access load for each period based on memory access load information set in advance for each processing step of each job;
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. When the plurality of jobs are a copy job and a print job, and the data conversion in the copy job and the RIP process in the print job overlap, the period predicting unit determines a period in which the processes overlap as the first period. To judge,
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The period predicting unit predicts the first period at the start of receiving a new job.
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The processing control unit performs the dummy execution before the first period and during a second period in which the memory access load is minimum.
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The processing control unit controls switching between the dummy execution and the actual execution using a flag.
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The dummy execution is an execution form in which an instruction corresponding to a job is read from the main memory and stored in the cache memory, and the actual execution is performed by reading the data corresponding to the job from the main memory and reading the data , And an execution mode for executing the instruction stored in the cache memory.
The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. The processing control unit executes the instruction without referring to the data in the dummy execution of the processing step.
The image forming apparatus according to claim 8 .   A parallel processing control program that operates in an image forming apparatus that includes a plurality of processor cores that hold cache memory, and the plurality of processor cores includes a multi-core processor that shares one main memory,
  In the image forming apparatus,
  A first process for calculating a memory access load to the main memory for each period defined in accordance with an overlap of processing steps of a plurality of jobs;
  A second process for predicting a first period in which the memory access load on the main memory is maximized based on the memory access load for each period;
  Any one of the plurality of processing steps scheduled to be executed in the first period is performed by a processor core that has not processed the plurality of jobs in a period before the first period. Performing a dummy execution, and after the dummy execution is completed, causing the processing step to execute a third process that is actually executed by the processor core that performed the dummy execution.
  A parallel processing control program characterized by that.   A parallel processing control method in an image forming apparatus having a plurality of processor cores that hold a cache memory, and wherein the plurality of processor cores includes a multi-core processor that shares one main memory,
  A first process for calculating a memory access load to the main memory for each period defined in accordance with an overlap of processing steps of a plurality of jobs;
  A second process for predicting a first period in which the memory access load on the main memory is maximum based on the memory access load for each period;
  Any one of the plurality of processing steps scheduled to be executed in the first period is performed by a processor core that has not processed the plurality of jobs in a period before the first period. Performing a dummy execution, and after the dummy execution is completed, execute the processing step and a third process that is actually executed by the processor core that performed the dummy execution.
  The parallel processing control method characterized by the above-mentioned.

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