JP6453997B2 - ヘテロジニアスプロセッサシステムにおけるキャッシュ間のデータ移動 - Google Patents

ヘテロジニアスプロセッサシステムにおけるキャッシュ間のデータ移動 Download PDF

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JP6453997B2
JP6453997B2 JP2017506322A JP2017506322A JP6453997B2 JP 6453997 B2 JP6453997 B2 JP 6453997B2 JP 2017506322 A JP2017506322 A JP 2017506322A JP 2017506322 A JP2017506322 A JP 2017506322A JP 6453997 B2 JP6453997 B2 JP 6453997B2
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cache
data items
data
moving
memory
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JP2017527027A (ja
JP2017527027A5 (enExample
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グー ジュンリ
グー ジュンリ
エム． ベックマン ブラッドフォード
エム． ベックマン ブラッドフォード
シエ ユエン
シエ ユエン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/154—Networked environment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2017506322A 2014-08-05 2015-08-04 ヘテロジニアスプロセッサシステムにおけるキャッシュ間のデータ移動 Active JP6453997B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/452,058 2014-08-05
US14/452,058 US9652390B2 (en) 2014-08-05 2014-08-05 Moving data between caches in a heterogeneous processor system
PCT/US2015/043620 WO2016022566A1 (en) 2014-08-05 2015-08-04 Moving data between caches in a heterogeneous processor system

Publications (3)

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JP2017527027A JP2017527027A (ja) 2017-09-14
JP2017527027A5 JP2017527027A5 (enExample) 2018-09-13
JP6453997B2 true JP6453997B2 (ja) 2019-01-16

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JP2017506322A Active JP6453997B2 (ja) 2014-08-05 2015-08-04 ヘテロジニアスプロセッサシステムにおけるキャッシュ間のデータ移動

Country Status (5)

Country Link
US (1) US9652390B2 (enExample)
EP (1) EP3178006B1 (enExample)
JP (1) JP6453997B2 (enExample)
KR (1) KR102479394B1 (enExample)
WO (1) WO2016022566A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108269224B (zh) 2017-01-04 2022-04-01 意法半导体股份有限公司 可重新配置的互连
US10402527B2 (en) * 2017-01-04 2019-09-03 Stmicroelectronics S.R.L. Reconfigurable interconnect
US11520913B2 (en) * 2018-05-11 2022-12-06 International Business Machines Corporation Secure execution support for A.I. systems (and other heterogeneous systems)
US11029950B2 (en) 2019-07-03 2021-06-08 International Business Machines Corporation Reducing latency of common source data movement instructions
US11593609B2 (en) 2020-02-18 2023-02-28 Stmicroelectronics S.R.L. Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks
US11531873B2 (en) 2020-06-23 2022-12-20 Stmicroelectronics S.R.L. Convolution acceleration with embedded vector decompression

Family Cites Families (17)

* Cited by examiner, † Cited by third party
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US6704842B1 (en) * 2000-04-12 2004-03-09 Hewlett-Packard Development Company, L.P. Multi-processor system with proactive speculative data transfer
US6633959B2 (en) * 2001-06-21 2003-10-14 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data
US6615322B2 (en) * 2001-06-21 2003-09-02 International Business Machines Corporation Two-stage request protocol for accessing remote memory data in a NUMA data processing system
US20040111563A1 (en) 2002-12-10 2004-06-10 Edirisooriya Samantha J. Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors
US7093080B2 (en) 2003-10-09 2006-08-15 International Business Machines Corporation Method and apparatus for coherent memory structure of heterogeneous processor systems
US7934054B1 (en) * 2005-11-15 2011-04-26 Oracle America, Inc. Re-fetching cache memory enabling alternative operational modes
US20090172353A1 (en) * 2007-12-28 2009-07-02 Optillel Solutions System and method for architecture-adaptable automatic parallelization of computing code
EP2399198A4 (en) 2009-02-17 2012-07-25 Rambus Inc COALESCENCE TECHNIQUE OF ATOMIC OPERATIONS IN MULTIPLE CHIP SYSTEMS
US20110066830A1 (en) * 2009-09-11 2011-03-17 Andrew Wolfe Cache prefill on thread migration
US8782236B1 (en) * 2009-06-16 2014-07-15 Amazon Technologies, Inc. Managing resources using resource expiration data
KR101662829B1 (ko) 2009-11-19 2016-10-05 삼성전자주식회사 다중 프로세서 및 그것의 캐시 일관성 관리 장치 및 방법
JP2012064158A (ja) * 2010-09-17 2012-03-29 Toshiba Corp メモリ管理装置及びメモリ管理方法
US9135172B2 (en) * 2012-08-02 2015-09-15 Qualcomm Incorporated Cache data migration in a multicore processing system
US9218289B2 (en) 2012-08-06 2015-12-22 Qualcomm Incorporated Multi-core compute cache coherency with a release consistency memory ordering model
US20140205012A1 (en) * 2013-01-21 2014-07-24 Mediatek Inc. Method and apparatus using software engine and hardware engine collaborated with each other to achieve hybrid video encoding
US9325639B2 (en) * 2013-12-17 2016-04-26 At&T Intellectual Property I, L.P. Hierarchical caching system for lossless network packet capture applications
US10019368B2 (en) * 2014-05-29 2018-07-10 Samsung Electronics Co., Ltd. Placement policy for memory hierarchies

Also Published As

Publication number Publication date
KR102479394B1 (ko) 2022-12-20
EP3178006B1 (en) 2021-05-19
US20160041909A1 (en) 2016-02-11
US9652390B2 (en) 2017-05-16
EP3178006A4 (en) 2018-01-24
KR20170041816A (ko) 2017-04-17
JP2017527027A (ja) 2017-09-14
WO2016022566A1 (en) 2016-02-11
EP3178006A1 (en) 2017-06-14

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