JP6439363B2 - Storage control device and control method of storage control device - Google Patents

Description

  The present invention relates to a storage control device and a control method for the storage control device.

  In the information processing apparatus, data reliability is improved by storing data and redundant data for correcting an error of the data in a plurality of disk devices as compared with a case where redundant data is not used. An information processing device including this type of disk device has a nonvolatile memory for storing command information including a write command (see, for example, Patent Document 1). Then, after writing the data to the disk device, the information processing device outputs a write completion notification to the host computer before writing the redundant data, and writes the redundant data after outputting the completion notification. Thereby, the response time for data writing is shortened. Further, even when a power failure occurs, redundant data is reproduced by accessing the disk device based on command information stored in the nonvolatile memory.

Japanese Patent Laid-Open No. 4-31146

  Incidentally, some types of SDRAM (Synchronous Dynamic Random Access Memory) mounted on an information processing apparatus have a function of detecting a command and address error caused by noise or the like and notifying the outside. However, if the storage control device that controls access to the SDRAM does not have a function of reissuing an access request in response to an error notification received from the SDRAM, it is difficult to recover from the malfunction when an error occurs. End up.

  In the storage control device and the storage control device control method disclosed herein, when the storage device detects an error in the operation instruction, the system is stopped by reissuing the operation instruction based on the error notification from the storage device. The purpose is to suppress this.

According to one aspect, a storage control device that controls access to a memory device based on an access request output from the control device includes a plurality of request holding units that respectively hold access requests output from the control device, select one of the access requests respectively held in a plurality of request holding unit, an access request is selected, and outputs to the memory device as an operation instruction for operating the memory device, if the deletion of the access request is inhibited A request selection unit that selects a target access request that is an access request for which deletion has been suppressed and outputs it to the memory device as an operation instruction; The access request is deleted from the request holding unit holding the access request selected by the selection unit, and If the instruction is received error information indicating that it contains an error from the memory device, among the plurality of request holding unit, request holding from selection by request selection unit holds the first access request has not elapsed time A request control unit for suppressing deletion of an access request from the unit.

According to another aspect, the control method of the storage control device includes a plurality of request holding units that respectively hold access requests output from the control device, and controls access to the memory device based on the access request. request selection unit which device has selects one of the access request held in a plurality of request holding unit, and outputs the access request selected, the memory device as an operation instruction for operating the memory device, the storage control When the request control unit included in the apparatus deletes the access request from the request holding unit holding the access request selected by the request selection unit when the first time has elapsed since the selection of the access request by the request selection unit, If the operation instruction is received error information indicating that it contains an error from the memory device, among the plurality of request holding unit, the request election Deletion of an access request from a request holding unit that holds a target access request that is an access request for which the first time has not elapsed since selection by the unit is suppressed. The request is selected again and output to the memory device as an operation instruction.

  In the storage control device and the storage control device control method disclosed herein, when the storage device detects an error in the operation instruction, the system is stopped by reissuing the operation instruction based on the error notification from the storage device. Can be deterred.

It is a figure which shows one Embodiment of the storage control apparatus and the control method of a storage control apparatus. It is a figure which shows another embodiment of the storage control apparatus and the control method of a storage control apparatus. It is a figure which shows an example of a structure of the signal used with the memory | storage control apparatus shown in FIG. It is a figure which shows an example of the access request holding | maintenance part shown in FIG. FIG. 5 is a diagram illustrating an example of the operation of each entry in the access request holding unit illustrated in FIG. 4. FIG. 3 is a diagram illustrating an example of a refresh request holding unit illustrated in FIG. 2. FIG. 7 is a diagram illustrating an example of an entry operation of the refresh request holding unit illustrated in FIG. 6. It is a figure which shows an example of the state transition of the state control part shown in FIG. 4 and FIG. It is a figure which shows an example of operation | movement of the request | requirement selection part shown in FIG. It is a figure which shows an example of the pipeline control part shown in FIG. It is a figure which shows an example of the request issue release notification production | generation part shown in FIG. It is a figure which shows an example of the error detection part shown in FIG. It is a figure which shows an example of the transition of the mode information by the retry control part shown in FIG. FIG. 3 is a diagram illustrating an example of an operation at the time of receiving command parity error information in the storage controller illustrated in FIG. It is a figure which shows an example of operation | movement of step S400 shown in FIG. It is a figure which shows an example of operation | movement of step S500 shown in FIG. FIG. 3 is a diagram illustrating an example of an operation of the storage control device illustrated in FIG. 2. FIG. 3 is a diagram illustrating an example of an operation of the storage control device illustrated in FIG. 2. FIG. 18 is a diagram showing a continuation of the operation of FIG. 17. It is a figure which shows the continuation of the operation | movement of FIG. It is a figure which shows an example of operation | movement of the pipeline control part shown in FIG. It is a figure which shows another embodiment of the storage control apparatus and the control method of a storage control apparatus. It is a figure which shows an example of the access request holding | maintenance part shown in FIG. FIG. 24 is a diagram illustrating an example of the operation of each entry in the access request holding unit illustrated in FIG. 23. It is a figure which shows an example of the refresh request holding | maintenance part shown in FIG. FIG. 26 is a diagram illustrating an example of an entry operation of the refresh request holding unit illustrated in FIG. 25. It is a figure which shows an example of the state transition of the state control part shown to FIG. 23 and FIG. It is a figure which shows an example of the pipeline control part shown in FIG. It is a figure which shows an example of the request issue release notification production | generation part shown in FIG. It is a figure which shows an example of the error detection part shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a storage control device and a control method of the storage control device. A storage control device 100 illustrated in FIG. 1 is connected between the control device 200 and the storage device 300, and controls access to the storage device 300 based on a memory access request MRQ output from the control device 200. For example, the storage control device 100, the control device 200, and the storage device 300 are included in a system such as an information processing device.

  The control device 200 is a controller such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The storage device 300 is a semiconductor memory such as SDRAM or SRAM (Static Random Access Memory). Note that the storage device 300 may be in the form of a memory module.

  The storage control device 100 includes a plurality of request holding units 110 (110a, 110b, 110c), a request selection unit 120, an output generation unit 130, and a request control unit 140. Each of the request holding units 110a, 110b, and 110c holds a memory access request MRQ output from the control device 200 in order to access the storage device 300.

  The request selection unit 120 selects any one of the memory access requests MRQ held in the request holding units 110a, 110b, and 110c. Although not particularly limited, the request selection unit 120 suppresses selection of the memory access request MRQ while receiving the error information ERR indicating that the error of the command CMD generated by the output generation unit 130 has been detected from the storage device 300. To do. The command CMD is an example of an operation instruction for operating the storage device 300.

  Based on the memory access request MRQ selected by the request selection unit 120, the output generation unit 130 generates a command CMD for operating the storage device 300 and error detection information P for causing the storage device 300 to detect an error in the command CMD. To the storage device 300. The request control unit 140 deletes the memory access request MRQ selected by the request selection unit 120 from any of the request holding units 110 when the first time T1 has elapsed from the selection of the memory access request MRQ by the request selection unit 120. . When the request control unit 140 receives the error information ERR from the storage device 300, the request control unit 140 receives the memory access request MRQ from which the first time T1 has not elapsed since the selection by the request selection unit 120. Suppress deletion of access requests.

  In the lower brackets in FIG. 1, an example of the operation of the storage control device 100 is shown. In this example, control device 200 sequentially outputs memory access requests MRQa, MRQb, and MRQc to storage control device 100. The storage control device 100 holds the memory access requests MRQa, MRQb, and MRQc in the request holding unit 110 (FIGS. 1A, 1B, and 1C).

  The request selection unit 120 selects the memory access request MRQa held in the request holding unit 110a and outputs it to the output generation unit 130 and the request control unit 140 (FIG. 1 (d)). The output generation unit 130 generates a command CMD and error detection information P based on the memory access request MRQa, and outputs it to the storage device 300 (FIG. 1 (e)). For example, the error detection information P is a logical parity of a control signal representing the command CMD. The output generation unit 130 may generate the error detection information P from the command CMD and the address supplied from the storage control device 100 to the storage device 300 together with the command CMD. Further, the request selection unit 120 may have the function of the output generation unit 130.

  The storage device 300 detects that there is no error in the command CMD based on the error detection information P, and operates according to the command CMD. When the command CMD is a write command, the storage device 300 writes the write data received from the control device 200 via the storage control device 100 to the memory cell. When the command CMD is a read command, the storage device 300 reads data from the memory cell and outputs the read data to the control device 200 via the storage control device 100.

  After the request selection unit 120 selects the memory access request MRQa, the request control unit 140 outputs a deletion instruction DEL for deleting the memory access request MRQa from the request holding unit 110a based on the elapse of the first time T1 ( FIG. 1 (f)). The request holding unit 110a deletes the memory access request MRQa based on the deletion instruction DEL. Then, the request holding unit 110a can hold a new memory access request MRQ from the control device 200 (FIG. 1 (g)).

  Next, the request selection unit 120 selects the memory access request MRQb held in the request holding unit 110b and outputs it to the output generation unit 130 and the request control unit 140 (FIG. 1 (h)). The output generation unit 130 generates a command CMD and error detection information P based on the memory access request MRQb, and outputs it to the storage device 300 (FIG. 1 (i)). Similarly, the request selection unit 120 selects the memory access request MRQc held in the request holding unit 110c and outputs it to the output generation unit 130 and the request control unit 140 (FIG. 1 (j)). The output generation unit 130 generates a command CMD and error detection information P based on the memory access request MRQc, and outputs it to the storage device 300 (FIG. 1 (k)).

  The storage device 300 detects an error in the command CMD corresponding to the memory access request MRQb based on the error detection information P, and outputs error information ERR (FIG. 1 (l)). For example, the request selection unit 120 suppresses selection of the memory access request MRQ while receiving the error information ERR. As a result, it is possible to prevent a command CMD error from occurring and supply a new command CMD to the storage device 300 that has stopped the access operation, and to prevent malfunctions of the storage control device 100 and the storage device 300. can do.

  When receiving the error information ERR, the request control unit 140 suppresses deletion of the memory access requests MRQb and MRQc from which the first time T1 has not elapsed since the selection by the request selection unit 120 from the request holding units 110b and 110c. (FIG. 1 (m), (n)). That is, the request control unit 140 does not output a deletion instruction DEL for instructing deletion of the memory access requests MRQb and MRQc (FIG. 1 (m)). For this reason, the request holding units 110b and 110c continue to hold the memory access requests MRQb and MRQc, which are target access requests to be suppressed that are deleted (FIG. 1 (o) and (p)).

  After the output of the error information ERR is stopped, the request selection unit 120 selects the memory access request MRQb whose deletion is suppressed (FIG. 1 (q)). The output generation unit 130 generates a command CMD and error detection information P based on the memory access request MRQb, and outputs it to the storage device 300 (FIG. 1 (r)). The storage device 300 detects that there is no error in the command CMD based on the error detection information P, and operates according to the command CMD.

  The request control unit 140 deletes the memory access request MRQb from the request holding unit 110b after the first time T1 has elapsed from the selection of the memory access request MRQb by the request selection unit 120 (FIG. 1 (s)). As a result, the request holding unit 110b can hold a new memory access request MRQ from the control device 200.

  Similarly, the request selection unit 120 selects the memory access request MRQc whose deletion is suppressed, and the output generation unit 130 generates a command CMD and error detection information P based on the memory access request MRQc, and stores them in the storage device 300. It outputs (FIG. 1 (t), (u)). Then, after the first time T1 has elapsed from the selection of the memory access request MRQc by the request selection unit 120, the memory access request MRQc is deleted from the request holding unit 110b (FIG. 1 (v)).

  As described above, in FIG. 1, when the storage device 300 detects an error in the command CMD, the memory access requests MRQb and MRQc selected by the request selection unit 120 are deleted even after the first time T1 has elapsed. Without being held in the request holding units 110b and 110c. As a result, the storage control device 100 can reissue (retry) the memory access requests MRQb and MRQc that have not been executed in the storage device 300. As a result, the system including the storage control device 100, the control device 200, and the storage device 300 can be continued without stopping the operation. That is, it is possible to prevent a decrease in system reliability, and it is possible to improve system performance.

  FIG. 2 shows another embodiment of the storage control device and the control method of the storage control device. In FIG. 2, double square marks indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used. Note that description of I / O (Input / Output) circuits such as buffer circuits connected to external terminals is omitted.

  The storage control device MAC shown in FIG. 2 includes an access request holding unit 10, a refresh control unit 12, a refresh request holding unit 14, a request selection unit 16, an access signal generation unit 18, a pipeline control unit 20, and a request issue release notification generation unit. 22. The storage control device MAC includes an error detection unit 24, a write data control unit 26, a read data control unit 28, and a data input / output unit 30.

  The storage controller MAC is connected between a CPU and a DIMM (Dual Inline Memory Module). The DIMM includes a plurality of SDRAMs. The SDRAM has a plurality of dynamic memory cells connected to word lines and bit lines. The SDRAM may include a plurality of banks. An SDRAM and a DIMM are examples of storage devices whose access is controlled by the storage control device MAC based on an access request. The CPU is an example of a control device that outputs an access request for accessing an SDRAM (DIMM). The CPU, the storage control device MAC, and the DIMM are included in a system such as an information processing device.

  Based on the memory access request MRQ from the CPU, the storage controller MAC outputs the command CMD, the address AD, and the command CMD and the parity P of the address AD to the SDRAM, and controls access to the SDRAM. The command CMD includes a chip address signal, a clock enable signal, a row address strobe signal, a column address strobe signal, and a write enable signal. The command CMD is an example of an operation instruction for operating the SDRAM and the DIMM.

  The CPU may be a single core type or a multi-core type. A plurality of CPUs may be connected to the storage controller MAC, and a bus master such as a DSP or a direct memory access controller (DMAC) may be connected to the storage controller MAC.

  The SDRAM is designed according to, for example, DDR4 (Double Data Rate 4) SDRAM standard. The SDRAM has a function of outputting the command parity error information CAPE for a predetermined period when the error of the command CMD or the address AD is detected based on the parity P, and suppressing the execution of the memory access operation based on the command CMD.

  The command parity error information CAPE is, for example, 1 bit and does not include information for identifying the command CMD and the address AD in which the parity error has occurred. For this reason, the storage controller MAC has been output from the request selection unit 16 when the command parity error information CAPE is received, and all the command CMDs for which the access operation has not started are affected by the occurrence of the parity error. It is determined that the command is CMD. The storage controller MAC reissues (retrys) the command CMD determined to be affected by the occurrence of the parity error after the output of the command parity error information CAPE is stopped. The reissue process (retry process) associated with the occurrence of the command parity error information CAPE will be described with reference to FIGS.

  Note that the SDRAM may be designed according to the DDR3 SDRAM standard. In this case, the DIMM has a function of outputting the command parity error information CAPE when the error of the command CMD or the address AD is detected based on the parity P, and causing the SDRAM to suppress the execution of the access operation based on the command CMD. .

  In FIG. 2, the storage controller MAC is connected to four DIMMs, but the number of connected DIMMs may be one or two. For example, the data bus width of each DIMM is 64 bits, and the data bit width of four DIMMs is 256 bits. When storing the parity (for example, 8 bits) of data in the SDRAM in the DIMM, a 72-bit wide DIMM is used. Note that the storage controller MAC may be directly connected to the SDRAM.

  The access request holding unit 10 has a plurality of entries ENT that hold a memory access request MRQ from the CPU, and outputs access request information ARQI indicating the memory access request MRQ held in each entry ENT to the request selection unit 16. Each entry ENT is an example of a request holding unit that holds a memory access request MRQ output from the CPU.

  Each entry ENT detects that the request selection unit 16 has selected the memory access request MRQ based on the access request issue notification ARQS. Each entry ENT deletes the access request information ARQI held in the entry ENT based on the access request completion notification ARQE indicating that the memory access request MRQ has been accepted by the SDRAM. Further, each entry ENT maintains the output of the access request information ARQI in order to retry the command CMD (write command or read command) when the command parity error information CAPE is received from the SDRAM. An example of the access request holding unit 10 is shown in FIG. 4, and an example of the operation of the entry ENT of the access request holding unit 10 is shown in FIG.

  The refresh control unit 12 outputs a refresh request RRQ for causing the SDRAM to perform a refresh operation at a predetermined cycle. The refresh request holding unit 14 has one entry ENTR that holds the refresh request RRQ, and outputs refresh request information RRQI indicating the refresh request RRQ held in the entry ENTR to the request selecting unit 16. The entry ENTR deletes the refresh request information RRQI held in the entry ENTR based on the refresh request completion notification RRQE indicating that the refresh request RRQ has been accepted by the SDRAM. Furthermore, when the entry ENTR receives the command parity error information CAPE from the SDRAM, the entry ENTR maintains the output of the refresh request information RRQI in order to retry the command CMD (refresh command). An example of the refresh request holding unit 14 is shown in FIG. 6, and an example of the operation of the entry ENTR is shown in FIG.

  The request selection unit 16 selects either access request information ARQI or refresh request information RRQI, and outputs it as issue request information RQINF. The request selection unit 16 outputs issue request information RQINF indicating a precharge request based on the retry control request RTRQ. Thereafter, in order to retry the command CMD, the request selection unit 16 outputs issuance request information RQINF indicating either the access request information ARQI or the refresh request information RRQI.

  The request selection unit 16 determines the output timing of the issue request information RQINF indicating the precharge request and the issue request information RQINF indicating the retry request (memory access request MRQ or refresh request RRQ) based on the mode information MD. An example of the operation of the request selection unit 16 is shown in FIG. The precharge request is converted into a precharge command by the access signal generator 18. The SDRAM resets the word line and precharges the bit line to a predetermined voltage based on the precharge command.

  The access signal generation unit 18 generates a command CMD and an address AD that cause the SDRAM to execute an access operation based on the issue request information RQINF, and outputs the command CMD and the address AD to the SDRAM. The access signal generation unit 18 includes a parity generator PGEN that generates at least one parity P of the command CMD and the address AD, and outputs the generated parity P together with the command CMD and the address AD to the SDRAM. The parity P is an example of error detection information that causes the SDRAM to detect an error in the command CMD. The access signal generation unit 18 is an example of an output generation unit that generates a command CMD.

  Although not particularly limited, when the issue request information RQINF indicates a write request for writing data to the SDRAM, the access signal generation unit 18 sequentially outputs an active command and a write command with auto precharge to the SDRAM. As a result, after the write operation in response to the write request, the SDRAM enters a precharged standby state.

  When the issue request information RQINF indicates a read request for reading data from the SDRAM, the access signal generator 18 sequentially outputs an active command and a read command with auto precharge to the SDRAM. As a result, after the read operation in response to the read request, the SDRAM enters a precharged standby state.

  When the issue request information RQINF indicates a refresh request, the access signal generator 18 outputs an auto-refresh command to the SDRAM. The SDRAM that has received the auto-refresh command uses the built-in refresh address counter to execute the refresh operation without receiving the refresh address, and returns to the standby state. By the refresh operation, data held in the dynamic memory cell in the SDRAM is rewritten, and the data is held in the dynamic memory cell without being lost.

  In this way, the storage controller MAC supplies a write request, a read request, or a refresh request to the standby SDRAM. When retrying a write request, a read request or a refresh request, the storage controller MAC supplies a precharge command to the SDRAM in order to set the SDRAM to a standby state. Thereby, even when the SDRAM is in an active state upon receiving an active command, the retry operation of the SDRAM can be correctly executed. The retry operation and retry precharge command will be described with reference to FIG. Since the storage controller MAC accesses the SDRAM using a write command and a read command with auto precharge, it does not use the precharge command except for retry.

  After receiving the issuance request information RQINF from the request selection unit 16, the pipeline control unit 20 has a sequencer function that outputs a control signal for controlling the operation of each unit in the storage control device MAC every predetermined clock cycle. Have. When the issue request information RQINF is a write request, the pipeline control unit 20 sequentially outputs an access request completion notification ARQE, a write data request WDRQ, and a write data control signal WDCNT. When the issue request information RQINF is a read request, the pipeline control unit 20 sequentially outputs an access request completion notification ARQE, a read data control signal RDCNT, a valid signal VLD (R), and a request identification number RQID (R). When the issue request information RQINF is a normal refresh request, the pipeline control unit 20 outputs a refresh request completion notification RRQE. When the issue request information RQINF indicates a precharge command based on the retry control request RTRQ, the pipeline control unit 20 outputs a retry control request completion notification RTRQE. Further, the pipeline control unit 20 has a function of detecting an access request to be retried and a refresh request to be retried based on the command parity error information CAPE. An example of the pipeline control unit 20 is shown in FIG.

  Based on the issue request information RQINF, the request issue release notification generation unit 22 outputs an access request issue notification ARQS or a refresh request issue notification RRQS indicating that the command CMD is output to the SDRAM. Further, the request issuance release notification generation unit 22 outputs memory access request release information MRQR indicating that the memory access request MRQ has been accepted by the SDRAM to the CPU based on the access request completion notification ARQE. When the access request completion notification ARQE is not generated by receiving the command parity error information CAPE, the request issue release notification generation unit 22 suppresses the output of the memory access request release information MRQR to the CPU. Thereby, the CPU can suppress erroneous recognition that the access operation corresponding to the memory access request MRQ not accepted by the SDRAM is started (that is, malfunction). An example of the request issuance release notification generator 22 is shown in FIG.

  Based on the command parity error information CAPE and the retry control request completion notification RTRQE, the error detection unit 24 outputs a retry control request RTRQ for controlling the retry of the command and mode information MD indicating the mode controlled by the error detection unit 24. . The retry control request RTRQ (precharge request) is output corresponding to the memory access request MRQ or the refresh request RRQ in which the state ST shown in FIG. 8 is “issued”. The error detection unit 24 is an example of a standby request generation unit that generates a standby request (precharge request) for setting the SDRAM to a standby state (precharge state) after output of the command parity error information CAPE from the SDRAM is stopped. It is.

  Further, the error detection unit 24 outputs the system error information SYSE to the CPU when the number of occurrences of the command parity error information CAPE (that is, the number of retries) reaches a predetermined value VT. For example, when the command line CMD wired between the storage controller MAC and the DIMM is disconnected or short-circuited, the command parity error information CAPE is repeatedly generated. In this case, the CPU can detect a failure based on the system error information SYSE, and can suppress a decrease in system reliability.

  The write data control unit 26 outputs the write data WD output from the CPU to the DIMM via the data input / output unit 30 based on the write data control signal WDCNT. For example, the write data control unit 26 receives the 1024-bit (128 bytes) write data WD from the CPU divided into four times, and outputs the received write data WD into four DIMMs (burst length). = 4). When writing the parity of the write data to the DIMM together with the write data WD, the write data control unit 26 may include a parity generator that generates the parity.

  The read data control unit 28 outputs read data RDT received from the DIMM via the data input / output unit 30 to the CPU based on the read data control signal RDNT. For example, the read data control unit 28 receives 1024 bits (8 bytes) of read data RDT in four times from four DIMMs (burst length = 4), and the received read data RDT is divided into four times in the CPU. Output to. When the parity is received from the DIMM together with the read data RDT, the read data control unit 28 may include a circuit that detects an error in the read data RDT based on the parity and corrects the error.

  The data input / output unit 30 outputs write data WD to the DIMM via the data terminal DT at the time of DIMM write access, and receives read data RDT from the DIMM via the data terminal DT at the time of read access to the DIMM.

  FIG. 3 shows an example of the configuration of signals used in the storage controller MAC shown in FIG. The valid VLD is set to logic 1 when each signal is valid, and is set to logic 0 when each signal is invalid. The request identification number RQID is a unique number for identifying each memory access request MRQ, and is assigned by the CPU. The write data identification number WDID is a unique number for identifying write data for each memory access request MRQ indicating a write request, and is assigned by the CPU. The state ST of the access request information ARQI indicates the state of each entry ENT in the access request holding unit 10. The state ST of the refresh request information RRQI indicates the state of the entry ENTR of the refresh request holding unit 14. An example of the transition of the state ST of the access request holding unit 10 and the refresh request holding unit 14 is shown in FIG.

  In the memory access request MRQ, the command indicates a write command or a read command, and the address indicates the head address of the memory space to be accessed. In the refresh request RRQ, the command indicates a refresh command, and the address indicates the start address of the memory space to be refreshed. In the retry control request RTRQ, the command indicates a write command, a read command, or a refresh command to be retried, and the address indicates a memory space to be accessed or an address space to be refreshed.

  In the issue request information RQINF, the command indicates a write command, a read command, or a refresh command, and the address indicates a memory space to be accessed or an address space to be refreshed. In the read data RD, the request identification number RQID is output to the CPU for association with the memory access request MRQ (read request) issued by the CPU. In the write data request WDRQ, the write data identification number WDID is used to identify the write data requested by the storage control device MAC to the CPU.

  FIG. 4 shows an example of the access request holding unit 10 shown in FIG. The access request holding unit 10 has n entries (ENT1, ENT2, ENT3,..., ENTn) (n is an integer of 2 or more). Since the entries ENT are the same or similar to each other, the configuration of the entry ENT1 will be described below.

  The entry ENT1 has a holding area HLD that holds the valid VLD, command, address, request identification number RQID, and write data identification number WDID included in the memory access request MRQ. The entry ENT1 includes a state control unit STCNT having an area for holding the state ST. The state control unit STCNT changes the state ST based on reception of the memory access request MRQ, the access request issue notification ARQS, the command parity error information CAPE, and the access request completion notification ARQE. An example of the transition of the state ST is shown in FIG. When receiving the memory access request MRQ from the CPU, the access request holding unit 10 holds the received memory access request MRQ in one of the entries ENT1 whose state ST is in the idle state. The entry ENT1 outputs access request information ARQI indicating the held valid VLD, command, address, request identification number RQID, write data identification number WDID, and state ST to the request selection unit 16. An example of the operation of each entry ENT in the access request holding unit 10 is shown in FIG.

  FIG. 5 shows an example of the operation of each entry ENT of the access request holding unit 10 shown in FIG. For example, the process shown in FIG. 5 is executed by the hardware of the state control unit STCNT of each entry ENT. Note that FIG. 5 is an exploded view of the operation of each entry ENT for easy understanding of the description. In an actual operation, some of the steps may be executed in parallel. For example, steps S104 and S106 may be executed in parallel, and steps S118 and S120 may be executed in parallel.

  First, in step S102, the entry ENT determines whether or not the access request holding unit 10 has instructed to hold the memory access request MRQ. The entry ENT shifts the process to step S104 when instructed to hold the memory access request MRQ, and repeats the process of step S102 when not instructed to hold the memory access request MRQ.

  In step S104, the entry ENT holds the valid VLD, command, address, request identification number RQID, and write data identification number WDID included in the memory access request MRQ in the holding area HLD. In the valid VLD area of the holding area HLD, a logic 1 indicating the holding of a valid memory access request MRQ is stored.

  Next, in step S106, the entry ENT rewrites the state ST with information indicating “unissued”. “Not issued” indicates that the memory selection request MRQ held in the entry ENT is not selected by the request selection unit 16. That is, “unissued” indicates that the memory access request MRQ held in the entry ENT is not supplied to the DIMM.

  Next, in step S108, the entry ENT determines whether or not an access request issue notification ARQS corresponding to the memory access request MRQ held in the entry ENT has been received. If the entry ENT receives the corresponding access request issue notification ARQS, the entry ENT shifts the process to step S110. If the entry ENT does not receive the corresponding access request issue notification ARQS, the entry ENT repeats the process of step S108.

  In step S110, the entry ENT rewrites the state ST with information indicating “issued”. “Issued” indicates that the memory selection request MRQ held in the entry ENT is selected by the request selection unit 16. That is, “issued” indicates that the memory access request MRQ held in the entry ENT is supplied to the DIMM.

  Next, in step S112, the entry ENT determines whether or not the command parity error information CAPE has been received. If the entry ENT receives the command parity error information CAPE, the process proceeds to step S114. If the entry ENT does not receive the command parity error information CAPE, the process proceeds to step S116.

  In step S114, the entry ENT rewrites the state ST with information indicating “retry”, and returns the process to step S108. “Retry” indicates that the memory access request MRQ held in the entry ENT is reissued to the DIMM when the command parity error information CAPE is generated.

  The memory access request MRQ that has not received the access request completion notification ARQE after receiving the access request issue notification ARQ is a memory access request MRQ that is not accepted by the SDRAM. When the SDRAM detects a command parity error before receiving the memory access request MRQ and outputs the command parity error information CAPE, the memory access request MRQ becomes a target of retry.

  If the command parity error information CAPE is not received, in step S116, the entry ENT determines whether or not an access request completion notification ARQE corresponding to the memory access request MRQ held in the entry ENT has been received. When the entry ENT receives the corresponding access request completion notification ARQE, the entry ENT determines that the memory access request MRQ held in the entry ENT has been accepted by the SDRAM, and shifts the processing to step S118. On the other hand, if the entry ENT has not received the corresponding access request completion notification ARQE, the entry ENT determines that the memory access request MRQ held in the entry ENT is not accepted by the SDRAM, and returns the process to step S112. The access request completion notification ARQE is generated after a predetermined clock cycle after the request selection unit 16 outputs the issuance request information RQINF, as will be described with reference to FIG.

  In step S118, the entry ENT resets the valid VLD held in the holding unit HLD to the low level L (logic 0), and invalidates the memory access request MRQ held in the entry ENT. Next, in step S120, the entry ENT rewrites the state ST with information indicating “idle”. “Idle” indicates that the entry ENT does not hold a valid memory access request MRQ and is in a free state capable of holding a new memory access request MRQ. The entry ENT returns the process to step S102 after the process of step S120. Then, the above-described operation is repeated.

  FIG. 6 shows an example of the refresh request holding unit 12 shown in FIG. The refresh request holding unit 12 has one entry ENTR. The entry ENTR includes a valid VLD included in the refresh request RRQ, a holding unit HLD that holds a command and an address, and a state control unit STCNT having a region that holds the state ST. The state control unit STCNT changes the state ST based on reception of the refresh request RRQ, the refresh request issue notification RRQS, the command parity error information CAPE, and the refresh request completion notification RRQE. An example of the transition of the state ST is shown in FIG. The entry ENTR outputs refresh request information RRQI indicating the held valid VLD, command and address, and state ST. An example of the operation of the entry ENTR of the refresh request holding unit 12 is shown in FIG.

  FIG. 7 shows an example of the operation of the entry ENTR of the refresh request holding unit 12 shown in FIG. The same or similar operations as those shown in FIG. 5 are denoted by the same reference numerals as those in FIG. In the flow shown in FIG. 7, steps S102, S104, S108, and S116 shown in FIG. 5 are replaced with steps S102r, S104r, S108r, and S116r.

  In step S102r, the entry ENTR determines whether or not a refresh request RRQ has been received. The entry ENTR shifts the process to step S104r when receiving the refresh request RRQ, and repeats the process of step S102r when not receiving the refresh request RRQ.

  In step S104r, the entry ENTR holds the valid VLD, command, and address included in the refresh request RRQ in the holding unit HLD. In the valid VLD area of the holding area HLD, a logic 1 indicating the holding of a valid memory access request MRQ is stored. The processing in step S106 is the same as that in FIG. “Unissued” in the state ST indicates that the request selection unit 16 has not selected the refresh request RRQ held in the entry ENTR. That is, “unissued” indicates that the refresh request RRQ held in the entry ENTR is not supplied to the DIMM.

  Next, in step S108r, the entry ENTR determines whether or not a refresh request issue notification RRQS corresponding to the refresh request RRQ held in the entry ENTR has been received. If the entry ENTR receives the corresponding refresh request issuance notification RRQS, the process proceeds to step S110. If the entry ENTR has not received the corresponding refresh request issuance notification RRQS, the entry ENTR repeats the processing of step S108r.

  The process in step S110 is the same as that in FIG. The “issued” state ST indicates that the refresh request RRQ held in the entry ENTR has been selected by the request selection unit 16. That is, “issued” indicates that the refresh request RRQ held in the entry ENTR is supplied to the DIMM.

  The processes in steps S112 and S114 are the same as those in FIG. “Retry” in the state ST in step S114 indicates that the refresh request RRQ held in the entry ENT is issued again to the DIMM when the command parity error information CAPE is generated.

  The refresh request RRQ that has not received the refresh request completion notification RRQE after receiving the refresh request issue notification RRQS is a refresh request RRQ that has not been accepted by the SDRAM. When the SDRAM detects a command parity error before receiving the refresh request RRQ and outputs the command parity error information CAPE, the refresh request RRQ becomes a target of retry.

  When the command parity error information CAPE is not received, in step S116r, the entry ENTR determines whether or not a refresh request completion notification RRQE corresponding to the refresh request RRQ held in the entry ENTR has been received. When the entry ENTR receives the corresponding refresh request completion notification RRQE, it determines that the refresh request RRQ held in the entry ENT has been accepted by the SDRAM, and shifts the processing to step S118. On the other hand, if the entry ENTR has not received the corresponding refresh request completion notification RRQE, the entry ENTR determines that the refresh request RRQ held in the entry ENT is not accepted by the SDRAM, and returns the process to step S112. The processing in steps S118 and S120 is the same as that in FIG. Then, the entry ENTR returns the process to step S102r after the process of step S120.

  FIG. 8 shows an example of transition of the state ST of the state control unit STCNT shown in FIG. 4 and FIG. In FIG. 8, the underlined characters indicate the operation of the state control unit STCNT of the access request holding unit 10, and the characters in parentheses indicate the operation of the state control unit STCNT of the refresh request holding unit 14. In the following, the transition of the state ST in the state control unit STCNT of each entry ENT of the access request holding unit 10 will be described. The transition of the state ST in the state control unit STCNT of the entry ENTR of the refresh request holding unit 14 will be described by reading the following description as follows. The memory access request MRQ is read as a refresh request RRQ, the access request issuance notification ARQS is read as a refresh request issuance notification RRQS, and the access request completion notification ARQE is read as a refresh request completion notification RRQE.

  Prior to receiving the memory access request MRQ, the state control unit STCNT sets the state ST to “idle”. “Idle” is an initial state after the storage controller MAC is powered on or reset, and indicates a state of waiting for reception of the memory access request MRQ.

  When the memory access request MRQ is received during “idle”, the state control unit STCNT of the entry ENT holding the access request MRQ sets the state ST to “unissued”. “Not issued” indicates a state of waiting to receive an access request issue notification ARQS.

  When the access request issue notification ARQS is received during “not issued”, the state control unit STCNT of the entry ENT holding the memory access request MRQ corresponding to the access request issue notification ARQS sets the state ST to “issued”. . “Issued” indicates a state of waiting for reception of an access request completion notification ARQE.

  When the access request completion notification ARQE is received during “issued”, the state control unit STCNT of the entry ENT holding the memory access request MRQ corresponding to the access request completion notification ARQE returns the state ST to “idle”. On the other hand, when the command parity error information CAPE is received during “issued”, the state control unit STCNT sets the state ST to “retry”. “Retry” indicates a state of waiting for reception of an access request issue notification ARQS corresponding to the access request MRQ to be retried.

  When the access request issue notification ARQS is received during “retry”, the state control unit STCNT of the entry ENT holding the memory access request MRQ corresponding to the access request issue notification ARQS sets the state ST to “issued”.

  FIG. 9 shows an example of the operation of the request selection unit 16 shown in FIG. For example, the process illustrated in FIG. 9 is realized by the hardware of the request selection unit 16. Note that FIG. 9 is an exploded view of the operation of the request selection unit 16 for easy understanding of the description. In an actual operation, some of the steps may be executed in parallel. For example, steps S202, S208, and S210 may be executed in parallel.

  First, in step S202, the request selection unit 16 proceeds to step S204 when the mode information MD from the error detection unit 24 indicates the normal mode, and performs the process when the mode information MD does not indicate the normal mode. The process proceeds to S208.

  In step S204, the request selection unit 16 determines whether there is access request information ARQI or refresh request information RRQI including the “unissued” state ST. If there is access request information ARQI or refresh request information RRQI including the “unissued” state ST, the process proceeds to step S206. If there is no access request information ARQI and refresh request information RRQI including the “unissued” state ST, the process returns to step S202.

  In step S206, the request selection unit 16 selects one of the access request information ARQI and the refresh request information RRQI including the “unissued” state ST, and outputs it as the issue request information RQINF. That is, the access request MRQ or the refresh request RRQ is output to the DIMM, and the access operation or the refresh operation is executed. After step S206, the process returns to step S202.

  On the other hand, in step S208, the request selection unit 16 returns the process to step S202 when the mode information MD indicates the restart waiting mode, and proceeds to step S210 when the mode information MD does not indicate the restart waiting mode. As described with reference to FIG. 13, the restart wait mode is an assertion period of command parity error information CAPE in which the SDRAM prohibits acceptance of commands, and is a state of waiting for restart of output of the issue request information RQINF. For this reason, the request selection unit 16 does not select the access request MRQ or the refresh request RRQ, and the command CMD is not supplied to the SDRAM.

  In step S210, if the mode information MD indicates the pre-retry preparation mode, the request selection unit 16 proceeds to step S212. If the mode information MD does not indicate the pre-retry preparation mode, the request selection unit 16 proceeds to step S216. . If the mode information MD does not indicate the pre-retry preparation mode, the request selection unit 16 determines that the mode information MD is the retry mode.

  In step S212, if the request selection unit 16 receives a retry control request RTRQ (precharge request) from the error detection unit 24, the request selection unit 16 proceeds to step S214. If the request selection unit 16 does not receive the retry control request RTRQ, the processing is performed. It returns to step S202. In step S214, the request selection unit 16 selects a retry control request RTRQ and outputs it as issue request information RQINF. Note that the access signal generation unit 18 outputs, for example, an all-bank precharge command to the DIMM based on the issue request information RQINF corresponding to the retry control request RTRQ. All SDRAMs in the DIMM receive an all-bank precharge command, execute a precharge operation in all banks, and enter a standby state in which an active command and a refresh command can be received.

  On the other hand, in step S216, the request selection unit 16 determines whether there is access request information ARQI or refresh request information RRQI including the “retry” state ST. When there is access request information ARQI or refresh request information RRQI including the “retry” state ST, the process proceeds to step S218. If there is no access request information ARQI and refresh request information RRQI including the “retry” state ST, the process returns to step S202.

  In step S218, the request selection unit 16 selects either one of the access request information ARQI or the refresh request information RRQI including the “retry” state ST, and outputs it as issuance request information RQINF. That is, a retry process is executed in which a command that has not been executed in the SDRAM is reissued to the SDRAM due to the occurrence of a command parity error. After step S218, the process returns to step S202.

  FIG. 10 shows an example of the pipeline control unit 20 shown in FIG. The pipeline control unit 20 includes a shift register SFTR that sequentially holds the issue request information RQINF for each clock cycle. The pipeline control unit 20 includes a request completion notification generation unit RQEG, a write data request generation unit WDRQG, a write data control signal generation unit WDCNTG, a read data control signal generation unit RDCNTG, and a read data generation unit RDG.

  The shift register SFTR has a plurality of stages STG (STG1-STG28) that hold the issue request information RQINF in the order of issue. Each stage STG holds command parity error information CAPE, a write data identification number WDID, a request identification number RQID, an address AD, a command CMD, and a valid VLD included in the issue request information RQINF. Command parity error information CAPE and issue request information RQINF held in each stage STG are transferred to the next stage STG in synchronization with the clock.

  For example, after the request selection unit 16 shown in FIG. 2 selects the memory access request MRQ or the refresh request RRQ, it takes a maximum of 7 clock cycles until the command CMD corresponding to the memory access request MRQ or the refresh request RRQ is accepted by the SDRAM. That is, after the request selection unit 16 outputs the issue request information RQINF, it takes a maximum of 7 clock cycles until the SDRAM determines that there is no error in the command CMD corresponding to the issue request information RQINF. In other words, after the request selection unit 16 outputs the issuance request information RQINF, until the storage controller MAC receives the command parity error information CAPE indicating the error of the command CMD corresponding to the issuance request information RQINF, up to 7 clocks. It takes a cycle.

  Therefore, the request completion notification generation unit RQEG, based on the information held in the stage STG8 after it is determined that there is no error in the command CMD, the access request completion notification ARQE, the refresh request completion notification RRQE, or the retry control request completion notification RTRQE Is output. The retry control request completion notification RTRQE indicates that a precharge command supplied before retrying the memory access request MRQ or the refresh request RRQ is accepted by the SDRAM.

  As described above, the storage control device MAC uses the pipeline control unit 20 to determine that the command has been received by the SDRAM without receiving a command CMD reception status notification from the SDRAM. The eight clock cycles from the output of the issue request information RQINF until the command CMD is received by the SDRAM are determined based on the operation specifications of the memory control circuit MAC and the operation specifications of the DIMM and SDRAM.

  The request completion notification generation unit RQEG suppresses the output of the access request completion notification ARQE, the refresh request completion notification RRQE, and the retry control request completion notification RTRQE when the logic 1 is held in the “CAPE” area of the stage STG8. Thereby, it is possible to prevent the memory access request MRQ that is not accepted by the SDRAM from being deleted from the access request holding unit 10. Further, it is possible to prevent the refresh request RRQ that is not accepted by the SDRAM from being deleted from the refresh request holding unit 14. Furthermore, it is possible to prevent a retry control request RTRQ (precharge request) that is not received by the SDRAM from being deleted from the error detection unit 24.

  The request completion notification generation unit RQEG and the state control unit STCNT shown in FIG. 4 are examples of a request control unit that deletes the memory access request MRQ held in the holding unit HLD of the entry ENT or suppresses deletion of the memory access request MRQ. It is. Further, the request completion notification generation unit RQEG and the state control unit STCNT shown in FIG. 6 are examples of a request control unit that deletes the refresh request RRQ held in the holding unit HLD of the entry ENTR or suppresses the deletion of the refresh request RRQ. It is.

  The write data request generation unit WDRQG outputs a write data request WDRQ based on the information held in the stage STG12. Further, the write data request generation unit WDRQG suppresses the output of the write data request WDRQ when the logic 1 is held in the “CAPE” area of the stage STG12. As a result, the write data request WDRQ is output even though the SDRAM does not accept the write command, and the CPU can be prevented from outputting the write data (that is, malfunction).

  The write data control signal generation unit WDCNTG outputs a write data control signal WDCNT based on the information held in the stage STG16. Further, the write data control signal generation unit WDCNTG suppresses the output of the write data control signal WDCNT when the logic 1 is held in the “CAPE” area of the stage STG16. Thus, it is possible to prevent invalid write data from being output from the write data control unit 26 to the SDRAM (that is, malfunction) even though the SDRAM does not accept the write command.

  The read data control signal generation unit RDCNTG outputs a read data control signal RDCNT based on the information held in the stage STG24. Further, the read data control signal generation unit RDCNTG suppresses the output of the read data control signal RDCNT when the logic 1 is held in the “CAPE” area of the stage STG24. As a result, the read data control signal RDCNT is output even though the SDRAM does not accept the read command, and invalid read data is prevented from being output from the read data control unit 28 to the CPU (that is, malfunction). be able to.

  The read data generation unit RDG outputs a valid signal VLD (R) and a request identification number RQID (R) based on the information held in the stage STG28. Further, the read data generation unit RDG suppresses the output of the valid signal VLD (R) and the request identification number RQID (R) when the logic 1 is held in the “CAPE” area of the stage STG28.

  As described above, after the request selection unit 16 outputs the issue request information RQINF, the maximum time until the SDRAM receives the command parity error information CAPE indicating the error of the command CMD corresponding to the issue request information RQINF is 7 clocks. Cycle. For this reason, when the command parity error information CAPE is received before seven clock cycles have elapsed from the issue of the issue request information RQINF, the issue request information RQINF becomes a retry target. That is, when the command parity error information CAPE is received, the memory access request MRQ and the refresh request RRQ whose state ST is “issued” are subject to retry.

  In order to suppress the output of the access request completion notification ARQE and the refresh request completion notification RRQE corresponding to the issue request information RQINF to be retried, a logic circuit is inserted in the input path of the command parity error information CAPE in the stages STG1 to STG8. .

  For example, the stage STG1 receives a logic that is a logical product (AND) of the command parity error information CAPE from the DIMM and the valid VLD. Stages STG2 to STG8 receive a logical product of the logical product (AND) of the command parity error information CAPE from the DIMM and the valid VLD and the logical sum (OR) of the command parity error information CAPE from the previous stage. Stages STG9 to STG28 receive command parity error information CAPE from the previous stage.

  As a result, the output of the write data request WDRQ and the write data control signal WDCNT corresponding to the memory access request MRQ (write command) determined as the retry target can be suppressed. Further, the output of the read data control signal RDCNT, the valid signal VLD (R), and the request identification number RQID (R) corresponding to the memory access request MRQ (read command) determined to be a retry target may be suppressed. it can. An example of the operation of the pipeline control unit 20 is shown in FIG.

  FIG. 11 shows an example of the request issuance release notification generator 22 shown in FIG. The request issuance release notification generation unit 22 includes a request release notification generation unit 221 and a request issuance notification generation unit 222. The request release notification generation unit 221 outputs memory access request release information MRQR to the CPU based on the reception of the access request completion notification ARQE. That is, the memory access request release information MRQR indicating that the command CMD corresponding to the memory access request MRQ from the CPU has been received by the SDRAM is output.

  The request issuance notification generation unit 222 outputs an access request issuance notification ARQS or a refresh request issuance notification RRQS based on reception of the issuance request information RQINF. That is, the access request holding unit 10 is notified that the memory access request MRQ is supplied to the DIMM, or the refresh request holding unit 14 is notified that the refresh request RRQ is supplied to the DIMM.

  FIG. 12 shows an example of the error detection unit 24 shown in FIG. The error detection unit 24 includes a retry control unit RTCNT. When retrying the memory access request MRQ or the refresh request RRQ, the retry control unit RTCNT includes a register MDR that holds mode information MD indicating the state of the retry process, and a counter RCOUNT that counts the number of retry processes. The counter RCOUNT may be disposed outside the error detection unit 24. An example of mode transition by the register MDR is shown in FIG.

  When retrying the memory access request MRQ or the refresh request RRQ, the retry control unit RTCNT outputs a retry control request RTRQ (precharge request) to cause the SDRAM to execute a precharge operation. Further, the retry control unit RTCNT counts up the count value of the counter RCOUNT every time the command parity error information CAPE is received. Then, the retry control unit RTCNT outputs the system error information SYSE to the CPU when the number of times the command parity error information CAPE is received (that is, the number of retries) reaches a predetermined value VT. The retry control unit RTCNT is an example of a system error detecting unit that outputs system error information SYSE indicating a system error to the CPU when the count value of the counter RCOUNT reaches a predetermined value VT.

  FIG. 13 shows an example of transition of mode information MD by the retry control unit RTCNT shown in FIG. Before receiving the command parity error information CAPE, the retry control unit RTCNT sets the mode information MD to the normal mode. The normal mode is an initial state after power-on or reset of the storage control device MAC, and indicates a state where no retry process has occurred.

  When the command parity error information CAPE is received during the normal mode, the retry control unit RTCNT changes the mode information MD to the restart waiting mode. The output of the issue request information RQINF is suppressed during “waiting for resumption”. The resumption waiting mode is a state until the asserted command parity error information CAPE is negated, and is a state of waiting for resumption of output of the issue request information RQINF.

  When the command parity error information CAPE is negated during the restart waiting mode, the retry control unit RTCNT shifts the mode information MD to the pre-retry preparation mode. The pre-retry preparation mode is a state in which the operation state of the SDRAM is reset (precharged) before executing the retry process.

  When the retry control request completion notification RTRQE is received during the pre-retry preparation mode, the retry control unit RTCNT changes the mode information MD to the retry mode. That is, when the precharge operation of the SDRAM is completed, the retry control unit RTCNT transitions the mode information MD to the retry mode in order to retry the memory access request MRQ or the refresh request RRQ. When the retry of the memory access request MRQ or the refresh request RRQ is completed during the retry mode, the retry control unit RTCNT changes the mode information MD to the normal mode.

  FIG. 14 shows an example of the operation at the time of receiving the command parity error information CAPE in the storage controller MAC shown in FIG. FIG. 14 shows the overall operation of the storage controller MAC. FIG. 14 shows the operation of the storage control device MAC in an exploded manner for easy understanding of the description. In an actual operation, some of the steps may be executed in parallel.

  First, in step S302, if the command parity error information CAPE is asserted to a high level H, the storage controller MAC moves the process to step S400. When the command parity error information CAPE is not asserted (low level), the storage controller MAC repeats step S302. In step S400, the storage control device MAC executes the state ST setting operation of the state control unit STCNT shown in FIG. 4 and FIG. An example of step S400 is shown in FIG.

  Next, in step S306, the storage control device MAC counts up the count value of the counter RCOUNT of the error detection unit 24 shown in FIG. Next, in step S308, the storage control device MAC stores mode information MD indicating the restart waiting mode in the mode register MDR of the error detection unit 24.

  Next, in step S310, the storage controller MAC waits for the command parity error information CAPE to be negated to a low level L. If the command parity error information CAPE is negated, the process proceeds to step S312. The assertion period of the command parity error information CAPE is a period in which the SDRAM does not accept a command.

  In step S312, the storage controller MAC stores the mode information MD indicating the pre-retry preparation mode in the mode register MDR of the error detection unit 24. Next, in step S314, the storage control device MAC issues a retry control request RTRQ from the error detection unit 24, and causes the SDRAM to execute a precharge operation.

  Next, in step S316, when the command parity error information CAPE is asserted to the high level H (when CAPE is continuously generated), the storage controller MAC moves the process to step S332. If the command parity error information CAPE is not asserted, the storage controller MAC moves the process to step S318.

  In step S318, when the retry control request completion notification RTRQE is generated, the storage control device MAC shifts the processing to step S320 because the precharge command is accepted by the SDRAM. When the retry control request completion notification RTRQE does not occur, the storage controller MAC returns the process to step S316.

  In step S320, the storage control device MAC stores mode information MD indicating the retry mode in the mode register MDR of the error detection unit 24.

  Next, in step S500, the storage controller MAC executes a retry process for the memory access request MRQ or the refresh request RRQ. An example of step S500 is shown in FIG.

  Next, in step S324, if the command parity error information CAPE is asserted to a high level H (generation of CAPE for the retry command MCD), the storage controller MAC moves the process to step S332. If the command parity error information CAPE is not asserted, the storage controller MAC moves the process to step S326.

  In step S326, the storage control device MAC shifts the processing to step S328 when all the retry processing is completed, and shifts the processing to step S500 when there is a retry processing that has not been executed. In step S328, the storage controller MAC resets the count value of the counter RCOUNT to an initial value such as “0”. Next, in step S330, the storage control device MAC stores mode information MD indicating the normal mode in the mode register MDR of the error detection unit 24, and returns the process to step S302.

  On the other hand, in step S322, the storage control device MAC determines whether or not the count value of the counter RCOUNT has reached the threshold value VT. When the count value reaches the threshold value VT, the storage controller MAC shifts the processing to step S334. If the count value has not reached the threshold value VT, the storage controller MAC returns the process to step S400.

  In step S334, the storage controller MAC outputs system error information SYSE indicating that the operation of the SDRAM or DIMM is not normal to the CPU, and ends the operation.

  FIG. 15 shows an example of the operation in step S400 shown in FIG. First, in step S402, the storage controller MAC initializes the variable k to “1”. Next, in step S404, the storage controller MAC determines whether or not the state ST of the kth entry ENTk is “issued” in the access request holding unit 10. If the state ST of the kth entry ENTk is “issued”, the process proceeds to step S406 in order to retry the memory access request MRQ. If the state ST of the kth entry ENTk is not “issued”, the process proceeds to step S408 because the memory access request MRQ is not a retry target.

  In step S406, the storage controller MAC sets the state ST of the kth entry ENTk to “retry” in order to retry the memory access request MRQ, and the process proceeds to step S408. In step S408, the storage controller MAC increases the variable k by “1”, and the process proceeds to step S410.

  In step S410, if the variable k exceeds the number n of entries ENT, the storage controller MAC shifts the process to step S412. If the variable k is equal to or less than the number n of entries ENT, the storage control device MAC shifts the process to step S404. .

  In step S412, the storage control device MAC determines whether or not the state ST of the entry ENTR of the refresh request holding unit 14 is “issued”. If the state ST of the entry ENTR is “issued”, the process proceeds to step S414 to retry the refresh request RRQ. If the state ST of the entry ENTR is not “issued”, the operation ends because there is no refresh request RRQ to be retried.

  In step S414, the storage controller MAC sets the state ST of the entry ENTR to “retry” in order to retry the refresh request RRQ, and ends the operation.

  FIG. 16 shows an example of the operation in step S500 shown in FIG. First, in step S502, the storage control device MAC moves the process to step S504 when an access request issue notification ARQS occurs, and moves the process to step S506 if no access request issue notification ARQS occurs.

  In step S504, the storage control device MAC sets the state ST of the corresponding entry ENT holding the same request identification number RQID as the request identification number RQID included in the generated access request issue notification ARQS to “issued”. After step S504, the storage controller MAC moves the process to step S510.

  In step S506, the storage control device MAC moves the process to step S508 when the refresh request issue notification RRQS occurs, and moves the process to step S510 when the refresh request issue notification RRQS does not occur. In step S508, the storage controller MAC sets the state ST of the entry ENTR of the refresh request holding unit 14 to “issued”, and the process proceeds to step S510.

  In step S510, when the access request completion notification ARQE occurs, the storage controller MAC shifts the process to step S512, and when the access request completion notification ARQE does not occur, the storage control device MAC shifts the process to step S516.

  In step S512, the storage controller MAC sets the state ST of the corresponding entry ENT holding the same request identification number RQID as the request identification number RQID included in the generated access request completion notification ARQE to “idle”. Next, in step S514, the storage controller MAC sets the valid VLD of the entry ENT in which the state ST is set to “idle” to logic 0, deletes the memory access request MRQ, and ends the operation.

  In step S516, if the refresh request completion notification RRQE has occurred, the storage controller MAC proceeds to step S518, and if the refresh request completion notification RRQE has not occurred, the storage controller MAC ends the operation. In step S518, the storage controller MAC sets the state ST of the entry ENTR of the refresh request holding unit 14 to “idle”, and the process proceeds to step S520.

  In step S520, the storage controller MAC sets the valid VLD of the entry ENTR of the refresh request holding unit 14 to logic 0, deletes the refresh request RRQ, and ends the operation.

  17 and 18 show an example of the operation of the storage controller MAC shown in FIG. 2, and FIG. 19 and FIG. 20 show the continuation of the operation of FIG. 17 and FIG. 17 to 20 form one timing diagram by arranging FIG. 17 in the upper left, FIG. 18 in the lower left, FIG. 19 in the upper right, and FIG. 20 in the lower right.

  The numbers shown on the upper side of FIGS. 17 to 20 indicate the number of clock cycles. In FIG. 17 to FIG. 20, reference characters W0 and W3 indicate write requests (write commands), and reference characters R1 and R2 indicate read requests (read commands). Symbol R indicates a refresh request (refresh command), and symbol P indicates a precharge request (precharge command). The numbers at the end of the read requests R1 and R2 indicate the request identification number RQID, and the numbers at the end of the write requests W0 and W3 indicate the request identification number RQID and the write data identification number WDID. In the memory access request MRQ, refresh request RRQ, issue request information RQINF, access request issue notification ARQS, etc., the valid VLD is set to logic 1 when the requests W0, R1, R2, W3, R, and P are generated. Description of the address AD is omitted.

  In the state ST of the entry ENTk (“k” is a positive integer), ENTk + 1, ENTk + 2, and ENTk + 3 in the access request holding unit 10, the code IDL indicates “idle”, “not yet” indicates “not issued”, “ “Done” indicates “Issued”. The sign of the state ST of the entry ENTR of the refresh request holding unit 14 is the same as the sign of the state ST of the entries ENTk, ENTk + 1, ENTk + 2, and ENTk + 3.

  The storage controller MAC operates in response to four memory access requests MRQ (write request W0, read requests R1, R2, and write request W3) in order from the CPU (FIG. 17A). The refresh control unit 12 outputs a refresh request RRQ between the read request R2 and the write request W3 (FIG. 17 (b)).

  The entry ENTk changes the state ST from the idle IDL to “unissued” with the holding of the write request W0 (FIG. 17C). Similarly, each of the entries ENTk + 1, ENTk + 2 and ENTk + 3 transitions the state ST from the idle IDL to “unissued” with the holding of the read requests R1, R2 and the write request W3 (FIGS. 17D and 17E). (F)). The entry ENTR transitions the state ST from the idle IDL to “unissued” with the holding of the refresh request R (FIG. 17 (g)).

  The request selection unit 16 sequentially outputs a write request W0 and read requests R1, R2 as issue request information RQINF, and commands CMD corresponding to the write request W0 and read requests R1, R2 are sequentially supplied to the DIMM ( FIG. 17 (h)). The pipeline control unit 20 sequentially outputs the access request issue notification ARQS corresponding to the write request W0 and the read requests R1 and R2 (FIG. 17 (i)).

  The states ST of the entries ENTk, ENTk + 1, and ENTk + 2 are set to “issued” based on the access request issue notification ARQS (W0, R1, R2), respectively (FIGS. 17 (j), (k), (l)). .

  The request selection unit 16 outputs the issue request information RQINF corresponding to the refresh request R, and the command CMD corresponding to the refresh request R2 is supplied to the DIMM (FIG. 17 (m)). The pipeline control unit 20 outputs a refresh request issue notification RRQS corresponding to the refresh request R (FIG. 17 (n)). The state ST of the entry ENTR is set to “issued” based on the refresh request issue notification RRQS (R) (FIG. 17 (o)).

  In FIG. 18, stages STG1 to STG28 of the pipeline control unit 20 sequentially transfer a write request W0 and read requests R1 and R2. Then, the pipeline control unit 20 outputs an access request completion notification ARQE corresponding to the write request W0 and the read request R1 based on the fact that the stage STG8 holds the write request W0 and the read request R1, respectively (FIG. 18 ( a), (b)).

  The entries ENTk and ENTk + 1 shown in FIG. 17 set the state ST to idle IDL based on the corresponding access request completion notification ARQE (FIGS. 17 (p) and (q)).

  The pipeline control unit 20 outputs a write data request WDRQ corresponding to the write request W0 to the CPU based on the fact that the stage STG12 holds the write request W0 (FIG. 18 (c)). The pipeline control unit 20 outputs the write data control signal WDCNT for 4 clock cycles based on the fact that the stage STG 16 holds the write request W0 (FIG. 18 (d)). The write data control unit 26 transfers the write data D0, D1, D2, and D3 output from the CPU to the DIMM during the output period of the write data request WDRQ (FIG. 18 (e)). Then, the SDRAM write operation executed in response to the write request W0 is executed.

  The pipeline control unit 20 outputs the read data control signal RDCNT for 4 clock cycles based on the fact that the stage STG 24 holds the read request R1 (FIG. 18 (f)). The read data control unit 28 outputs data output from the DIMM as read data D4, D5, D6, and D7 to the CPU during the output period of the read data control signal RDCNT (FIG. 18 (g)). Then, the DIMM read operation executed in response to the read request R1 is completed.

  On the other hand, in FIG. 17, the DIMM (SDRAM) detects a parity error of the read request R2, and asserts command parity error information CAPE for a period of 9 clock cycles (FIG. 17 (r)). Note that the assertion period of the command parity error information CAPE is not limited to 9 clock cycles. The mode information MD shifts to the restart waiting mode based on the command parity error information CAPE, and the count value of the counter RCOUNT is incremented to “1” (FIG. 17 (s)). The restart waiting mode indicates that command parity error information CAPE is being received, and selection of the memory access request MRQ and the refresh request RRQ by the request selection unit 16 is suppressed. The SDRAM does not accept a new command CMD while outputting the command parity error information CAPE. For this reason, by suppressing selection of the memory access request MRQ and the refresh request RRQ during the restart waiting mode, it is possible to prevent the useless command CMD from being supplied to the SDRAM.

  The read request R2 and the refresh request R held in the entries ENTk + 2 and ENTk + 3 whose state ST is “issued” are subject to retry. For this reason, the state ST of the entries ENTk + 2 and ENTk + 3 is set to “retry” (FIG. 17 (t), (u)).

  In FIG. 18, the output of the access request completion notification ARQE is masked for the read request R2 held in any of the stages STG1 to STG8 during the period when the command parity error information CAPE is asserted (FIG. 18 (h)). . In the read request R2 held in any of the stages STG1 to STG8 during the period when the command parity error information CAPE is asserted, the output of the read data control signal RDCNT is masked (FIG. 18 (i)). Similarly, for the refresh request R held in any of the stages STG1 to STG8 during the period when the command parity error information CAPE is asserted, the output of the refresh request completion notification RRQE is masked (FIG. 18 (j)).

  If the entry ENTk + 2 holds the write request W2 instead of the read request R2, and a command parity error occurs in response to the write request W2, the output of the corresponding write data request WDRQ and the write data control signal WDCNT is masked. The

  In FIG. 17, the error detection unit 24 waits for the command parity error information CAPE to be negated, outputs a retry control request RTRQ (precharge request P), and sets the mode information MD to the pre-retry preparation mode (FIG. 17 ( v)). The request selection unit 16 outputs a precharge command P to the DIMM based on the retry control request RTRQ (precharge request P) (FIG. 17 (w)).

  In FIG. 18, the pipeline control unit 20 outputs a retry control request completion notification RTRQE corresponding to the precharge request P based on the fact that the stage STG8 holds the precharge request P (FIG. 18 (k)).

  In FIG. 17, the error detection unit 24 sets the mode information MD to the retry mode based on the retry control request completion notification RTRQE (FIG. 17 (x)). Since the mode information MD indicates the retry mode, the request selection unit 16 sequentially outputs the read request R2 and the refresh request R as the issuance request information RQINF for retry (FIGS. 17 (y) and (z)). The SDRAM sequentially receives an active command corresponding to the read request R2, a read command, and a refresh command corresponding to the refresh request R, and starts a read operation and a refresh operation. In the example shown in FIG. 17, the command parity error of the retry read request R2 and the refresh request RRQ does not occur.

  The pipeline control unit 20 outputs an access request issuance notification ARQS corresponding to the retry read request R2 and outputs a refresh request issuance notification RRQS corresponding to the retry refresh request R (FIG. 17 (a1, b1)). ). The state ST of the entry ENTk + 2 is set to “issued” based on the access request issue notification ARQS (R2) (FIG. 17 (c1)). The state ST of the entry ENTk + 3 is set to “issued” based on the refresh request issue notification RRQS (R) (FIG. 17 (d1)).

  In FIG. 18, the pipeline control unit 20 outputs an access request completion notification ARQE corresponding to the read request R2 based on the fact that the stage STG8 holds the read request R2 (FIG. 18 (l)). In FIG. 17, the state ST of the entry ENTk + 2 is set to the idle IDL based on the access request completion notification ARQE (FIG. 17 (e1)).

  In FIG. 20, the pipeline control unit 20 outputs a refresh request completion notification RRQE corresponding to the refresh request R based on the fact that the stage STG 8 holds the retry refresh request R (FIG. 20 (a)).

  The entry ENTR shown in FIG. 19 sets the state ST to idle IDL based on the refresh request completion notification RRQE (FIG. 19 (a)). The error detection unit 24 completes all retries when there is no state ST indicating “retry” in the access request information ARQI from the access request holding unit 10 and the refresh request information RRQI from the refresh request holding unit 14. Detect that Then, the error detection unit 24 resets the count value of the counter RCOUNT, and sets the mode information MD to the normal mode (FIG. 19B).

  The request selection unit 16 outputs issuance request information RQINF corresponding to the write request W3, and the active command and the write command corresponding to the write request W3 are supplied to the DIMM (FIG. 19 (c)). The pipeline control unit 20 outputs an access request issue notification ARQS corresponding to the write request W3 (FIG. 19 (d)). The state ST of the entry ENTk + 3 is set to “issued” based on the access request issue notification ARQS corresponding to the write request W3 (FIG. 19E).

  In FIG. 20, the pipeline control unit 20 outputs an access request completion notification ARQE corresponding to the write request W3 based on the fact that the stage STG8 holds the write request W3 (FIG. 20 (b)).

  The pipeline control unit 20 outputs the write data request WDRQ corresponding to the write request W3 based on the fact that the stage STG12 holds the write request W3 (FIG. 20 (c)). The pipeline control unit 20 outputs the write data control signal WDCNT for 4 clock cycles based on the fact that the stage STG 16 holds the write request W3 (FIG. 20 (d)). The write data control unit 26 transfers the write data D8, D9, Da, Db output from the CPU to the DIMM during the output period of the write data request WDRQ (FIG. 20 (e)). Then, the SDRAM write operation executed in response to the write request W3 is started.

  The entry ENTk + 3 shown in FIG. 19 sets the state ST to idle IDL based on the corresponding access request completion notification ARQE (W3) (FIG. 19 (f)). Then, a write operation, a read operation, and a refresh operation in response to a write request W0, a read request R1, R2, a write request W3, and a refresh request R generated by the refresh control unit 12 are executed by the SDRAM. .

  FIG. 21 shows an example of the operation of the pipeline control unit 20 shown in FIG. FIG. 21 shows the operation of the pipeline control unit 20 corresponding to the operations shown in FIGS.

  Information included in the issue request information RQINF held in the stage STG1 of the shift register SFTR of the pipeline control unit 20 is sequentially transferred to the subsequent stage SG every clock cycle. Further, the read request R2 and the refresh request R held in any of the stages STG1 to STG8 during the assertion period of the command parity error information CAPE are invalidated. That is, the read request R2 and the refresh request R indicated by a thick frame sandwiched between two one-dot chain lines are invalidated and subjected to retry.

  For this reason, the pipeline control unit 20 does not output the access request completion notification ARQE even when the stage STG8 holds the thick frame read request R2 (FIG. 21A). The pipeline control unit 20 does not output the refresh request completion notification RRQE even when the stage STG 8 holds the refresh request R with a thick frame (FIG. 21B).

  Further, the pipeline control unit 20 does not output the read data control signal RDCNT even when the stage STG 24 holds the thick frame read request R2 (FIG. 21 (c)). The pipeline control unit 20 does not output the valid signal VLD (R) and the request identification number RQID (R) even when the stage STG 28 holds the thick frame read request R2 (FIG. 21 (d)).

  As described above, also in the embodiment shown in FIGS. 2 to 21, the same effect as that of the embodiment shown in FIG. 1 can be obtained. That is, when the SDRAM detects a parity error of the command CMD or the address AD, the access request MRQ selected by the request selection unit 16 is not deleted but stored in the access request holding unit 10 even after being held in the stage STG8. Retained. Similarly, when the SDRAM detects a parity error of the command CMD or address AD, the refresh request holding unit 14 does not delete the refresh request RRQ selected by the request selection unit 16 even after it is held in the stage STG8. Retained.

  As a result, the storage controller MAC can reissue the memory access request MRQ and the refresh request RRQ that were not executed in the SDRAM to the SDRAM. As a result, the system including the storage control devices MAC, CPU, and DIMM can continue without stopping the operation even when the command parity error information CAPE occurs. Since the memory access request MRQ or the refresh request RRQ that has not been accepted by the SDRAM due to the occurrence of a command parity error is retried thereafter, it is possible to prevent the system reliability from being lowered, and to improve the system performance. it can.

  Furthermore, in the embodiment shown in FIGS. 2 to 21, it is possible to prevent the CPU or the storage control device MAC from executing the operation after receiving the command CMD even though the SDRAM does not receive the command CMD. . As a result, malfunctions of the CPU and storage controller MAC can be suppressed.

  After receiving the command parity error information CAPE, the storage controller MAC issues a precharge command to the SDRAM before retrying the memory access request MRQ or the refresh request RRQ. Thereby, it is possible to cause the SDRAM to execute a retry operation without causing the SDRAM to malfunction.

  FIG. 22 shows another embodiment of the storage control device and the control method of the storage control device. The same or similar elements as those described in FIGS. 2 to 21 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The storage control device MACa shown in FIG. 22 has an access request holding unit 10A and a refresh request holding unit 14A instead of the access request holding unit 10 and the refresh request holding unit 14 of the storage control device MAC shown in FIG. Further, the storage control device MACa has a pipeline control unit 20A instead of the pipeline control unit 20 of the storage control device MAC shown in FIG. Furthermore, the storage control device MACa has a request issue release notification generation unit 22A and an error detection unit 24A instead of the request issue release notification generation unit 22 and the error detection unit 24 of the storage control device MAC shown in FIG. The other configuration of the storage controller MACa is the same as that of the storage controller MAC shown in FIG.

  The access request holding unit 10A does not receive the access request completion notification ARQE from the pipeline control unit 20A but generates the access request completion notification ARQE for each entry ENT. Then, the access request holding unit 10A outputs the generated access request completion notification ARQE to the request issuance release notification generation unit 22. An example of the access request holding unit 10A is shown in FIG.

  The refresh request holding unit 14A has the same function as the refresh request holding unit 14 shown in FIG. 2 except that it operates without receiving a refresh request completion notification RRQE (FIG. 2) from the pipeline control unit 20A. An example of the refresh request holding unit 14A is shown in FIG.

  The pipeline control unit 20A deletes the function of outputting the access request completion notification ARQE, the refresh request completion notification RRQE, and the retry control request completion notification RTRQE from the pipeline control unit 20 shown in FIG. An example of the pipeline control unit 20A is shown in FIG.

  The error detection unit 24A has the same function as the error detection unit 24A shown in FIG. 2 except that it operates without receiving a retry control request completion notification RTRQE (FIG. 2) from the pipeline control unit 20A. An example of the error detection unit 24A is shown in FIG.

  FIG. 23 illustrates an example of the access request holding unit 10A illustrated in FIG. Elements that are the same as or similar to those in the access request holding unit 10 shown in FIG. 4 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The access request holding unit 10A has a function in which the state control unit STCNT of each entry ENT1-ENTn has a timer TM and outputs an access request completion notification ARQE. The other configuration of the access request holding unit 10A is the same as that of the access request holding unit 10 shown in FIG. 4 except that the access request completion notification ARQE is not received.

  The state control unit STCNT of each entry ENT starts the timer TM in response to receiving the access request issue notification ARQS corresponding to the memory access request MRQ held in the entry ENT. In addition, when the timer TM measures a predetermined time without receiving the access request completion notification ARQE (FIG. 4), the state control unit STCNT of each entry ENT outputs the access request completion notification ARQE and changes the state ST to “ Transition from “issued” to “idle”. The predetermined time measured by the timer TM is equivalent to the time from when the request selection unit 16 selects the memory access request MRQ until the request completion notification generation unit RQEG shown in FIG. 10 outputs the access request completion notification ARQE. . That is, each state control unit STCNT can generate the same timing as the output timing of the access request completion notification ARQE by the pipeline control unit 20 shown in FIG.

  If each state control unit STCNT receives the command parity error information CAPE before the timer TM measures a predetermined time, the state control unit STCNT does not output the access request completion notification ARQE and maintains the state ST in “issued”. When the command parity error information CAPE occurs, the state ST is kept “issued”, so that the memory access request MRQ can be retried.

  Each state control unit STCNT may include a counter that counts up or down every predetermined period instead of the timer TM. In this case, the counter starts a counting operation in response to reception of the access request issue notification ARQS, and outputs a timing signal corresponding to the access request completion notification ARQE when a count value corresponding to a predetermined time is engraved.

  FIG. 24 shows an example of the operation of each entry ENT of the access request holding unit 10A shown in FIG. The same or similar operations as those shown in FIG. 5 are denoted by the same reference numerals as those in FIG. 24 is different from the flow shown in FIG. 5 in that step S111 is inserted between steps S110 and S112, and step S116 is replaced with steps S115 and S117.

  After receiving the access request issue notification ARQS, the entry ENT of the access request holding unit 10A activates the timer TM in step S111, and the process proceeds to step S112.

  In step S115, the entry ENT determines whether or not the timer TM has completed measurement for a predetermined time. If the timer TM has completed the measurement of the predetermined time, the process proceeds to step S117. If the timer TM has not completed the measurement of the predetermined time, the process returns to step S112. In step S117, the entry ENT outputs an access request completion notification ARQE to the request issuance release notification generation unit 22A, and the process proceeds to step S118. The request issue release notification generation unit 22A outputs memory access request release information MRQR to the CPU based on the access request completion notification ARQE from the entry ENT.

  With the above operation, the access request holding unit 10A can generate the timing for outputting the memory access request release information MRQR to the CPU without using the pipeline control unit 20A.

  FIG. 25 shows an example of the refresh request holding unit 12A shown in FIG. Elements that are the same as or similar to those in the refresh request holding unit 12 shown in FIG. 6 are assigned the same reference numerals, and detailed descriptions thereof are omitted.

  The refresh request holding unit 12A has a function in which the state control unit STCNT of the entry ENTR has a timer TM and changes the state ST from “issued” to “idle” based on measurement of a predetermined time by the timer TM. The other configuration of the refresh request holding unit 12A is the same as that of the refresh request holding unit 12 shown in FIG. 6 except that the refresh request completion notification RRQE is not received.

  The operation of the state control unit STCNT of the entry ENTR is the same as the operation of the state control unit STCNT of the access request holding unit 10A shown in FIG. That is, the state control unit STCNT starts the timer TM in response to receiving the refresh request issue notification RRQS. Further, the state control unit STCNT changes the state ST from “issued” to “idle” when the timer TM measures a predetermined time without receiving the command parity error information CAPE. The predetermined time of the timer TM is the same as the timer TM of the access request holding unit 10A. The pipeline control unit 20 shown in FIG. 2 receives the refresh request completion notification RRQE after receiving the issue request information RQINF indicating the refresh request RRQ. It is equal to the time to output.

  If the state control unit STCNT receives the command parity error information CAPE before the timer TM measures a predetermined time, the state control unit STCNT maintains the state ST as “issued”. As a result, the state control unit STCNT maintains the state ST “issued” when the command parity error information CAPE is generated, as in the refresh request holding unit 14 shown in FIG. 6, and retries the refresh request RRQ. Can be executed.

  Note that the state control unit STCNT may include a counter that counts up or down every predetermined period instead of the timer TM. In this case, the state control unit STCNT causes the counter to start counting in response to reception of the refresh request issue notification RRQS, and sets the state ST to “idle” when the counter engraves a count value corresponding to a predetermined time. change.

  FIG. 26 shows an example of the operation of the refresh request holding unit 12A shown in FIG. The same or similar operations as those shown in FIGS. 7 and 24 are denoted by the same reference numerals as those in FIGS. 7 and 24, and detailed description thereof will be omitted. 26 is different from the flow shown in FIG. 7 in that step S111 is inserted between steps S110 and S112, and step S116r is replaced with step S115.

  After receiving the refresh request issuance notification RRQS, the entry ENT of the refresh request holding unit 14A starts the timer TM in step S111, and the process proceeds to step S112.

  In step S115, the entry ENT shifts the process to step S118 when the timer TM completes the measurement of the predetermined time, and returns the process to step S112 when the timer TM has not completed the measurement of the predetermined time.

  FIG. 27 shows an example of transition of the state ST of the state control unit STCNT shown in FIGS. Detailed description of the same transition as in FIG. 8 is omitted. Also in FIG. 27, as in FIG. 8, the underlined characters indicate the operation of the state control unit STCNT of the access request holding unit 10, and the characters in parentheses indicate the state control unit STCNT of the refresh request holding unit 14. The operation is shown.

  The state control unit STCNT shown in FIG. 23 and FIG. 25 changes the state ST to “idle” based on the completion of the measurement of the predetermined time by the timer TM during the period in which the state ST is “issued”. Other transitions are the same as those in FIG.

  FIG. 28 shows an example of the pipeline control unit 20A shown in FIG. Elements that are the same as or similar to the pipeline control unit 20 shown in FIG. 10 are given the same reference numerals, and detailed descriptions thereof are omitted. The pipeline control unit 20A deletes the request completion notification generation unit RQEG from the pipeline control unit 20 illustrated in FIG. Other configurations and functions of the pipeline control unit 20A are the same as those of the pipeline control unit 20 shown in FIG. The access request completion notification ARQE generated by the request completion notification generation unit RQEG of the pipeline control unit 20 shown in FIG. 10 is generated by the access request holding unit 10A shown in FIG.

  FIG. 29 shows an example of the request issuance release notification generator 22A shown in FIG. Elements that are the same as or similar to those in the request issuance release notification generation unit 22 illustrated in FIG. 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The request release notification generation unit 221 of the request issue release notification generation unit 22A outputs the memory access request release information MRQR to the CPU based on the access request completion notification ARQE from each entry ENT of the access request holding unit 10A. Other configurations and functions of the request issuance release notification generation unit 22A are the same as those of the request issuance release notification generation unit 22 shown in FIG.

  FIG. 30 shows an example of the error detection unit 24A shown in FIG. Elements that are the same as or similar to those of the error detection unit 24 shown in FIG. 12 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The retry controller RTCNT of the error detector 24A has a timer TM that measures a predetermined time from the output of a retry control request RTRQ (precharge request). The retry control unit RTCNT generates a retry control request completion notification RTRQE based on the completion of measurement of the predetermined time by the timer TM. The retry control unit RTCNT changes the mode information MD from the pre-retry preparation mode to the retry mode based on the generation of the retry control request completion notification RTRQE. Other configurations and functions of the error detection unit 24A are the same as those of the error detection unit 24 illustrated in FIG. 12 except that the retry control request completion notification RTRQE is not received. The transition of the mode information MD by the retry control unit RTCNT is the same as or similar to that in FIG.

  The operation of the storage control device MACa shown in FIGS. 22 to 30 is the same as that of FIGS. 17 to 20. That is, when the storage controller MACa receives the command parity error information CAPE, the storage control device MACa retries the memory access request MRQ (or refresh request RRQ) held in the entry ENT (or ENTR) whose state ST is “issued”. To. The storage controller MACa suppresses output of the memory access request release information MRQR corresponding to the memory access request MRQ to be retried to the CPU. The storage controller MACa issues a precharge command to the DIMM before reissuing the memory access request MRQ (or refresh request RRQ) to be retried.

  As described above, also in the embodiment shown in FIGS. 22 to 30, the same effect as that of the embodiment shown in FIGS. 1 to 21 can be obtained. That is, the system including the storage control device MACa, CPU, and DIMM can continue without stopping the operation even when the command parity error information CAPE occurs. That is, it is possible to prevent a decrease in the reliability of the system and improve the performance of the system.

  Further, in the embodiment shown in FIGS. 22 to 30, the access request completion notification ARQE, the refresh request completion notification RRQE, the retry control request RTRQ, or a timing signal instead thereof is generated without going through the pipeline control unit 20. can do. As a result, the control in the storage control device MACa can be simplified compared to the control in the storage control device MAC shown in FIG. 2, and the timing design and the like can be facilitated.

  The embodiments shown in FIGS. 2 to 20 may be applied to a storage control device that controls access to other storage devices such as SRAM, ferroelectric memory, and MRAM (Magnetoresistive RAM). The SRAM returns to the standby state after the access operation without receiving the precharge command. For this reason, the error detection units 24 and 24A of the storage control devices MAC and MACa that control access to the SRAM do not have the pre-retry preparation mode as the mode information MD. Further, when the embodiment shown in FIGS. 2 to 20 is applied to SRAM, ferroelectric memory, or MRAM, the storage control devices MAC and MACa do not have the refresh control unit 12 and the refresh request holding unit 14.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  10, 10A ... access request holding unit; 12, 12A ... refresh control unit; 14 ... refresh request holding unit; 16 ... request selection unit; 18 ... access signal generation unit; 20, 20A ... pipeline control unit; Request issuance release notification generation unit; 24, 24A ... error detection unit; 26 ... write data control unit; 28 ... read data control unit; 30 ... data input / output unit; 100 ... storage control device: 110a, 110b, 110c ... request holding 120: Request selection unit; 130 ... Output generation unit; 140 ... Request control unit; 200 ... Control device; 300 ... Storage device; AD ... Address; ARQE ... Access request completion notification; ARQI ... Access request information; CAPE ... Command parity error information; CMD ... Command; ENT, ENTR ... En HLD ... holding unit; MAC ... storage controller; MD ... mode information; MRQ ... memory access request; MRQR ... memory access request release information; P ... parity; RDCNT ... read data control signal; RDCNTG ... read data control signal generation Unit: RDG ... read data generation unit; RDT ... read data; RQEG ... request completion notification generation unit; RQINF ... issue request information; RCOUNT ... counter; RRQ ... refresh request; RRQE ... refresh request completion notification; RRQS ... Refresh request issue notification; RTRQ ... Retry control request; RTRQE ... Retry control request completion notification; STCNT ... State control unit; WD ... Write data; WDCNT ... Write data control signal; WDCNTG ... Write data control signal generated Department; WDRQ ... write data request; WDRQG ... write data request generating unit

Claims (15)

In a storage controller that controls access to a memory device based on an access request output from the controller,
A plurality of request holding units respectively holding access requests output from the control device;
Select one of the access requests held in each of the plurality of request holding units, output the selected access request to the memory device as an operation instruction for operating the memory device, and suppress the deletion of the access request A request selecting unit that re-selects the target access request that is an access request whose deletion is suppressed, and outputs the selected request to the memory device as the operation instruction;
When a first time has elapsed since the selection of the access request by the request selection unit, the access request is deleted from the request holding unit holding the access request selected by the request selection unit, and the operation instruction causes an error. When the error information indicating that the request is included is received from the memory device , among the plurality of request holding units, a request holding that holds an access request for which the first time has not elapsed since selection by the request selecting unit A storage control device comprising a request control unit that suppresses deletion of an access request from a unit. If the request is selected access request by the selection unit writing data to the memory device write request, after the second time from the lapse of the first time, it requests the write data to be written to the memory device to the controller A write data request generation unit that outputs a write data request to be
When the error information is output from the memory device , the write data request generation unit outputs the write data request corresponding to a write request for which the first time has not elapsed since selection by the request selection unit. The storage control device according to claim 1, wherein the storage control device is suppressed. A write data control unit that holds the write data output from the control device based on the write data request, and outputs the held write data to the memory device ;
When the access request selected by the request selection unit is the write request, the write data held in the write data control unit is stored in the write data control unit after a third time from the elapse of the first time and the second time. A write data control signal generator for outputting a write data control signal to be output to the memory device ;
When the error information is output from the memory device , the write data control signal generation unit generates the write data control signal corresponding to the write request for which the first time has not elapsed since selection by the request selection unit. 3. The storage control device according to claim 2, wherein output is suppressed. A read data control unit that holds data read from the memory device and outputs the held data to the control device;
When the access request selected by the request selection unit is a read request for reading data from the memory device , the data held in the read data control unit is controlled after the fourth time from the elapse of the first time. A read data control signal generation unit that outputs a read control signal to be output to the apparatus;
The read data control signal generation unit, when the error information is output from the memory device , outputs the read control signal corresponding to a read request for which the first time has not elapsed since selection by the request selection unit The storage control device according to any one of claims 1 to 3, wherein the storage control device is suppressed. The access request release information indicating that the memory device has accepted the access request selected by the request selection unit based on the elapse of the first time from the selection of the access request by the request selection unit. A release notification generator for outputting to the device;
When the error information is output from the memory device , the release notification generation unit outputs the access request release information corresponding to an access request for which the first time has not elapsed since selection by the request selection unit. 5. The storage control device according to claim 1, wherein the storage control device suppresses the storage control device. A refresh control unit for generating a refresh request for causing the memory device to perform a refresh operation for rewriting data held in a memory cell in the memory device ;
A refresh request holding unit for holding a refresh request generated by the refresh control unit;
The request selection unit selects any one of the access requests held in the plurality of request holding units or the refresh request held in the refresh request holding unit, and outputs the request to the memory device as the operation instruction.
The request control unit deletes the access request selected by the request selection unit from any of the plurality of request holding units when the first time has elapsed since the selection of the access request by the request selection unit, When the first time has elapsed from the selection of the refresh request by the request selection unit, the refresh request selected by the request selection unit is deleted from the refresh request holding unit, and the error information is output from the memory device If the request selection section according to elapse of the first time after selection by deletion and the request selection part of the access request from the request holding unit that holds the access request has not passed the first time after selection It is possible to suppress the deletion of refresh requests from the refresh holding unit that holds unrefreshed refresh requests. The storage controller according to any one of claims 1 to 5 and. A standby request generator for generating a standby request for setting the memory device to a standby state after the output of the error information from the memory device is stopped;
The request selection unit selects the standby request before selecting the access request after the output of the error information from the memory device is stopped, and outputs the standby request to the memory device as the operation instruction. The storage control device according to any one of claims 1 to 5. The memory device includes a dynamic memory cell, the operation instruction to set the memory device in the standby state, the storage control device according to claim 7, wherein it is a precharge command. A counter for counting the number of times the error information is received;
A system error detector that outputs system error information indicating a system error to the control device when the counter of the counter reaches a predetermined value;
The system error detection unit resets the counter when all the access requests whose deletion is suppressed based on the error information are selected again by the request selection unit and accepted by the memory device. The storage control device according to any one of claims 1 to 8.   10. Each of the plurality of request holding units includes a measuring unit that measures a time from when an access request is selected by the request selecting unit until the first time elapses. The storage control device according to any one of the above. Said request selection unit, while the error information is output from the memory device, the storage controller according to any one of claims 1 to 10, characterized in that to prevent the selection of the access request. 12. The error information is output from the memory device before the first time elapses from selection of an access request by the request selection unit. The storage control device described. An output generation unit configured to generate the operation instruction and error detection information for causing the memory device to detect an error in the operation instruction based on the access request selected by the request selection unit and to output the error detection information to the memory device; The storage control device according to claim 1, wherein the storage control device is a storage control device. A shift register including a plurality of stages for sequentially holding the access request selected by the request selection unit and the error information;
Of the plurality of stages, each of the second to mth stages is a logical sum of the logic indicated by the error information output from the memory device and the logic indicated by the error information output from the preceding stage. By holding the logic that has taken the error information based on the output of the error information from the memory device,
The m-th stage is a stage in which the access request and error information held in the first stage are held when the first time has elapsed,
The write data request generation unit generates the write data request based on an access request output from one of the stages after the m-th stage, and the one of the stages after the m-th stage is error information. 3. The storage control device according to claim 2, wherein output of the write data request is suppressed when the data is held. In a control method of a storage control device that includes a plurality of request holding units each holding an access request output from a control device, and controls access of a memory device based on the access request,
Said memory device request selection unit, the selected plurality of request holding unit in one of access request held respectively, the access request selected as an operation instruction for operating the memory device in which the storage control device has Output to
When a first time elapses after the request control unit included in the storage control device has selected an access request by the request selection unit, an access request is received from a request holding unit holding the access request selected by the request selection unit When the error information indicating that the operation instruction includes an error is received from the memory device , the first time elapses from the selection by the request selection unit among the plurality of request holding units. Suppress the deletion of access requests from the request holding unit that holds the target access request that is not
The method for controlling a storage control device, wherein the request selection unit reselects the target access request whose deletion has been suppressed, and outputs the selected request to the memory device as the operation instruction.

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