JP6436209B2 - Display device and electronic device - Google Patents

Description

  The present invention relates to an active matrix display device using an organic EL (Electro-Luminescence) panel. Furthermore, the present invention relates to an electronic device using such a display device.

  The organic EL panel includes an organic light-emitting diode (OLED) in which a light-emitting layer is made of an organic compound and disposed in a plurality of pixels. The organic light emitting diode emits light when molecules of an organic compound excited by energy generated by the combination of electrons and holes injected into the light emitting layer return from the excited state to the ground state. In the organic EL panel, impulse-type lighting is performed with luminance according to the current value by passing a current between the anode (anode) and the cathode (cathode) of the light emitting diode.

  As driving methods of the organic EL panel, there are a passive matrix type and an active matrix type. According to the passive matrix type, the organic light emitting diodes of the respective pixels are connected between the plurality of wirings of the anode driver and the plurality of wirings of the cathode driver. Although the structure is simple as described above, since light is emitted for each line, it is necessary to increase the light emission luminance, the life of the device is shortened, and the image quality deterioration due to crosstalk becomes a problem.

  On the other hand, according to the active matrix type, a plurality of transistors are arranged in each pixel, and a high light emission efficiency and high image quality can be realized by flowing a current through the organic light emitting diode in a predetermined period. However, if an amorphous silicon TFT (thin film transistor) is used as the transistor of the pixel circuit, the secular change becomes large, and if a low temperature polycrystalline silicon TFT is used, the variation of the threshold voltage for each pixel becomes large. In any case, the structure of the pixel circuit is complicated to compensate for them.

  In a conventional active matrix display device, in order to average the influence of the arrangement of transistors and wirings on the image quality, the layout of the pixel circuit is repeated in the same pattern, or the pixel circuit is reduced in size. Therefore, the layout of the pixel circuit is a mirror arrangement that is symmetrical left and right and / or up and down.

  As a related technique, Patent Document 1 discloses an image display device capable of efficiently arranging pixel circuits in a display area. This image display device is an image display device that displays an image by causing a light emitting element arranged in each of a plurality of pixel regions obtained by dividing the display region into a grid shape to display each of the plurality of pixel regions. A pixel circuit for controlling light emission of the arranged light emitting element, a portion protruding from the pixel region toward another adjacent pixel region, and a portion where another adjacent pixel circuit protrudes into the pixel region; It is formed in the area | region which has.

  Patent Document 2 discloses an organic electroluminescence device having an improved aperture ratio. The organic electroluminescence device is formed on a substrate, a plurality of gate wirings on the top of the substrate, a plurality of data wirings on the substrate crossing the plurality of gate wirings, and connected to each other. A plurality of switching elements and driving elements, and power supply wirings formed on the substrate and electrically connected to at least two driving elements in parallel with the plurality of data wirings. With such a configuration, the number of power supply lines can be reduced to ½, so that the aperture ratio is improved as compared with the conventional case, and the current level does not need to be increased, so that the lifetime of the element can be extended.

  In Patent Document 1, the layout of the pixel circuit is a mirror arrangement that is symmetrical left and right and up and down, but the data signal line (DAT, see FIGS. 1 and 3C) formed at the end of the pixel circuit is adjacent to the pixel circuit. It is adjacent to the data signal line of the pixel circuit. In Patent Document 2, the layout of the pixel circuit is a mirror arrangement symmetrical to the left and right, but the data wiring (111, see FIG. 5) formed at the end of the pixel circuit is the same as the data wiring of the adjacent pixel circuit. Adjacent.

  In an active matrix display device using an organic EL panel, a capacitor that drives a current to the organic light emitting diode is driven by a pixel signal (charge) written to the capacitor of the pixel circuit via a data line. At this time, if the two data lines are adjacent to each other, when the pixel signal once written in the capacitor of the pixel circuit writes the pixel signal to the capacitor of the adjacent pixel circuit, the two data lines are adjacent to each other. Depending on the parasitic capacitance, the gray level may be affected.

JP 2010-210905 A (paragraphs 0007-0009) JP 2004-6341 A (paragraphs 0039-0041)

  As described above, in an active matrix display device using an organic EL panel, since a plurality of transistors are arranged in each pixel circuit, it is difficult to reduce the size of the pixel circuit and display a high-definition image. However, when the pixel pitch is reduced, manufacturing restrictions are imposed. Further, when the layout of the pixel circuit is a mirror arrangement symmetrical to the left and right, crosstalk due to parasitic capacitance between two adjacent data lines becomes a problem. Accordingly, a first object of the present invention is to provide a display device that can easily realize downsizing of a pixel circuit. A second object of the present invention is to reduce crosstalk due to parasitic capacitance between data lines in two adjacent pixel circuits.

  In order to solve the above problems, a display device according to one aspect of the present invention is an active matrix display device using an organic EL (electroluminescence) panel, and is disposed in a pixel region of the organic EL panel. A plurality of pixel circuits each including a plurality of transistors that drive the organic light emitting diode and the organic light emitting diode, a plurality of scanning lines arranged along a first direction in the organic EL panel, and a first in the organic EL panel A plurality of data lines arranged along a second direction orthogonal to the first direction, and in at least one set of pixel circuits adjacent in the first direction, gate electrodes and impurity diffusion regions of the plurality of transistors Are laid out in line symmetry, and at least one set of transistors arranged symmetrically in at least one set of pixel circuits. The gate electrode of Njisuta are integrally constructed.

  According to one aspect of the present invention, in at least one set of pixel circuits adjacent in the first direction, the gate electrodes and the impurity diffusion regions of the plurality of transistors are laid out in line symmetry, thereby efficiently wiring in the wiring layer. Can be arranged. In addition, the gate electrodes of at least one set of transistors arranged symmetrically in at least one set of pixel circuits adjacent in the first direction are integrated and configured integrally, whereby the gate electrodes of these transistors are individually set. Compared with the case of the configuration, the distance between the transistors can be narrowed by the space between the gate electrodes, and the pixel pitch can be reduced.

  The display device may further include a shield line disposed between two data lines respectively connected to a set of pixel circuits adjacent in the first direction. Accordingly, even if the layout of a set of pixel circuits adjacent in the first direction is mirror-arranged, it is possible to prevent two data lines from being adjacent to each other and reduce crosstalk due to parasitic capacitance between the data lines. Can do.

  Each of the plurality of pixel circuits includes a first transistor that supplies a current to the organic light emitting diode according to a potential of the capacitor connected to the gate, and a first transistor that operates according to the potential of the scanning line connected to the gate. A second transistor connecting the gate to one data line may be included. Thus, even when the pixel circuit includes only two transistors, an image can be displayed on the organic EL panel.

  Here, the gate electrodes of the second transistors of the pair of pixel circuits adjacent in the first direction may be integrally formed. Thereby, the interval between the second transistors of one set of pixel circuits can be reduced.

  In addition, each of the plurality of pixel circuits includes a third transistor that opens and closes a connection between the gate and the drain of the first transistor according to a signal supplied to the gate, and a first signal according to the signal supplied to the gate. A fourth transistor that opens and closes a connection between the drain of the transistor and the anode of the organic light emitting diode, and a second transistor that opens and closes a connection between the anode of the organic light emitting diode and the reset potential line according to a signal supplied to the gate. 5 transistors may be further included. Thereby, the image quality and functions can be further improved.

  In that case, in the first to third pixel circuits adjacent in the first direction, the gate electrodes of the second transistors of the second and third pixel circuits are integrally formed, and the second and second The gate electrode of the third transistor of the third pixel circuit is integrally formed, the gate electrode of the fourth transistor of the first and second pixel circuits is integrally formed, and the second and second The gate electrodes of the fifth transistors of the three pixel circuits may be integrally formed. As a result, the distance between one set of second transistors, the distance between one set of third transistors, the distance between one set of fourth transistors, and the distance between one set of fifth transistors can be reduced. .

  The display device may further include a shield line disposed between two wirings respectively connected to the gate electrodes of the first transistors of the pair of pixel circuits adjacent in the first direction. . Since the shielding effect is increased by arranging the shield lines in such a layout pattern, it is possible to reduce the influence of crosstalk on display between adjacent pixels.

  In the above, the integrally configured gate electrodes of at least one set of transistors arranged symmetrically in at least one set of pixel circuits adjacent in the first direction are connected to one wiring at one connection point. Also good. Thereby, the number of through holes and contacts can be reduced and the pixel circuit can be miniaturized.

  An electronic device according to one aspect of the present invention includes a display device according to any one of the aspects of the present invention. Accordingly, it is possible to provide an electronic device such as an electric viewfinder or a head mounted display with a reduced pixel pitch in order to display a high-definition image.

1 is a block diagram illustrating an electronic apparatus using a display device according to an embodiment of the present invention. The perspective view which shows an example of the display apparatus which concerns on one Embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a pixel portion illustrated in FIG. 1. The top view which shows the layout of the gate electrode and impurity diffusion area | region in a pixel circuit. The top view which shows the layout of the 1st wiring layer in a pixel circuit. The top view which shows the layout of the 2nd wiring layer in a pixel circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration of an electronic apparatus using a display device according to an embodiment of the present invention. This electronic apparatus is an electronic apparatus such as an electric viewfinder or a head-mounted display. In FIG. 1, only the part related to image display is shown.

  As shown in FIG. 1, the electronic apparatus includes an image data processing circuit 10, a display timing generation circuit 20, a scanning line driver 30, a data line driver 40, and a pixel unit 50. Here, at least the scanning line driver 30 to the pixel unit 50 constitute an active matrix display device using an organic EL panel.

  The pixel unit 50 includes a plurality of pixel circuits respectively formed in a plurality of pixel regions of the organic EL panel. In an organic EL panel, a pixel circuit may be formed by forming a TFT with amorphous silicon or low-temperature polycrystalline silicon on a transparent substrate. Alternatively, an organic EL panel in which an organic light emitting diode (OLED) is formed thereon using a silicon (Si) semiconductor substrate on which a pixel circuit is formed may be used. Such an organic EL panel is also referred to as “SiOLED”.

  In the case of SiOLED, even if the number of transistors constituting each pixel circuit is increased, these transistors can be easily formed on a semiconductor substrate. In addition to the scanning line driver 30 to the pixel unit 50, at least a part of the image data processing circuit 10 and the display timing generation circuit 20 may be formed on a semiconductor substrate.

  The image data processing circuit 10 inputs image data and a clock signal, and performs various image processing on the image data. For example, the image data processing circuit 10 may perform gamma correction processing or afterimage correction processing on the image data. The image data processing circuit 10 supplies the image data subjected to the image processing to the data line driver 40.

  The display timing generation circuit 20 generates various timing signals for controlling the display device in synchronization with an externally supplied vertical synchronization signal, horizontal synchronization signal, and dot clock signal. For example, the display timing generation circuit 20 generates a start signal and a line clock signal and supplies them to the scanning line driver 30. The start signal includes a start pulse that defines the start timing of vertical scanning and serves as a trigger for starting scanning of the pixel unit 50.

  The scanning line driver 30 includes a shift register and an output buffer. When a start pulse is applied, the scanning line driver 30 sequentially selects a plurality of scanning lines G1, G2,... In synchronization with a line clock signal. A scanning signal is supplied to the selected scanning line. Thereby, all the scanning lines are sequentially selected with the start pulse as a trigger, and one vertical scanning driving is performed. Further, the scanning line driver 30 may supply various control signals for controlling the operation of the pixel unit 50 to the pixel unit 50.

  The data line driver 40 includes a plurality of D / A converters, and generates a plurality of pixel signals corresponding to gradations represented by the image data supplied from the image data processing circuit 10. The data line driver 40 supplies these pixel signals to the plurality of data lines D1, D2,... At a timing synchronized with the scanning signal.

  In the pixel unit 50, a plurality of scanning lines G1, G2,... Are arranged along a first direction (X-axis direction in the drawing) in the organic EL panel. A plurality of data lines D1, D2,... Are arranged along a second direction (Y-axis direction in the drawing) perpendicular to each other. A plurality of pixel circuits are provided at positions where the scanning lines and the data lines intersect.

  A plurality of rows of pixel circuits are sequentially selected by a scanning signal supplied from the scanning line driver 30. Each pixel signal is written into the selected pixel circuit of one row from the data line driver 40 via the plurality of data lines D1, D2,. Each pixel circuit includes an organic light emitting diode, and the organic light emitting diode emits light with an intensity corresponding to the written pixel signal, and gradation display is performed for each pixel.

  FIG. 2 is a perspective view showing an example of a display device according to an embodiment of the present invention. Here, a display device using SiOLED will be described. As shown in FIG. 2, the display device 60 includes an organic EL panel 70 and a flexible substrate 80. The organic EL panel 70 includes a silicon semiconductor substrate 71, a light emitting layer (OLED layer) 72 made of an organic compound deposited on the semiconductor substrate 71, and a cover glass 73 provided on the OLED layer 72. The display panel of the mold. A plurality of pixel circuits are formed on the semiconductor substrate 71, and display light emitted from the OLED layer 72 is emitted from the cover glass 73 side.

  The organic EL panel 70 includes a display area 70a having a plurality of pixels arranged in a matrix. As shown enlarged in the upper right of FIG. 2, red (R), green (G), and blue (B) light emitting elements are periodically arranged in the display area 70a, and these light emitting elements emit light. A full color image is displayed by the light that is emitted.

  A scanning line driver 30 and a data line driver 40 (see FIG. 1) are formed on the periphery (frame portion) of the display area 70a of the organic EL panel 70. Circuit elements constituting these circuits are formed on the semiconductor substrate 71 in the same manner as the pixel circuit. A flexible substrate 80 is connected to a region where the semiconductor substrate 71 protrudes from the cover glass 73.

  A plurality of terminals for connecting to an external device or a dedicated controller is formed at the end of the flexible substrate 80. The organic EL panel 70 displays images, characters, and the like in the display area 70a by receiving supply of image data, power, and control signals from an external device or controller via the flexible substrate 80.

FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of the pixel portion illustrated in FIG. 1. FIG. 3 shows three pixel circuits 1 to 3 adjacent to each other in the first direction (the X-axis direction shown in FIG. 1) and a test control circuit. The pixel circuits 1 to 3 are provided in, for example, three pixel regions where RGB light emitting elements are formed. The pixel circuits 1 to 3 are supplied with a power supply potential V _EL (for example, 8 V) and a power supply potential V _CT (for example, 0 V).

  The pixel circuit 1 includes an organic light emitting diode D arranged in a pixel region of the organic EL panel, a plurality of transistors that drive the organic light emitting diode D, and a capacitor C that holds a pixel signal. For example, the pixel circuit includes P-channel MOS transistors QP1 and QP2, and may further include P-channel MOS transistors QP3 to QP5 as an option.

The source of the transistor QP1 is connected to the power supply potential V _EL , and the drain of the transistor QP1 is connected to the source of the transistor QP4. When the transistor QP4 is not provided, the drain of the transistor QP1 is connected to the anode of the organic light emitting diode D. The cathode of the organic light emitting diode D is connected to the power supply potential _VCT . The first electrode of the capacitor C is connected to the power supply potential V _EL , and the second electrode of the capacitor C is connected to the gate of the transistor QP1.

  The source of the transistor QP2 is connected to the data line D1, and the drain of the transistor QP2 is connected to the second electrode of the capacitor C and the gate of the transistor QP1. The gate of the transistor QP2 is connected to one scanning line, and the transistor QP2 connects the gate of the transistor QP1 to the data line D1 in accordance with the potential of the scanning line connected to the gate.

  That is, when the scanning line potential is activated to a low level, the transistor QP2 is turned on, and the potential of the data line D1 is supplied to the gate of the transistor QP1. The transistor QP1 supplies a current to the organic light emitting diode D according to the potential held in the second electrode of the capacitor C connected to the gate. The organic light emitting diode D emits light with a luminance corresponding to the supplied current value.

  On the other hand, when the potential of the scanning line is deactivated to a high level, the transistor QP2 is turned off and the gate of the transistor QP1 is disconnected from the data line D1. A current can be supplied to the organic light emitting diode D according to the potential held in the C second electrode.

  As described above, even when the pixel circuit 1 includes only two transistors QP1 and QP2, an image can be displayed on the organic EL panel. However, in the following, in order to further improve the image quality and functions, A case where circuit 1 further includes P-channel transistors QP3 to QP5 will be described.

  The source of the transistor QP3 is connected to the gate of the transistor QP1, and the drain of the transistor QP3 is connected to the drain of the transistor QP1. Further, a threshold compensation signal is supplied to the gate of the transistor QP3, and the transistor QP3 opens and closes the connection between the gate and the drain of the transistor QP1 in accordance with the threshold compensation signal.

  That is, when the threshold compensation signal is activated to a low level, the transistor QP3 is turned on and the gate and drain of the transistor QP1 are connected, so that the transistor QP1 is equivalent to a diode. At this time, when the potential of the data line D1 is fixed to a predetermined potential (for example, 0 V) and the transistor QP2 is turned on, a forward voltage is generated at both ends of the equivalent diode, and the voltage is held in the capacitor C. .

  As a result, even if the threshold voltage of the transistor QP1 varies in the plurality of pixel circuits, the voltage corresponding to the threshold voltage is held in the capacitor C. Therefore, due to the variation in the threshold voltage of the transistor QP1. Variations in drain current can be compensated. Thereafter, by supplying the pixel signal to the data line D1 in a state where the threshold compensation signal is deactivated to a high level and the transistor QP3 is turned off, the potential of the pixel signal is applied to the second electrode of the capacitor C. Superposed on the held potential.

  The source of the transistor QP4 is connected to the drain of the transistor QP1, and the drain of the transistor QP4 is connected to the anode of the organic light emitting diode D. A light emission control signal is supplied to the gate of the transistor QP4, and the transistor QP4 opens and closes a connection between the drain of the transistor QP1 and the anode of the organic light emitting diode D according to the light emission control signal.

  That is, when the light emission control signal is activated to a low level, the transistor QP4 is turned on, and the drain current of the transistor QP1 is supplied to the organic light emitting diode D. On the other hand, when the light emission control signal is deactivated to a high level, the transistor QP4 is turned off and the drain current of the transistor QP1 is not supplied to the organic light emitting diode D. Thus, the light emission period of the organic light emitting diode D can be controlled according to the period during which the light emission control signal is activated.

  The source of the transistor QP5 is connected to the reset potential line R1, and the drain of the transistor QP5 is connected to the anode of the organic light emitting diode D. The LED reset signal is supplied to the gate of the transistor QP5, and the transistor QP5 opens and closes the connection between the anode of the organic light emitting diode D and the reset potential line R1 according to the LED reset signal.

  That is, when the LED reset signal is activated to a low level, the transistor QP5 is turned on, and a predetermined reset potential (for example, 0 V) is applied to the anode of the organic light emitting diode D. Thereby, light emission of the organic light emitting diode D can be stopped completely. On the other hand, when the LED reset signal is deactivated to a high level, the transistor QP5 is turned off, and the organic light emitting diode D can emit light.

  The reset potential line R1 can also be used to measure the drain current of the transistor QP1 in the test mode. For this purpose, a first transmission gate constituted by a P-channel MOS transistor QP11 and an N-channel MOS transistor QN11 is connected between the reset potential line R1 and the test line T1. A second transmission gate constituted by a P channel MOS transistor QP12 and an N channel MOS transistor QN12 is connected between the reset potential line R1 and the reset potential.

  In the test mode, the test control signal is activated to a low level, and the output signal of the inverter INV becomes a high level. Accordingly, the transistors QP11 and QN11 of the first transmission gate are turned on, the transistors QP12 and QN12 of the second transmission gate are turned off, and the reset potential line R1 is connected to the test line T1. Thus, when the transistor QP5 is on, the drain current of the transistor QP1 can be measured via the test line T1.

  On the other hand, in the normal operation mode, the test control signal is deactivated to a high level, and the output signal of the inverter INV becomes a low level. Accordingly, the transistors QP11 and QN11 of the first transmission gate are turned off, the transistors QP12 and QN12 of the second transmission gate are turned on, and the reset potential line R1 is connected to the reset potential.

  Although the configuration of the pixel circuit 1 has been described above, the configuration of the pixel circuits 2 and 3 is the same as that of the pixel circuit 1. Here, a shield line S1 is provided on the left side of the pixel circuit 1 in the drawing, and a shield line S2 is provided between the pixel circuit 1 and the pixel circuit 2, and the pixel circuit 2, the pixel circuit 3, Between them, a shield line S3 is provided. A transmission gate constituted by a P channel MOS transistor QP13 and an N channel MOS transistor QN13 is connected between the shield lines S1 to S3 and the reset potential.

  In the test mode, the transmission gate transistors QP13 and QN13 are turned off, and the shield lines S1 to S3 are disconnected from the reset potential. On the other hand, in the normal operation mode, the transistors QP13 and QN13 of the transmission gate are turned on, and the shield lines S1 to S3 are connected to the reset potential.

  Next, the layout of the pixel circuit shown in FIG. 3 will be described. In the case of a SiOLED, a gate electrode is formed on a partial region of a silicon semiconductor substrate through a gate insulating film, impurity diffusion regions serving as a source and a drain are formed in the semiconductor substrate on both sides thereof, and a transistor Is formed.

  On the semiconductor substrate on which the transistor is formed, a first wiring layer is formed via a first interlayer insulating film, and further, a first wiring layer is formed thereon via a second interlayer insulating film. In this way, a necessary number of wiring layers are formed. For example, the interlayer insulating film is made of silicon dioxide, and the wiring layer is made of aluminum.

  FIG. 4 is a plan view showing a layout of gate electrodes and impurity diffusion regions in the pixel circuit shown in FIG. FIG. 5 is a plan view showing the layout of the first wiring layer in the pixel circuit shown in FIG. 3, and FIG. 6 is a plan view showing the layout of the second wiring layer in the pixel circuit shown in FIG. 5 and 6, the layout of each wiring layer is shown in gray on the layout of the gate electrode and the impurity diffusion region. Further, the x mark represents a through hole formed in the interlayer insulating film in order to connect the wiring of each wiring layer to the lower layer.

  4 to 6 show three pixel circuits 1 to 3 that are adjacent to each other in the first direction (X-axis direction shown in FIG. 1), the layout of other pixel circuits is also the first direction. In FIG. 1, the adjacent one set (two) of pixel circuits is in a mirror arrangement. For a pair of pixel circuits adjacent in the second direction (Y-axis direction shown in FIG. 1), the same pattern may be repeated or a mirror arrangement may be used. Note that the first direction and the second direction in the layout of the pixel circuit are not limited to the X-axis direction and the Y-axis direction shown in FIG.

  As shown in FIG. 4, in the pixel circuits 1 and 2 adjacent in the first direction, the gate electrodes (G), the source (S), and the drain (D) of the transistors QP1 to QP5 are the boundary lines of the pixel circuit. Is laid out with line symmetry. Further, the gate electrodes of a pair of transistors QP4 arranged symmetrically are integrally formed.

  In the pixel circuits 2 and 3 adjacent in the first direction, the gate electrodes (G), the sources (S), and the drains (D) of the transistors QP1 to QP5 are symmetric with respect to the boundary lines of the pixel circuits. Has been. Furthermore, the gate electrodes of the pair of transistors QP2 that are symmetrically arranged are integrally configured, and the gate electrodes of the pair of transistors QP3 that are symmetrically arranged are integrally configured, and are arranged symmetrically. The gate electrodes of the set of transistors QP5 are integrally formed.

  As described above, in at least one set of pixel circuits adjacent in the first direction, the gate electrodes and the impurity diffusion regions of the plurality of transistors are laid out in line symmetry so that the wiring can be efficiently arranged in the wiring layer. . In addition, the gate electrodes of at least one set of transistors arranged symmetrically in at least one set of pixel circuits adjacent in the first direction are integrated and configured integrally, whereby the gate electrodes of these transistors are individually set. Compared with the case of the configuration, the distance between the transistors can be narrowed by the space between the gate electrodes, and the pixel pitch can be reduced.

  As shown in FIG. 5, the first wiring layer includes a scanning line, a shield line, a threshold compensation signal wiring, a light emission control signal wiring, and an LED reset signal wiring along the first direction. Is formed. In the pixel circuits 1 and 2, the gate electrode formed integrally with one set of the transistors QP 4 is connected to the light emission control signal wiring at one connection point. Further, in the pixel circuit 2 and the pixel circuit 3, the gate electrode formed integrally with the one set of transistors QP2 is connected to one scanning line at one connection point, and the one set of transistors QP3 is integrated. Are connected to the threshold compensation signal wiring at one connection point, and the gate electrode formed integrally with one set of transistors QP5 is connected to the LED reset signal at one connection point. Connected to the wiring.

  In this way, by integrally connecting the gate electrodes formed integrally with one set of transistors arranged symmetrically in one set of pixel circuits in the first direction to one wiring at one connection point The pixel circuit can be downsized by reducing the number of through holes and contacts.

  The shield line is not only arranged between the scanning line and the threshold compensation signal wiring, but in each of the pixel circuits 1 to 3, the wiring connected to the gate electrode of the transistor QP1 and the scanning line It is also arranged between. Further, the shield line is also arranged between two wirings respectively connected to one set of transistors QP1 arranged symmetrically in one set of adjacent pixel circuits. Since the shielding effect is increased by arranging the shield lines in such a layout pattern, it is possible to reduce the influence of crosstalk on display between adjacent pixels.

  As shown in FIG. 6, shield lines S1 to S3, data lines D1 to D3, and reset potential lines R1 to R3 are formed along the second direction in the second wiring layer. Here, the shield line S3 is disposed between the two data lines D2 and D3 connected to the pixel circuits 2 and 3 adjacent to each other in the first direction. Accordingly, even if the layout of a set of pixel circuits adjacent in the first direction is mirror-arranged, it is possible to prevent two data lines from being adjacent to each other and reduce crosstalk due to parasitic capacitance between the data lines. Can do.

Also, as shown in FIGS. 4 to 6, in a set of pixel circuits adjacent in the first direction, the layout of the portions in contact with the upper layer is also arranged in a mirror so that the wiring between the wirings in these pixel circuits is made. There is no difference in capacitive coupling. Further, a wiring for supplying the power supply potential V _EL is arranged in the third wiring layer, and this wiring is electrically connected to the source of the transistor QP1 through the second wiring layer and the first wiring layer. Is done. Thus, by separately providing the third wiring layer for supplying the power supply potential V _EL , it is possible to reduce the influence of noise generated from the first and second wiring layers on the source potential of the transistor QP1. .

The capacitor C shown in FIG. 3 is formed with, for example, an MIM (metal-insulator-metal) structure in which an insulating layer is sandwiched between metals. In that case, the first electrode of the capacitor C is formed in the third wiring layer, the second electrode of the capacitor C is formed in the fourth wiring layer, and the first electrode of the capacitor C is formed in the fifth wiring layer. The capacitor C may have a laminated structure. The power supply potential V _EL is supplied to the first electrode of the capacitor C formed in the third and fifth wiring layers.

Thus, by making the potential of the first electrode of the capacitor C the same as the source potential and the back gate potential of the transistor QP1, the power supply potential V _EL supplied to the first electrode of the capacitor C is changed to the transistor QP1. It can be stably supplied to a source or the like with low impedance.

  In the above embodiment, the case where the P-channel MOS transistor is used in the pixel circuit has been described. However, the present invention can also be applied to the case where the N-channel MOS transistor is used in the pixel circuit.

  Thus, the present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those who have ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 1-3 ... Pixel circuit, 10 ... Image data processing circuit, 20 ... Display timing generation circuit, 30 ... Scan line driver, 40 ... Data line driver, 50 ... Pixel part, 60 ... Display apparatus, 70 ... Organic EL panel, 70a ... Display area 71 ... Semiconductor substrate 72 ... OLED layer 73 ... Cover glass 80 ... Flexible substrate G1, G2, ... Scan line, D1, D2, ... Data line, S1-S3 ... Shield line, R1-R3 ... reset potential line, T1-T3 ... test line, D ... organic light emitting diode, QP1-QP13 ... P-channel MOS transistor, QN11-QN13 ... N-channel MOS transistor, C ... capacitor

Claims (8)

A first data line and a second data line extending in a first direction;
A light emission control line;
A first light emitting element; a first transistor for passing a first current through the first light emitting element in response to a first pixel signal from the first data line; and a connection between the first transistor and the first light emitting element. A first pixel circuit comprising: a second transistor ,
A second light emitting element, a third transistor for passing a second current through the second light emitting element in response to a second pixel signal from the second data line, and a connection between the third transistor and the second light emitting element. A second pixel circuit including a fourth transistor,
Have
The display device , wherein the gate electrode of the second transistor and the gate electrode of the fourth transistor are integrally formed and connected to the light emission control line at a connection point . The display device according to claim 1, wherein the second transistor is arranged so as to be line-symmetric with the fourth transistor . Further comprising the placed shielded wire between the second data line and the first data line, a display device according to claim 1 or 2. The display device according to claim 1, wherein the first transistor is arranged so as to be line-symmetric with the third transistor . 5. The device according to claim 1, wherein the first data line, the second data line, the light emission control line, the first pixel circuit, and the second pixel circuit are formed on a semiconductor substrate. The display device described. The display device according to claim 1, wherein the first light emitting element and the second light emitting element are organic light emitting diodes . The display device according to claim 1, wherein the light emission control line is formed on a first wiring layer different from a gate electrode of the second transistor and a gate electrode of the fourth transistor .   An electronic apparatus comprising the display device according to claim 1.