JP6425933B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Various types of semiconductor devices have been proposed to perform specific functions with respect to external current input / output (see, for example, Patent Document 1). Generally, in order to fulfill the function of this semiconductor device, a plurality of elements, each of which constitutes a part of an electric circuit, are incorporated. Metal leads are used to support and conduct these elements. The number, shape and size of the leads are determined in accordance with the function, shape and size of the plurality of elements. The plurality of elements mounted on the leads are covered with a sealing resin. The sealing resin is for protecting these elements and part of the leads. Such a semiconductor device is mounted on, for example, a circuit board of an electronic device and used.

  The formation of the leads is often performed by, for example, punching using a mold. The method using a mold has an advantage that the lead can be formed efficiently and accurately. However, generally, the number, size, and shape of the leads differ depending on the plurality of elements. For this reason, when the function or the like required for the semiconductor device is changed, it is necessary to change the size and shape of the lead. In order to realize this, it is forced to remake the above mold. Since the mold is relatively expensive, the cost of the semiconductor device may be increased if the semiconductor device is produced in a small amount.

  Moreover, since the said lead | read | reed is what processed the metal plate, it is generally flat shape. Arbitrary drawing may be performed to obtain a three-dimensional shape, but some restrictions are imposed. The semiconductor devices are required to have higher functionality and multifunctionality year after year. In order to meet this demand, high-density mounting of the plurality of elements, or three-dimensional arrangement other than flat arrangement is required.

Unexamined-Japanese-Patent No. 2012-99673

  The present invention has been conceived under the above-described circumstances, and an object thereof is to provide a semiconductor device capable of reducing the manufacturing cost. Another object of the present invention is to provide a semiconductor device which can be downsized by relaxing the restriction on the arrangement of a plurality of elements. Another object of the present invention is to manufacture such a semiconductor device properly and to function properly.

  According to a first aspect of the present invention, there is provided a semiconductor device provided with a main surface, an outer side surface intersecting with the main surface, and a concave portion recessed from the main surface, and made of a semiconductor material; A wiring layer formed on the substrate, one or more elements contained in the recess, and a sealing resin covering at least a part of the one or more elements, and the outer side surface is a standing outer side surface And an inclined outer surface which is interposed between the main surface and the rising outer surface and which is inclined with respect to any of the main surface and the rising outer surface.

  In a preferred embodiment of the present invention, the inclined outer side surface is smooth as compared to the upright outer side surface.

  In a preferred embodiment of the present invention, the upright outer side surface is perpendicular to the main surface.

  In a preferred embodiment of the present invention, the outer side surface surrounds the main surface as viewed in the normal direction of the main surface and has a rectangular ring shape.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the recess has an inclined inner side inclined to the main surface and a bottom.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the recess has four inclined inner surfaces.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the inclined inner surface with respect to the main surface.

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided, and the recess receives a first recess for receiving the one or more elements and the additional element. A second concave portion positioned closer to the main surface than the first concave portion, the bottom surface constituting a first bottom surface constituting the first concave portion, and the second concave portion; A second bottom surface positioned closer to the main surface than the bottom surface, and the inclined inner side surface constitutes a first inclined inner side surface constituting the first concave portion and the second concave portion, and the second bottom surface And a second inclined inner side surface connected to the main surface.

  In a preferred embodiment of the present invention, a resin forming portion formed on at least one of the main surface and the recess is further provided.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of external terminals formed on the main surface.

  In a preferred embodiment of the present invention, the resin forming portion includes a first resin forming portion formed on the main surface, and the external terminal is formed on the first resin forming portion.

  In a preferred embodiment of the present invention, the additional element is supported by the second bottom surface and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.

  According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of recesses recessed from the main surface in a substrate material having a main surface; A step of forming an inclined groove recessed from the main surface, a step of forming a wiring layer on the substrate material including the plurality of recesses, and a plurality of elements are mounted such that at least one is accommodated in each of the recesses. And forming a sealing resin covering the plurality of elements, and cutting along a cutting line included in the inclined groove when viewed in the normal direction of the main surface. .

  In a preferred embodiment of the present invention, the substrate material is Si, and in the step of forming the recess and the step of forming the inclined groove, the main surface of the substrate material is anisotropically etched. By the same time.

  In a preferred embodiment of the present invention, the recess has an inclined inner side inclined to the main surface and a bottom.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the recess has four inclined inner surfaces.

  In a preferred embodiment of the present invention, in the step of forming the recess, a first recess having a first bottom surface and a first sloped inner surface, a second bottom surface connected to the first sloped inner surface, and the second surface Forming a second recess having a bottom surface and a second inclined inner side surface connected to the main surface;

  In a preferred embodiment of the present invention, in the step of forming the sealing resin, the inclined groove is exposed from the sealing resin.

  According to a third aspect of the present invention, there is provided a semiconductor device comprising: a main surface; and a substrate made of a semiconductor material and having a recess recessed from the main surface, and a wiring layer at least a part of which is formed on the substrate. A sealing resin covering at least a part of the one or more elements, and a resin forming portion formed on at least one of the main surface and the depression, the at least one element housed in the concave portion. It is characterized by

  In a preferred embodiment of the present invention, the resin forming portion includes a first resin forming portion formed on the main surface, and the wiring layer includes a plurality of external terminals formed on the first resin forming portion. Have.

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided.

  In a preferred embodiment of the present invention, the recess has an inclined inner side inclined to the main surface and a bottom.

  In a preferred embodiment of the present invention, the resin forming portion includes a second resin forming portion formed on the bottom surface, and the additional element is mounted on the second resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer is formed in the second resin forming portion, and has a plurality of second resin forming portion pads for mounting the additional element.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the recess has four inclined inner surfaces.

  In a preferred embodiment of the present invention, the recess includes a first recess containing the one or more elements, and a second recess located closer to the main surface than the first recess, and the bottom surface The method includes a first bottom surface forming the first recess, and a second bottom surface forming the second recess and located closer to the main surface than the first bottom surface, and the inclined inner side surface And a second inclined inner side surface that constitutes the first concave portion and the second inclined inner side surface that constitutes the second concave portion and is connected to the second bottom surface and the main surface, and the second resin forming portion It is formed on the second bottom surface.

  In a preferred embodiment of the present invention, the substrate has an outer surface intersecting with the main surface, and the outer surface is interposed between a rising outer surface, the main surface and the rising outer surface. And an inclined outer surface inclined with respect to any of the main surface and the rising outer surface.

  In a preferred embodiment of the present invention, the inclined outer side surface is smooth as compared to the upright outer side surface.

  In a preferred embodiment of the present invention, the outer side surface surrounds the main surface as viewed in the normal direction of the main surface and has a rectangular ring shape.

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided, and the recess accommodates the one or more elements and has a first bottom surface and a first inclined inner side surface. And a second recess having a second bottom surface connected to the first inclined inner side surface and a second inclined inner side surface connected to the second bottom surface and the main surface.

  In a preferred embodiment of the present invention, the resin forming portion includes a second resin forming portion formed on the second bottom surface, and the additional element is mounted on the second resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer is formed in the second resin forming portion, and has a plurality of second resin forming portion pads for mounting the additional element.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, the first recess has four first inclined inner side surfaces, and the second recess has four of the first 2 has an inclined inner surface.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the first inclined inner surface and the second inclined inner surface with respect to the main surface.

  According to a fourth aspect of the present invention, there is provided a semiconductor device provided with a main surface, an outer side surface intersecting with the main surface, and a concave portion recessed from the main surface and made of a semiconductor material; A wiring layer formed on the substrate, one or more elements contained in the recess, a sealing resin covering at least a part of the one or more elements, and a metal film formed on the outer surface It is characterized by having.

  In a preferred embodiment of the present invention, the outside surface is between the rising outside surface and the main surface and the rising outside surface, and is inclined with respect to any of the main surface and the rising outside surface. And the metal film is formed on the inclined outer surface and exposes the upright outer surface.

  In a preferred embodiment of the present invention, the inclined outer side surface is smooth as compared to the upright outer side surface.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of external terminals formed on the main surface, and the metal film has a connection path connected to any of the plurality of external terminals.

  In a preferred embodiment of the present invention, the metal film surrounds the main surface as a whole in the normal direction of the main surface.

  In a preferred embodiment of the present invention, the one or more elements include a wireless communication element.

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided, and an additional metal film located between the additional element and the one or more elements is provided.

  In a preferred embodiment of the present invention, the outer side surface surrounds the main surface as viewed in the normal direction of the main surface and has a rectangular ring shape.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the recess has an inclined inner side inclined to the main surface and a bottom.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, and the recess has four inclined inner surfaces.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the inclined inner surface with respect to the main surface.

  In a preferred embodiment of the present invention, a resin forming portion formed on at least one of the main surface and the recess is further provided.

  In a preferred embodiment of the present invention, the resin forming portion includes a first resin forming portion formed on the main surface, and the wiring layer includes a plurality of external terminals formed on the first resin forming portion. Have.

  In a preferred embodiment of the present invention, an additional element covering at least a part of the one or more elements is provided, and the recess accommodates the one or more elements and has a first bottom surface and a first inclined inner side surface. And a second recess having a second bottom surface connected to the first inclined inner side surface and a second inclined inner side surface connected to the second bottom surface and the main surface.

  In a preferred embodiment of the present invention, the additional element is supported by the second bottom surface and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the first inclined inner surface and the second inclined inner surface with respect to the main surface.

  According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a main surface; and a substrate made of a semiconductor material and having a recess recessed from the main surface, and a wiring layer at least a part of which is formed on the substrate. A plurality of elements accommodated in the recess, and a sealing resin covering at least a part of the plurality of elements, the recess having a bottom surface and at least two inclined inner side surfaces sandwiching the bottom surface The plurality of elements are one or more first elements, an opposing main surface opposite to the first element with respect to the first element, and an opposing main surface facing the first element, and the opposing main surface And a second element having an inclined inclined side surface, wherein the inclined side surface of the second element is supported by the inclined inner side surface of the substrate.

  In a preferred embodiment of the present invention, at least one of the one or more first elements is supported on the bottom surface.

  In a preferred embodiment of the present invention, the wiring layer is formed on the sloped inner side surface and has a sloped inner side surface pad for mounting the second element.

  In a preferred embodiment of the present invention, the substrate and the second element are constituted by a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, each of the main surface and the opposite main surface is either the (100) plane or the (110) surface, and the inclination angle of the inclined side with respect to the opposite main surface is Same as the inclination angle of the inclined inner side surface with respect to the main surface.

  In a preferred embodiment of the present invention, the substrate has an outer surface intersecting with the main surface, and the outer surface is interposed between a rising outer surface, the main surface and the rising outer surface. And an inclined outer surface inclined with respect to any of the main surface and the rising outer surface.

  In a preferred embodiment of the present invention, the inclined outer side surface is smooth as compared to the upright outer side surface.

  In a preferred embodiment of the present invention, the outer side surface surrounds the main surface as viewed in the normal direction of the main surface and has a rectangular ring shape.

  In a preferred embodiment of the present invention, the inclination angle of the inclined outer surface with respect to the main surface is the same as the inclination angle of the inclined inner surface with respect to the main surface.

  In a preferred embodiment of the present invention, a conductive wiring pattern is formed in a predetermined region extending from the inclined side surface to the opposing main surface of the second element.

  In a preferred embodiment of the present invention, the second element has the two inclined side surfaces sandwiching the opposing main surface, and is supported by the two inclined inner side surfaces via the two inclined surface sides. There is.

  In a preferred embodiment of the present invention, the second element is an integrated circuit element.

  In a preferred embodiment of the present invention, the wiring layer has a plurality of external terminals formed on the main surface.

  In a preferred embodiment of the present invention, a resin forming portion formed on the main surface is further provided, and the wiring layer has a plurality of external terminals formed on the resin forming portion.

  In a preferred embodiment of the present invention, the sealing resin comprises a first sealing resin which covers the one or more first elements, and a second sealing resin which covers the second element.

  In a preferred embodiment of the present invention, the second sealing resin exposes the external terminal.

  In a preferred embodiment of the present invention, the second sealing resin has a portion located outward of the main surface in the normal direction of the main surface.

  In a preferred embodiment of the present invention, an additional resin forming portion formed in the recess is further provided.

  In a preferred embodiment of the present invention, the opposite main surface of the second element is supported by the additional resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer is formed in the additional resin forming portion and has a plurality of additional resin forming portion pads for mounting the second element.

  In a preferred embodiment of the present invention, a plurality of the second elements are provided at intervals in the normal direction of the main surface.

  According to a sixth aspect of the present invention, there is provided a semiconductor device comprising: a main surface; and a substrate made of a semiconductor material and having a recess recessed from the main surface; A sealing resin for covering at least a part of the one or more first elements accommodated in the recess and the one or more first elements, and filling the recess with the sealing resin; and a depth of the recess And a plurality of columnar conductive portions penetrating in a direction and each connected to a portion of the wiring layer formed in the concave portion.

  In a preferred embodiment of the present invention, the recess has an inclined inner side surface inclined with respect to the main surface, and a bottom surface, and the columnar conductive portion is formed by the method of the main surface from the inclined inner side surface It extends along the line direction.

  In a preferred embodiment of the present invention, the wiring layer is formed on the inclined inner side surface, and has a plurality of inclined inner side surface pads to which one end of the columnar conductive portion is connected.

  In a preferred embodiment of the present invention, a plurality of external terminals are provided to each of which the other end of the columnar conductive portion is connected.

  In a preferred embodiment of the present invention, the sealing resin covers at least a part of the main surface.

  In a preferred embodiment of the present invention, the one end surface of the sealing resin facing outward in the normal direction of the main surface and the other end of the columnar conductive portion are flush with each other, and the sealing resin An external terminal pad for mounting the external terminal is formed on the one end surface.

  In a preferred embodiment of the present invention, the recess has two inclined inner side surfaces sandwiching the bottom surface.

  In a preferred embodiment of the present invention, the plurality of columnar conductive portions extend along the normal direction of the main surface from the two inclined inner side surfaces.

  In a preferred embodiment of the present invention, all of the plurality of columnar conductive portions extend from one of the two inclined inner side surfaces along the normal direction of the main surface, and the plurality of external terminals The plurality of first external terminals in a position overlapping with any one of the columnar conductive portions in the normal direction of the main surface and the plurality of first external terminals are spaced apart from each other across the bottom surface. And a plurality of second external terminals.

  In a preferred embodiment of the present invention, a resin forming portion formed in the recess is further provided.

  In a preferred embodiment of the present invention, the resin forming portion is formed on the bottom surface.

  In a preferred embodiment of the present invention, a second element covering at least a part of the one or more first elements is provided, and the second element is mounted on the resin forming portion.

  In a preferred embodiment of the present invention, the wiring layer is formed in the resin forming portion, and has a plurality of resin forming portion pads for mounting the second element.

  In a preferred embodiment of the present invention, a second element covering at least a part of the one or more first elements is provided, and the recess is a first recess for accommodating the one or more first elements; A second recess that accommodates the two elements and is positioned closer to the main surface than the first recess, the bottom surface includes a first bottom surface forming the first recess, and the second recess; A second bottom surface positioned closer to the main surface than the first bottom surface, and the inclined inner side surface constitutes a first inclined inner side surface constituting the first concave portion, and the second concave portion; And a second inclined inner side surface connected to the second bottom surface and the main surface.

  In a preferred embodiment of the present invention, the second element is supported by the second bottom surface, and overlaps at least a part of the first recess when viewed in the normal direction of the main surface.

  In a preferred embodiment of the present invention, the columnar conductive portion extends from the second inclined inner side surface along the normal direction of the main surface.

  In a preferred embodiment of the present invention, the inclined inner side surface pad is formed on the second inclined inner side surface.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface, the first recess has four first inclined inner side surfaces, and the second recess has four of the first 2 has an inclined inner surface.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a principal part perspective view showing a semiconductor device based on a 1st embodiment of the present invention. It is a principal part top view which shows the semiconductor device of FIG. It is sectional drawing in alignment with the III-III line of FIG. It is sectional drawing in alignment with the IV-IV line of FIG. It is a perspective view which shows the board | substrate of the semiconductor device of FIG. FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main-portion cross-sectional view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 7 is a main portion perspective view showing an example of a method of manufacturing the semiconductor device of FIG. 1; FIG. 27 is an essential part cross sectional view showing an example different from FIG. 26 in the manufacturing method of the semiconductor device of FIG. 1; It is a figure which shows the step following FIG. It is a principal part top view showing a semiconductor device based on a 2nd embodiment of the present invention. FIG. 31 is a cross-sectional view taken along the line XXXI-XXXI of FIG. 30. FIG. 32 is a cross-sectional view similar to FIG. 31 showing a modification of the semiconductor device shown in FIGS. 30 and 31; It is a principal part top view showing a semiconductor device based on a 3rd embodiment of the present invention. It is sectional drawing which follows the XXXIV-XXXIV line | wire of FIG. FIG. 35 is a cross-sectional view similar to FIG. 34 showing a modified example of the semiconductor device shown in FIGS. 33 and 34; FIG. 35 is a cross-sectional view similar to FIG. 34 showing another modified example of the semiconductor device shown in FIGS. 33 and 34. FIG. It is a principal part top view showing a semiconductor device based on a 4th embodiment of the present invention. FIG. 38 is a cross-sectional view taken along the line XXXVIII-XXXVIII of FIG. 37. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. It is sectional drawing for demonstrating the formation procedure of a columnar electroconductive part. FIG. 39 is a cross-sectional view similar to FIG. 38 showing a modification of the semiconductor device shown in FIG. 37 and FIG. 38; It is a schematic plan view of the semiconductor device shown in FIG. FIG. 39 is a cross-sectional view similar to FIG. 38 showing another modified example of the semiconductor device shown in FIG. 37 and FIG. 38;

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  1 to 4 show a semiconductor device according to a first embodiment of the present invention. The semiconductor device 1A of the present embodiment includes a substrate 100A, resin forming portions 130A and 140A, wiring layers 200A, three direction sensor elements 311A, 312A and 313A, integrated circuit element 330A, two capacitors 343A, sealing resin 400A and metal. A membrane 500A is provided. In FIGS. 1 and 2, for convenience of understanding, the sealing resin 400A is omitted, and the three direction sensor elements 311A, 312A, 313A, the integrated circuit element 330A and the two capacitors 343A are shown by imaginary lines. There is. 3 is a cross-sectional view in the yz plane along the line III-III in FIG. 2, and FIG. 4 is a cross-sectional view in the zx plane along the line IV-IV in FIG.

  The semiconductor device 1A is configured as an orientation detection module that can detect azimuths in three directions and can be surface-mounted by the configuration described below. As an example of the size of the semiconductor device 1A, the dimensions in plan view are about 1.5 mm × 2.0 mm and the thickness is about 0.6 mm.

  The substrate 100A is a base of the semiconductor device 1A, and includes a base 106A and an insulating layer 107A. The substrate 100A has a main surface 101A, a back surface 102A, four outer surfaces 103A, and a recess 108A. The thickness of the substrate 100A is, for example, about 600 μm. In the present embodiment, the main surface 101A and the back surface 102A face in opposite directions in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1A. Also, the x direction and the y direction are both perpendicular to the z direction.

The base 106A is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. In addition, the insulating layer 107A is made of SiO ₂ in the present embodiment. In addition, the material of the base 106A is not limited to Si, as long as it can form the recess 108A satisfying the intention described later. The insulating layer 107A covers a portion of the base 106A that faces from the opposite side to the back surface 102A. The thickness of insulating layer 107A is, for example, about 0.1 to 1.0 μm.

  FIG. 5 is a perspective view showing the substrate 100A. In the present embodiment, the (100) plane of the base 106A is employed as the main surface 101A. The recess 108A is recessed from the main surface 101A toward the back surface 102A. In the present embodiment, the recess 108A includes the first recess 110A and the second recess 120A. The first recess 110A is located on the back surface 102A side and has a first bottom surface 111A and four first inclined inner side surfaces 112A. The second recess 120A is located closer to the main surface 101A than the first recess 110A, and has two second bottom surfaces 121A and four second inclined inner side surfaces 122A. The shapes of the first recess 110A and the second recess 120A depend on the fact that the (100) plane is adopted as the main surface 101A.

  By forming the concave portion 108A, the main surface 101A has a rectangular annular shape in plan view. More specifically, in the main surface 101A, two portions located apart in the y direction across the recess 108A are significantly larger than two portions located away in the x direction across the recess 108A. ing.

  The first recess 110A is rectangular in plan view. The depth of the first recess 110A is, for example, about 440 μm. The first bottom surface 111A is rectangular in plan view. The four first inclined inner side surfaces 112A surround the first bottom surface 111A in plan view, and have a substantially trapezoidal shape with a portion in contact with the first bottom surface 111A as an upper bottom. Each first inclined inner side surface 112A is inclined with respect to the first bottom surface 111A. In the present embodiment, the inclination angle of the first inclined inner side surface 112A with respect to the xy plane is about 55 °. The point that the first inclined inner side surface 112A is substantially trapezoidal and the inclination angle is 55 ° depends on adopting the (100) plane as the main surface 101A.

  The second recess 120A is rectangular in plan view. The depth of the second recess 120A is, for example, about 120 μm. The two second bottom surfaces 121A are rectangular in plan view, and sandwich the first recess 110A. Each second bottom surface 121A is connected to the first inclined inner side surface 112A. The four second inclined inner side surfaces 122A surround the two second bottom surfaces 121A in a plan view, and have a substantially trapezoidal shape. Each second inclined inner side surface 122A is inclined with respect to the second bottom surface 121A. In the present embodiment, the inclination angle of the second inclined inner side surface 122A with respect to the xy plane is about 55 °. The point that the second inclined inner side surface 122A is substantially trapezoidal and the inclination angle is 55 ° depends on the adoption of the (100) plane as the principal surface 101A.

  The resin forming portions 130A and 140A are for providing a predetermined level difference on the substrate 100A, and are formed on the substrate 100A (insulating layer 107A). In the present embodiment, the resin forming portion 130A is formed on the main surface 101A, and is a portion to be a base of the external terminal 221 described later. The resin forming portion 130A is formed at two portions of the main surface 101A which are disposed apart in the y direction across the recess 108A. The height of the resin forming portion 130A is, for example, about 50 μm. The resin forming portion 140A is formed on each of the two second bottom surfaces 121A of the second recess 120A, and is a portion on which the integrated circuit element 330A is mounted. In the present embodiment, the height of the resin forming portion 140A is, for example, about 50 μm. These resin forming portions 130A and 140A have flat top surfaces and side surfaces 132A and 142A inclined with respect to the top surfaces. As a material of these resin formation parts 130A and 140A, an epoxy resin, a phenol resin, a polyimide resin, polybenzoxazole (PBO) resin, a silicone resin is mentioned, for example. The resin forming portions 130A and 140A may be either translucent resin or non-translucent resin, but in the present embodiment, non-translucent resin is preferable.

  The wiring layer 200A is for mounting the three direction sensor elements 311A, 312A, 313A, the integrated circuit element 330A, and the two capacitors 343A, and for forming a current path for input / output to these. The wiring layer 200A is mainly formed on the insulating layer 107A, and in the present embodiment, the barrier / seed layer 201A and the plating layer 202A are stacked.

  The barrier / seed layer 201A is a so-called base layer for forming a desired plating layer 202A, and is mainly formed on the insulating layer 107A. The barrier / seed layer 201A is formed of, for example, a Ti layer as a barrier layer formed on the insulating layer 107A and a Cu layer as a seed layer stacked on the barrier layer. Barrier and seed layer 201A is formed, for example, by sputtering. In the present embodiment, the barrier / seed layer 201A is formed on a predetermined portion of the insulating layer 107A and the resin forming portions 130A and 140A.

  The plating layer 202A is made of, for example, Cu and is formed by electrolytic plating using the barrier / seed layer 201A. The thickness of the plating layer 202A is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200A includes a first bottom surface pad 211A, a first inclined inner side surface pad 212A, a resin forming portion pad 213A, an external terminal 221A, and connection paths 231A, 234A, 235A, 236A.

  The first bottom surface pad 211A is formed on the first bottom surface 111A of the first recess 110A, and has, for example, a rectangular shape. In the present embodiment, four first bottom surface pads 211A are formed. In the present embodiment, the first bottom surface pad 211A is used to mount the orientation sensor element 311A.

  The first sloped inner side surface pad 212A is formed on the first sloped inner side surface 112A of the first recess 110A, and has, for example, a rectangular shape. In the present embodiment, four first sloped inner side surface pads 212A are formed on two first sloped inner side surfaces 112A which are disposed apart in the y direction with the first bottom surface 111A interposed therebetween. These four first inclined inner side surface pads 212A are used to mount the orientation sensor elements 312A and 313A. Further, in the present embodiment, two first inclined inner side surface pads 212A are formed on the two first inclined inner side surfaces 112A disposed apart in the x direction with the first bottom surface 111A interposed therebetween. These two inclined inner side pads 212A are used to mount two capacitors 343A.

  The resin forming portion pad 213A is formed on the resin forming portion 140A on the second bottom surface 121A, and has, for example, a rectangular shape. In the present embodiment, a plurality of resin formed portion pads 213A are formed in the resin formed portion 140A of each second bottom surface 121. More specifically, nine resin forming portion pads 213A arranged in the x direction are spaced apart in the y direction with the first recess 110A interposed therebetween. In the present embodiment, the resin forming portion pad 213A is used to mount the integrated circuit element 330A.

  The external terminal 221A is formed in the resin forming portion 130A on the main surface 101A, and is used to, for example, surface mount the semiconductor device 1A on a circuit board of an electronic device not shown. In the present embodiment, four external terminals 221A are formed for each of the resin forming portions 130A provided in two portions of the main surface 101A that are separated in the y direction across the recess 108A. The external terminal 221A has a structure in which a bump obtained by electroless plating of a metal such as Ni, Pd, Au or the like is formed on the barrier / seed layer 201A and the plating layer 202A described above. Thereby, as shown in FIG. 3, the external terminal 221A has a shape which bulges in the z direction.

  The connection paths 231A, 234A, 235A, 236A are provided to form paths connecting the first bottom surface pad 211A, the first inclined inner side surface pad 212A, the resin forming portion pad 213A, and the external terminal 221A to each other.

  The connection path 231A constitutes a path from the main surface 101A (the resin forming portion 130A) to the second bottom surface 121A, and mainly conducts the external terminal 221A and the resin forming portion pad 213A. As shown in FIG. 2, in the present embodiment, each connection path 231A reaches the second bottom surface 121A via the second inclined inner side surface 122A of the second recess 120A. The portion of each connection path 231A formed on the second inclined inner side surface 122A extends along the y direction in plan view and is not inclined with respect to the y direction.

  The connection path 234A constitutes a path from the second bottom surface 121A to the first inclined inner side surface 112A, and electrically connects the resin forming portion pad 213A and the first inclined inner side surface pad 212A. In the present embodiment, some connection paths 234A extend in the y direction in plan view. In addition, the other connection path 234A is bent at the first inclined inner side surface 112A.

  The connection path 235A constitutes a path from the second bottom surface 121A to the first bottom surface 111A via the first inclined inner side surface 112A, and electrically connects the resin forming portion pad 213A and the first bottom surface pad 211A. . In the present embodiment, one connection path 235A extends in the y direction in plan view. In addition, the other communication path 235A is bent at the first inclined inner side surface 112A.

  The connection path 236A constitutes a path from the first inclined inner side surface 112A to the first bottom surface 111A, and electrically connects the first inclined inner side surface pad 212A and the first bottom surface pad 211A.

  In the present embodiment, the external terminal 221A positioned second from the left in the upper side of FIG. 2 is a so-called ground terminal. Further, the connection path 231A electrically connected to the external terminal 221A, the resin forming portion pad 213A, the connection path 235A, the first bottom surface pad 211A, the connection path 236A, and the first inclined inner side surface pad 212A are grounded.

  As shown in FIG. 2, the four outer side surfaces 103A of the substrate 100A surround the main surface 101A in the z-direction view, and form a rectangular ring shape. More specifically, each outer side surface 103A is configured to include an inclined outer side surface 104A and an upright outer side surface 105A. The inclined outer side surface 104A is interposed between the main surface 101A and the standing outer side surface 105A, and is inclined with respect to both the main surface 101A and the standing outer side surface 105A. In the present embodiment, the inclined outer side surface 104A is connected to the main surface 101A, and the rising outer side surface 105A is connected to the back surface 102A. In the present embodiment, the inclination angle of the inclined outer side surface 104A with respect to the xy plane is about 55 °. In addition, the point whose said inclination angle is 55 degrees depends on having employ | adopted the (100) surface as 101A of main surfaces.

  Here, the inclination angle of the inclined outer side surface 104A with respect to the xy plane (main surface 101A) is the same as the inclination angles of the first inclined inner side surface 112A and the second inclined inner side surface 122A with respect to the main surface 101A. Although details will be described later, the inclined outer side surface 104A, the first inclined inner side surface 112A, and the second inclined inner side surface 122A are intended to be at the same angle by forming by collective etching. The difference which can be inevitably caused by the variation of the etching conditions etc. is included in the same range in the present invention.

  The upright outer side surface 105A is substantially perpendicular to the major surface 101A and substantially parallel to the zx plane or the yz plane. In the present embodiment, the inclined outer side surface 104A is smoother than the upright outer side surface 105A. The fact that the inclined outer side surface 104A is smoother than the rising outer side surface 105A depends on the method of manufacturing the semiconductor device 1A described later.

  The metal film 500A is formed on the inclined outer side surface 104A. In the present embodiment, as shown in FIG. 2, the metal film 500A covers most of the inclined outer side surface 104A, and the metal film 500A as a whole surrounds the main surface 101A in the z direction. In the present embodiment, the metal film 500A is in the form of an integral ring. The metal film 500A has a connection path 510A for connecting to the external terminal 221. In the present embodiment, the connection path 510A is connected to the external terminal 221 positioned second from the upper left in FIG. Since the external terminal 221 is a ground terminal as described above, the metal film 500A conducted to the external terminal 221 is also grounded. The metal film 500A has a structure in which a barrier / seed layer 201A and a plating layer 202A are stacked in the same manner as the wiring layer 200A. The metal film 500A may have, for example, a configuration in which a plurality of elements, each of which is connected to ground, are annularly disposed instead of the annular configuration in which the whole is integrated.

  The three direction sensor elements 311A, 312A, and 313A have detection reference axes along different directions, and are used, for example, to detect the attitude of the semiconductor device 1A with respect to the geomagnetism. In the present embodiment, the orientation sensor elements 311A, 312A, and 313A have magnetic cores 314A, 315A, and 316A, as shown in FIG. The magnetic cores 314A, 315A, and 316A are metal rod-shaped members extending in a predetermined direction, and the longitudinal direction thereof corresponds to the detection reference axis of the direction sensor elements 311A, 312A, and 313A. The orientation sensor elements 311A, 312A, 313A further include coils (not shown) formed so as to surround the magnetic cores 314A, 315A, 316A. The thickness of the orientation sensor elements 311A, 312A, 313A is, for example, about 80 μm.

  In the present embodiment, the orientation sensor element 311A is supported by the first bottom surface 111A, and is mounted via the solder 351A using the four first bottom surface pads 211A. By such mounting form, the magnetic core 314A of the direction sensor element 311A is along the y direction.

  The orientation sensor element 312A is supported by the first inclined inner side surface 112A at the upper side in the drawing in FIG. 2, and is mounted via the solder 351A using four first inclined inner side surface pads 212A. With such a mounting form, the magnetic core 315A of the orientation sensor element 312A is perpendicular to the x direction and is along the direction included in the yz plane. This direction is parallel to the first inclined inner side surface 112A supporting the orientation sensor element 312A.

  The orientation sensor element 313A is supported by the first inclined inner side surface 112A at the lower side in the drawing in FIG. 2, and is mounted via the solder 351A using four first inclined side surface pads 212A. With such a mounting form, the magnetic core 316A of the orientation sensor element 313A is perpendicular to the x direction and is along the direction included in the yz plane. This direction is parallel to the first inclined inner side surface 112A supporting the orientation sensor element 313A.

  Further, in the present embodiment, the top surfaces of the orientation sensors 311A, 312A, and 313A located on the side opposite to the bottom surface are smaller than the bottom surface on the substrate 100A side. Further, the side surfaces connecting the bottom and top surfaces are inclined with respect to the direction in which the bottom and top surfaces are separated.

  The integrated circuit element 330A is for controlling an azimuth detection process using the three azimuth sensor elements 311A, 312A, and 313A. In the present embodiment, the integrated circuit element 330A is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and its thickness is about 80 to 100 μm.

  The integrated circuit element 330A is supported by the second bottom surface 121A via the resin forming portion 140A, and is mounted via the solder 351A using the resin forming portion pad 213A. As shown in FIG. 2, the integrated circuit element 330 </ b> A is mounted by using a plurality of resin forming portion pads 213 </ b> A spaced apart in the y direction, thereby supporting two sides. Further, the integrated circuit element 330A covers most of the first recess 110A except for a part thereof in plan view. Further, the integrated circuit element 330A overlaps with all of the orientation sensor elements 311A, 312A, and 313A in plan view, and also overlaps with the two capacitors 343A. As shown in FIGS. 3 and 4, the integrated circuit element 330A is accommodated in the second recess 120A in the z direction for the most part except its upper end. On the other hand, the upper end of the integrated circuit element 330A protrudes upward from the second recess 120A.

  The azimuth detection process by integrated circuit element 330A using azimuth sensor elements 311A, 312A, and 313A is performed, for example, as follows. As described above, the orientation sensor elements 311A, 312A, and 313A each have a magnetic core 314A, 315A, and 316A surrounded by the coil. The orientation sensor elements 311A, 312A, and 313A, that is, the magnetic cores 314A, 315A, and 316A, are in directions different from each other because the orientation sensor elements 311A, 312A, and 313A are in the mounting form described above. The directions along which these magnetic cores 314A, 315A, and 316A are stored are stored in the integrated circuit element 330A as known information.

  The two capacitors 343A are supported by the first inclined inner side surface 112A, and are spaced apart in the x direction across the orientation sensor element 311A. Thus, the two capacitors 343A and the direction sensor element 311A are arranged side by side in the x direction.

  Semiconductor device 1A is three-dimensionally used to determine the attitude with respect to the geomagnetism by using orientation sensor elements 311A, 312A, and 313A based on the method disclosed in, for example, JP-A-2006-47267. Can be detected (three-axis detection). The integrated circuit element 330A outputs the direction detection result of the semiconductor device 1A as a signal according to an external command from the external terminal 221A or autonomously.

  The sealing resin 400A covers the direction sensor elements 311A, 312A, 313A and the integrated circuit element 330A, and is filled in the recess 108A. In the present embodiment, the sealing resin 400A is made of the first sealing resin 410A and the second sealing resin 420A.

  The first sealing resin 410A is generally filled in the first concave portion 110A, and covers the entire orientation sensor elements 311A, 312A, and 313A. On the other hand, the first sealing resin 410A does not cover the resin forming portion pad 213A and the integrated circuit element 330A.

  The second sealing resin 420A is generally filled in the second recess 120A and covers the entire integrated circuit element 330A. On the other hand, the second sealing resin 420A exposes the external terminal 221A.

  Examples of the material of the first sealing resin 410A and the second sealing resin 420A include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The first sealing resin 410A and the second sealing resin 420A may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Next, a method of manufacturing the semiconductor device 1A will be described below with reference to FIGS. 6 to 26 show cross sections in the yz plane along the line III-III in FIG.

  First, as shown in FIG. 6, a substrate material 100A 'is prepared. Substrate material 100A 'consists of a single crystal of semiconductor material, and consists of Si single crystal in this embodiment. The thickness of the substrate material 100A 'is, for example, about 600 μm. The substrate material 100A 'is sized so that a plurality of substrates 100A of the above-described semiconductor device 1A can be obtained. That is, in the subsequent manufacturing steps, it is assumed that the plurality of semiconductor devices 1A are manufactured collectively. A method of manufacturing one semiconductor device 1A may be used, but in consideration of industrial efficiency, a method of manufacturing a plurality of semiconductor devices 1A collectively is realistic.

The substrate material 100A ′ has a main surface 101A and a back surface 102A facing in opposite directions in the z direction. In the present embodiment, a plane having a (100) crystal orientation and a (100) plane are adopted as the main surface 101A. Then, the main surface 101A is oxidized, for example, to form a mask layer 191A made of SiO ₂ . The thickness of mask layer 191A is, for example, about 0.7 to 1.0 μm.

  Then, as shown in FIG. 7, patterning by etching, for example, is performed on mask layer 191A. Thus, the openings 181A and 182A are formed in the mask layer 191A. The shape and size of the openings 181A and 182A are set in accordance with the shape and size of the first recess 110A and the inclined outer side surface 104A to be finally obtained. The opening 181A is, for example, rectangular, and the opening 182A is formed in a rectangular ring shape so as to surround the opening 181A in the z direction.

  Next, as shown in FIG. 8, the first recess 110A and the inclined groove 183A are formed. The formation of the first recess 110A and the inclined groove 183A is simultaneously performed by anisotropic etching using, for example, KOH. KOH is an example of an alkaline etching solution that can achieve good anisotropic etching for Si single crystals. By performing this anisotropic etching, a slope having a first recess 110A having a first bottom surface 111A and four first sloped inner side surfaces 112A and two slopes facing each other (slopes facing each other in the y direction in FIG. 8) A groove 183A is formed. The angle formed by the first inclined inner side surface 112A with respect to the xy plane and the angle formed by the inclined groove 183A with the xy plane are each approximately 55 °.

  Next, the mask layer 191A is further patterned to form a mask layer 192A having an opening 184A. The mask layer 192A has a larger opening area than the mask layer 191A. The opening 184A is, for example, rectangular. The shape and size of the opening 184A are set in accordance with the shape and size of the second recess 120A to be finally obtained.

  Next, as shown in FIG. 10, the recess 108A is formed. In order to form the recess 108A, for example, the aforementioned anisotropic etching using KOH is performed. By this anisotropic etching, the first recess 110A is made deeper and larger, and a second recess 120A is newly formed. The second recess 120A has two second bottom surfaces 121A sandwiching the first recess 110A and four second inclined inner side surfaces 122A surrounding the first recess 110A. The second inclined inner side surface 122A, like the first inclined inner side surface 112A, forms an angle of about 55 ° with the xy plane. By passing through two anisotropic etchings in this manner, a two-step concave portion 108A having the first concave portion 110A and the second concave portion 120A is formed. In the present embodiment, the depth of the first recess 110A is about 440 μm, and the depth of the second recess 120A is about 120 μm.

  Next, as shown in FIG. 11, the mask layer 192A is removed. This removal is performed by etching using, for example, HF.

Next, as shown in FIG. 12, an insulating layer 107A made of, eg, SiO ₂ is formed. The formation of the insulating layer 107A is performed by oxidizing the entire portion of the substrate material 100A 'opposite to the back surface 102A. Thereby, insulating layer 107A having a thickness of, for example, about 0.7 to 1.0 μm is obtained.

  Next, as shown in FIG. 13, a resin layer 193A is formed. The resin layer 193A is formed, for example, by spray application of a photosensitive epoxy resin. Next, as shown in FIG. 14, the resin layer 193A is patterned. This patterning is performed by removing a desired portion by performing exposure and development using, for example, a photolithography method on the resin layer 193A. By this patterning, resin forming portions 130A and 140A are formed at predetermined positions on main surface 101A and second bottom surface 121A.

  Next, as shown in FIG. 15, a barrier / seed layer 201A is formed. Formation of barrier / seed layer 201A is performed, for example, by sputtering. Specifically, a layer made of Ti is formed on the insulating layer 107A by sputtering. The layer made of Ti functions as a barrier layer. Then, a layer of Cu is formed on the barrier layer by sputtering. The layer made of Cu functions as a seed layer. The barrier / seed layer 201A is obtained by such sputtering.

  Next, as shown in FIG. 16, a mask layer 291A is formed. The formation of the mask layer 291A is performed by, for example, spray coating of a photosensitive resist resin.

  Next, as shown in FIG. 17, the mask layer 291A is patterned. This patterning is performed by removing a desired portion by performing exposure and development using, for example, a photolithography method on the mask layer 291A. The shape of the mask layer 291A obtained by this patterning corresponds to the shapes of the wiring layer 200A and the metal film 500A described above. The exposure may be performed a plurality of times while changing the focal depth of the exposure in response to the recess 108A having a certain depth.

  Next, as shown in FIG. 18, a plating layer 202A is formed. The plating layer 202A is formed, for example, by electrolytic plating using the above-mentioned seed layer of the barrier / seed layer 201A. As a result, a plating layer 202A made of, for example, Cu is obtained. The thickness of the plating layer 202A is, for example, about 5 μm. The plating layer 202A has the shape of the above-described wiring layer 200A and metal film 500A.

  Next, as shown in FIG. 19, the mask layer 291A is removed. Next, as shown in FIG. 20, the portion of the barrier / seed layer 201A exposed from the plating layer 202A is removed. The removal of the barrier / seed layer 201A is performed, for example, by wet etching. As a result, a wiring layer 200A composed of the barrier / seed layer 201A and the plating layer 202A patterned together is obtained. Further, in the present embodiment, the metal film 500A including the barrier / seed layer 201A and the plating layer 202A can be obtained simultaneously with the formation of the wiring layer 200A.

  Next, as shown in FIG. 21, the orientation sensor elements 311A, 312A, and 313A are mounted. In the orientation sensor elements 311A, 312A, and 313A, solder balls to be the solder 351A are formed. Also, flux is applied to these solder balls. The orientation sensor element 311A is mounted on the first bottom surface 111A and the orientation sensor elements 312A and 313A are mounted on the first inclined inner side surface 112A by using the adhesiveness of the flux. Then, the solder balls are melted by a reflow furnace and then cured to complete the mounting of the orientation sensor elements 311A, 312A, and 313A. In addition, two capacitors 343A are mounted on the first inclined inner side surface 112A different from the direction sensor elements 312A and 313A.

  Next, as shown in FIG. 22, a first sealing resin 410A is formed. The formation of the first sealing resin 410A is performed, for example, by filling the first concave portion 110A mainly with a resin material which is excellent in permeability and is cured by exposure to light and curing the resin material. At this time, the direction sensor elements 311A, 312A, 313A are entirely covered with the resin material. On the other hand, the resin forming portion pad 213A of the second bottom surface 121A is surely exposed. In addition, if the material for forming 1st sealing resin 410A is illustrated, an epoxy resin, a phenol resin, a polyimide resin, polybenzoxazole (PBO) resin, a silicone resin will be mentioned, for example. The first sealing resin 410A may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Next, as shown in FIG. 23, the integrated circuit element 330A is mounted. Solder balls to be solder 351A are formed on the integrated circuit element 330A. Also, flux is applied to these solder balls. The integrated circuit element 330A is placed on the resin forming portion 140A on the second bottom surface 121A by utilizing the adhesiveness of the flux. Then, the solder balls are melted by a reflow furnace and then hardened to complete the mounting of the integrated circuit element 330A.

  Next, as shown in FIG. 24, a second sealing resin 420A is formed. The formation of the second sealing resin 420A is performed, for example, by filling the second concave portion 120A mainly with a resin material which is excellent in permeability and is cured by exposure to light and curing the resin material. At this time, the entire integrated circuit element 330A is covered with this resin material. On the other hand, a part of the plating layer 202A on the main surface 101A is reliably exposed. Further, the second sealing resin 420A is formed so as not to overlap in a cutting region described later. In addition, if the material for forming the 2nd sealing resin 420A is illustrated, an epoxy resin, a phenol resin, a polyimide resin, polybenzoxazole (PBO) resin, a silicone resin will be mentioned, for example. The second sealing resin 420A may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Then, as shown in FIG. 25, a bump such as bulging in the z direction is formed on the external terminal 221A by electroless plating of a metal such as Ni, Pd, Au or the like.

  Next, as shown in FIGS. 26 and 27, the substrate material 100A 'is cut by, for example, a dicer Dc. The cutting by the dicer Dc cuts along the cutting line CL included in the inclined groove 183A in the z-direction view. At this time, only the substrate material 100A 'is cut by the dicer Dc, and for example, the second sealing resin 420A is not cut. Through this cutting, the semiconductor device 1A shown in FIGS. 1 to 4 is obtained. And the exposed surface which arises by this cutting | disconnection becomes the standing outer side surface 105A. The standing outer side surface 105A produced by the cutting has a relatively rough surface. On the other hand, the inclined outer side surface 104A derived from the inclined groove 183A formed by anisotropic etching has a relatively flat surface and is smoother than the rising outer side surface 105A.

  Next, the operation of the semiconductor device 1A and the method of manufacturing the semiconductor device 1A will be described.

  According to this embodiment, the three orientation sensor elements 311A, 312A, and 313A are accommodated in the first recess 110A of the recess 108A of the substrate 100A made of a semiconductor material. For this reason, it is not necessary to provide a lead for supporting the three direction sensor elements 311A, 312A, 313A. The substrate 100A made of a semiconductor material is less expensive to reshape than the case of molding the leads. Therefore, the cost of semiconductor device 1A can be reduced. In particular, when the semiconductor device 1A is produced in a small amount, the cost reduction effect is remarkable.

  When manufacturing the semiconductor device 1A, when the substrate material 100A 'is cut along the cutting line CL included in the inclined groove 183A formed on the main surface 101A, the outer surface 103 of the chip-shaped substrate 100A cut and separated is It includes an inclined outer side surface 104A which is a part of the area which was the inclined groove 183A. In the manufacture of the semiconductor device 1A, the cutting operation of the substrate material 100A 'proceeds while being guided by the inclined groove 183A. According to such a configuration, it is possible to suppress the occurrence of defects such as wafer breakage or chipping in the substrate material 100A 'or the substrate 100A when the substrate material 100A' is cut. This is suitable for efficiently manufacturing the semiconductor device 1A.

  In the manufacture of the semiconductor device 1A, the formation of the inclined groove 183A and the formation of the recess 108A (the first recess 110A) are simultaneously performed collectively by anisotropic etching. Then, the substrate material 100A 'is cut along the cutting line CL when the substrate material 100A' is cut. Since the cutting line CL is included in the inclined groove 183A, the cutting depth of the substrate material 100A 'is smaller than the thickness of the substrate material 100A'. According to such a configuration, the cutting operation of the substrate material 100A 'can be performed efficiently.

  In addition, the standing outer side surface 105A which comprises the outer side surface 103A becomes a trace which cut | disconnected board | substrate material 100A 'in the site | part of inclination groove 183A. That is, the inclined outer side surface 104A formed by anisotropic etching is smoother than the upright outer side surface 105A formed by cutting the substrate material 100A '.

  Since the substrate 100A is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112A and the second inclined inner side surface 122A are at predetermined known angles with respect to the first bottom surface 111A and the second bottom surface 121A. It can be finished as an inclined surface. In particular, the substrate 100A is made of Si, and by adopting the (100) plane as the main surface 101A, the four first inclined inner side surfaces 112A and the four second inclined inner side surfaces 122A with respect to the first bottom surface 111A and the second bottom surface 121A. Can be set to about 55 °. Thereby, the semiconductor device 1A can be formed into a well-balanced shape.

  Using the first recess 110A as a dedicated space for accommodating the orientation sensor elements 311A, 312A, 313A and the two capacitors 343A by forming the recess 108A in a two-step shape by the first recess 110A and the second recess 120A it can.

  Resin forming portions 130A and 140A are provided on the main surface 101A and the recess 108A. According to the configuration including the resin forming portions 130A and 140A, steps can be provided at appropriate positions of the main surface 101A and the concave portion 108A, and formation of the external terminal 221A and mounting of the integrated circuit element 330A can be appropriately performed. For example, as can be understood with reference to FIG. 3 and FIG. 4, if the integrated circuit element 330A is mounted on the second bottom surface 121A without the resin forming portion 140A, the integrated circuit element 330A may interfere with the capacitor 343A. There is. On the other hand, by forming the resin forming portion 140A on the second bottom surface 121A, the main surface of the integrated circuit element 330A avoiding interference with the capacitor 343A without changing the shape or position of the second bottom surface 121A itself. It can be mounted at a position displaced to the 101A side. Further, as shown in FIG. 3, the integrated circuit element 330A protrudes above the main surface 101A. On the other hand, the external terminals 221A can be made to project in the z direction so as to be suitable for surface mounting of the external terminals 221A by forming the external terminals 221A on the main surface 101A through the resin forming portion 130A.

  Since the side surfaces 132A and 142A of the resin forming portions 130A and 140A are inclined, the connection path of the wiring layer 200A formed on the side surfaces 132A and 142A should be connected to the external terminal 221A and the resin forming portion pad 213A. Can.

  A metal film 500A is formed on the inclined outer side surface 104A, and when the semiconductor device 1A is mounted, the metal film 500A is connected to ground via the connection path 510A and the external terminal 221A. The metal film 500A having such a configuration functions as an electromagnetic shield for preventing the influence of electromagnetic waves from the outside on each element accommodated in the recess 108A. In addition, the metal film 500A surrounds the main surface 101A as a whole in the z-direction view (view in the normal direction of the main surface 101A). According to such an arrangement of the metal film 500A, it can be expected to further enhance the effect as an electromagnetic shield.

  The formation range of the metal film 500A may be changed as appropriate. When the metal film 500A is formed in a wider area than the mode shown in FIG. 2, for example, the inclined outer side surface 104A is formed wider so that the area of the inclined outer side surface 104A is larger than that of this embodiment. The metal film 500A may be formed in a wider region with respect to the side surface 104A.

  The formation of the metal film 500A is performed simultaneously with the formation of the wiring layer 200. Therefore, the metal film 500A can be formed efficiently. Further, the inclined outer side surface 104A on which the metal film 500A is formed is a smooth surface formed in the same manner as the recess 108A by anisotropic etching using, for example, KOH. Therefore, the metal film 500A can be appropriately formed on the smooth inclined outer side surface 104A.

  The integrated circuit element 330A is supported by the second bottom surface 121A and overlaps a part of the first recess 110A in plan view, whereby the orientation sensor element 311A, 312A, 313A and the two capacitors 343A and the integrated circuit are integrated in the z direction. The elements 330A can be arranged three-dimensionally. As a result, it is possible to achieve both miniaturization and high functionality of the semiconductor device 1A.

  Since the wiring layer 200A includes the connection paths 231A, 234A, 235A, 236A, desired ones of the external terminal 221A, the resin forming portion pad 213A, the first bottom surface pad 211A, and the first inclined inner side surface pad 212A are appropriately selected. It can be conducted. Since the connection path 231A passes through the second inclined inner side surface 122A, it is possible to properly conduct the external terminal 221A and the resin forming portion pad 213A formed on the three-dimensionally shaped substrate 100A. There is little risk of disconnection. Further, since the connection paths 234A, 235A, 236A pass through the first inclined inner side surface 112A, there is little possibility of disconnection or the like.

  The three orientation sensor elements 311A, 312A, 313A and the two capacitors 343A are covered with the sealing resin 400A, so that these orientation sensor elements 311A, 312A, 313A and the two capacitors 343A can be protected appropriately. it can. By forming the sealing resin 400A with the first sealing resin 410A and the second sealing resin 420A, the two-step concave portion 108A consisting of the first concave portion 110A and the second concave portion 120A is appropriately filled up. be able to.

  Since the first sealing resin 410A is mainly filled in the first recess 110A, the three azimuth sensor elements 311A, 312A, 313A and the two capacitors 343A are mounted before the integrated circuit element 330A is mounted. It can be covered properly. Also, by covering the integrated circuit element 330A with the second sealing resin 420A, an unintended gap is not generated between the integrated circuit element 330A and the three direction sensor elements 311A, 312A, 313A and the two capacitors 343A. The sealing resin 400A can be formed. Since the second sealing resin 420A exposes the external terminal 221A, the semiconductor device 1A can be easily surface-mounted, and, for example, the circuit board on which the semiconductor device 1A is mounted and the integrated circuit element 330A or three azimuths Unreasonable conduction of the sensor elements 311A, 312A, 313A and the two capacitors 343A can be appropriately avoided.

  In the method of manufacturing semiconductor device 1A, as a method of cutting substrate material 100A ', in addition to the cutting using dicer Dc shown in FIG. 26, for example, a method of deep etching such as plasma dicing or BOSCH method. For example, various methods can be adopted.

  When the substrate material 100A 'is cut using a deep etching method, for example, the first step of digging the substrate material 100A' to a predetermined depth and the second step of polishing the back surface side of the substrate material Material 100A 'may be cut. In this case, in the first step, as shown in FIG. 28, the vertical groove 185 is formed by digging from the formation position of the inclined groove 183A to the predetermined depth in the thickness direction by deep etching. Next, the main surface 101A side of the substrate material 100A 'is supported by a support such as a tape material (not shown). Next, as shown in FIG. 29, the substrate material 100A 'is polished from the back surface 102A side to reach the formation position of the vertical groove 185A. Thereby, the substrate material 100A 'is separated and cut into the plurality of substrates 100A, and the formation site of the vertical groove 185 becomes the rising outer side surface 105A.

  30 and 31 show a semiconductor device according to the second embodiment of the present invention. The semiconductor device 1B of the present embodiment includes a substrate 100B, a resin forming unit 150B, a wiring layer 200B, an integrated circuit element 330B, a wireless communication element 350B, a sealing resin 400B, and a metal film 500B. In FIG. 30, for convenience of understanding, the sealing resin 400B is omitted. Further, in FIG. 30 and FIG. 31, the communication route is omitted.

  The substrate 100B is a base of the semiconductor device 1B, and includes a base 106B and an insulating layer 107B. The substrate 100B has a main surface 101B, a back surface 102B, four outer surfaces 103B, and a recess 108B. The thickness of the substrate 100B is, for example, about 600 μm. In the present embodiment, the main surface 101B and the back surface 102B face in opposite directions in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1B. Also, the x direction and the y direction are both perpendicular to the z direction.

The base 106B is made of a single crystal of a semiconductor material, and in the present embodiment, is made of an Si single crystal. In addition, the insulating layer 107B is made of SiO ₂ in the present embodiment. In addition, the material of the base material 106B is not limited to Si, and it may be any material that can form the recess 108B satisfying the intention described later. The insulating layer 107B covers a portion of the base 106B that faces from the opposite side to the back surface 102B. The thickness of insulating layer 107B is, for example, about 0.1 to 1.0 μm.

  In the present embodiment, the (100) plane of the base 106B is adopted as the main surface 101B. The recess 108B is recessed from the main surface 101B toward the back surface 102B. In the present embodiment, the recess 108B is composed of the first recess 110B. The first recess 110B has a first bottom surface 111B and four first inclined inner side surfaces 112B. The shape of the first recess 110B depends on the fact that the (100) plane is adopted as the main surface 101B.

  By forming the recess 108B, the main surface 101B has a rectangular annular shape in plan view. The first recess 110B is rectangular in plan view. The depth of the first recess 110B is, for example, about 440 μm. The first bottom surface 111B is rectangular in plan view. The four first inclined inner side surfaces 112B surround the first bottom surface 111B in a plan view, and have a substantially trapezoidal shape having a portion in contact with the first bottom surface 111B as an upper bottom. Each first inclined inner side surface 112B is inclined with respect to the first bottom surface 111B. In the present embodiment, the inclination angle of the first inclined inner side surface 112B with respect to the xy plane is about 55 °. The point that the first inclined inner side surface 112B has a substantially trapezoidal shape and the inclination angle is 55 ° depends on the adoption of the (100) plane as the main surface 101B.

  The resin forming portion 150B is for providing a predetermined level difference on the substrate 100B, and is formed on the substrate 100B (insulating layer 107B). In the present embodiment, the resin forming portion 150B is formed on the bottom surface (first bottom surface 111B) of the recess 108B (first recess 110B), and is a portion on which the wireless communication element 350B is mounted. In the present embodiment, the resin forming portion 150B is formed at two portions of the first bottom surface 111B which are separated in the y direction. The height of resin forming portion 150B is, for example, about 150 μm. The resin forming portion 150B has a flat top surface and a side surface 152B inclined with respect to the top surface. As a material of resin formation part 150B, an epoxy resin, a phenol resin, a polyimide resin, polybenzoxazole (PBO) resin, a silicone resin is mentioned, for example. The resin forming portion 150B may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  The wiring layer 200B is for mounting the integrated circuit element 330B and the wireless communication element 350B, and for forming a current path for input / output to / from these. The wiring layer 200B is mainly formed on the insulating layer 107B, and in the present embodiment, the barrier / seed layer 201B and the plating layer 202B are stacked.

  The barrier / seed layer 201B is a so-called base layer for forming a desired plating layer 202B, and is formed on the insulating layer 107B. The barrier / seed layer 201B is formed of, for example, a Ti layer as a barrier layer formed on the insulating layer 107B and a Cu layer as a seed layer stacked on the barrier layer. Barrier and seed layer 201B is formed, for example, by sputtering. In the present embodiment, the barrier / seed layer 201B is formed on predetermined portions of the insulating layer 107B and the resin forming portion 150B.

  The plating layer 202B is made of, for example, Cu and is formed by electrolytic plating using the barrier / seed layer 201B. The thickness of the plating layer 202B is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200B has a first bottom surface pad 211B, a resin forming portion pad 214B, an external terminal 221B, and a connection path (not shown) for electrically connecting them.

  The first bottom surface pad 211B is formed on the first bottom surface 111B of the first recess 110B. In the present embodiment, a plurality of first bottom surface pads 211B are formed, and these first bottom surface pads 211B are used to mount the integrated circuit element 330B.

  The resin forming portion pad 214B is formed on the resin forming portion 150B. In the present embodiment, a plurality of resin formation portion pads 214B are formed in each of the resin formation portions 150B which are disposed apart from each other on the first bottom surface 111B. The resin forming unit pads 214B are used to mount the wireless communication element 350B. Further, since the side surface 152B of the resin forming portion 150B is inclined, the connection path (not shown) of the wiring layer 200B formed on the side surface 152B can be connected to the resin forming portion pad 214B.

  The external terminal 221B is formed on the main surface 101B, and is used to, for example, surface mount the semiconductor device 1B on a circuit board of an electronic device (not shown). In the present embodiment, a plurality of external terminals 221B are formed at two portions of the main surface 101B which are separated in the y direction across the recess 108B. The external terminal 221B has a structure in which a bump obtained by electroless plating of a metal such as Ni, Pd, Au or the like is formed on the barrier / seed layer 201B and the plating layer 202B described above. Thus, the external terminal 221B has a shape that bulges in the z direction. In the present embodiment, at least one external terminal 221B is a so-called ground terminal.

  As shown in FIG. 30, the four outer side surfaces 103B of the substrate 100B surround the main surface in the z direction, and form a rectangular ring shape. More specifically, each outer side surface 103B is configured to include an inclined outer side surface 104B and a rising outer side surface 105B. The inclined outer side surface 104B is interposed between the main surface 101B and the rising outer side surface 105B, and is inclined with respect to both the main surface 101B and the rising outer side surface 105B. In the present embodiment, the inclined outer side surface 104B is connected to the main surface 101B, and the rising outer side surface 105B is connected to the back surface 102B. In the present embodiment, the inclination angle of the inclined outer side surface 104B with respect to the xy plane is about 55 °. In addition, the point whose said inclination angle is 55 degrees is dependent on having employ | adopted the (100) plane as the main surface 101B.

  Here, the inclination angle of the inclined outer side surface 104B with respect to the xy plane (main surface 101B) is the same as the inclination angle of the first inclined inner side surface 112B with respect to the main surface 101B. The inclined outer side surface 104B and the first inclined inner side surface 112B are intended to have the same angle by being formed by collective etching. The difference which can be inevitably caused by the variation of the etching conditions etc. is included in the same range in the present invention.

  The upright outer side surface 105B is substantially perpendicular to the major surface 101B and substantially parallel to the zx or yz plane. In the present embodiment, the inclined outer side surface 104B is smoother than the rising outer side surface 105B. The fact that the inclined outer side surface 104B is smoother than the rising outer side surface 105B depends on the method of manufacturing the semiconductor device 1B. Since the rising outer side surface 105B is an exposed surface produced by cutting the substrate material, the inclined outer side surface 104B formed by etching is smoother than the rising outer side surface 105B.

  The wireless communication element 350B is an element for near field wireless data communication conforming to, for example, the Bluetooth (registered trademark) standard, and is supported by the first bottom surface 111B via the resin forming portion 150B. The wireless communication element 350B is mounted via the solder 351B using the plurality of resin forming unit pads 214B. The wireless communication element 350 </ b> B is mounted by using the plurality of resin forming portion pads 214 </ b> B spaced apart in the y direction, so that two sides are supported. Further, the wireless communication element 350B overlaps with all the integrated circuit elements 330B in a plan view, and is accommodated in the first recess 110B (the recess 108B).

  The integrated circuit element 330B is supported by the first bottom surface 111B, and is mounted via the solder 351B using the plurality of first bottom surface pads 211B. The integrated circuit element 330B is for controlling the wireless communication element 350B. In the present embodiment, the integrated circuit element 330B is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and the thickness thereof is about 80 to 100 μm. When manufacturing the semiconductor device 1B, the mounting of the integrated circuit element 330B on the first bottom surface 111B is performed later than the formation of the resin forming portion 150B.

  The sealing resin 400B covers the integrated circuit element 330B and the wireless communication element 350B, and is filled in the recess 108B (first recess 110B). In the present embodiment, the sealing resin 400B is composed of the first sealing resin 410B and the second sealing resin 420B.

  The first sealing resin 410B covers the entire integrated circuit element 330B. On the other hand, the first sealing resin 410B does not cover the resin forming portion pad 214B and the wireless communication element 350B.

  The second sealing resin 420B covers the entire wireless communication element 350B. On the other hand, the second sealing resin 420B exposes the external terminal 221B.

  Examples of the material of the first sealing resin 410B and the second sealing resin 420B include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin. The first sealing resin 410B and the second sealing resin 420B may be either light-transmitting resin or non-light-transmitting resin, but in the present embodiment, non-light-transmitting resin is preferable.

  Next, the operation of the semiconductor device 1B will be described.

  According to the present embodiment, the integrated circuit element 330B and the wireless communication element 350B are arranged and accommodated in the recess 108B (the first recess 110B) of the substrate 100B made of a semiconductor material. Therefore, there is no need to provide a lead for supporting the integrated circuit element 330B and the wireless communication element 350B. As compared with the case of molding the leads, the substrate 100B made of a semiconductor material is less expensive to reshape. Therefore, the cost of the semiconductor device 1B can be reduced. In particular, when the semiconductor device 1B is produced in a small amount, the cost reduction effect is remarkable.

  Since the substrate 100B is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112B can be finished as a surface accurately inclined at a known predetermined angle with respect to the first bottom surface 111B. In particular, the angle of the four first inclined inner side surfaces 112B with respect to the first bottom surface 111B can be set to about 55 ° by employing the substrate 100B made of Si and adopting the (100) plane as the main surface 101B. . Thereby, it is possible to make the semiconductor device 1B a well-balanced shape.

  A metal film 500B is formed on the inclined outer side surface 104B, and the metal film 500B is grounded through the connection path 510B and the external terminal 221B when the semiconductor device 1B is mounted. The metal film 500B having such a configuration functions as an electromagnetic shield that prevents the elements housed in the recess 108B from the influence of the electromagnetic wave from the outside. In addition, the metal film 500B surrounds the main surface 101B as a whole in the z-direction view (view in the normal direction of the main surface 101B). According to such an arrangement of the metal film 500B, it can be expected to further enhance the effect as an electromagnetic shield. In addition, since the semiconductor device 1B of the present embodiment includes the wireless communication element 350B that is easily affected by an electromagnetic wave from the outside, the electromagnetic shielding effect by the metal film 500B can be more appropriately obtained.

  By forming the resin forming portion 150B at an appropriate position in the concave portion 108B (the first concave portion 110B), a space for housing the integrated circuit element 330B and the wireless communication element 350B can be formed in a two-step shape. By mounting the integrated circuit element 330B on the first bottom surface 111B and mounting the wireless communication element 350B on the resin forming portion 150B, the integrated circuit element 330B and the wireless communication element 350B are three-dimensionally disposed at different positions in the z direction. be able to. As a result, it is possible to achieve both miniaturization and high functionality of the semiconductor device 1B.

  By forming the resin forming portion pad 214B in the resin forming portion 150B, the wireless communication element 350B can be appropriately mounted on the resin forming portion 150B.

  FIG. 32 shows a modification of the above-described semiconductor device 1B. The semiconductor device 1B 'shown in FIG. 32 includes a substrate 100B, a resin forming portion 150B, a wiring layer 200B, an integrated circuit element 330B, an inductor 360B, a sealing resin 400B, a metal film 500B and a metal film 520B. Compared to the above-described semiconductor device 1B, the semiconductor device 1B 'illustrated in FIG. 32 includes an inductor 360B instead of the wireless communication element 350B, and additionally includes a metal film 520B.

  The inductor 360B is mounted on the resin forming portion 150B and covers at least a part of the integrated circuit element 330B.

  The metal film 520B is located between the inductor 360B and the integrated circuit element 330B and covers the entire integrated circuit element 330B. The metal film 520B is formed, for example, by forming a metal thin film of a predetermined shape on the first sealing resin 410B. For example, the first sealing resin 410B is formed to have the same height position as the resin forming portion 150B, and a pattern of metal such as Cu is formed on the first sealing resin 410B by a method such as mask deposition. The metal film 520B is formed by the formation. The metal film 520B is conductively connected to a connection path (not shown) formed in the recess 108B (the first inclined inner side surface 112B) and the resin forming portion 150B, and is also conductive to the ground terminal external terminal 221A. The integrated circuit element 330B may malfunction if it is affected by the magnetic field of the inductor 360B, and the metal film 520B is disposed between the inductor 360B and the integrated circuit element 330B to prevent the malfunction of the integrated circuit element 330B. can do.

  33 and 34 show a semiconductor device according to the third embodiment of the present invention. The semiconductor device 1C of the present embodiment includes a substrate 100C, a wiring layer 200C, a first element 370C, a second element 380C, and a sealing resin 400C. In FIG. 33, for convenience of understanding, the sealing resin 400C is omitted. Further, in FIGS. 33 and 34, the communication route is omitted.

  The substrate 100C is a base of the semiconductor device 1C, and includes a base 106C and an insulating layer 107C. The substrate 100C has a main surface 101C, a back surface 102C, four outer surfaces 103C, and a recess 108C. The thickness of the substrate 100C is, for example, about 600 μm. In the present embodiment, the main surface 101C and the back surface 102C face each other in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1C. Also, the x direction and the y direction are both perpendicular to the z direction.

The base 106C is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. In addition, the insulating layer 107C is made of SiO ₂ in the present embodiment. In addition, the material of the base 106C is not limited to Si, as long as it can form the recess 108C satisfying the intention described later. The insulating layer 107C covers a portion of the base 103C facing from the opposite side to the back surface 102C. The thickness of insulating layer 107C is, for example, about 0.1 to 1.0 μm.

  In the present embodiment, the (100) plane of the base 106C is employed as the main surface 101C. The recess 108C is recessed from the main surface 101C toward the back surface 102C. In the present embodiment, the recess 108C is composed of a first recess 110C. The first recess 110C has a first bottom surface 111C and four first inclined inner side surfaces 112C. The shape of the first recess 110C depends on the fact that the (100) plane is adopted as the main surface 101C.

  By forming the recess 108C, the main surface 101C has a rectangular annular shape in plan view. The first recess 110C is rectangular in plan view. The depth of the first recess 110C is, for example, about 440 μm. The first bottom surface 111C is rectangular in plan view. The four first inclined inner side surfaces 112C surround the first bottom surface 111C in a plan view, and have a substantially trapezoidal shape whose upper bottom corresponds to a portion in contact with the first bottom surface 111C. Each first inclined inner side surface 112C is inclined with respect to the first bottom surface 111C. In the present embodiment, the inclination angle of the first inclined inner side surface 112C with respect to the xy plane is about 55 °. The point that the first inclined inner side surface 112C has a substantially trapezoidal shape and the above-mentioned inclination angle is 55 ° depends on adopting the (100) plane as the main surface 101C.

  The wiring layer 200C is for mounting a first element 370C and a second element 380C, and for forming a current path for input to and output from the first element 370C and the second element 380C. The wiring layer 200C is formed on the insulating layer 107C, and in this embodiment, has a structure in which the barrier / seed layer 201C and the plating layer 202C are stacked.

  The barrier / seed layer 201C is a so-called base layer for forming a desired plating layer 202C, and is formed on the insulating layer 107C. The barrier / seed layer 201C is formed of, for example, a Ti layer as a barrier layer formed on the insulating layer 107C and a Cu layer as a seed layer stacked on the barrier layer. Barrier and seed layer 201C is formed, for example, by sputtering. In the present embodiment, the barrier / seed layer 201C is formed at a predetermined portion on the insulating layer 107C.

  The plating layer 202C is made of, for example, Cu and is formed by electrolytic plating using the barrier / seed layer 201C. The thickness of the plating layer 202C is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200C has a first bottom surface pad 211C, a first inclined inner side surface pad 212C, an external terminal 221C, and a connection path (not shown) for electrically connecting them.

  The first bottom surface pad 211C is formed on the first bottom surface 111C of the first recess 110C. In the present embodiment, a plurality of first bottom surface pads 211C are formed, and these first bottom surface pads 211C are used to mount the first element 370C.

  The first inclined inner side surface pad 212C is formed on the first inclined inner side surface 112C. In the present embodiment, a plurality of first sloped inner side surface pads 212C are formed on the two first sloped inner side surfaces 112C which are disposed apart in the y direction with the first bottom surface 111C interposed therebetween. The plurality of first inclined inner side surface pads 212C are used to mount the second element 380C.

  The external terminal 221C is formed on the main surface 101C, and is used to, for example, surface-mount the semiconductor device 1C on a circuit board of an electronic device (not shown). In the present embodiment, a plurality of external terminals 221C are formed at two portions of the main surface 101C which are separated in the y direction with the recess 108C interposed therebetween. The external terminal 221C has a structure in which a bump obtained by electroless plating a metal such as Ni, Pd, Au or the like on the barrier / seed layer 201C and the plating layer 202C described above is formed. Thus, the external terminal 221C has a shape that bulges in the z direction. In the present embodiment, at least one external terminal 221C is a so-called ground terminal.

  As shown in FIG. 33, the four outer side surfaces 103C of the substrate 100C surround the main surface in the z-direction view, and form a rectangular ring shape. More specifically, each outer side surface 103C is configured to include an inclined outer side surface 104C and a rising outer side surface 105C. The inclined outer side surface 104C is interposed between the main surface 101C and the standing outer side surface 105C, and is inclined with respect to both the main surface 101C and the standing outer side surface 105C. In the present embodiment, the inclined outer side surface 104C is connected to the main surface 101C, and the rising outer side surface 105C is connected to the back surface 102C. In the present embodiment, the inclination angle of the inclined outer side surface 104C with respect to the xy plane is about 55 °. In addition, the point whose said inclination angle is 55 degrees is dependent on having employ | adopted the (100) surface as 101C of main surfaces.

  Here, the inclination angle of the inclined outer side surface 104C with respect to the xy plane (main surface 101C) is the same as the inclination angle of the first inclined inner side surface 112C with respect to the main surface 101C. The inclined outer side surface 104C and the first inclined inner side surface 112C are intended to have the same angle by being formed by collective etching. The difference which can be inevitably caused by the variation of the etching conditions etc. is included in the same range in the present invention.

  The upright outer side surface 105C is substantially perpendicular to the major surface 101C and substantially parallel to the zx plane or the yz plane. In the present embodiment, the inclined outer side surface 104C is smoother than the upright outer side surface 105C. The fact that the inclined outer side surface 104C is smoother than the rising outer side surface 105B depends on the method of manufacturing the semiconductor device 1C. Since the rising outer side surface 105C is an exposed surface generated by cutting the substrate material, the inclined outer side surface 104C formed by etching is smoother than the rising outer side surface 105C.

  The first element 370C is supported by the first bottom surface 111C, and is mounted via the solder 351C using the first bottom surface pad 212C.

  The second element 380C is supported by the first inclined inner side surface 112C, and is mounted via the solder 351C using the plurality of first inclined inner side surface pads 212C. In the present embodiment, the second element 380C is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and its thickness is about 80 to 100 μm. Further, in the present embodiment, the second element 380C has an opposing main surface 381C, an opening side main surface 382C, and two inclined side surfaces 383C. The opposing major surface 381C opposes the first element 370C. The opening-side main surface 382C is located on the opposite side to the opposing main surface 381C in the z direction. The area of the opening-side main surface 382C is larger than that of the facing main surface 381C. The two inclined side surfaces 383C are two side surfaces separated from each other in the y direction among the four side surfaces connecting the opposite main surface 381C and the opening side main surface 382C. The inclined side surface 383C is inclined with respect to the opposing main surface 381C, and in the present embodiment, the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is about 55 °.

  In the present embodiment, the second element 380C is made of a single crystal of a semiconductor material, and for example, the single crystal is Si. Further, the (100) plane of the second element 380C is adopted as the opposing main surface 381C. The point that the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is 55 ° depends on adopting the (100) plane as the opposing main surface 381C. Here, the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is the same as the inclination angle of the first inclined inner side surface 112C with respect to the above-described main surface 101C. The inclined side surface 383C and the first inclined inner side surface 112C are intended to have the same angle by being formed by the same anisotropic etching. The difference which can be inevitably caused by the variation of the etching conditions etc. is included in the same range in the present invention.

  In the second element 380C, a wiring pattern 384C made of a conductive metal thin film is formed in a predetermined region extending from the inclined side surface 383C to the opposing main surface 381C. With such a configuration, when the second element 380C is mounted, the first inclined inner side surface 112C and the inclined side surface 383C of the second element 380C face each other so as to be substantially parallel to each other. Therefore, the second element 380C is configured such that the two first inclined inner side surfaces 112C spaced apart in the y direction in the first recess 110B support the two inclined side surfaces 383C separated by sandwiching the opposing main surface 381C. There is. The second element 380C overlaps all of the first element 370C in plan view, and is accommodated in the first recess 110C (the recess 108C).

  The sealing resin 400C covers the first element 370C and the second element 380C, and is filled in the recess 108C (the first recess 110C). In the present embodiment, the sealing resin 400C is composed of a first sealing resin 410C and a second sealing resin 420C.

  The first sealing resin 410C covers the entire first element 370C. On the other hand, the first sealing resin 410C does not cover the first inclined inner side surface pad 212C and the second element 380C.

  The second sealing resin 420C covers all of the second element 380C. On the other hand, the second sealing resin 420C exposes the external terminal 221C.

  Examples of the material of the first sealing resin 410C and the second sealing resin 420C include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The first sealing resin 410C and the second sealing resin 420C may be either translucent resin or non-translucent resin, but in this embodiment non-translucent resin is preferable.

  Next, the operation of the semiconductor device 1C will be described.

  According to the present embodiment, the first element 370C and the second element 380C are arranged and accommodated in the recess 108C (the first recess 110C) of the substrate 100C made of a semiconductor material. For this reason, it is not necessary to provide a lead for supporting the first element 370C and the second element 380C. The substrate 100C made of a semiconductor material is less expensive to reshape than the case of molding the leads. Therefore, the cost of the semiconductor device 1C can be reduced. In particular, when the semiconductor device 1C is produced in a small amount, the cost reduction effect is remarkable.

  Since the substrate 100C is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112C can be finished as a surface which is accurately inclined by a known predetermined angle with respect to the first bottom surface 111C. In particular, the angle of the four first inclined inner side surfaces 112C with respect to the first bottom surface 111C can be set to about 55 ° by adopting the substrate 100C made of Si and adopting the (100) plane as the main surface 101C. . As a result, the semiconductor device 1C can have a well-balanced shape.

  The second element 380C has an inclined side 383C. By mounting the second element 380C on the first inclined inner side surface 112C using the inclined side surface 383C, the second element 380C is between the bottom surface 111C and the single first recessed portion 110C (recessed portion 108C). Can be spaced apart. Then, the first element 370C can be mounted on the first bottom surface 111C so as to be accommodated at this interval. Therefore, the first element 370C and the second element 380C can be three-dimensionally arranged at different positions in the z direction, without forming the space for housing the first element 370C and the second element 380C in two steps. . As described above, the configuration of the present embodiment in which no step is provided in the accommodation space of the first element 370C and the second element 380C can simplify the process for forming the accommodation space, so the efficiency of the semiconductor device 1C can be improved. Suitable for manufacturing well.

  The formation of the inclined side surface 381C of the second element 380C can be performed simultaneously and simultaneously with the formation of the recess 108C by anisotropic etching. Thus, the inclination angle of the inclined side surface 383C with respect to the opposing main surface 381C is the same as the inclination angle of the first inclined inner side surface 112C with respect to the main surface 101C of the substrate 100C. Therefore, at the time of mounting on the first inclined inner side surface 112C using the inclined side surface 383C, the posture of the second element 380C can be in a well-balanced state.

  When manufacturing the semiconductor device 1C, when the substrate material is cut along the cutting lines included in the inclined grooves formed in the main surface 101C, the outer surface 103C of the chip-shaped substrate 100C cut and separated is the inclined grooves. And an inclined outer surface 104C that is part of the In the manufacture of the semiconductor device 1C, the cutting operation of the substrate material proceeds while being guided by the inclined groove. According to such a configuration, it is possible to suppress the occurrence of defects such as wafer breakage or chipping in the substrate material or the substrate 100C when the substrate material is cut. This is suitable for efficiently manufacturing the semiconductor device 1C.

  In the manufacture of the semiconductor device 1C, the formation of the recess 108C (the first recess 110C) and the formation of the inclined groove can be simultaneously performed collectively by anisotropic etching. Then, the substrate material is cut along the cutting line when cutting the substrate material. Since this cutting line is included in the inclined groove, the cutting depth of the substrate material is smaller than the thickness of the substrate material. Thereby, the cutting operation of the substrate material can be efficiently performed, and the semiconductor device 1C can be efficiently manufactured.

  FIG. 35 shows a modification of the above-described semiconductor device 1C. The semiconductor device 1C 'shown in FIG. 35 includes a substrate 100C, a resin forming portion 150C, a wiring layer 200C, a first element 370C, a second element 380C, and a sealing resin 400C. The semiconductor device 1C 'shown in FIG. 35 includes a resin forming portion 150C as compared with the above-described semiconductor device 1C, and accordingly, the support structure of the second element 380C is different.

  The resin forming portion 150C is for providing a predetermined level difference in the recess 108C (the first recess 110C). In the present embodiment, the resin forming portion 150C is formed on the bottom surface (first bottom surface 111C) of the recess 108C (first recess 110C), and one end side in the y direction of the first bottom surface 111C (closer to the right end in the drawing) It is formed at the site of). The resin forming portion 150C is for mounting a portion close to one end in the y direction of the second element 380C. The height of resin forming portion 150C is, for example, about 150 μm. The resin forming portion 150C has a flat top surface and a side surface 152C inclined with respect to the top surface. Examples of the material of the resin forming portion 150C include epoxy resin, phenol resin, polyimide resin, polybenzoxazole (PBO) resin, and silicone resin.

  A resin forming portion pad 214C is formed on the resin forming portion 150C. In the present embodiment, a plurality of resin-formed pads 214C are formed side by side in the x-direction (the direction perpendicular to the sheet of FIG. 35). These resin forming portion pads 214C are used to mount the second element 380C. Further, since the side surface 152C of the resin forming portion 150C is inclined, the connection path (not shown) of the wiring layer 200C formed on the side surface 152C can be connected to the resin forming portion pad 214C.

  In the semiconductor device 1C 'shown in FIG. 35, among the four first inclined inner side surfaces 112C in the recess 108C, the first inclined inner side surface pads 212C are formed only on the first inclined inner side surface 112C on the left side in the drawing.

  In the second element 380C, only the side surface on the left side in the drawing is the inclined side surface 383C. In the second element 380C, the left side (inclined side 383C) in the drawing is supported by the first inclined inner side 112C, and the right side (opposing main surface 381C) in the drawing is supported by the resin forming portion 150C. At the time of mounting the second element 380C, the second element 380C can be easily set at a desired position in the z direction by adjusting the height dimension of the resin forming portion 150C.

  FIG. 36 shows another modification of the semiconductor device 1C described above. The semiconductor device 1C ′ ′ shown in FIG. 36 includes the substrate 100C, the resin forming portion 130C, the wiring layer 200C, the first element 370C, the two second elements 380C, and the sealing resin 400C. The semiconductor device 1C ′ ′ includes two second elements 380C as compared with the above-described semiconductor device 1C, and additionally includes a resin forming portion 130C.

  The resin forming portion 130C is for providing a predetermined level difference on the substrate 100C, and is formed on the substrate 100C (insulating layer 107C). In the semiconductor device 1C ′ ′ shown in FIG. 36, the resin forming portion 130C is formed on the main surface 101C and serves as a base of the external terminal 221. The resin forming portion 130C is a recess in the main surface 101C. The resin-formed portion 130C has a height of, for example, about 50 μm, and the resin-formed portion 130C has a flat top surface and the top surface. Since the side surface 132C of the resin forming portion 130C is inclined, the connection path (not shown) of the wiring layer 200C formed on the side surface 132C is connected to the external terminal 221C. can do.

  In the semiconductor device 1C ′ ′ shown in FIG. 36, a plurality of (two) second elements 380C are provided at an interval in the z direction. An additionally provided second element positioned in the upper side in the drawing Although 380C basically has the same configuration as the second element 380C located below in the drawing, the dimension in the y direction is larger than that of the second element 380C located below.

  In the first inclined inner side surface 112C supporting the two second elements 380C, a plurality of first inclined inner side surface pads 212C are formed at intervals in the z direction.

  The upper end portion of the second element 380C located in the upper side in the drawing protrudes upward from the recess 108C (the first recess 110C). The second sealing resin 420C covers all of the upper second element 380C. Thus, the second sealing resin 420C has a portion located outward of the main surface 101C in the normal direction of the main surface 101C.

  According to the semiconductor device 1C ′ ′ shown in FIG. 36, the number of elements (first elements) at different positions in the z direction can be increased without making the space for housing the first element 370C and the second element 380C in two steps. 370C and two second elements 380C) can be arranged in three dimensions.

  Further, as shown in FIG. 36, the second element 380C located in the upper side in the drawing protrudes above the main surface 101C. On the other hand, the external terminals 221C can be made to project in the z direction so as to be suitable for surface mounting of the external terminals 221C by forming the external terminals 221C on the main surface 101C via the resin forming portion 130C.

  FIGS. 37 and 38 show a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device 1D of the present embodiment includes a substrate 100D, a resin forming portion 150D, a wiring layer 200D, a columnar conductive portion 230D, a first element 370D, a second element 380D, and a sealing resin 400D. In FIG. 37, the sealing resin 400D is omitted for the sake of understanding. Further, in FIGS. 37 and 38, the communication route is omitted.

  The substrate 100D is a base of the semiconductor device 1D, and includes a base 106D and an insulating layer 107D. The substrate 100D has a main surface 101D, a back surface 102D, and a recess 108D. The thickness of the substrate 100D is, for example, about 600 μm. In the present embodiment, the main surface 101D and the back surface 102D face each other in the z direction, and the z direction corresponds to the thickness direction of the semiconductor device 1D. Also, the x direction and the y direction are both perpendicular to the z direction.

The substrate 106D is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. The insulating layer 107D, in this embodiment, consists of SiO _2. The material of the base 106D is not limited to Si, and any material that can form the recess 108D satisfying the intention described later may be used. The insulating layer 107D covers a portion of the base 106D facing from the opposite side to the back surface 102D. The thickness of insulating layer 107D is, for example, about 0.1 to 1.0 μm.

  In the present embodiment, the (100) plane of the base material 106D is adopted as the main surface 101D. The recess 108D is recessed from the main surface 101D toward the back surface 102D. In the present embodiment, the recess 108D comprises a first recess 110D. The first recess 110D has a first bottom surface 111D and four first inclined inner side surfaces 112D. The shape of the first recess 110D depends on the fact that the (100) plane is adopted as the main surface 101D.

  By forming the recess 108D, the main surface 101D has a rectangular annular shape in plan view. The first recess 110D is rectangular in plan view. The depth of the first recess 110D is, for example, about 440 μm. The first bottom surface 111D is rectangular in plan view. The four first inclined inner side surfaces 112D surround the first bottom surface 111D in a plan view, and have a substantially trapezoidal shape with a portion in contact with the first bottom surface 111D as an upper bottom. Each first inclined inner side surface 112D is inclined with respect to the first bottom surface 111D. In the present embodiment, the inclination angle of the first inclined inner side surface 112D with respect to the xy plane is about 55 °. The point that the first inclined inner side surface 112D has a substantially trapezoidal shape and the inclination angle is 55 ° depends on adopting the (100) plane as the main surface 101D.

  The resin forming portion 150D is for providing a predetermined level difference on the substrate 100D, and is formed on the substrate 100D (insulating layer 107D). In the present embodiment, the resin forming portion 150D is formed on the bottom surface (first bottom surface 111D) of the recess 108D (first recess 110D), and is a portion on which the second element 380D is mounted. In the present embodiment, the resin forming portion 150D is formed at two portions of the first bottom surface 111D that are separated in the y direction. The height of resin forming portion 150D is, for example, about 150 μm. The resin forming portion 150D has a flat top surface and a side surface 152D inclined with respect to the top surface. As a material of resin formation part 150D, an epoxy resin, a phenol resin, a polyimide resin, polybenzoxazole (PBO) resin, a silicone resin is mentioned, for example. The resin forming portion 150D may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  The wiring layer 200D is for forming a current path which is input to and output from the first element 370D and the second element 380D. The wiring layer 200D is mainly formed on the insulating layer 107D, and in the present embodiment, the barrier / seed layer 201D and the plating layer 202D are stacked.

  The barrier / seed layer 201D is a so-called base layer for forming a desired plating layer 202D, and is formed on the insulating layer 107D. The barrier / seed layer 201D is formed of, for example, a Ti layer as a barrier layer formed on the insulating layer 107D and a Cu layer as a seed layer stacked on the barrier layer. Barrier and seed layer 201D is formed, for example, by sputtering. In the present embodiment, the barrier / seed layer 201D is formed on a predetermined portion of the insulating layer 107D and the resin forming portion 150D.

  The plating layer 202D is made of, for example, Cu and is formed by electrolytic plating using the barrier / seed layer 201D. The thickness of the plating layer 202D is, for example, about 5 μm.

  In the present embodiment, the wiring layer 200D has a first bottom surface pad 211D, a resin forming portion pad 214D, a first inclined inner side surface pad 212D, and a connection path (not shown) for electrically connecting them. .

  The first bottom surface pad 211D is formed on the first bottom surface 111D of the first recess 110D. In the present embodiment, a plurality of first bottom surface pads 211D are formed, and these first bottom surface pads 211D are used to mount the first element 370D.

  The resin forming portion pad 214D is formed on the resin forming portion 150D. In the present embodiment, a plurality of resin forming portion pads 214D are formed in each of the resin forming portions 150D which are disposed apart from each other on the first bottom surface 111D. These resin forming portion pads 214D are used to mount the second element 380D. Further, since the side surface 152D of the resin forming portion 150D is inclined, the connection path (not shown) of the wiring layer 200D formed on the side surface 152D can be connected to the resin forming portion pad 214D.

  The first inclined inner side surface pad 212D is formed on the first inclined inner side surface 112D of the first recess 110D. In the present embodiment, a plurality of first sloped inner side surface pads 212D are formed on two first sloped inner side surfaces 112D disposed apart in the y direction with the first bottom surface 111D interposed therebetween. The first inclined inner side surface pad 212D is a portion to which one end of the columnar conductive portion 230D is connected.

  An external terminal 250D is provided on the sealing resin 400D. The external terminal 250D is used to, for example, surface mount the semiconductor device 1D on a circuit board of an electronic device (not shown). In the present embodiment, the external terminal 250D is provided on the upper surface 421D facing outward in the normal direction of the main surface 101D in the sealing resin 400D (second sealing resin 420D described later). In the present embodiment, a plurality of external terminals 250D are formed at two portions separated in the y direction with the recess 108D interposed therebetween. The external terminal 250D has a structure in which a bump obtained by electroless plating of a metal such as Ni, Pd, or Au, for example, is formed on an external terminal pad 240D described later. Thus, the external terminal 250D has a shape that bulges in the z direction. In the present embodiment, at least one external terminal 250D is a so-called ground terminal.

  The first element 370D is supported by the first bottom surface 111D, and is mounted via the solder 351D using the first bottom surface pad 211D.

  The second element 380D is supported by the resin forming unit 150D, and is mounted via the solder 351C using the plurality of resin forming unit pads 214D. In the present embodiment, the second element 380D is configured as a so-called ASIC (Application Specific Integrated Circuit) element, and the thickness thereof is about 80 to 100 μm.

  The sealing resin 400D covers the first element 370D and the second element 380D, and is filled in the recess 108D (the first recess 110D). In the present embodiment, the sealing resin 400D is composed of a first sealing resin 410D and a second sealing resin 420D.

  The first sealing resin 410D covers the entire first element 370D. On the other hand, the first sealing resin 410D does not cover the first inclined inner side surface pad 212D and the second element 380D.

  The second sealing resin 420D covers all of the second element 380D. The second sealing resin 420D has an upper surface 421D. The upper surface 421D faces outward in the normal direction of the main surface 101D. The second sealing resin 420D covers a part of the main surface 101D. On the other hand, the second sealing resin 420D exposes the external terminal 250D.

  Examples of the material of the first sealing resin 410D and the second sealing resin 420D include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The first sealing resin 410D and the second sealing resin 420D may be either translucent resin or non-translucent resin, but in the present embodiment, non-translucent resin is preferable.

  As shown in FIG. 38, the columnar conductive portion 230D penetrates the sealing resin 400D (second sealing resin 420D) in the depth direction of the recess 108D. The columnar conductive portion 230D is connected to a portion of the wiring layer 200D formed in the recess 108D, and extends along the z direction (the normal direction of the main surface 101D). In the present embodiment, the lower end of the columnar conductive portion 230D in the drawing is connected to a first inclined inner side surface pad 212D formed on the first inclined inner side surface 112D. The columnar conductive portion 230D is made of, for example, Cu, and is formed by electrolytic plating using the first inclined inner side surface pad 212D. In the present embodiment, a plurality of columnar conductive portions 230D extend from the two first inclined inner side surfaces 112D separated in the y direction with the bottom surface 111D interposed therebetween. The upper end of the columnar conductive portion 230D in the drawing and the upper surface 421D of the second sealing resin 420D are flush with each other.

  An external terminal pad 240D is formed on the sealing resin 400D. The external terminal pad 240D is formed on the upper surface 421D of the second sealing resin 420D. In the present embodiment, the external terminal pads 240D are made of, for example, Cu, and a plurality of the external terminal pads 240D are provided at positions corresponding to the plurality of columnar conductive portions 230D. The external end pad 240D and the external terminal 250D formed thereon overlap the columnar conductive portion 230D in the z direction. The external terminal pad 240D covers the upper end of the columnar conductive portion 230D, and is joined to the upper end of the columnar conductive portion 230D.

  Next, the procedure for forming the columnar conductive portion 230D penetrating the sealing resin 400D (the second sealing resin 420D) will be described with reference to FIGS.

  FIG. 39 shows a state in which the recess 108D is formed and the resin forming portion 150D and the wiring layer 200D are formed on the substrate material 100D '. Thereafter, as shown in FIG. 40, a resist layer 600D is formed. The formation of resist layer 600D is performed, for example, by spray coating of a photosensitive resist resin.

  Next, as shown in FIG. 41, the resist layer 600D is patterned. This patterning is performed by removing a desired portion by performing exposure and development on the resist layer 600D using, for example, a photolithography method. The shape of the resist layer 600D obtained by this patterning corresponds to the shape of the columnar conductive portion 230D described above. Here, an opening 610D corresponding to the shape of the columnar conductive portion 230D is formed in the resist layer, and a part of the first inclined inner side surface pad 212D is exposed. Note that the exposure may be performed a plurality of times while changing the focal depth of the exposure in response to the recess 108D having a certain depth.

  Next, as shown in FIG. 42, a columnar conductive portion 230D is formed. The formation of the columnar conductive portion 230D is performed by electrolytic plating using, for example, the first inclined inner side surface pad 212D. As a result, for example, a columnar conductive portion 230D made of Cu is obtained.

  Next, as shown in FIG. 43, the resist layer 600D is removed, and mounting of the first element 370D, formation of the first sealing resin 410D, and mounting of the second element 380D are sequentially performed (see FIG. 44).

  Next, as shown in FIG. 45, a second sealing resin 420 is formed. At this time, the upper end of the columnar conductive portion 230D protrudes from the upper end surface of the second sealing resin 420D. Next, as shown in FIG. 46, the upper portion of the second sealing resin 420D is polished, and the upper end of the columnar conductive portion 230D in the drawing and the upper surface 421D of the second sealing resin 420D are flush with each other.

  Next, the operation of the semiconductor device 1D will be described.

  According to the present embodiment, the first element 370D and the second element 380D are arranged and accommodated in the recess 108D (the first recess 110D) of the substrate 100D made of a semiconductor material. Therefore, it is not necessary to provide a lead for supporting the first element 370D and the second element 380D. The substrate 100D made of a semiconductor material is less expensive to reshape, as compared to when the leads are molded. Therefore, the cost of the semiconductor device 1D can be reduced. In particular, when the semiconductor device 1D is produced in a small amount, the cost reduction effect is remarkable.

  Since the substrate 100D is made of a single crystal of a semiconductor material typified by Si, the first inclined inner side surface 112D can be finished as a surface which is accurately inclined by a known predetermined angle with respect to the first bottom surface 111D. In particular, the angle of the four first inclined inner side surfaces 112D with respect to the first bottom surface 111D can be set to about 55 ° by employing the substrate 100D made of Si and adopting the (100) plane as the main surface 101D. . As a result, it is possible to make the semiconductor device 1D a well-balanced shape.

  A columnar conductive portion 230D penetrating the sealing resin 400D is provided. The columnar conductive portion 230D extends in the z direction from the recess 108 of the substrate 100D, and is conductively connected to the external terminal 250D. According to such a configuration, the external terminal 250D can be disposed inside the recess 108D in the z-direction view (view in the normal direction of the main surface 101D). In the present embodiment, the dimension in the y direction of the substrate 100D can be reduced, which is suitable for miniaturizing the semiconductor device 1D.

  The columnar conductive portion 230D extends in the z direction from the first inclined inner side surface 112D. As a result, the first element 370D, the second element 370D, and the columnar conductive portion 230D can achieve a three-dimensional arrangement in a narrow space while avoiding mutual interference.

  The lower end of the columnar conductive portion 230D is connected onto the first inclined inner side surface pad 212D. The columnar conductive portion 230D rises from the slope toward the z direction on the first inclined inner side surface pad 212D using an electrolytic plating method or the like, and is appropriately electrically connected to the first inclined inner side surface pad 212D.

  The upper end of the columnar conductive portion 230D is flush with the upper surface 421D of the second sealing resin 420D, and is covered by the external terminal pad 240D. According to such a configuration, the columnar conductive portion 230D and the external terminal 250D can be appropriately conductively connected via the external terminal pad 240D.

  By forming the resin forming portion 150D at an appropriate position in the recess 108D (the first recess 110D), the space for housing the first element 370D and the second element 380D can be formed in a two-step shape. By mounting the integrated circuit element 370D on the first bottom surface 111D and mounting the second element 380D on the resin forming portion 150D, the first element 370D and the second element 380D are three-dimensionally disposed at different positions in the z direction. be able to. As a result, it is possible to achieve both miniaturization and high functionality of the semiconductor device 1D.

  47 and 48 show a modification of the above-described semiconductor device 1D. The semiconductor device 1D 'shown in FIGS. 47 and 48 includes a substrate 100D, a resin forming portion 150D, a wiring layer 200D, a columnar conductive portion 230D, a first element 370D, a second element 380D, and a sealing resin 400D. . The semiconductor device 1D 'shown in FIG. 47 and FIG. 48 mainly differs from the above-described semiconductor device 1D in the arrangement of the columnar conductive portions 230D and the support structure of the second element 380D.

  In the semiconductor device 1D ′ shown in FIG. 47, the resin forming portion 150D is formed on the bottom surface (first bottom surface 111D) of the recess 108D (first recess 110D), and one end of the first bottom surface 111D in the y direction. It is formed in the part near the side (right side in the figure). The resin forming portion 150D is for mounting a portion close to one end in the y direction of the second element 380D.

  In the semiconductor device 1D 'shown in FIGS. 47 and 48, the plurality of columnar conductive portions 230D all extend in the z direction from one first inclined inner side surface 112D located on the right side in the drawing. The plurality of external terminals 250D include a plurality of external terminals 250D (251D) positioned on the right side in the drawing and a plurality of external terminals 250D (252D) positioned on the left side in the drawing. The external terminal 251D overlaps the columnar conductive portion 230D in the z-direction view (view in the normal direction of the main surface 101D). On the other hand, the external terminal 252D is spaced apart from the external terminal 251D with the bottom surface 111D interposed therebetween. The external terminal 252D and the columnar conductive portion 230 are formed on the second sealing resin 420D and are conducted via the wiring pattern 260D. The wiring pattern 260D and the second sealing resin 420D are covered with a resist 700D made of an insulating material. The resist 700D exposes the external terminals 251D and 252D and covers the entire surface in the other z direction.

  The left end of the second element 380D in the drawing is supported by the first inclined inner side surface 112D, and is mounted via the solder 351D using the plurality of first inclined inner side pads 212D. The second element 380D has an opposing main surface 381D, an opening side main surface 382D, and an inclined side surface 383D. The opposing major surface 381D opposes the first element 370D. The opening side main surface 382D is located on the opposite side to the opposing main surface 381D in the z direction. The area of the opening-side main surface 382D is larger than that of the facing main surface 381D. The inclined side surface 383D is a side surface facing one side (left in the drawing) in the y direction among the four side surfaces connecting the opposite main surface 381D and the opening side main surface 382D. The inclined side surface 383D is inclined with respect to the opposing main surface 381D, and in the present embodiment, the inclination angle of the inclined side surface 383D with respect to the opposing main surface 381D is about 55 °.

  In the second element 380D, a wiring pattern 384D made of a conductive metal thin film is formed in a predetermined region extending from the inclined side surface 383D to the opposing main surface 381D. With such a configuration, when the second element 380D is mounted, the first inclined inner side surface 112D and the inclined side surface 383D of the second element 380D face each other so as to be substantially parallel to each other.

  In the semiconductor device 1D 'shown in FIGS. 47 and 48, all columnar conductive portions 230D are collectively formed on the first inclined inner side surface 112D on the right side in the drawing which is one region. In the second element 380D, the inclined side surface 383D on the left side in the drawing is supported by the first inclined inner side surface 112D. Therefore, interference between the plurality of columnar conductive portions 230D and the second element 380D can be avoided. Therefore, it is suitable to miniaturize the entire semiconductor device 1D 'while increasing the size of the second element 380D. On the other hand, the external terminal 251D and the external terminal 252D are spaced apart in the y direction. Thus, the semiconductor device 1D 'can be mounted on the substrate of the electronic device in a balanced manner.

  FIG. 49 shows another modification of the semiconductor device 1D described above. The semiconductor device 1D ′ ′ shown in FIG. 49 includes a substrate 100D, a wiring layer 200D, a columnar conductive portion 230D, a first element 370D, a second element 380D, and a sealing resin 400D. The semiconductor device shown in FIG. Compared with the above-described semiconductor device 1D, 1D ′ ′ mainly differs in the shape of the recess 108D of the substrate 100D, and does not include the resin forming portion 150D.

  In the semiconductor device 1D ′ ′ shown in FIG. 49, the recess 108D includes the first recess 110D and the second recess 120D. The first recess 110D is located on the back surface 102D side, and the first bottom surface 111D and the four first The second recess 120D is located closer to the major surface 101D than the first recess 110D, and has two second bottom surfaces 121D and four second sloped inner surfaces 122D. The shapes of the 110D and the second recess 120D depend on the adoption of the (100) plane as the main surface 101 D. The configuration of the first recess 110D and the second recess 120D is the same as that shown in FIG. The configuration is similar to the configuration of the first recess 110A and the second recess 120A.

  The second recess 120D is rectangular in plan view. The two second bottom surfaces 121D are rectangular in plan view, and sandwich the first recess 110D. In addition, each second bottom surface 121D is connected to the first inclined inner side surface 112D. The four second inclined inner side surfaces 122D surround the two second bottom surfaces 121D in a plan view, and have a substantially trapezoidal shape. Each second inclined inner side surface 122D is inclined with respect to the second bottom surface 121D. In the present embodiment, the inclination angle of the second inclined inner side surface 122D with respect to the xy plane is about 55 °. The point that the second inclined inner side surface 122D is substantially trapezoidal and the inclination angle is 55 ° depends on the adoption of the (100) plane as the principal surface 101D.

  In the semiconductor device 1D ′ ′ shown in FIG. 49, the wiring layer 200D includes the first bottom surface pad 211D, the second bottom surface pad 215D, the second inclined inner side surface pad 216D, and a connection path (not shown) for electrically connecting them. have.

  The second bottom surface pad 215D is formed on the second bottom surface 121D. In the present embodiment, a plurality of second bottom surface pads 215D are formed on each of the second bottom surfaces 121D spaced apart in the y direction with the first bottom surface 111D interposed therebetween. These second bottom pads 215D are used to mount the second element 380D.

  The second inclined inner side surface pad 216D is formed on the second inclined inner side surface 122D of the second recess 120D. In the present embodiment, a plurality of second sloped inner side surface pads 216D are formed on the two second sloped inner side surfaces 122D which are spaced apart in the y direction with the first bottom surface 111D interposed therebetween. The second inclined inner side surface pad 216D is a portion to which one end of the columnar conductive portion 230D is connected.

  In the semiconductor device 1D ′ ′ shown in FIG. 49, by forming the recess 108D into a two-step shape by the first recess 110D and the second recess 120D, a space dedicated to housing the first element 370D and the first recess 110D. Thus, the first element 370D and the second element 380D can be appropriately arranged in three dimensions.

  The semiconductor device according to the present invention is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device according to the present invention can be varied in design in many ways.

1A to 1D, 1B ', 1C', 1C ", 1D ', 1D" Semiconductor devices 100A to 100D Substrates 101A to 101D Main surfaces 102A to 102D Back surfaces 103A to 103D Outer surfaces 104A to 104D Inclined outer surfaces 105A to 105D Standing outer surfaces 106A to 106D base materials 107A to 107D insulating layers 108A to 108D concave portions 110A to 110D first concave portions 111A to 111D first bottom surfaces 112A to 112D first inclined inner side surfaces 120A, 120D second concave portions 121A, 121D second bottom surfaces 122A, 122D 2 Inclined inner side surface 130A, 130C resin forming portion 140A resin forming portion 150B, 150C, 150D resin forming portion 183A inclined groove 200A to 200D wiring layer 211A to 211D first bottom surface pad 213A resin forming portion pad 214B to 214D resin forming portion pad 12A, 212C, 212D first inclined side surface pad 215D second bottom surface pad 216D second inclined inner side surface pad 221A to 221C external terminal 230D columnar conductive portion 231A, 234A, 235A, 236A connection path 240D external terminal pad 250D, 251D, 252D External terminal 260D Wiring pattern 311A, 312A, 313A Directional sensor element 330A, 330B Integrated circuit element 343A Capacitor 350B Wireless communication element 351A to 351D Solder 360B Inductor 370C, 370D First element 380C, 380D Second element 381C, 381D Opposing main surface 382C , 382D Opening side main surface 383C, 383D Inclined side surface 400A to 400D Sealing resin 410A to 410D First sealing resin 420A to 420D Second sealing resin 500A, 500 B metal film 510A, 510B connection path

Claims (19)

A substrate comprising a main surface, an outer side surface intersecting the main surface, and a recess recessed from the main surface, and made of a semiconductor material;
A wiring layer at least a part of which is formed on the substrate;
One or more elements accommodated in the recess;
A sealing resin covering at least a part of the one or more elements;
A metal film formed on the outer side surface,
Equipped with
The outer side includes a rising outer side, and an inclined outer side interposed between the main surface and the rising outer side and inclined with respect to both the main side and the rising outer side,
The metal film is formed on the inclined outer surface and exposes the rising outer surface,
The semiconductor device according to claim 1, wherein the inclined outer side surface is smoother than the upright outer side surface. The wiring layer has a plurality of external terminals formed on the main surface,
The semiconductor device according to claim 1, wherein the metal film has a connection path connected to any one of the plurality of external terminals connected to ground.   The semiconductor device according to claim 2, wherein the metal film surrounds the main surface as a whole when viewed in the normal direction of the main surface.   The semiconductor device according to claim 2, wherein the one or more elements include a wireless communication element. An additional element covering at least a portion of the one or more elements;
The semiconductor device according to any one of claims 1 to 4, comprising an additional metal film located between the additional element and the one or more elements.   The semiconductor device according to claim 5, wherein the additional metal film overlaps the entire one of the one or more elements in the normal direction of the main surface. The semiconductor device according to any one of claims 1 to 6 , wherein the outer side surface surrounds the main surface as viewed in the normal direction of the main surface and has a rectangular ring shape. The semiconductor device according to claim 7 , wherein the substrate is made of a single crystal of a semiconductor material. The semiconductor device according to claim 8 , wherein the semiconductor material is Si. The semiconductor device according to claim 9 , wherein the recess has an inclined inner side surface inclined with respect to the main surface and a bottom surface. The main surface is a (100) surface,
The semiconductor device according to claim 10 , wherein the recess has four the inclined inner side surfaces. The semiconductor device according to claim 11 , wherein an inclination angle of the inclined outer side surface with respect to the main surface is the same as an inclination angle of the inclined inner side surface with respect to the main surface.   The semiconductor device according to any one of claims 1 to 4, further comprising a resin forming portion formed in at least one of the main surface and the recess. The resin forming portion includes a first resin forming portion formed on the main surface,
The semiconductor device according to claim 13 , wherein the wiring layer has a plurality of external terminals formed in the first resin forming portion. An additional element covering at least a portion of the one or more elements;
The recessed portion accommodates the one or more elements, and includes a first recessed portion having a first bottom surface and a first sloped inner surface, a second bottom surface connected to the first sloped inner surface, and the second bottom surface and the main surface The semiconductor device according to claim 14 , further comprising: a second recess having a connected second inclined inner side surface. The semiconductor device according to claim 15 , wherein the additional element is supported by the second bottom surface and overlaps at least a part of the first recess in a normal direction of the main surface. The substrate is made of a single crystal of semiconductor material, the semiconductor device according to claim 15 or 16. The semiconductor device according to claim 17 , wherein the semiconductor material is Si. The semiconductor device according to claim 18 , wherein an inclination angle of the inclined outer side surface with respect to the main surface is the same as an inclination angle of the first inclined inner side surface and the second inclined inner side surface with respect to the main surface.

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