JP6416232B2 - CMUT device manufacturing method, CMUT device, and apparatus - Google Patents

Description

  The present invention has a first electrode on a substrate and a second electrode embedded in an electrically insulating membrane, and a cavity formed by removal of a sacrificial material between the first electrode and the membrane is a first. The present invention relates to a method of manufacturing a capacitive micro-machined ultrasound transducer (CMUT) device that separates an electrode and a membrane.

  The present invention further relates to a CMUT device having a first electrode on a substrate and a second electrode embedded in an electrically insulating membrane, wherein the first electrode and the membrane are separated by a cavity.

  The invention further relates to an apparatus comprising such a CMUT device.

  For example, capacitive micromachined ultrasonic transducer (CMUT) devices are rapidly becoming the default choice as sensors in the area of sensing devices such as imaging devices. This is because CMUT devices are often capable of providing superior bandwidth and acoustic impedance characteristics, making them more preferable than, for example, piezoelectric transducers.

  By applying pressure (eg, using ultrasound), vibration of the CMUT membrane (membrane) can be triggered, or vibration of the CMUT membrane can be induced electrically. An electrical connection to a CMUT device, often by an integrated circuit (IC), such as an application specific integrated circuit (ASIC), supports both the transmit and receive modes of the device. In the reception mode, a change in the membrane position causes a change in capacitance, which can be detected electronically. In the transmission mode, vibration of the membrane is generated by applying an electric signal.

  CMUT devices generally operate with a bias voltage applied. The CMUT device can be operated in a so-called collapse mode in which the applied bias voltage is increased above the collapse voltage to constrain the membrane and constrain a portion of it against the substrate. The frequency of operation of the CMUT device is characterized by the membrane material and physical properties, such as stiffness, and the size of the cavity. The bias voltage and application of the CMUT device also affects the mode of operation. CMUT devices are often used in ultrasonic imaging apparatus applications and other applications where the CMUT device is used to detect fluid or air pressure. The pressure causes membrane deflection, which is electronically detected as a change in capacitance. A pressure reading can then be derived.

  Manufacturing CMUT devices that meet design specifications is not a simple task. To obtain a cost-effective device, it is desirable to manufacture a CMUT device with existing manufacturing technology, for example. CMOS is a non-limiting example of such technology. For example, US Pat. No. 8,309,428 discloses a CMOS manufacturing method for such a device.

  However, it has been found difficult to obtain acceptable CMUT devices with high yield from wafers manufactured with such technology. What has been found by the inventor of the present application is that, over the wafer, a significant number of manufactured CMUT devices suffer from membrane bowing, which renders the device nonfunctional. This problem occurs, for example, when a device is manufactured according to the teachings of US Patent Application Publication No. 2013/0069480.

U.S. Pat. No. 8,309,428 US Patent Application Publication No. 2013/0069480

  The present invention seeks to provide a method of manufacturing a CMUT device that improves the yield of the manufacturing process.

  The present invention further seeks to provide a wafer obtainable by this manufacturing process.

  The present invention further seeks to provide a CMUT device obtainable by this manufacturing process.

  The present invention further seeks to provide an apparatus having such a CMUT device.

  According to one aspect, there is provided a method for manufacturing a capacitive micromachined ultrasonic transducer (CMUT) device having a first electrode on a substrate and a second electrode embedded in an electrically insulating membrane, the first electrode And the membrane are separated by a cavity formed by removal of the sacrificial material between the first electrode and the membrane, and the method includes: a membrane portion on the second electrode; And forming a further membrane portion extending toward the substrate, wherein the thickness of each of the membrane portion and the further membrane portion exceeds the thickness of the sacrificial material prior to forming the cavity .

  The inventor of the present application has surprisingly discovered that many of the non-functional CMUT devices and / or CMUT devices that operate outside the design tolerances obtained from such manufacturing processes are state-of-the-art manufacturing processes. In which, after release of the cavity, the membrane is finished when access to the cavity is sealed by a suitable sealing material, for example an electrically insulating (dielectric) material that is also used to form the membrane. It is generated by the facts. Such a process is disclosed, for example, in US Pat. While such a process is attractive because cavity sealing and membrane completion can be accomplished by a single deposition step, the inventors of the present application have noticed that this is because the membrane is relatively thin When encapsulating the cavity in spite of that, it results in a relatively large number of CMUT devices having a deformed membrane on the finished wafer. It has been found that the reason for this is that such a sealing step is typically performed at an elevated temperature, for example about 400 ° C., and the thermal expansion coefficient of the second electrode and membrane dielectric material. This is because excessive stress can be generated in the membrane, resulting in membrane warping or buckling. This yield can be dramatically improved by ensuring that the thickness of the membrane covering the second electrode exceeds the thickness of the sacrificial material prior to forming the cavity.

  Patent Document 1 (US Pat. No. 8,309,428) discloses a CMOS manufacturing process of a CMUT device in which a protective layer is formed to cover an upper electrode before removing a sacrificial layer. However, this protective layer is for protecting the electrode from contamination, and Patent Document 1 completely talks about the thickness of this protective layer and its effect on preventing membrane deformation during cavity formation. Absent.

  In one embodiment, the thickness of the additional membrane portion exceeds the thickness of the membrane portion. This further increases the robustness of the membrane during the cavity formation process, thereby further improving the yield of the manufacturing process.

  The thickness of the membrane portion may be at least 5 times, or even 10 times the thickness of the sacrificial material. This is because these thicknesses achieve the desired membrane robustness during cavity formation. For larger cavities, eg, CMUT devices having a cavity diameter of at least 100 microns, a membrane portion thickness of at least 10 times the thickness of the sacrificial material is preferred.

  In one embodiment, removing the sacrificial material comprises creating access to the sacrificial material, and the method further comprises sealing the access after forming the cavity, and the sealing step includes Forming a seal on the membrane part and further membrane part. This further increases the thickness of the membrane and the robustness of the final device. This is particularly advantageous for CMUT devices having a membrane diameter in the micron range, for example a membrane diameter of 50 microns or more.

  In another embodiment, the method further includes forming an etch stop layer on the membrane portion and etching away the seal portion from the membrane portion prior to the sealing step, the etch stop layer. Etching removed above and removing the etch stop layer after the etch removing step.

  The etch stop layer may be dimensioned such that the seal ring remains on the additional membrane portion upon completion of the etch-off step. It has been found that such a ring further strengthens the membrane without significantly affecting the flexibility of the membrane.

  In one embodiment, the membrane forms a first dielectric material layer at least partially over the sacrificial material, forms a second electrode on the first dielectric material layer, and the second dielectric material. Formed by forming a membrane portion, which is a layer, on the second electrode. The dielectric material may be silicon nitride or some other suitable dielectric material.

  A wafer having a plurality of CMUT devices obtained by a method according to an embodiment of the invention may be provided. Such wafers benefit from an acceptable CMUT device being removed from the wafer with a much higher yield.

  According to another aspect, a capacitive micromachined ultrasonic transducer (CMUT) device is provided having a first electrode on a substrate and a second electrode embedded in an electrically insulating membrane, the first electrode and the membrane Are separated by a cavity, the membrane having a single layer membrane portion on the second electrode and a further membrane portion extending from the single layer membrane portion along the side of the cavity toward the substrate; The single layer membrane portion and the further membrane portion each have a thickness that exceeds the height of the cavity, which thickness is at least 5 times and preferably 10 times the height of the cavity. Such devices benefit from being cost effective because they can be manufactured with high yields while exhibiting excellent bandwidth and acoustic impedance characteristics.

  In one embodiment, the thickness of the additional membrane portion exceeds the thickness of the single layer membrane portion. This further improves the robustness of the CMUT device.

  In one embodiment, the CMUT device further comprises a ring of electrically insulating material on the further membrane portion, and the single layer membrane portion is at least partially exposed inside the ring. This increases the strength of the membrane without significantly affecting the dynamic properties of the membrane.

  In one embodiment, the CMUT device further includes a protrusion of sealing material extending from the cavity. In this embodiment, this protrusion seals the cavity without adding the overall thickness of the membrane covering the second electrode.

  The CMUT device may be obtained by a method according to one embodiment of the present invention.

  According to another aspect, there is provided an apparatus having a CMUT device according to an embodiment of the present invention. Such a device may be, for example, an ultrasound imaging device or a pressure sensing device.

Embodiments of the present invention will now be described in more detail by way of example with reference to the accompanying drawings.
It is a figure which shows typically the CMUT device of a prior art. FIG. 2 schematically illustrates an undesirable deformation of the membrane of the prior art CMUT device of FIG. FIG. 2 is a stress sensitivity plot showing stress sensitivity of the prior art CMUT device of FIG. 1. FIG. 6 schematically illustrates various processing steps for manufacturing a CMUT device according to an embodiment of the present invention. FIG. 6 is a diagram schematically showing an important processing step for manufacturing a CMUT device according to another embodiment of the present invention. FIG. 6 is a diagram schematically illustrating an important process for manufacturing a CMUT device according to still another embodiment of the present invention. FIG. 2 is a stress sensitivity plot showing the stress sensitivity of the prior art CMUT device of FIG. 1 and the CMUT device according to an embodiment of the present invention. FIG. 2 shows a microscopic image of a portion of a prior art wafer (top view) and a portion of a wafer manufactured according to an embodiment of the invention (bottom view). FIG. 6 shows a typical capacitance-voltage curve for a CMUT device. FIG. 5 is a plot showing the collapse voltage characteristics of prior art CMUT devices as a function of their wafer position. 6 is a plot showing the collapse voltage characteristics of CMUT devices according to an embodiment of the invention as a function of their wafer position. FIG. 4 is a plot showing the acoustic performance of CMUT devices according to one embodiment of the present invention as a function of their wafer position.

  It should be understood that the drawings are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings to refer to the same or like parts.

  FIG. 1 schematically shows a typical structure of a CMUT device. The CMUT device has a substrate 10 on which a first electrode (not shown for clarity) is formed in a cavity 30. The cavity 30 is delimited by a membrane 20 having a second electrode (not shown for clarity) embedded in the membrane 20. The membrane 20 typically includes a first portion 22 above the cavity 30 and a second portion 24 that extends from the first portion 22 toward the substrate 10 and serves as the wall of the cavity 30. Have.

  The cavity 30 may have a diameter 2R or radius R and a height g. The first membrane portion 22 has a thickness t, and the second membrane portion 24 has a thickness w. Typical dimensions of the completed CMUT device are g to 0.25 μm, t to 0.5-4 μm, w to t, and R to 15 to 150 μm. However, before the release of the cavity 30, the thickness t (and w) is typically smaller. This is because, as described above, the membrane 20 is typically completed at the same time as sealing an access, such as a via, through which the cavity 30 is released. It should be understood that FIG. 1 is schematically depicted in a simplified manner. For example, it should be understood that one or more layers forming the membrane 20 extend above the substrate 10 as will be apparent from subsequent figures. Such extended layers are omitted in FIG. 1 for clarity only.

  During the sacrificial etch that releases the cavity 30, the CMUT device is exposed to temperatures up to 400 ° C. It has been recognized by the inventor that the difference between the thermal expansion coefficients of the second electrode material and the material of the membrane 20 causes the membrane 20 to generate stress that can lead to deformation of the membrane 20 as shown in FIG. . The stress on the membrane 20 can cause the first portion 22 to be pushed out of the horizontal plane by a distance h and the second portion (ie, the wall section) 24 to be pushed out of the vertical plane by an angle θ. It has been found that this deformation is a typical state-of-the-art CMUT device in which a relatively thin membrane is present on the sacrificial material during removal of the sacrificial material to form (release) the cavity 30. This is the main reason for the low yield in the manufacturing process.

  The amount of deformation is the following analytical formula derived by the inventor:

を用いてモデル化され得る。

Can be used to model.

  In this equation, S is the stress in the membrane (in MPa) and E is the Young's modulus, which has a typical value in the range of 50-250 GPa. The force on the second portion 24 resulting from the out-of-plane deformation of the first portion 22 causes a rhombic deformation of the second portion 24 as shown in FIG.

  Analytical equation (1) can be used to calculate a deformation plot for the first membrane portion 22 as a function of the ratio t / w (x-axis) and g / t (y-axis). Such a plot is shown in FIG. The black dots in this plot are typical out-of-plane bends of the first membrane portion 22 of a typical prior art CMUT device with a thin membrane 20 during release of the cavity 30 at g / t˜1. h. The deformation h also correlates with the relative position of the CMUT device on the wafer, and the membrane of the device at the periphery of the wafer is more susceptible to such deformation than the device located at the center of the wafer. This is caused, for example, by wafer position dependent non-uniformities introduced by the deposition tool used to form the membrane 20. This is illustrated in more detail below.

  In some application areas, such as low frequency application areas, it is necessary to increase the radius R of the cavity 30. As can be appreciated, this problem is exacerbated for larger CMUT devices, ie, CMUT devices with larger R, because the amount of out-of-plane bend h increases linearly with radius R. As can be understood from the analytical expression in the present invention, the amount of out-of-plane bending of the first membrane portion 22 can be reduced by reducing the ratio g / t and / or the ratio t / w. Embodiments of the present invention provide a method for manufacturing a CMUT device in which at least one of these ratios is reduced to improve the yield of the CMUT device manufacturing process.

  FIG. 4 schematically depicts one embodiment of a CMUT manufacturing method. The method begins in step (a) with the provision of a substrate 110 that may be any suitable substrate, such as, for example, a silicon substrate, a silicon-on-insulator substrate, a silicon germanium substrate, and a gallium nitride substrate. Silicon-based substrates can be used, for example, in CMOS manufacturing processes. A first electrode 112 is formed over the substrate 110. The electrode may be formed from any suitable conductive material, for example a metal or metal alloy. For example, it is particularly advantageous to use metals that are readily available for the selected manufacturing technology. This requires only a minimal redesign of the manufacturing flow, which is attractive in terms of cost. For example, in a CMOS process, a conductive material such as Al, W, Cu, Ti, TiN, and combinations of such materials can be used to form the first electrode 112. In one embodiment, the first electrode 112 is selected from Al, an AlNd alloy, or an Al / Mo stack. The formation of such electrodes is well known per se and will not be described in further detail for the sake of brevity.

  Thereafter, optionally, the first electrode 112 and the substrate 110 may be covered by an electrically insulating material layer 114. This is shown in step (b). The electrically insulating layer is also referred to herein as a dielectric layer. Such a dielectric layer 114 can, for example, electrically insulate the first electrode 112 from its counter electrode (counter electrode) (shown later) to prevent shorting between these electrodes during operation of the CMUT device. Can be used to Further, the dielectric layer 114 can be used to protect the first electrode 112 and the substrate 110 from damage during removal of the sacrificial material to form a cavity above the first electrode 112.

  Although the dielectric layer 114 is shown to cover the entire surface of the substrate 110, the patterned dielectric is such that only certain portions of the substrate 110 along with the first electrode 112 are covered by the dielectric layer 114. Providing the body layer 114 is equally feasible. Any suitable dielectric material may be used to protect the first electrode 112 and the substrate 110. In one embodiment, the dielectric layer 114 is silicon oxide, such as TEOS or the like, although any suitable dielectric material may be used for the dielectric layer 114. Thus, the dielectric layer 114 may be formed in any suitable manner, such as using suitable deposition techniques such as, for example, CVD and PECVD, the formation of which is more particularly for simplicity. I do not explain.

  In step (c), a sacrificial material is formed on the dielectric layer 114 by, for example, a suitable deposition technique. The sacrificial material may further have a second portion 116 ′ that is patterned to form a first portion 116 from which a cavity is formed and that acts as a channel through which the sacrificial material is removed. . Corresponding to the gap height g shown in FIG. 1 of the cavity to be formed, the height of the first part 116 and the second part 116 ′ of the sacrificial material is typically in the range of 100-1000 nm. However, it should be understood that values outside this range may be contemplated.

  In one embodiment, the first portion 116 may be deposited as a circular portion having several tooth-like protrusions (eg, 2-8 protrusions) as the second portion 116 '. A top view of such a sacrificial material portion is shown in step (c '). Here, four such protrusions are shown merely as a non-limiting example. The toothed second portion 116 ′ is typically used as a cavity access platform outside the formed membrane that can provide access to the first portion 116 to open or release the cavity. Is done. It should be understood that the first portion 116 and the second portion 116 'are typically formed to the same thickness or height, and the membrane formed is between the toothed second portions 116'. Extending toward the substrate 110. In the various figures of the present application, the second portion 116 ′ is different to indicate this point, that is, the membrane of the CMUT device extends toward the substrate 110 between the toothed second portions 116 ′. It is shown as having a thickness. This should not be interpreted as the first portion 116 and the second portion 116 'actually having different thicknesses.

  In principle, any suitable sacrificial material may be used, but for device performance reasons it is preferred to use a sacrificial material that can be efficiently removed in subsequent etching steps. For example, the use of metals such as Al, Cr and Mo, or the use of non-metals such as amorphous silicon and silicon oxide can be contemplated. For example, materials such as Al, amorphous silicon and silicon oxide are readily available in, for example, CMOS processes, and among these materials Al can be removed particularly efficiently by etching. The patterned sacrificial material may be formed in any suitable manner, for example using a suitable deposition and patterning technique, the formation of which is not described in more detail for the sake of brevity.

  As will be appreciated, the diameter of the first portion 116 defines the diameter of the cavity of the CMUT device being formed. In one embodiment, this diameter is selected within the range of 20-500 microns, more preferably within the range of 50-300 microns, but it should be understood that, for example, diameters up to 1000 microns. Larger diameters can also be contemplated.

  In step (d), a first dielectric layer 120 of the membrane to be formed is deposited covering the first and second portions 116 and 116 ′ of the sacrificial material and the exposed portion of the dielectric layer 114. The Since both the first dielectric layer 120 and the dielectric layer 114 are exposed to an etching recipe for removing the sacrificial material, the first dielectric layer 120 and the dielectric layer 114 can be of the same material. However, it is natural that different materials are used for the first dielectric layer 120 and the dielectric layer 114, respectively. In one embodiment, the first dielectric layer 120 and the dielectric layer 114 each comprise a silicon oxide layer, such as, for example, a TEOS layer or the like. The first dielectric layer 120 may be formed as a layer stack, such as an oxide-nitride stack or an oxide-nitride-oxide stack. Similarly, the dielectric layer 114 may be formed as such a stack. Again, any suitable dielectric material may be used for the dielectric layer 114 and the first dielectric layer 120.

  Next, as shown in step (e), the second electrode 122 is formed on the first dielectric layer 120 so that the second electrode 122 faces the opposite side of the first electrode 112. The second electrode 122 is preferably formed of the same conductive material as the first electrode 112, but it should be understood that the second electrode 122 and the first electrode 112 are instead of different materials. It may be formed. The second electrode 122 may be formed of any suitable conductive material such as, for example, Al, W, Cu, Ti, TiN, and combinations of such materials. In one embodiment, the second electrode 122 is selected from Al, an AlNd alloy, or an Al / Mo stack. The second electrode 122 can be formed using well-known techniques, which will not be described in further detail for the sake of brevity. The first electrode 112 and the second electrode 122 can be formed to any suitable thickness, for example, 200-700 nm thick.

  In step (f), a second dielectric layer 124 of the membrane to be formed is formed covering the second electrode 122 and the first dielectric layer 120. The second dielectric layer typically includes a first portion 22 above the second electrode, alongside the first portion of the sacrificial material 116 from the first portion 22 and, as described above, of the sacrificial material. And a second portion 24 extending toward the substrate 10 between (and above) the second portions 116 ′. The first portion 22 has an initial thickness t1, the second portion has an initial thickness w1, and w1 and t1 are typically (approximately) equal. In order to avoid misunderstanding, t1 corresponds to t in FIG. 1, and w1 corresponds to w in FIG. According to one embodiment of the present invention, t1 is selected to be greater than the height of the first portion 116 in order to reduce the ratio t / g described above with the help of FIG. In a preferred embodiment, the ratio t / g is selected in the range of 4-20, more preferably in the range of 5-10, in order to give the membrane the desired robustness during the formation of the cavities. For example, the height g of the sacrificial portion 116 is selected within a range of 100 to 700 nm, and the first portion 22 is at least five times thicker than the sacrificial portion 116 so that the thickness of the first portion 22 is It is selected within the range of 0.5-10 microns.

  The second dielectric layer 124 can be made of the same material as at least the upper layer of the first dielectric layer stack 120 and is generally made of a suitable electrically insulating material such as silicon oxide or silicon nitride. Of course, it is also feasible that the second dielectric layer 124 is made of a different material than the first dielectric layer 120. However, in that case, the thermal expansion coefficients of each of these different materials are equal to avoid building heat induced stress between the layers at the temperature at which the sacrificial material is removed to form the cavity. Or care should be taken to be the same. As described above, the second dielectric layer 124 may be formed by any suitable technique.

  In step (g), an etch stop layer 126 is formed over the first portion of the second dielectric layer 124, and then the first portion to provide access to the second portion 116 'of the sacrificial material. An access or via 128 is formed through the dielectric layer 120 and the second dielectric layer 124. This is shown in step (h). The access or via typically lands on one of the sacrificial material toothed second portions 116 'outside the periphery of the membrane, as previously described. The formation of such access or via 128 is well known per se and will not be described in further detail merely for the sake of brevity.

  Next, in step (i), the second electrode 122 embedded between the first dielectric layer 120 and the second dielectric layer 124 of the membrane of the CMUT device, In order to form a cavity 130 between the first and second portions 116 and 116 'of the sacrificial material through the access or via 128 using a suitable etch recipe. Suitable etch recipes for such conventional sacrificial materials are well known per se, and those skilled in the art will use their general knowledge to select an appropriate etch recipe without difficulty.

  Thereafter, in step (j), the access or via 128 is sealed using a suitable sealing material, such as a suitable additional dielectric material, thereby etching stop layer 126 and second dielectric layer 124. A further dielectric material layer 132 is created and a sealing plug 132 ′ in the access or via 128 is created. In one embodiment, the minimum thickness of the additional dielectric material layer 132 is twice the height g of the cavity 130 to ensure effective sealing of the access or via 128. This additional dielectric material may be any suitable dielectric material that may be deposited in any suitable manner, as is known per se. In one embodiment, the additional dielectric material is the same material as the material of the second dielectric layer 124, such as silicon oxide or silicon nitride. The formation of a further dielectric material layer 132 increases the thickness of the cavity wall portion defined by the second portion 24 to w1 + w2, as shown in step (j). To avoid misunderstanding, w1 + w2 corresponds to w in FIG.

  In order to reduce the CMUT device ratio t / w, in step (k), a portion of the further dielectric material layer 132 above the first portion 22 stops on the etch stop layer 126, for example an isotropic dry It is selectively removed using a suitable etching recipe such as an etching recipe. It should be apparent at this point that the etch stop layer material is selected to be highly resistant to the etch recipe used to remove selected portions of the additional dielectric material layer 132. Such materials are known per se and it is therefore sufficient to say that any suitable etch stop material may be selected and deposited and patterned in any suitable manner.

  Thereafter, in step (k), the etching stopper layer is removed by, for example, etching so as to form the opening 134, whereby the thickness of the first portion 22 above the second electrode 122 is t1. A CMUT device is created having a membrane that is and the thickness of the second portion 24 along the side of the cavity 130 is w1 + w2, ie, t1 + w2 when t1-w1. Accordingly, since g << t and t << w at the stage of removing the sacrificial material for forming the cavity 130, a CMUT device with improved membrane robustness during the cavity release process is obtained. Furthermore, since the second dielectric layer 124 is deposited, for example, prior to the release of the cavity 130, a membrane with improved flatness is obtained. This is because the presence of the sacrificial material prevents deformation of the first dielectric layer 120 during the formation of the second dielectric layer 124.

  The CMUT device further includes a ring 136 of a further dielectric material layer 132 above the second portion 24, which defines the first portion 22. It has been found that the presence of such a rim or ring structure (which can be shaped like a heel ear or similar pointed ear, for example) is a cavity release step. Further enhance the robustness of the membrane inside. In the context of the present application, it should be understood that robustness is used to describe the ability of a membrane to withstand out-of-plane deformation 'h' as shown in FIG.

  However, such a ring 136 may be omitted from the CMUT device design in other embodiments. One such embodiment is shown in FIG. 5, which illustrates selected alternative steps to the manufacturing method shown in FIG. 4 and described above. Step (a) in FIG. 5 replaces step (g) in FIG. 4, and step (b) in FIG. 5 replaces step (k) in FIG. Although not explicitly included in FIG. 5 for the sake of brevity, the other steps shown in FIG. 4 also form part of the process flow depicted in FIG.

  In step (a), the etch stop layer 226 is dimensioned to cover the first portion 22 and the second portion 24 of the second dielectric layer 124. This is because in the subsequent process, particularly in the selective removal of the additional dielectric material layer 132 formed in step (j) of FIG. It has the result that it results in a CMUT device that is not (significantly) increased, i.e. tw in this embodiment. This is because the etch stop layer 226 protects a larger area of the underlying second dielectric layer 124 against an etch recipe that removes selected portions of the additional dielectric material layer 132. As will become apparent, the additional dielectric material layer 132 is removed over a wider area of the second dielectric layer 124. Instead, as shown in step (b) of FIG. 5, the resulting CMUT device includes a sealing plug 132 ′ in the access or via 128 and the additional dielectric that extends upward from the sealing plug. A portion 232 of the material layer. The combination of the sealing plug 132 'and the portion 232 can be compared to a pin that is pushed into the access or via 128, with the portion 232 forming the head of the pin. As can be understood from analytical equation (1), the CMUT device shown in FIG. 5 (b) is still g << t at the stage of removal of the sacrificial material to form the cavity 130, so that during the cavity release process The improvement of membrane robustness is shown. Furthermore, since the second dielectric layer 124 is deposited, for example, prior to the release of the cavity 130, a membrane with improved flatness is obtained. This is because the presence of the sacrificial material prevents deformation of the first dielectric layer 120 during the formation of the second dielectric layer 124.

  In one embodiment, the additional dielectric layer 132 may be replaced by a metal sealing layer, such as an Al sealing layer. This improves the vacuum in the cavity 130. This is because metals are typically deposited in the gas phase, leaving a high residual pressure in the cavity 130, as opposed to depositing dielectric materials such as silicon nitride, using high vacuum deposition techniques. It is because it is deposited. Accordingly, the sealing plug 132 'and the portion 232 may be made of a suitable metal such as aluminum or a metal alloy such as an Al-based alloy.

  Another embodiment of a method for manufacturing a CMUT device having a ratio g / t << 1 at the time of release of the cavity 130 is shown in FIG. The starting point in FIG. 6 is the intermediate structure obtained after steps (a)-(e) in FIG. 4, ie, not explicitly shown in FIG. Steps (a)-(e) shown in FIG. 6 also form part of the manufacturing method shown in FIG.

  After formation of the second electrode 122, the method proceeds as shown in step (a) of FIG. 6 where the second dielectric layer 124 is between the first electrode 112 and the second electrode 122. By forming to a first thickness t1 ′ that exceeds the thickness of the first portion 116 of the sacrificial material, the cavity gap height g is much smaller than the thickness t1 ′ after the formation of the cavity 130, ie g / t1 ′ << 1. Preferably, t1 ′ ≧ 5 g. This occurs during the release of the cavity 130 in step (b), i.e., the formation of the access or via 128 and subsequent sacrificial material formation as described in more detail in steps (h) and (i) of FIG. During the release of the cavity 130 by removal of the first portion 116 and the second portion 116 ', it is ensured that the membrane still exhibits improved membrane robustness during the cavity release process. This is because g << t1 'at the stage of removing the sacrificial material for forming the cavity 130. Furthermore, since the second dielectric layer 124 is deposited, for example, prior to the release of the cavity 130, a membrane with improved flatness is obtained. This is because the presence of the sacrificial material prevents deformation of the first dielectric layer 120 during the formation of the second dielectric layer 124.

  In contrast to the method shown in FIGS. 4 and 5, no etch stop layer is formed on the second dielectric layer 124. Alternatively, the access or via in step (c) by the formation of a further dielectric layer 132 including the access 132 or plug 132 ′ in the via 128 described in more detail with the help of step (j) of FIG. At 128 seals, the membrane thickness is further increased. In one embodiment, the additional dielectric layer 132 is significantly thinner than the second dielectric layer 124. As described above, the additional dielectric layer 132 is formed at least twice the height of the cavity 130 to effectively seal the access or via 128. This again yields a CMUT device where t and w shown in FIG. 1 are approximately equal. This is because the second dielectric layer 124 and the further dielectric layer 132 are typically formed conformally.

  It should be noted at this point that the CMUT device groups formed in accordance with the respective embodiments of FIGS. 4-6 preferably have the same final membrane to ensure that the devices exhibit the same or similar acoustic characteristics. Have a thickness. Accordingly, the second dielectric layer 124 is typically formed to a greater thickness in the embodiment of FIGS. 4 and 5 compared to the embodiment of FIG. This is because, in contrast to the embodiment shown in FIG. 6, the sealing layer or further dielectric layer 132 does not add the final thickness of at least the first portion 22 of the membrane covering the cavity 130. is there.

  The above embodiments have a CMUT device having a cavity radius of, for example, 50 μm or more, in particular 100 μm or more, for example 500 or even 1000 μm, or a cavity radius in the range of 20-500 μm, 30-500 μm, or 30-300 μm. It illustrates that a relatively large CMUT device, such as a device having a high yield, can be created. This is because, by forming the thick second dielectric layer 124 above the second electrode 122 prior to the formation of the cavity 130, excessive deformation of the CMUT membrane, particularly at the periphery of the wafer, was avoided. It is.

  It should be noted at this point that the CMUT device according to the embodiment of the present invention, which can be a ring shape, is, for example, in the case of Patent Document 2 (US Patent Application Publication No. 2013/0069480) (Patent Document). 2 can be easily distinguished from prior art devices in which the second dielectric layer 124 is formed after formation of the cavity 130 (see FIG. 4A-F in particular). This is because the removal of the sacrificial material to form the cavities 130 causes residual contamination to form on the exposed upper surface of the membrane (in the case of the CMUT device of US Pat. Will cause the presence of such contamination).

  In contrast, in the CMUT devices of FIGS. 4 (k), 5 (b), and 6 (c), such contamination is present on the exposed portion of the second dielectric material layer 124, which Thus, the location of such contamination points to the fact that the second dielectric material layer 124 of the membrane was present above the second electrode during removal of the sacrificial material to form the cavity 130. Become. In other words, in the lower region of the membrane, i.e. on the surface of the first dielectric layer 120 or in the region of the membrane facing the cavity 130 and having a thickness equal to the gap height g of the cavity 130. The absence of such contamination indicates that the CMUT device has been obtained according to one embodiment of the manufacturing method of the present invention.

  It should be noted that such contamination can be detected using tunneling electron microscope (TEM) imaging even when each dielectric material of the membrane is the same material, eg, silicon nitride. This is because contaminants appear as a clear depiction between layers of the same material that are subsequently deposited.

  The concept of the embodiment of FIGS. 4-6 is further described with the help of FIG. FIG. 7 again depicts a deformation plot for the first membrane portion 22 as a function of the ratios t / w (x axis) and g / t (y axis) as shown in FIG. The drawn deformation characteristic is modeled using the analytical expression (1). Label 700 is attached to the deformation characteristics of a prior art CMUT device. A first improvement in these properties is obtained by reducing the g / t ratio for CMUT devices manufactured according to the method shown in FIGS. 5 and 6 (this property is labeled 710). Further improvements in these properties are obtained by reducing the g / t and t / w ratios for CMUT devices manufactured according to the method shown in FIG. 4 (this property is labeled 720).

  FIG. 8 shows a thick second dielectric layer on the second electrode when there is no thick second dielectric layer 124 on the second electrode (top) and obtained by the method shown in FIG. For 124 (shown below), an image obtained using an optical microscope of a wafer having a plurality of circular CMUT devices is shown. The arrows in the plane above identify the optical ring in the membrane of the prior art CMUT device, which points to significant membrane deformation. The absence of the optical ring in the figure below illustrates the improved robustness of the CMUT device membrane according to the embodiment to such deformation.

  FIG. 9 represents a typical capacitance-voltage (CV) curve for a CMUT device. When an increasing bias voltage is applied across the first electrode 112 and the second electrode 122, the electrical force causes the membrane to collapse toward the first electrode 112 at a certain critical voltage. Become. This voltage is also known as the collapse voltage. As the voltage is lowered from the collapse voltage, the membrane will bounce back (snap back) to its original position at the snapback voltage. The CMUT device can be operated in collapsed mode, i.e., mode in which the membrane is in its collapsed state. For this purpose, a bias voltage exceeding the collapse voltage can be permanently applied to the first electrode 112 and the second electrode 122.

  The amount of membrane deformation h as shown in FIG. 2 has a significant effect on the magnitude of the collapse voltage and the acoustic characteristics of the CMUT device. Thus, the collapse voltage mapping of the CMUT device across the wafer provides a good indication of the stress insensitivity of the CMUT device during cavity formation. This is because the collapse voltage distribution across the wafer should illustrate such small changes in the case of such stress insensitivity.

  FIG. 10 is a contour plot of the collapse voltage Vc across the wafer in the upper view of FIG. 8 where each cavity 130 is formed in a CMUT device group across the wafer without the second dielectric layer 124 being sufficiently thick. Is drawn. At the center of the wafer, a typical value of Vc of approximately 90V was obtained, but at the periphery of the wafer, this voltage increased to over 150V, i.e. the wafer was at the collapse voltage Vc of the CMUT device across the wafer. A variation exceeding 65% is shown. This clearly indicates the out-of-plane bending of the membrane as shown in FIG. 2 at the wafer periphery, and a higher bias voltage is required to reverse this deformation and place the membrane in collapsed mode. .

  FIG. 11 shows a contour plot of the collapse voltage Vc across two wafers manufactured according to different embodiments of the present invention. The upper contour plot shows a wafer manufactured according to the method of FIG. 6, and the lower contour plot shows a wafer manufactured according to the method of FIG. As is apparent, only very small variations (less than 7% variation) exist between the collapse voltage Vc of the CMUT device at the center of the wafer and the collapse voltage Vc of the CMUT device at the wafer periphery.

  The upper diagram of FIG. 12 shows an arbitrarily selected CMUT device from position (−4,0) to (0, + 4) on the wafer manufactured according to the method of FIG. 9 shows a contour map of the output pressure of a linear array of nine CMUT devices including the device. Output pressure is an important indicator that indicates acoustic performance. The output pressure was generated by RF excitation of the CMUT device by changing the bias voltage (x axis) from −150 V to 150 V and changing the pulse length (y axis) from 20 ns to 140 ns. The lower diagram shows a histogram of the output pressure of each of these devices as a function of their position on the wafer. For all devices in this array, approximately equal contour plots were obtained with less than 2% variation in their output pressure. This indicates excellent uniformity in acoustic performance of (circular) CMUT devices on wafers manufactured according to embodiments of the present invention.

  It should be noted at this point that although not shown in various embodiments, it should be understood that a CMUT device according to a device on a wafer manufactured in accordance with the embodiment has additional circuit elements. These additional circuit elements may be integrated on the substrate 110, or may be provided on a separate substrate and a CMUT device from a wafer manufactured according to embodiments of the present invention. May be integrated into a single package with one or more of the above. Such additional circuitry may, for example, control one or more CMUT devices and / or one as described above, eg, to control transmission and / or reception modes of one or more CMUT devices. For example, an IC such as an ASIC for processing a signal generated by the above CMUT device may be used.

  One or more CMUT devices according to embodiments of the present invention can be advantageously incorporated into sensing devices such as pressure sensing devices, in particular medical imaging devices such as ultrasound imaging devices, and are based on CMUTs. The integration of the sensing elements can significantly improve the imaging resolution of the device (for example, small objects such as abnormalities such as tumors in the body of the subject being examined, eg, a mammalian body such as a human body). Improve detectability). In one embodiment, such an apparatus has a plurality of CMUT devices according to an embodiment of the present invention arranged in a matrix in which each CMUT device is individually addressable. Such an apparatus may have, for example, hundreds or thousands of such individually addressable CMUT devices.

  It should be noted that the above-described embodiments are illustrative rather than limiting, and those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The term “comprising” does not exclude the presence of elements or steps other than those listed in a claim. The term “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by hardware having several different elements. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims (15)

  A method of manufacturing a capacitive micromachined ultrasonic transducer (CMUT) device having a first electrode on a substrate and a second electrode embedded in an electrically insulating membrane, wherein the first electrode and the membrane Separated by a cavity formed by removal of the sacrificial material between the first electrode and the membrane, the method comprising: a membrane part on the second electrode; and a side of the sacrificial material from the membrane part. And forming a further membrane portion extending toward the substrate along a thickness of each of the membrane portion and the further membrane portion before the cavity is formed. A method that is at least five times greater than the thickness of.   The method of claim 1, wherein the thickness of the additional membrane portion exceeds the thickness of the membrane portion.   The method of claim 1 or 2, wherein the thickness of the membrane portion is at least 10 times the thickness of the sacrificial material.   The step of removing the sacrificial material comprises creating access to the sacrificial material, the method further comprising sealing the access after forming the cavity, and the step of sealing includes The method according to claim 1, comprising forming a sealing part on the membrane part and the further membrane part. Prior to the sealing step, forming an etch stop layer on the membrane portion;
Removing the sealing portion from the membrane portion by etching, and removing the etching that ends on the etching stop layer;
Removing the etch stop layer after the step of etching away;
The method of claim 4 further comprising:   6. The method of claim 5, wherein the etch stop layer is dimensioned such that upon completion of the etching away step, the seal ring remains on the additional membrane portion. The membrane is at least partially
Forming a first dielectric material layer over the sacrificial material;
Forming a second electrode on the first dielectric material layer, and forming the membrane portion on the second electrode, the membrane portion forming part of a second dielectric material layer;
The method according to claim 1, wherein the method is formed by:   A capacitive micromachined ultrasonic transducer (CMUT) device having a first electrode on a substrate and a second electrode embedded in an electrically insulating membrane, wherein the first electrode and the membrane are separated by a cavity. The membrane has a single layer membrane portion on the second electrode and a further membrane portion extending from the single layer membrane portion along the side of the cavity toward the substrate, The CMUT device, wherein the one-layer membrane portion and the further membrane portion each have a thickness that is at least five times greater than the height of the cavity.   9. The CMUT device of claim 8, wherein the single layer membrane portion and the further membrane portion each have a thickness that is at least 10 times greater than the height of the cavity.   10. The CMUT device according to claim 8 or 9, wherein the thickness of the further membrane part exceeds the thickness of the single layer membrane part.   11. The CMUT of claim 10, further comprising a ring of electrically insulating material on the further membrane portion, wherein the single layer membrane portion is at least partially exposed inside the ring. device.   The CMUT device according to any one of claims 8 to 10, further comprising a protruding portion of a sealing material extending from the cavity.   The CMUT device according to claim 12, wherein the sealing material is a metal such as aluminum or a metal alloy such as an aluminum-based alloy.   The CMUT device according to any one of claims 8 to 13, wherein the CMUT device is obtained by the method according to any one of claims 1 to 7.   An apparatus comprising the CMUT device according to claim 8.

Images