JP6398288B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Ferroelectrics have the property that the electric polarization once generated when an electric field is applied remains even if the electric field is no longer applied, and the direction of polarization reverses when an electric field of a certain strength is applied in the opposite direction. Have.

  Paying attention to the polarization inversion of the ferroelectric, a ferroelectric nonvolatile memory (hereinafter referred to as FeRAM) in which the insulating layer of the information storage capacitor of the memory cell is formed of a ferroelectric has been developed. .

  The peripheral circuit of the ferroelectric nonvolatile memory is provided with a capacitor in which an insulating layer is formed from the same ferroelectric film as the information storage capacitor. However, a capacitor in a peripheral circuit in which an insulating layer is formed from a ferroelectric film has a problem of poor leakage current characteristics.

  Therefore, a technique has been proposed for improving the leakage current characteristics of the peripheral circuit capacitor by heat-treating the ferroelectric film in the peripheral circuit capacitor portion without covering with a protective film to change the composition (for example, patents). Reference 1).

  Regarding the leakage current of the ferroelectric capacitor, the Pt electrode film is made amorphous by reacting with the Zr thin film, and the BST (Barium Strontium Titanate) thin film that becomes the insulating layer of the ferroelectric capacitor is formed on the Pt electrode film. Techniques for depositing have been reported. By depositing the BST thin film on the amorphous Pt electrode film, the grain size of the BST thin film is reduced and the leakage current of the ferroelectric capacitor is reduced (for example, Patent Document 2).

  Regarding a method for manufacturing a ferroelectric nonvolatile memory, a technique has been reported in which a resist in a cylinder groove whose inner wall is covered with a Ru film serving as a lower electrode is removed with a downflow ashing device (for example, Patent Documents). 3).

Japanese Patent Laid-Open No. 2003-282832 JP 2002-110935 JP JP 2005-93587 A Japanese Patent Laid-Open No. 2001-36027 JP 2006-245383 A Japanese Patent Laid-Open No. 2003-142659

  As described above, it is possible to improve the leakage current characteristics of the capacitor in the peripheral circuit to some extent by changing the composition of the ferroelectric film in the portion that becomes the capacitor in the peripheral circuit by heat treatment, but it is not sufficient. .

  Therefore, an object of the present invention is to solve such a problem.

  In order to solve the above problem, according to one aspect of the present apparatus, a first lower electrode provided on a first surface on a semiconductor substrate and a ferroelectric material provided on the first lower electrode are included. A first capacitor having a first ferroelectric layer and a first upper electrode provided on the first ferroelectric layer; a second lower electrode provided on the first surface; and the second lower electrode. A second ferroelectric layer provided on the electrode and having a lower degree of orientation than the first ferroelectric layer and including the ferroelectric material; a second upper electrode provided on the second ferroelectric layer; There is provided a semiconductor device comprising: a second capacitor having:

  According to the disclosed semiconductor device, the leakage current of the capacitor in which the insulating layer is formed of the same ferroelectric material as that of the cell capacitor can be significantly reduced.

FIG. 1 is an example of a device in which the semiconductor device of Embodiment 1 is provided. FIG. 2 is a partial cross-sectional view of the semiconductor device of First Embodiment. FIG. 3 is a partial cross-sectional view of the cell capacitor and the smoothing capacitor. FIG. 4 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 5 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 7 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 8 is a diagram illustrating an example of the orientation rate of the PZT film formed in each of the first capacitor region and the second capacitor region. FIG. 9 is a diagram illustrating an example of the leakage current of the monitoring capacitor formed in each of the first capacitor region and the second capacitor region. FIG. 10 is a diagram showing the relationship between the orientation rate of the ferroelectric film and the leakage current of the monitoring capacitor. FIG. 11 is a partial cross-sectional view of the first capacitor and the second capacitor of the second embodiment. FIG. 12 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment. FIG. 13 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment. FIG. 14 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment. FIG. 15 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment. FIG. 16 is a diagram illustrating an example of the orientation rate of the PZT film formed in each of the first capacitor region and the second capacitor region of the second embodiment. FIG. 17 is a diagram illustrating an example of the leakage current of the monitoring capacitor formed in each of the first capacitor region and the second capacitor region of the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. Note that, even if the drawings are different, corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 1)
(1) Structure FIG. 1 is an example of a device 4 provided with the semiconductor device 2 of the first embodiment. The device 4 in FIG. 1 is an IC (Integrated Circuit) card.

  As shown in FIG. 1, the device 4 according to the first embodiment includes a semiconductor device 2 and a loop antenna 6 that transmits and receives electromagnetic waves. The semiconductor device 2 includes a full-wave rectifier circuit 8 having an input terminal connected to the loop antenna 6 and a smoothing capacitor 10 to which an output terminal of the full-wave rectifier circuit 8 is connected. The semiconductor device 2 further includes a ferroelectric nonvolatile memory 12 (that is, FeRAM) to which power is supplied from the smoothing capacitor 10 and a processing unit 14 to which power is supplied from the smoothing capacitor 10.

  The processing unit 14 extracts information from the electromagnetic wave incident on the loop antenna 6 and processes it. The processing unit 14 reads data necessary for processing the extracted information from the FeRAM 12 and records information being processed and / or processing results in the FeRAM 12. The processing unit 14 further radiates an electromagnetic wave corresponding to the processing result from the loop antenna 6. Transmission / reception of signals between the loop antenna 6 and the processing unit 14 is performed via a pair of signal lines 16.

  FIG. 2 is a partial cross-sectional view of the semiconductor device 2 of the first embodiment.

  FIG. 2 shows the memory cell 18 of the FeRAM 12, the smoothing capacitor 10, the transistor 20 of the processing unit 14, and the wiring unit 22. The memory cell 18 includes a selection transistor 24 and a cell capacitor 26. The gate of the selection transistor 24 is connected to the selected word line 28.

  One of the source / drain regions of the selection transistor 24 is connected to the bit line 32 by, for example, a via 30a. The other of the source / drain regions of the selection transistor 24 is connected to the upper electrode of the cell capacitor 26 by, for example, a via 30b and a wiring 34a. The lower electrode of the cell capacitor 26 is connected to the plate line 36 by, for example, a via.

  The transistor 20 and the selection transistor 24 of the processing unit 14 are, for example, MOS (Metal-Oxide-Semiconductor) transistors formed on a semiconductor substrate 38 (for example, a Si substrate).

  The transistor 20 and the selection transistor 24 of the processing unit 14 are covered with the first interlayer insulating film 40a. The first interlayer insulating film 40a is covered with a first protective film 42a, a second protective film 42b, and a third protective film 42c. A cell capacitor capacitor 26 is provided on the first protective film 42a. The smoothing capacitor 10 is provided on the second protective film 42b. The third protective film 42 c covers the cell capacitor 26 and the smoothing capacitor 10. Between the first protective film 42a to the third protective film 42c and the first interlayer insulating film 40a, an antioxidant film (not shown) such as vias 30a and 30b is provided.

  A second interlayer insulating film 40b, a fourth protective film 42d, and a third interlayer insulating film 40c are provided in this order on the third protective film 42c. The wiring part 22 is provided on the third interlayer insulating film 40c.

  In the example shown in FIG. 2, the first protective film 42a and the second protective film 42b are separate protective films. However, the first protective film 42a and the second protective film 42b may be a single protective film. That is, the first protective film 42a and the second protective film 42b may be connected. The first protective film 42a to the fourth protective film 42d are, for example, aluminum oxide films (hereinafter referred to as ALO films).

  The wiring part 22 has at least one wiring layer 44. The wiring layer 44 includes wirings 34b (including electrode pads) that connect elements (for example, the selection transistor 24, the transistor 20 of the processing unit 14, and the like) provided on the semiconductor substrate 38 to each other. The wiring layer 44 further includes a fourth interlayer insulating film 40d covering the wiring 34b and a via 30c provided in the fourth interlayer insulating film 40d. The surface of the wiring part 22 is covered with a passivation film (for example, polyimide film) 46. The wiring 34b of the wiring unit 22 is connected to the transistor 20 of the processing unit 14 by a via 30d provided in the first interlayer insulating film 40a and a via 30e provided in the second interlayer insulating film 40b. The first interlayer insulating film 40a to the fourth interlayer insulating film 40d are, for example, silicon oxide films (hereinafter referred to as SIO films).

  The first protective film 42a and the second protective film 42b are formed by dry etching from one insulating film (for example, an ALO film). Alternatively, the first protective film 42a and the second protective film 42b are one insulating film. Therefore, the surfaces of the first protective film 42a and the second protective film 42b are on the same surface (hereinafter referred to as the first surface).

  FIG. 3 is a partial cross-sectional view of the cell capacitor 26 and the smoothing capacitor 10. On the left side of FIG. 3, a partial cross-sectional view of the cell capacitor 26 in which the region A of FIG. 2 is enlarged is shown. 3 is a partial cross-sectional view of the smoothing capacitor 10 in which the region B in FIG. 2 is enlarged.

  The cell capacitor 26 is a capacitor provided in the memory cell of the FeRAM 12 (see FIG. 1). As shown in FIG. 3, the cell capacitor 26 is provided on the first lower electrode 50a, the first ferroelectric layer 52a provided on the first lower electrode 50a, and the first ferroelectric layer 52a. A capacitor having a first upper electrode 54a (hereinafter referred to as a first capacitor 56a). The first lower electrode 50 a is a conductive layer provided on the first surface 48 on the semiconductor substrate 38. The first ferroelectric layer 52a is an insulating layer formed of a ferroelectric material (for example, lead zirconate titanate (PZT)) (that is, including a ferroelectric material). The first upper electrode 54a is a conductive layer provided on the first ferroelectric layer 52a.

  The smoothing capacitor 10 includes a second lower electrode 50b, a second ferroelectric layer 52b provided on the second lower electrode 50b, and a second upper electrode 54b provided on the second ferroelectric layer 52b. Capacitor (hereinafter referred to as second capacitor 56b). The second lower electrode 50 b is a conductive layer provided on the first surface 48. The second ferroelectric layer 52b is formed of the ferroelectric material of the first ferroelectric layer 52a (that is, includes the ferroelectric material of the first ferroelectric layer 52a) than the first ferroelectric layer 52a. It is a ferroelectric layer (insulating layer) with a low degree of orientation. The second upper electrode 54b is a conductive layer provided on the second ferroelectric layer 52b.

  The first lower electrode 50a and the second lower electrode 50b are, for example, platinum films (hereinafter referred to as Pt films) oriented in the [111] axis direction. The first ferroelectric layer 52a is a PZT layer that takes over the orientation of the first lower electrode 50a and is oriented in the [111] axial direction, for example.

  As described above, the degree of orientation of the second ferroelectric layer 52b is lower than the degree of orientation of the first ferroelectric layer 52a. In other words, the degree of orientation of the first ferroelectric layer 52a is higher than the degree of orientation of the second ferroelectric layer 52b. Therefore, in the first ferroelectric layer 52a, the proportion of microcrystals whose specific crystal axis (for example, [111] axis) is oriented in the direction perpendicular to the substrate 38 is higher than that in the second ferroelectric layer 52b. Therefore, as shown in the left diagram of FIG. 3, the crystal grain boundaries 58 extend in a direction perpendicular to the substrate. On the other hand, in the second ferroelectric layer 52b having a low degree of orientation, the crystal grain boundary 60 is bent in a complicated manner as shown in the right diagram of FIG.

  As will be described later, the leakage current of the ferroelectric layer mainly flows through the crystal grain boundaries 58 and 60. Therefore, the leakage current path in the second ferroelectric layer 52b is longer than the leakage current path in the first ferroelectric layer 52a. For this reason, the leakage current of the second capacitor 56b is smaller than the leakage current of the first capacitor 56a. Note that a gap may occur in the crystal grain boundary 58 of the first ferroelectric layer 52a as shown in the left diagram of FIG.

  In the first embodiment, the second capacitor 56b is used as a smoothing capacitor. When the orientation degree of the ferroelectric layer is lowered, the leakage current is reduced, but the hysteresis characteristic is deteriorated. However, since the second capacitor 56b (for example, a smoothing capacitor) does not use the hysteresis characteristic of the ferroelectric material, there is no problem even if the orientation degree is lowered.

The insulating layer of the second capacitor 56b is formed of a ferroelectric material having a high dielectric constant. For this reason, the second capacitor 56b can be made smaller than a MIM (Metal Insulator Metal) capacitor in which an insulating layer is formed of an SiO ₂ film or the like or a polycapacitor in which an insulating layer is formed of polycrystalline Si.

  By the way, a leak current larger than that of the second capacitor 56b flows through the first capacitor 56a. However, since the first capacitor 56a is a cell capacitor, there is no problem even if the leakage current is large to some extent. This is because the voltage applied to the cell capacitor is intermittent and the duration is short.

  The leakage current of the smoothing capacitor increases as the ferroelectric layer becomes thinner. In particular, when the ferroelectric layer is 120 nm or less, the leakage current of the smoothing capacitor increases significantly. Therefore, when the thickness of the second ferroelectric layer 52b (and the first ferroelectric layer 52a) is 120 nm or less, the first embodiment is extremely effective. The first embodiment is more effective when the thickness of the second ferroelectric layer 52b (and the first ferroelectric layer 52a) is 90 nm or less.

  However, when the second ferroelectric layer 52b becomes thinner than 10 nm, the problem of the leakage current of the second capacitor 56b becomes apparent again. Therefore, the thickness of the second ferroelectric layer 52b is preferably 10 nm or more. More preferably, the thickness of the second ferroelectric layer 52b is 20 nm or more.

-About the degree of orientation of the thin film-
The orientation degree of the thin film is the maximum value of the orientation degree calculated for each crystal axis direction.

The degree of orientation in the [h ₀ k ₀ l ₀ ] axial direction is calculated from the diffraction peak intensity I (hkl) of the diffraction pattern obtained by 2θ-θ X-ray diffraction method (hereinafter referred to as X-ray diffraction method) according to the Lotgering equation. Calculated.

Specifically, for example, first, the P value is calculated by the equation (1). Next, the F value is calculated by substituting the calculated P value into equation (2). The calculated F value is the degree of orientation in the [h ₀ k ₀ l ₀ ] axial direction.

Here, I (hkl) is the diffraction peak intensity of the (hkl) plane. ΣI (hkl) is the sum of all diffraction peak intensities. ΣI (h ₀ k ₀ l ₀ ) is the total sum of diffraction peak intensities of planes equivalent to the (h ₀ k ₀ l ₀ ) plane. P ₀ is the P value in the [h ₀ k ₀ l ₀ ] axial direction of the non-oriented sample.

  The maximum value among the calculated F values is referred to as the degree of orientation of the thin film. The orientation direction of the thin film is an axial direction in which the F value is maximized.

  The magnitude relationship of the degree of orientation can also be determined by cross-sectional observation of a thin film with a transmission electron microscope (hereinafter referred to as TEM).

  First, a thin film (for example, a PZT film) is cut together with the substrate to expose a cross section of the thin film. Next, the sample is thinned until an electron beam passes through to prepare a cross-sectional sample. Then, the produced cross-sectional sample is observed with TEM, and the electron diffraction pattern of each microcrystal contained in the thin film is measured. Based on this electron diffraction pattern, it is determined which direction the crystal axis of each microcrystal is oriented with respect to the substrate. Further, based on the determination result, the ratio of the microcrystals included in the cross-sectional sample whose specific crystal axis (eg, [111] axis) is oriented in the direction perpendicular to the substrate is calculated.

  There is a strong positive correlation between this ratio (hereinafter referred to as orientation by TEM observation) and the degree of orientation. Therefore, the magnitude relationship of the orientation degree in a plurality of thin films can be determined by TEM cross-sectional observation. The orientation by TEM observation is preferably a ratio weighted by the size of the microcrystal.

(2) Manufacturing Method FIGS. 4 to 7 are process cross-sectional views illustrating a method for manufacturing the semiconductor device 2.

(2-1) Formation of cell transistors and the like (see FIG. 4A)
First, the elements included in the full-wave rectifier circuit 8, the FeRAM 12, and the processing unit 14 are formed on the semiconductor substrate 38. Specifically, the diode of the full-wave rectifier circuit 8, the selection transistor 24, the transistor 20 of the processing unit 14, and the like are formed on the semiconductor substrate 38.

  For example, a silicon oxide film (hereinafter referred to as a TEOS film) generated from plasma of a mixed gas of TEOS (Tetra-Ethyl-Ortho-Silicate) and oxygen is deposited on the formed element. Next, the surface of the formed TEOS film is planarized by chemical mechanical polishing (hereinafter referred to as CMP) to form a first interlayer insulating film 40a as shown in FIG. .

  Next, vias 30a, 30b and 30d reaching the respective elements formed in the semiconductor substrate 38 are formed in the first interlayer insulating film 40a. A silicon oxynitride film (hereinafter referred to as a SION film) is deposited on the formed vias 30a, 30b, 30d and the first interlayer insulating film 40a, and a TEOS film is further deposited on the SION film to prevent oxidation. A film 62 is formed. The antioxidant film 62 prevents oxidation of the vias 30a, 30b, and 30d due to heat treatment (that is, recovery annealing) after RIE (Reactive Ion Etching) described later.

(2-2) Formation of lower electrode film and the like (see FIG. 4B)
For example, an ALO film (not shown) having a thickness of 10 nm to 30 nm is formed on the antioxidant film 62 by a DC (Direct Current) sputtering method. Further, as shown in FIG. 4B, a conductive lower electrode film 64 (for example, a Pt film having a thickness of 50 to 150 nm (preferably 100 nm)) is formed on the surface (first surface) of the ALO film. It is formed by a sputtering method. Note that thin films deposited by sputtering (lower electrode film 64, ferroelectric film described later, and upper electrode film described later) are amorphous.

  As described above, the lower electrode film 64 is formed on the first surface (the surface of the ALO film) on the semiconductor substrate 38. In addition, description "(circle)-(triangle | delta)" which shows numerical ranges, such as "10nm-30nm," shall represent "(circle) or more and below or less (it is the same).

(2-3) Treatment of the surface of the lower electrode film (see FIGS. 5A to 6A)
-Formation of resist pattern (see Fig. 5 (a))-
A region 66a of the lower electrode film 64 corresponding to the first capacitor 56a (hereinafter referred to as the first capacitor region) is covered, and a region 66b of the lower electrode film 64 corresponding to the second capacitor 56b (hereinafter referred to as the second capacitor region). A resist film 68 that exposes the upper electrode film 64 is formed on the lower electrode film 64.

-Plasma exposure (see Fig. 5 (b))-
Next, the second capacitor region 66b is exposed through the resist film 68 to, for example, plasma 70 generated from a mixed gas of oxygen and nitrogen by a downflow type ashing device (plasma generating device) (see FIG. 5B). ).

  The nitrogen concentration of the mixed gas converted into the flow rate is, for example, 5 to 15% (preferably 10%). The input power is, for example, 0.5 KW to 1.5 kW (preferably 1 kW).

  As a result, only the second capacitor region 66 b is exposed to the plasma 70. Thereby, the surface of the second capacitor region 66b is damaged and roughened (that is, the surface morphology is deteriorated).

  In the downflow type ashing apparatus, a substrate is disposed outside the plasma generation chamber. For this reason, the resist film is mainly removed by neutral active species. However, the resist film is also exposed to plasma to some extent. The surface of the second capacitor region 66b is roughened by this plasma.

  In an ashing apparatus in which a substrate is disposed in a plasma generation chamber, the resist film 68 is exposed to a large amount of plasma and rapidly removed. As a result, the first capacitor region 66a is also exposed to plasma, and the surface becomes rough.

  Therefore, it is preferable that the plasma exposure of the second capacitor region 66b is performed by a downflow type ashing apparatus. The plasma exposure of the second capacitor region 66b may be performed by plasma generated by an ECR (Electron Cyclotron Resonance) device, an ICP (Inductively Coupled Plasma) device, a helicon wave plasma source, or the like.

  Even if a downflow type ashing apparatus is used, when the substrate temperature exceeds 100 ° C., the resist film 68 is rapidly removed. As a result, the first capacitor region 66a is exposed to plasma, and the surface becomes rough. Therefore, the substrate temperature is preferably 100 ° C. or lower (more specifically, 20 ° C. to 100 ° C.).

-Stripping of resist film (see Fig. 6 (a))-
Next, the resist film 68 is stripped with a resist stripping solution (for example, an organic solvent such as acetone or a remover). When the resist film 68 is dry peeled by an ashing device, the surface of the first capacitor region 66a is also roughened. Therefore, wet stripping with a resist stripping solution is preferable.

  Through the above steps, the second capacitor region 66 b of the lower electrode film 64 is exposed to the plasma 70.

(2-4) Deposition of ferroelectric film (see FIG. 6B)
A ferroelectric film 72 (for example, PZT film) having a thickness of 35 nm to 105 nm (preferably 70 nm) is deposited on the lower electrode film 64 by, for example, RF (Radio Frequency) sputtering using Ar gas. On the ferroelectric film 72, a ferroelectric film (for example, a PZT film, not shown) having a thickness of 5 nm to 15 nm (preferably 10 nm) may be further deposited.

(2-5) Crystallization of ferroelectric film (see FIG. 7A)
The lower electrode film 64 and the ferroelectric film 72 are heat-treated at, for example, 550 ° C. to 650 ° C. (preferably 600 ° C.) for 60 seconds to 120 seconds (preferably 90 seconds) by an RTA (Rapid Thermal Anneal) method. By this heat treatment, the lower electrode film 64 (for example, Pt film) is self-oriented in the [111] axis direction, for example. Further, the ferroelectric film 72 is crystallized.

  On the first capacitor region 66a, a first ferroelectric layer 52a (for example, a PZT film oriented in the [111] axis direction) oriented by taking over the orientation of the lower electrode film 64 is formed. On the other hand, as shown in the right diagram of FIG. 3, a second ferroelectric layer 52b having a lower degree of orientation than the first ferroelectric layer 52a is formed on the second capacitor region 66b. This is because it is difficult to crystallize the ferroelectric film 72 while the lower electrode film 64 and the crystal lattice are continuous due to the surface roughness of the lower electrode film 64 on the second capacitor region 66b.

  In the first embodiment, the lower electrode film 64 and the ferroelectric film 72 are crystallized by one heat treatment. However, before the ferroelectric film 72 is deposited, the lower electrode film 64 may be crystallized by heat treatment in advance, and the ferroelectric film 72 may be deposited on the lower electrode film 64. In this case, after the ferroelectric film 72 is deposited, the lower electrode film 64 and the ferroelectric film 72 are heat-treated again.

(2-6) Formation of upper electrode film (see FIG. 7B)
Next, for example, by DC sputtering using iridium as a target and a mixed gas of argon and oxygen as a discharge gas, a thickness of 15 nm to 35 nm (preferably 25 nm) is formed on the ferroelectric film 72 as shown in FIG. ) Conductive upper electrode film 74 (for example, an iridium oxide film (hereinafter referred to as an IrOx film)). Thereafter, the upper electrode film 74 is heat-treated at 700 ° C. to 750 ° C. (preferably 725 ° C.) for 60 seconds to 180 seconds (preferably 120 seconds), for example, by the RTA method.

(2-7) Process after upper electrode film formation-Etching of ferroelectric film, etc.-
Thereafter, for example, the RIE using the resist film as a mask is repeated, and the upper electrode film 74, the ferroelectric film 72, and the lower electrode film 64 are etched. As a result, the first capacitor 56a (see FIG. 2) is formed in the first capacitor region 66a, and the second capacitor 56b (see FIG. 2) is formed in the second capacitor region 66b.

  In the last RIE, the ALO film on the antioxidant film 62 is etched together with the lower electrode film 64 to become the first protective film 42a and the second protective film 42b. However, the ALO film may not be etched. In that case, the first protective film 42a and the second protective film 42b become one connected protective film.

-Capacitor wiring and wiring section formation-
Next, a third protective film 42c (for example, an ALO film) that covers the first capacitor 56a and the second capacitor 56b is formed (see FIG. 2). An insulating film (for example, a TEOS film) is formed on the third protective film 42c. The insulating film is planarized by CMP to form a second interlayer insulating film 40b.

  A fourth protective film 42d (for example, an ALO film) is formed on the second interlayer insulating film 40b, and a third interlayer insulating film 40c (for example, a TEOS film) is formed on the fourth protective film 42d.

  Next, contact holes reaching the electrodes (upper electrode and lower electrode) of the first capacitor 56a and the second capacitor 56b are formed in the third interlayer insulating film 40c, the fourth protective film 42d, and the second interlayer insulating film 40b. . Further, contact holes reaching vias 30a, 30b, 30e formed in the first interlayer insulating film 40a are formed in the third interlayer insulating film 40c, the fourth protective film 42d, and the second interlayer insulating film 40b. Thereafter, the ferroelectric film 72 is subjected to heat treatment (recovery annealing) in an oxygen atmosphere in order to recover damage caused to the ferroelectric film 72 by RIE of the ferroelectric film 72 and the like.

  Next, the contact hole is filled with a conductive material (for example, tungsten) to form plugs 30a, 30b, and 30e. Thereafter, the bit line 32, the wiring 34a for connecting the cell capacitor 26 and the selection transistor 24, and the plate line 36 are formed of aluminum on the third interlayer insulating film 40c. At this time, the first-layer wiring of the wiring portion 22 is formed together with the bit line 32 and the like. Next, an interlayer insulating film covering the bit line 32 and the like and a plug connected to the bit line 32 and the like are formed.

  Thereafter, the interlayer insulating film 40d, the plug 30c, and the wiring 34b (including the pad-like electrode) are repeatedly formed to form the second and subsequent wiring layers 44. Thereby, the wiring part 22 is completed. Finally, the surface of the wiring part 22 is covered with, for example, a passivation film 46.

(3) Degree of Orientation of Ferroelectric Film and Leakage Current FIG. 8 is a diagram showing an example of the following orientation rate of the PZT film formed in each of the first capacitor region 66a and the second capacitor region 66b. The horizontal axis is the name of the capacitor region.

  The vertical axis represents the P value in the [111] axis direction (hereinafter referred to as the orientation ratio). The P value in FIG. 8 indicates the peak intensity I (222) of the X-ray diffraction pattern corresponding to the (222) plane of the PZT film, the peak intensity I (222) of the X-ray diffraction pattern corresponding to the (222) plane, and ( The value divided by the sum of the peak intensity I (101) of the X-ray diffraction pattern corresponding to the (101) plane and the peak intensity I (100) of the X-ray diffraction corresponding to the (100) plane (= I (222) / { I (222) + I (101) + I (100)}) (the same applies to the horizontal axis in FIG. 10 and the vertical axis in FIG. 16). The (222) plane is equivalent to the (111) plane.

  The measured lower electrode film 64 of the PZT film is a Pt film. The deposition conditions and heat treatment conditions of the lower electrode film 64 and the PZT film are the preferable conditions (conditions described in parentheses) described in “(2) Manufacturing method”. The X-ray source used for the X-ray diffraction measurement is Cu.

  As shown in FIG. 8, the orientation rate of the PZT film formed in the first capacitor region 66a is 0.9 or more. On the other hand, the orientation rate of the PZT film formed in the second capacitor region 66b is 0.3 or less. Accordingly, the degree of orientation of the second ferroelectric layer 52b formed in the second capacitor region 66b is the first ferroelectric formed in the first capacitor region 66a, as is apparent from the equations (1) and (2). It becomes lower than the orientation degree of the body layer 52a.

  FIG. 9 is a diagram illustrating an example of the leakage current of the monitoring capacitor formed in each of the first capacitor region 66a and the second capacitor region 66b. The horizontal axis is the name of each area. The vertical axis represents the leakage current. The voltage applied to the monitoring capacitor is 3V.

The monitoring capacitor was formed by depositing the upper electrode on the PZT film on the lower electrode. The conditions for forming the PZT film are the same as those of the sample of FIG. The electrode area of the monitoring capacitor is 2500 μm ² . As shown in FIG. 9, the leakage current of the second capacitor region 66b is 1/10 or less of the leakage current of the first capacitor region 66a. Therefore, the leakage current of the second capacitor 56b is much smaller than the leakage current of the first capacitor 56a.

  As a leakage current path, a crystal grain boundary and the inside of the crystal are considered. However, it is difficult to determine whether the leakage current passes through the crystal grain boundary or inside the crystal from the result of measuring the current-voltage characteristic of the monitoring capacitor.

  Incidentally, the decrease in the degree of orientation of the ferroelectric film indicates the granulation of the microcrystals forming the ferroelectric film. When the crystallites of the ferroelectric film are granulated, the grain boundaries of the microcrystals are bent in a complicated manner, and as a result, the path of the leak current flowing through the crystal grain boundaries becomes long.

  In the second capacitor region 66b, the leakage current decreases due to a decrease in the degree of orientation of the ferroelectric film. Therefore, in the second capacitor region 66b, it is considered that the path of the leak current flowing through the crystal grain boundary becomes longer due to the microcrystal of the ferroelectric film being granulated, and as a result, the leak current is reduced. Thereby, it can be seen that the leakage current mainly flows through the grain boundary.

  FIG. 10 is a diagram showing the relationship between the orientation ratio (P value) of the PZT film and the leakage current of the monitoring capacitor. The horizontal axis represents the orientation rate in the [222] axis direction of the PZT film. The vertical axis represents the leakage current.

  As shown in FIG. 10, when the orientation ratio is 0.2 to 0.5, the leakage current of the capacitor is remarkably reduced. Therefore, when the ferroelectric layer (second ferroelectric layer 52b) of the second capacitor 56b is a PZT film, the orientation ratio is preferably 0.2 to 0.5. More preferably, the orientation ratio of the second ferroelectric layer 52b is 0.2 to 0.4. Most preferably, the orientation ratio of the second ferroelectric layer 52b is 0.2 to 0.3.

  On the other hand, when the ferroelectric layer (first ferroelectric layer 52a) of the first capacitor 56a is a PZT film, the orientation ratio is preferably 0.7 or more. When the orientation ratio is within this range, the hysteresis of the first capacitor 56a increases, and the memory characteristics of the first capacitor 56a are improved. More preferably, the orientation ratio of the first ferroelectric layer 52a is 0.8 or more. Most preferably, the orientation ratio of the first ferroelectric layer 52a is 0.9 or more.

(Embodiment 2)
The second embodiment is similar to the first embodiment. Therefore, description of portions common to Embodiment 1 is omitted or simplified.

(1) Structure The semiconductor device 102 according to the second embodiment is provided in, for example, an IC (Integrated Circuit) card, as with the semiconductor device 2 according to the first embodiment (see FIG. 1).

  The cross-sectional structure of the semiconductor device 102 of the second embodiment is substantially the same as the cross-sectional structure of the semiconductor device 2 of the first embodiment described with reference to FIG.

  FIG. 11 is a partial cross-sectional view of first capacitor 156a and second capacitor 156b of the second embodiment. On the left side of FIG. 11, a partial cross-sectional view of the first capacitor 156a in which the region A of FIG. 2 is enlarged is shown. On the right side of FIG. 11, a partial cross-sectional view of the second capacitor 156b in which the region B of FIG. 2 is enlarged is shown.

  As shown in the left diagram of FIG. 11, the structure of the first capacitor 156a is substantially the same as the first capacitor 56a (see FIG. 3) of the first embodiment. On the other hand, unlike the first embodiment, the second capacitor 156b has a thin insulating film 90 (for example, disposed between the second lower electrode 50b and the second ferroelectric layer 152b, as shown in the right diagram of FIG. 11). ALO film having a thickness of 0.2 nm to 5.0 nm).

  Similar to the first embodiment, the orientation degree of the second ferroelectric layer 152b of the second capacitor 156b is lower than the orientation degree of the first ferroelectric layer 152a of the first capacitor 156a. For this reason, the leakage current of the second capacitor 156b is reduced.

(2) Manufacturing Method FIGS. 12 to 15 are process cross-sectional views illustrating a method of manufacturing the semiconductor device 102 according to the second embodiment. The manufacturing method of the second embodiment is substantially the same as the manufacturing method of the first embodiment until the lower electrode film 64 is formed. Therefore, the description until the lower electrode film 64 is formed is omitted.

(2-1) Treatment of the surface of the lower electrode film (see FIGS. 12A to 13B)
-Deposition of insulating film (see Fig. 12 (a))-
An insulating film 76 having a thickness of 0.2 nm to 5.0 nm (preferably 1 nm) is deposited on the lower electrode film 64 by, for example, RF sputtering. The insulating film 76 is an amorphous film.

The insulating film 76 is preferably an ALO film or a titanium oxide film (hereinafter referred to as a TiO ₂ film). The insulating film 76 may be another insulating film (for example, an SIO film). However, since the ALO film and the TiO ₂ film are difficult to peel off from the lower electrode film 64, they are preferable to other insulating films.

  However, the insulating film 76 is easily peeled off from the lower electrode film 64 when the thickness exceeds 5.0 nm. Further, in the etching of the ferroelectric film described later, if the thickness of the insulating film 76 exceeds 5.0 nm, the ferroelectric film residue is likely to be generated. On the other hand, when the thickness of the insulating film 76 is less than 0.2 nm, the degree of orientation of the ferroelectric film described later may not easily decrease.

  Therefore, the thickness of the insulating film 76 is preferably 0.2 nm or more and 5.0 nm or less. More preferably, the thickness of the insulating film 76 is not less than 0.4 nm and not more than 3.0 nm. Most preferably, the insulating film 76 has a thickness of 0.6 nm to 2.0 nm.

-Formation of resist pattern (see Fig. 12 (b))-
As shown in FIG. 12B, a resist film 78 is formed on the insulating film 76. The resist film 78 is a photoresist film that covers the insulating film 76 above the second capacitor region 166b corresponding to the second capacitor 156b. On the other hand, the resist film 78 exposes the insulating film 76 above the first capacitor region 166a corresponding to the first capacitor 156a.

-Insulating film patterning (see Fig. 13 (a))-
Next, the insulating film 76 is wet etched through the resist film 78 to form an insulating film pattern 80. When the insulating film 76 is an ALO film, the etching solution is, for example, a diluted HF solution.

  When the insulating film 76 is etched by dry etching, the surface of the first capacitor region 166a is roughened. Therefore, the etching of the insulating film 76 is preferably wet etching.

-Stripping of resist film (see Fig. 13 (b))-
Next, the resist film 78 is stripped with a resist stripping solution (for example, an organic solvent such as acetone or a remover). When the resist film 68 is dry peeled by an ashing device, the surface of the first capacitor region 166a is roughened. Therefore, wet stripping with a resist stripping solution is preferable.

(2-2) Deposition of ferroelectric film (see FIG. 14A)
A ferroelectric film 72 (for example, PZT film) having a thickness of 35 nm to 105 nm (preferably 70 nm) is deposited on the lower electrode film 64 on which the insulating film pattern 80 is formed by, for example, RF sputtering using Ar gas. To do. On the ferroelectric film 72, a ferroelectric film (for example, a PZT film) having a thickness of 5 nm to 15 nm (preferably 10 nm) may be further deposited.

(2-3) Crystallization of ferroelectric film (see FIG. 14B)
The lower electrode film 64 and the ferroelectric film 72 are heat-treated at 550 ° C. to 650 ° C. (preferably 600 ° C.) for 60 seconds to 120 seconds (preferably 90 seconds), for example, by the RTA method. By this heat treatment, the lower electrode film 64 (for example, Pt film) is self-oriented in the [111] axis direction, for example, and the ferroelectric film 72 is crystallized.

  On the first capacitor region 166a, as shown in FIG. 14B, a first ferroelectric layer 152a oriented in the [111] axis direction is formed. On the other hand, a second ferroelectric layer 152b having a lower degree of orientation than the first ferroelectric layer 152a is formed on the second capacitor region 166b.

  This is because, on the second capacitor region 166b, since the surface of the lower electrode film 64 is covered with the insulating film pattern 80, the ferroelectric film 72 cannot be crystallized while continuing the lower electrode film 64 and the crystal lattice. Because.

(2-4) Formation of upper electrode film (see FIG. 15)
Next, the upper electrode film 74 is deposited on the ferroelectric film 72 and then heat-treated by substantially the same procedure and conditions as in the first embodiment.

(2-5) Process after Upper Electrode Film Formation Finally, the semiconductor device 102 is completed according to the procedure described in “(2-7) Process after upper electrode film formation” in the first embodiment.

(3) Degree of Orientation of Ferroelectric Film and Leakage Current FIG. 16 is a diagram showing an example of the orientation rate of the PZT film formed in each of the first capacitor region 166a and the second capacitor region 166b. The horizontal axis is the name of the capacitor region. The vertical axis represents the orientation rate (P value) in the [111] axial direction. The measured lower electrode film 64 of the PZT film is a Pt film. The deposition conditions and heat treatment conditions for the PZT film are the preferred conditions shown in parentheses in “(2) Manufacturing method”.

  As shown in FIG. 16, the orientation ratio of the PZT film formed in the first capacitor region 166a is 0.9 or more. On the other hand, the orientation rate of the PZT film formed in the second capacitor region 166b is at most 0.2. Therefore, as is apparent from the equations (1) and (2) described in the first embodiment, the degree of orientation of the second ferroelectric layer 152b formed in the second capacitor region 166b is in the first capacitor region 166a. It becomes lower than the degree of orientation of the first ferroelectric layer 152a to be formed.

  FIG. 17 is a diagram illustrating an example of the leakage current of the monitoring capacitor formed in each of the first capacitor region 166a and the second capacitor region 166b. The horizontal axis is the name of each area. The vertical axis represents the leakage current. The applied voltage is 3 V as in the first embodiment. The structure of the monitoring capacitor is the same as that of the monitoring capacitor of the first embodiment.

  As shown in FIG. 17, the leakage current of the second capacitor region 166b is about 1/50 of the leakage current of the first capacitor region 166a. That is, the leakage current of the second capacitor 156b is much smaller than the leakage current of the first capacitor 156a.

  As is clear from comparison between FIG. 9 and FIG. 17, according to the second embodiment, the leakage current can be reduced as compared with the first embodiment. As is apparent from the comparison between FIG. 8 and FIG. 16, according to the second embodiment, the orientation degree of the second ferroelectric layer 152b is equal to the orientation degree of the second ferroelectric layer 52b of the first embodiment. This is because it can be made lower.

  In the first and second embodiments, the first lower electrodes 50a and 150a and the second lower electrodes 50b and 150b are Pt electrodes, and the first ferroelectric layers 52a and 152a and the second ferroelectric layers 52b and 152b are PZT. Is a layer. However, the first lower electrode and the second lower electrode may be electrodes other than the Pt electrode. The first ferroelectric layer and the second ferroelectric layer may be ferroelectric layers other than the PZT layer.

For example, the first lower electrode and the second lower electrode may be SRO electrodes (SrRuO ₃ electrodes), and the first ferroelectric layer and the second ferroelectric layer may be PZT layers. Alternatively, the first lower electrode and the second lower electrode may be Pt electrodes, and the first ferroelectric layer and the second ferroelectric layer may be BST (Barium Strontium Titanate) layers.

  In the first and second embodiments, the first upper electrode and the second upper electrode are IrOx layers (x is 1 or more and 2 or less). However, the first upper electrode and the second upper electrode may be conductive layers other than the IrOx layer. For example, the first upper electrode and the second upper electrode may be an Ir layer (iridium layer) or a Ru layer (ruthenium layer).

  In the first and second embodiments, the ferroelectric film is formed by sputtering. However, the ferroelectric film may be formed by a method other than the sputtering method. For example, the ferroelectric film may be formed by a Sol-gel method.

  In the first and second embodiments, the second capacitor is a smoothing capacitor. However, the second capacitor may be a capacitor other than the smoothing capacitor. For example, the second capacitor may be a coupling capacitor.

  In the first and second embodiments, the wiring of the semiconductor devices 2 and 102 is formed of aluminum. However, the wiring of the semiconductor devices 2 and 102 may be formed of a conductive material other than aluminum. For example, the wiring of the semiconductor devices 2 and 102 may be formed of copper.

  The device 4 provided with the semiconductor devices 2 and 102 of the first and second embodiments is an IC card. However, the device 4 may be another device. For example, the device 4 may be an ASIC (Application Specific Integrated Circuit).

  In the first and second embodiments, the first lower electrode and the second lower electrode are platinum films. However, the first lower electrode and the second lower electrode may be electrodes including, for example, a platinum film.

  Regarding the above first and second embodiments, the following additional notes are disclosed.

(Appendix 1)
A first lower electrode provided on a first surface on a semiconductor substrate, a first ferroelectric layer provided on the first lower electrode and including a ferroelectric material, and on the first ferroelectric layer A first capacitor having a first upper electrode provided on the first capacitor;
A second lower electrode provided on the first surface; and a second ferroelectric provided on the second lower electrode and having a lower degree of orientation than the first ferroelectric layer and comprising the ferroelectric material A semiconductor device comprising: a second capacitor having a layer and a second upper electrode provided on the second ferroelectric layer.

(Appendix 2)
The first lower electrode and the second lower electrode include a platinum film oriented in the [111] axial direction,
The semiconductor device according to appendix 1, wherein the first ferroelectric layer is oriented in the [111] axial direction.

(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the ferroelectric material is lead zirconate titanate.

(Appendix 4)
Of the peak intensity of the diffraction pattern obtained by measuring the second ferroelectric layer by 2θ-θX-ray diffraction method, the first peak intensity corresponding to the (222) plane is the first peak intensity and the peak intensity. Supplemental note 3 wherein the orientation ratio obtained by dividing the sum of the second peak intensity corresponding to the (101) plane and the third peak intensity corresponding to the (101) plane out of the peak intensities is 0.5 or less A semiconductor device according to 1.

(Appendix 5)
5. The semiconductor device according to claim 1, wherein the second capacitor further includes an insulating film disposed between the second lower electrode and the second ferroelectric layer.

(Appendix 6)
Forming a lower electrode film on the first surface of the semiconductor substrate;
Exposing the second capacitor region of the lower electrode film to plasma;
After the step of exposing to plasma, depositing a ferroelectric film on the lower electrode film;
Heat treating the lower electrode film and the ferroelectric film;
Forming an upper electrode film on the ferroelectric film;
The upper electrode film, the ferroelectric film, and the lower electrode film are etched to form a first capacitor in a first capacitor area different from the second capacitor area, and a second capacitor in the second capacitor area. Forming a semiconductor device.

(Appendix 7)
In the step of exposing to the plasma, the second capacitor region is exposed to the plasma through a resist film that covers the first capacitor region and exposes the second capacitor region,
7. The method of manufacturing a semiconductor device according to appendix 6, wherein the second capacitor region is exposed to the plasma, and then the resist film is stripped with a resist stripping solution.

(Appendix 8)
The method of manufacturing a semiconductor device according to appendix 6 or 7, wherein the plasma is generated by a downflow type plasma generating apparatus.

(Appendix 9)
The lower electrode film is a platinum film,
The method for manufacturing a semiconductor device according to any one of appendices 6 to 8, wherein the ferroelectric film is a lead zirconate titanate film.

(Appendix 10)
Forming a lower electrode film on the first surface of the semiconductor substrate;
Forming an insulating film pattern covering the second capacitor region of the lower electrode film;
After the step of forming the insulating film pattern, a step of depositing a ferroelectric film on the lower electrode film and the insulating film pattern;
Heat treating the lower electrode film and the ferroelectric film;
Forming an upper electrode film on the ferroelectric film;
The upper electrode film, the ferroelectric film, and the lower electrode film are etched to form a first capacitor in a first capacitor area different from the second capacitor area, and a second capacitor in the second capacitor area. Forming a semiconductor device.

(Appendix 11)
In the step of forming the insulating film pattern,
Depositing an insulating film on the lower electrode film;
After the step of depositing the insulating film, a resist film that exposes the insulating film above the first capacitor region and covers the insulating film above the second capacitor region is formed;
Wet etching the insulating film through the resist film to form the insulating film pattern,
11. The method of manufacturing a semiconductor device according to appendix 10, wherein the resist film is stripped with a resist stripping solution after the insulating film pattern is formed.

(Appendix 12)
12. The method for manufacturing a semiconductor device according to appendix 10 or 11, wherein the insulating film is a pattern of an aluminum oxide film having a thickness of 5 nm or less or a pattern of a titanium oxide film having a thickness of 5 nm or less.

(Appendix 13)
The lower electrode film is a platinum film,
The method for manufacturing a semiconductor device according to any one of appendices 10 to 12, wherein the ferroelectric film is lead zirconate titanate.

2,102 ... Semiconductor device 10 ... Smoothing capacitor 12 ... FeRAM
38 ... Semiconductor substrate 48 ... 1st surface 50a ... 1st lower electrode 50b ... 2nd lower electrode 52a, 152a ... 1st ferroelectric layer 52b, 152b ... 2nd strong Dielectric layer 54a ... first upper electrode 54b ... second upper electrode 56a, 156a ... first capacitor 56b, 156b ... second capacitor 64 ... lower electrode film 66a, 166a ... First capacitor region 66b, 166b ... Second capacitor region 68, 78 ... Resist film 70 ... Plasma 72 ... Ferroelectric film 74 ... Upper electrode film 76, 90 ... Insulating film 80 ... Insulating film pattern

Claims (2)

Forming a lower electrode film on the first surface of the semiconductor substrate;
Exposing the second capacitor region of the lower electrode film to plasma;
After the step of exposing to plasma, depositing a ferroelectric film on the lower electrode film;
Heat treating the lower electrode film and the ferroelectric film;
Forming an upper electrode film on the ferroelectric film;
The upper electrode film, the ferroelectric film, and the lower electrode film are etched to form a first capacitor in a first capacitor area different from the second capacitor area, and a second capacitor in the second capacitor area. Forming a semiconductor device. In the step of exposing to the plasma,
Through the resist film to expose the pre-Symbol second capacitor region covering said first capacitor region exposing the second capacitor region to the plasma,
The method of manufacturing a semiconductor device according to claim 1 , wherein after the second capacitor region is exposed to the plasma, the resist film is stripped with a resist stripping solution.

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