JP6391734B2 - Semiconductor manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor manufacturing method using plasma.

  For example, a technique for periodically turning on / off plasma with a dry etching apparatus using plasma is disclosed in Japanese Patent Application Laid-Open No. 1-149965 (Patent Document 1). Here, a method is described in which ions and radicals and the like are arbitrarily controlled temporally and spatially by utilizing the fact that the plasma composition varies depending on the afterglow in the off period by periodically turning on and off the plasma. The patent document 1 also describes that the pulse width is 1 ms or less and the period is 10 s or less. Also, in order to prevent damage caused by charged particles (ions, electrons) in the plasma, the plasma is generated at a distance from the wafer, the charged particles are removed by diffusing for a long distance, and particles having no charge such as F radicals. A method of performing etching by the method described in JP-A-62-31124 (Patent Document 2). This etching is called chemical dry etching.

JP-A-1-149965 JP-A-62-31124

  With the miniaturization of semiconductor elements, mass production of transistors having a three-dimensional structure called fin field effect transistors (Fin-FETs) has been started. Correspondingly, dry etching technology, which is the key to miniaturization, requires further miniaturization, high aspect and high-precision etching of complex shapes not found in conventional two-dimensional transistors, and requires breakthrough technology. It has become.

  Highly anisotropic shape processing can be performed by ion-assisted etching mainly composed of ions. On the other hand, chemical dry etching mainly composed of neutral radicals enables isotropic processing with a high selectivity. Both of these are required for processing a three-dimensional transistor. However, in the prior art, the structures of the ion assist etching apparatus and the chemical dry etching apparatus are greatly different, and the ion assist etching and the chemical dry etching cannot be performed continuously in the same apparatus.

  An object of the present invention is to provide a semiconductor manufacturing method capable of continuously performing ion-assisted etching and chemical dry etching in the same chamber.

In the present invention, in order to achieve the above object, in a semiconductor manufacturing method in which a sample is plasma-etched by continuous discharge plasma,
Generating a magnetic field in a plasma processing chamber in which the sample is plasma etched;
The semiconductor manufacturing method is characterized in that the magnetic flux density of the magnetic field on the sample is 100 G or less.
Moreover, in a semiconductor manufacturing method in which a sample is plasma etched by continuous discharge plasma,
Generating a magnetic field in a plasma processing chamber in which the sample is plasma etched;
The semiconductor manufacturing method is characterized in that the polarities of the respective currents flowing through the plurality of coils generating the magnetic field are reversed.

Further, in a semiconductor manufacturing method in which a sample is plasma etched by plasma,
An ion-assisted etching process that plasma etches the sample with a high frequency power of 1 W or more supplied to a sample stage on which the sample is placed using continuous plasma;
A chemical dry etching process in which the sample is plasma-etched with a high-frequency power supplied to the sample stage of 0 W using plasma generated by pulse-modulated high-frequency power,
The ion-assisted etching process and the chemical dry etching process are continuously performed in the same plasma processing chamber in which the sample is plasma-etched.

In addition, in a semiconductor manufacturing method in which a sample is plasma-etched with plasma containing ions and radicals generated by pulse-modulated high-frequency power,
For a sample placed in the same plasma processing chamber, the first plasma processing step in which the ratio of the number of incident ions to the number of incident radicals is relatively large, the number of incident ions and the number of incident radicals. And a second plasma processing step having a relatively small ratio.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the semiconductor manufacturing method which can perform ion assist etching and chemical dry etching continuously in the same chamber.

1 is a schematic overall configuration diagram of a semiconductor manufacturing apparatus used for performing a semiconductor manufacturing method (dry etching) according to a first embodiment of the present invention. The relationship between the duty ratio of the pulse and the saturated ion current density incident on the wafer in the semiconductor manufacturing method (dry etching) according to the first embodiment of the present invention is shown. The relationship between the magnetic flux density on a wafer and the saturation ion current density in the semiconductor manufacturing method (dry etching) concerning the 2nd example of the present invention is shown. The relationship between the height of the ECR plane and the saturation ion current density in the semiconductor manufacturing method (dry etching) according to the third embodiment of the present invention is shown. It is the schematic of the process process in the semiconductor manufacturing method (dry etching) based on the 5th Example of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an example of a plasma etching apparatus to which a semiconductor manufacturing method (dry etching) according to a first embodiment of the present invention is applied. Electron Cyclotron Resonance (Electron Cyclotron Resonance) using a microwave and a magnetic field as plasma generating means. 1 is a schematic view of a plasma etching apparatus (hereinafter referred to as ECR).

  This apparatus includes a chamber (plasma processing chamber) 101 that can be evacuated inside, a sample stage 103 on which a wafer 102 as a sample is placed, a microwave transmission window 104 such as quartz provided on the upper surface of the chamber 101, A waveguide 105 provided above, a magnetron 106, a solenoid coil 107 provided around the chamber 101, an electrostatic adsorption power supply 108 connected to the sample stage 103, and a high-frequency bias power supply 109 are provided.

  The wafer 102 is carried into the chamber 101 from the wafer carry-in port 110 and then electrostatically adsorbed to the sample stage 103 by the electrostatic adsorption power source 108. Next, process gas is introduced into the chamber 101 from the gas inlet 111. The inside of the chamber 101 is evacuated by a vacuum pump (not shown) and adjusted to a predetermined pressure (for example, 0.1 Pa to 50 Pa).

  Next, a microwave having a frequency of 2.45 GHz is oscillated from the magnetron 106 and supplied into the chamber 101 through the waveguide 105 and a microwave transmission window 104 such as quartz. The processing gas is excited by the interaction between the microwave and the magnetic field generated by the solenoid coil 107, and a plasma 112 containing ions and radicals is formed in the space above the wafer 102.

  The output of the magnetron 106 can be pulse-modulated, and the time modulation frequency is set as the plasma pulse frequency fp and the inverse is set as the plasma pulse period. On the other hand, a high-frequency bias power is applied to the sample stage 103 by a high-frequency bias power source 109, and ions in the plasma 112 are vertically accelerated and incident on the wafer 102. The wafer 102 is anisotropically etched by the action of radicals and ions from the plasma 112.

  In addition, a pulse generator 113 is connected to the high frequency bias power source 109, and the high frequency bias power supplied to the sample stage 103 from the high frequency bias power source 109 is pulse-modulated by a continuous pulse wave generated by the pulse generator 113. Can do.

  The frequency of this pulse modulation is a bias pulse frequency fb, and its reciprocal is a bias pulse cycle. Further, the pulse generator 113 has a function capable of arbitrarily setting the bias pulse frequency and the ratio between the on period and the off period in one cycle. Note that the ratio of the ON period to one cycle is referred to as a duty ratio.

  Next, an example for reducing the incidence of ions on the wafer will be described. FIG. 2 shows the relationship between the duty ratio of the magnetron 106, which is the first high-frequency power source, and the saturation ion current density incident on the wafer. The value of the saturated ion current density is a value averaged over time. Table 1 shows the plasma conditions. The duty ratios α and β in the conditions 1 and 2 mean that the duty ratio is changed, and the on / off frequency is 1000 Hz.

Whether the microwave power is 600 W or 1000 W, the saturated ion current density rapidly decreases from about 30% of the duty ratio, becomes about 20%, becomes an inflection point, and at the same time becomes 0.5 mA or less that allows radical-based etching.

  In order to investigate this cause, the time change of the saturation ion current density was measured using a high-speed measuring instrument. As a result, it was found that the saturation ion current density did not reach the steady value within the on time when the on time was 0.3 ms or less. That is, it can be seen that turning off the plasma before the saturation ion current density reaches a steady value is very effective in reducing the saturation ion current density on the wafer. Specifically, when the on-time is 0.2 ms or less and the duty ratio is 20% or less, the saturated ion current density can be sufficiently reduced. That is, by changing the duty ratio, ion-assisted etching (the ratio of the incident number of ions to the incident number of radicals is relatively large) and chemical etching (the ratio of the incident number of ions to the incident number of radicals is relatively small). Can be switched. Thereby, it is possible to perform integrated processing of ion-assisted etching and chemical etching in semiconductor manufacturing.

  Next, the solution of the problem at the time of processing chemical dry etching consistently from ion assist etching is explained. In chemical dry etching, the plasma density is lowered, which causes a problem that the plasma is difficult to ignite. In order to ignite stably, an ignition step having a high plasma density and being easy to ignite may be inserted before the chemical dry etching step. However, this would conflict with radical-based etching. In order to avoid this, a gas that has a low ionization voltage and does not affect the etching characteristics may be mixed in the chemical dry etching step. For example, this problem can be avoided by mixing 10% or less (however, 0% or more) of the total flow rate with Kr or Xe as a whole. As another method, there is a method in which the deposited film removing step and the ignition step are combined. For this purpose, the transition between the protective film removing step and the chemical dry etching step may be performed continuously without turning off the output of the first high-frequency power source for generating plasma.

  As described above, according to this embodiment, it is possible to provide a semiconductor manufacturing method capable of continuously performing ion-assisted etching and chemical dry etching in the same chamber.

  A semiconductor manufacturing method according to a third embodiment for reducing the saturated ion current density on the wafer will be described. Note that the matters described in the first embodiment but not described in the present embodiment can be applied to the present embodiment as long as there is no particular circumstance.

  FIG. 3 shows the relationship between the magnetic flux density just above the wafer center and the saturation ion current density. In addition, the plasma condition is the condition 3 in Table 2, and the measurement is performed by changing the coil.

FIG. 3 shows that the saturation ion current density on the wafer decreases as the magnetic flux density on the wafer surface decreases. There is a correlation between the saturated ion current density and the ion density. This is because the arrival of ions to the wafer is reduced by decreasing the magnetic flux density, and as a result, the saturated ion current density is also reduced. Further, when the magnetic flux density is 100 G, the amount of change in the saturation ion current density is the largest, and it can be said that the magnetic flux density on the wafer is desirably 100 G or less when performing radical etching.

  Furthermore, since the ion density can be reduced by reducing the magnetic flux density from the above results, the measurement was performed by changing the polarity of the current flowing through the coil. The conditions performed are shown in Table 2 (Condition 4). By changing the polarity of the current flowing through the coil of Table 2, the saturated ion current density on the wafer was also reduced. This is because, by changing the polarity of the current flowing through the coil, the magnetic lines of force in the chamber move toward the wall, and as a result, ions are guided toward the wall and the ion density on the wafer is reduced. It can be said that it decreased. That is, ion assist etching and chemical etching can be switched by changing the magnetic flux density or changing the polarity of the coil current. Thereby, it is possible to perform integrated processing of ion-assisted etching and chemical etching in semiconductor manufacturing.

  As described above, according to this embodiment, it is possible to provide a semiconductor manufacturing method capable of continuously performing ion-assisted etching and chemical dry etching in the same chamber.

  A semiconductor manufacturing method according to the third embodiment of the present invention will be described with reference to FIG. Note that matters described in the first or second embodiment but not described in the present embodiment can also be applied to the present embodiment unless there are special circumstances. The example shown in FIG. 4 shows the relationship between the height of the ECR plane and the saturation ion current density. FIG. 4 shows that the saturation ion current density is lowered by separating the ECR surface from the wafer. This is because the diffusion distance of ions is increased by separating the ECR surface from the wafer. When the diffusion distance increases, the number of ions and electrons that collide with the wall surface increase, and both recombine. Therefore, it can be said that the ion density is decreased by separating the ECR surface from the wafer, and the saturated ion current density is decreased. The reason why the saturated ion current density suddenly decreases from an ECR height of about 100 mm is that it decreases in proportion to the square of the normal distance, but the ECR surface becomes closer to the quartz microwave transmission window 104 and the attenuation at the wall is reduced. This is because it works as a synergistic effect. Further, when the ECR plane is formed above the top plate, the plasma density in the chamber is weakened and the ion density is reduced, and as a result, the saturated ion current density is also reduced.

  From the above, it can be said that it is desirable that the height of the ECR surface be 150 mm or more from the top of the wafer in order to suppress the generation of ions when performing radical etching. That is, the ion assist etching and the chemical etching can be switched by changing the height of the ECR plane. Thereby, it is possible to perform integrated processing of ion-assisted etching and chemical etching in semiconductor manufacturing.

  As described above, according to this embodiment, it is possible to provide a semiconductor manufacturing method capable of continuously performing ion-assisted etching and chemical dry etching in the same chamber.

  A semiconductor manufacturing method according to the fourth embodiment of the present invention will be described. Note that the matters described in any of the first to third embodiments but not described in the present embodiment can be applied to the present embodiment as long as there are no special circumstances.

  When the relationship between the pressure in the chamber 101 and the plasma density is obtained, when the pressure is increased from a low pressure, the plasma density decreases at 5 Pa or more. It can be said that as the pressure is increased, the amount of staying gas in the chamber increases, the density of ions and electrons becomes overcrowded, and ions and electrons collide and recombine, thereby reducing the plasma density. Therefore, when chemical dry etching is performed, it is effective to perform etching in a region of 5 Pa or more. That is, ion assist etching and chemical etching can be switched by changing the pressure in the chamber. Thereby, it is possible to perform integrated processing of ion-assisted etching and chemical etching in semiconductor manufacturing.

  As described above, according to this embodiment, it is possible to provide a semiconductor manufacturing method capable of continuously performing ion-assisted etching and chemical dry etching in the same chamber.

  A semiconductor manufacturing method according to the fifth embodiment of the present invention will be described. Note that matters described in any of the first to fourth embodiments but not described in the present embodiment can also be applied to the present embodiment unless there are special circumstances.

  In the embodiments so far, the chemical dry etching is a process method, but FIG. 5 shows an example in which chemical dry etching is consistently processed from ion-assisted etching. Table 3 shows the conditions.

FIG. 5A shows a thin film structure to be a substrate to be processed. An oxide film (SiO ₂ or the like) 501 is provided as a first film, and a Si layer 503 as a second film and a SiGe layer 502 as a third film alternately form a laminated structure thereunder. Here, the Si layer 503 and the SiGe layer 502 are crystalline Si and crystalline SiGe produced by an epitaxial growth method.

  Next, as shown in FIG. 5B, ion-assisted etching of the Si layer 503 and the SiGe layer 502 is performed using the oxide film 501 as a mask (steps 1 and 2). In this step, a deposition film 504 is formed on the sidewalls of the Si layer 503 and the SiGe layer 502 and ion-assisted etching is performed. The bias power applied to the sample at this time is 100 W, but it can be applied if it is 1 W or more.

  Next, chemical dry etching is performed in the same chamber. Since radical-based etching does not use ion energy, it is greatly affected by residual gas in the chamber and the surface state of the wafer. In order to perform stable processing, it is effective to provide a step of evacuating the chamber once as shown in Step 3 of Table 3.

  Further, it is effective to include a step of removing deposits on the wafer generated during ion-assisted etching as in step 4 of Table 3. FIG. 5C shows a step 4 of removing the deposited film on the side walls of the Si layer 503 and the SiGe layer 502 after the ion-assisted etching. Regarding the removal of the deposited film on the side wall, the change in emission from plasma is measured. If the completion of the removal of the sidewall deposition film is confirmed, continuous processing can be performed with higher accuracy. FIG. 5D shows a cross-sectional shape after removing the deposited film on the side wall. Note that the high-frequency bias power applied to the sample in steps 4 and 5 was set to 0 W.

  FIG. 5E shows a cross-sectional shape obtained by performing chemical dry etching after removing the deposited film on the side wall.

  In order to perform chemical dry etching after ion-assisted etching as described above, chemical dry etching can be processed consistently from ion-assisted etching by including a step of removing the deposited film.

  As described above, according to this embodiment, it is possible to provide a semiconductor manufacturing method capable of continuously performing ion-assisted etching and chemical dry etching in the same chamber.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

DESCRIPTION OF SYMBOLS 101 ... Chamber (plasma processing chamber), 102 ... Wafer {sample}, 103 ... Sample stand, 104 ... Microwave transmission window, 105 ... Waveguide, 106 ... Magnetron, 107 ... Solenoid coil, 108 ... Electrostatic adsorption power supply, DESCRIPTION OF SYMBOLS 109 ... High frequency bias power source, 110 ... Wafer inlet, 111 ... Gas inlet, 112 ... Plasma, 113 ... Pulse generator, 501 ... Oxide film, 502 ... Silicon germanium layer (SiGe), 503 ... Silicon layer (Si), 504: Deposited film (reaction product).

Claims (3)

In a semiconductor manufacturing method in which a sample is plasma etched in a plasma processing chamber,
A first step of ion-assisted etching the sample by using a continuous plasma,
A second step of evacuating the plasma processing chamber after the first step;
A third step of removing the deposited film deposited on the sample after the second step ;
Have a, a fourth step of chemical dry etching the sample using the following the third step, generated by the high frequency power is pulse-modulated plasma,
A method for manufacturing a semiconductor , comprising performing the first step to the fourth step continuously in the same plasma processing chamber . The semiconductor manufacturing method according to claim 1,
The first step is performed by setting the high frequency power supplied to the sample stage on which the sample is placed as 1 W or more,
The fourth step, a semiconductor manufacturing process, characterized in that, taken in the 0W high frequency power supplied to the sample stage. In the semiconductor manufacturing method according to claim 1 or 2 ,
The third step is performed using plasma generated by pulse-modulated high-frequency power,
Transition from the third step to the fourth step is performed while continuing the plasma of the third step .

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