JP6391336B2 - Scan BIST LFSR seed generation method and storage medium for storing the program - Google Patents

Description

  The present invention is a seed generation method for built-in self-test of a semiconductor integrated circuit. More specifically, a high failure detection rate can be obtained, seed generation can be performed at high speed, and the number of seeds can be reduced. The present invention relates to a scan BIST LFSR seed generation method and a storage medium for storing the program.

  Recent advances in device technology have improved the integration of digital integrated circuits, making it possible to mount large-scale systems on LSIs. However, with an increase in circuit scale, testing becomes more difficult, and an increase in test cost, such as an increase in test generation time, has become a problem. There is a correlation between test cost and testability, and it is conceivable to facilitate testing in order to reduce the increased test cost. In order to facilitate the test, incorporating an additional circuit in the circuit is called a testability design, and one of them is a scan design. In the scan design, the state of each flip-flop constituting the sequential circuit can be freely set from the outside, and the state of those flip-flops can be observed from the outside. The test generation problem of the scan-designed sequential circuit can be treated as a test generation problem of the combinational circuit, and the test generation easiness is improved.

  As a design method for simplifying the external test apparatus, there is a built-in self test method (BIST: Built-in self test). In BIST, a circuit that generates a test pattern and a circuit that checks an output response to the test pattern are used. As a pattern generation circuit in BIST, a linear feedback shift register (LFSR) that generates a pseudo-random pattern is mainly used, and a circuit that checks an output response uses a multiple-input signature register (MISR). . The MISR is a circuit that compresses the output response of the circuit, but in the present invention, only the pattern generation circuit and the circuit to be inspected are handled.

  The LFSR of the pattern generation circuit can generate all patterns except the all zero pattern pseudo-randomly depending on the feedback position. However, since the operation of the LFSR is decisive, some circuits cannot achieve a high failure detection rate with a pseudo-random pattern. A fault that is resistant to a test using a pseudo-random pattern is referred to as a random pattern resistant fault. In order to achieve a high failure detection rate in a circuit having such a failure, the initial value of the LFSR register (the value initially set in the LFSR register is referred to as a seed) is reset (reseed). Is known to be effective.

  Specifically, several patterns are generated from a certain seed, a test is performed, a seed that can detect each failure is re-seed for a failure that has not been detected in the tests applied so far, and the test is repeated.

JP 2009-156761 A JP-A-6-52005 JP 2008-117383 A

  As a conventional LFSR seed generation method, there is a method of generating a test for the failure and converting the obtained test pattern into an LFSR seed. However, the conversion is not always possible, and the failure detection rate may decrease. is there. In addition, there is a problem that the number of seeds increases due to generation of a test with don't care for improving the conversion rate to seeds. In view of these problems, an object of the present invention is to provide a new LFSR seed generation method for improving the failure detection rate of scan BIST.

  In the first aspect of the present invention, in order to solve the above problem, a seed generation model of a scan BIST is formed, and a test generation of a target fault is performed on the formed seed generation model to generate a seed of the LFSR. The seed generation model includes an XOR network configured by expanding the LFSR of the scan BIST for a scan path length in a scan FF of a circuit to be inspected, and a combinational circuit portion of the circuit to be inspected. A method for generating an LFSR seed for a scan BIST, wherein the XOR network output is connected to the combinational circuit portion.

  In the first aspect, in the seed generation model, a phase shifter group may be connected between the XOR network and a combinational circuit portion of the circuit to be inspected. A random inverting circuit group may be connected between the XOR network and the combinational circuit portion of the circuit under test. Each random inverting circuit of this random inverting circuit group includes an inverting logic circuit inserted between the XOR network and the combinational circuit portion of the circuit under test, a second XOR network, and a second XOR network. An inversion control circuit for controlling the operation of the inversion logic circuit using an output. Further, the target failure may be a stuck-at failure. Moreover, the test generation of the target failure may be performed using an automatic test pattern generation tool.

  Further, in the first aspect, the seed generation model further includes a multiplexer for temporally switching the XOR network output and the scan FF output and inputting the output to the combinational circuit portion, and a timing for switching the multiplexer. And a timing generator to be controlled. The seed generation model may further include a phase shifter group or a random inversion circuit group.

  Further, in the first aspect, the seed generation model further includes a second combinational circuit portion that is a duplicate of the combinational circuit portion, and an input of the second combinational circuit portion includes an output of the XOR network. The output of the combinational circuit portion may be connected.

  Further, in the first aspect, the seed generation model further includes a second XOR network configured by expanding the LFSR of the scan BIST by a time corresponding to a scan path length + 1 scan shift in a scan FF of a circuit to be inspected, and the XOR A multiplexer for switching the network output and the second XOR network output in time and inputting them to the combinational circuit portion, and a timing generator for controlling the switching timing of the multiplexer may be provided.

  In the second aspect of the present invention, in order to solve the above-mentioned problem, an XOR network is formed by developing the LFSR of the scan BIST for the scan path length in the scan FF of the circuit to be inspected, and the XOR network is To cause a computer to execute a procedure for forming a seed generation model by connecting to a combinational circuit portion of a circuit, and generating a seed for the LFSR by performing test generation of a target fault on the seed generation model A storage medium for storing the program is provided.

  In the third aspect of the present invention, in order to solve the above-mentioned problem, an XOR network configured by expanding the LFSR of the scan BIST by the time corresponding to the scan path length in the scan FF of the circuit to be inspected, the XOR network output, and the scan A step of forming a seed generation model by a multiplexer that switches the FF output in time and applies it to the combinational circuit portion of the circuit under test; and a timing generator that controls the switching timing of the multiplexer; and the seed generation model A storage medium is provided for storing a program for causing a computer to perform test generation of a target failure and forming a seed for the LFSR.

In a fourth aspect of the present invention, in order to solve the above-mentioned problem, an XOR network formed by expanding the LFSR of the scan BIST by the time corresponding to the scan path length in the scan FF of the circuit to be inspected, and a combinational circuit of the circuit to be inspected And a second combinational circuit part replicating the combinational circuit part, connecting the XOR network output to an input of the combinational circuit part, and connecting the XOR network output and the combinational circuit part output to the second And a step of forming a seed generation model by connecting to the input of the combinational circuit portion and a step of performing test generation of the target fault on the seed generation model to form a seed of the LFSR. A storage medium for storing a program for storing the program is provided.

  In a fifth aspect of the present invention, in order to solve the above-mentioned problem, an XOR network formed by expanding the LFSR of the scan BIST by the time corresponding to the scan path length in the scan FF of the circuit to be inspected, and a combinational circuit of the circuit to be inspected And the combination circuit by temporally switching the XOR network or the second XOR network output, and a second XOR network configured by expanding the LFSR by a time corresponding to a scan path length plus one scan shift in the scan FF A step of forming a seed generation model by a multiplexer to be applied to the part and a timing generator for controlling a switching timing of the multiplexer; and a test generation of a target fault with respect to the seed generation model to generate a seed for the LFSR Forming the procedure, and the computer Storing a program for causing the row, it provides a storage medium.

  According to the LFSR seed generation method of the scan BIST of the present invention, a high failure detection rate can be obtained, seeds can be generated at high speed, and an excellent effect of reducing the number of seeds can be exhibited. That is, according to the method of the present invention, the same operation as the scan BIST circuit in the test mode can be simulated for the circuit to be inspected. Since the seed can be obtained directly, it is not necessary to generate a test with don't care, and the number of patterns can be suppressed as compared with the conventional method. In addition, it is not necessary to perform a fault simulation again in order to check how many faults can be detected by the seed generated in the process of generating seeds. This has the advantage of reducing test time.

The figure which shows the conventional seed production | generation method. The figure which shows the seed production | generation method concerning this invention. The figure which shows a BIST model. The figure which shows the seed production | generation model which concerns on the 1st Embodiment of this invention. The figure which shows the seed production | generation model which concerns on the 2nd Embodiment of this invention. The figure which shows the other Example of the model shown to FIG. 5 (A). FIG. 6 is a timing chart showing the LoC test operation targeted by the model of FIG. The figure which shows the seed production | generation model which concerns on the 3rd Embodiment of this invention. The figure which shows the seed production | generation model which concerns on the 4th Embodiment of this invention. The timing chart which shows the test operation | movement of the LoS system made into object by the model of FIG. 7 (A). The figure which shows the sample circuit of 3 stage LFSR, the number of external inputs 2, and scan path length 3. The figure which shows an example of the time expansion | deployment of LFSR. The figure which shows an example of an XOR network. The figure which shows an example of a seed production | generation model. The figure which shows an example of the sample circuit which has a stuck-at fault. The figure which shows the seed production | generation example which concerns on one Embodiment of this invention. The figure which shows an example of the test production | generation by a conventional method, and seed conversion. The figure which shows a combination circuit. The figure which shows a sequential circuit. The figure which shows D type flip-flop. The figure which shows 0 degeneracy failure of AND gate input. The figure which shows test generation. The figure which shows the flip-flop by which the scan design was carried out. The figure which shows the sequential circuit by which the scan design was carried out. The figure which shows the structure of LFSR. The figure which shows the structure of 3 stage LFSR. The block diagram which shows the structure of BIST. The figure which shows BIST of the circuit by which the scan design was carried out. The figure which shows the circuit with a random pattern tolerance failure. The figure which shows the BIST model provided with the phase shifter. The figure which shows the BIST model provided with the random inversion circuit. The figure which shows the seed production | generation model with a phase shifter (static). The figure which shows the seed production | generation model (delay) with a phase shifter. The figure which shows the seed production | generation model with static inversion (static). The figure which shows the seed production | generation model (delay) with a random inversion. The figure for demonstrating a transition fault. LoC (broadside) timing chart. Time expansion model expression of LoC method test (broadside test). The timing chart of a LoS (skewed load) system. The figure which shows the seed production | generation model 1 for delay faults. Timing chart of seed generation model 1 The figure which shows detection rate transition with respect to b21-all failures. The figure which shows detection rate transition with respect to the undetected failure after b21-10k application. The figure which shows detection rate transition with respect to the undetected failure after b19-50k application. The figure which shows detection rate transition with respect to the undetected failure after b19-50k application.

  An embodiment of the present invention will be described below with reference to the drawings. The following embodiments are provided for the purpose of explaining the present invention, and do not limit the present invention. The present invention is limited only by the claims.

  FIG. 1 is a block diagram conceptually showing a conventional LFSR seed generation method of scan BIST. In the conventional method, first, a test pattern is generated by processing a net list of a circuit under test (CUT) by an automatic test pattern generation tool (ATPG). Next, the test pattern obtained in this way is subjected to seed conversion to obtain a seed for LFSR. As described above, in the conventional method, the seed of the LFSR is obtained through two-stage processing (two-pass) of test pattern generation and seed generation. However, in this method, there is a case where the test pattern cannot be converted into a seed, and as a result, there is a problem that the failure detection rate is lowered.

  In contrast to such a conventional two-pass seed generation method, the present inventors considered that all seeds can be created if seeds can be directly generated by ATPG without creating a test pattern from a netlist. .

  FIG. 2 is a block diagram conceptually showing the procedure of the one-pass seed creation method proposed by the present inventors. In this method, in order to directly create a seed by ATPG, first, a circuit to be manufactured (circuit under test, CUT) is artificially converted from the netlist into a circuit suitable for making a seed, and the converted circuit is converted. Apply ATPG to generate a seed. In FIG. 2, the converted circuit is shown as a seed generation model. By realizing this one-pass seed generation method, complete seed generation can be performed, and improvement in seed quality can be expected. In addition, since the effect of simulation can be expected, the number of seeds may be reduced.

  In the present invention, in order to realize the one-pass seed generation of FIG. 2, the LFSR used as a test pattern generator in the BIST and the state information of each scan FF of the sequential circuit that is a circuit under test are temporally expanded. An XOR (Exclusive-OR) network is constructed, and a seed generation model is proposed in which the XOR network is connected to the combinational circuit portion of the CUT.

  FIG. 3 is a block diagram showing the target BIST model. In FIG. 3, 1 is an LFSR, 2 is a circuit under test (CUT), and 3 is a response compressor (MISR). The CUT 2 includes a sequential circuit combinational circuit portion 20 and a scan FF chain 30. In the present invention, the response compressor 3 is not considered.

  FIG. 4 is a diagram showing a configuration of a seed generation model according to the first embodiment of the present invention. The model of the present embodiment is a base model and targets static failures. As shown in the figure, the seed generation model of this embodiment is a combinational circuit portion of an XOR network 10 configured by temporally expanding a BIST LFSR1 by the length of the longest scan path of a scan FF 30 (see FIG. 3). Connected to 20 inputs. Here, when the scan FF 30 is removed from the circuit under test (CUT) 2 shown in FIG. 3, the input from the original scan FF 30 to the combinational circuit portion 20 is set as a pseudo external input (PPIs). Are output to the scan FF 30 as pseudo external outputs (PPOs). This model can simulate the same operation as the scan BIST circuit in the test mode. Therefore, if an ATPG for a single stuck-at fault model or the like is applied to this seed generation model, as shown in FIG. 2, a seed for detecting a fault of the fault model without generating a test pattern for the CUT Can be obtained directly. The XOR network will be described later with reference to FIGS.

  The following FIG. 5A, FIG. 5B, FIG. 6 and FIG. 7A show seed generation models for delay fault detection. The seed generation model shown in FIG. 5A is a seed generation model 1 for delay fault LoC test, and FIG. 6 shows a seed generation model 2 for delay fault LoC test. Further, the model shown in FIG. 7A is a seed generation model for the delay fault LoS test.

  The model shown in FIG. 5A is a seed generation model for testing a delay fault by a launch-off capture (or broadside, hereinafter referred to as LoC) method, and shows a model corresponding to multi-clock capture. This model has a configuration in which a multiplexer 40 and a timing generation circuit 50 that temporally switches the inputs of the multiplexer 40 are added to the base model (XOR network 10 and combinational circuit portion 20) shown in FIG. The multiplexer 40 serves to switch the input signal to the combinational circuit portion 20 between the output of the XOR network 10 and the output of the scan FF 30. The multiplexer 40 is set to 1 during scan shift and when the first pattern is applied, and is set to 0 (0 during capture in multi-cycle capture) when the second pattern is applied.

  FIG. 5B is a diagram showing another example of the model shown in FIG. 5A, and is a model for detecting a delay fault by a two-pattern test (two-cycle capture). A circuit indicated by a dotted line 52 is an example of a timing generation circuit in the case of a two-pattern test. FIG. 5C is a timing chart of test pattern capture in the LoC test corresponding to the two pattern test.

  In the LoC test, first, the scan enable signal (SE) is set to 1 (scan shift mode), and the scan clock is applied for the cycle corresponding to the scan path length (the number of scan FFs in the longest scan path when there are multiple scan paths). Thus, the test pattern is set (shifted in) from the scan input (SI) to the scan FF, and at the same time, the value of the scan FF (response to the two-pattern test) is observed (shifted out) from the scan output (SO). The pattern set here corresponds to the first pattern of the two-pattern test. Next, SE is set to 0 (normal operation mode) and a normal clock is applied for two cycles. At this time, the value loaded in the FF in the first cycle becomes the second pattern of the two-pattern test. In addition, the value loaded in the FF in the second cycle becomes a response to the two-pattern test. The test is performed by repeating this. Note that a test in which a normal clock is input for two or more cycles in the normal operation mode is called a multi-cycle capture test.

  FIG. 6 shows a seed generation model 2 for LoC testing. This model includes an XOR network 10, a combinational circuit portion 20 of the circuit to be detected, and a second combinational circuit portion 20 ′ obtained by duplicating the combinational circuit portion 20. It is known that a test for a stuck-at fault can generate a two-pattern test for a delay fault. For this, a two-time expansion model is used. Duplicate two combinational circuit parts, PI is connected to the output of XOR network with both circuits, and two patterns test with only combinational circuit by connecting PPO of the first circuit and PPI of the second circuit Can be generated. For example, in order to consider that the test generation of the rising transition fault is performed on a signal line with the target circuit, the first combinational circuit has the same part as the signal line assuming the target circuit fault. It may be set to 0 and a test generation may be performed assuming a 0 stuck-at fault in the same part in the second combinational circuit.

  FIG. 7A shows a seed generation model for testing a delay fault by a launch-off shift (or skewed load, hereinafter, LoS) method. This model has a second XOR network 10 ′ configured by temporally expanding the LFSR 1 of FIG. 3 by the longest scan path length of the scan FF 30 plus one scan shift with respect to the base model of FIG. And a timing generation circuit 50 are added to select the output of the second XOR network 10 ′ in time and apply it to the combinational circuit portion 20. The model shown is compatible with multi-clock capture, but if a circuit that outputs 1 when the first pattern is applied and outputs 0 in synchronization with the second pattern capture clock is used as the timing generation circuit, it corresponds to the 2-pattern test. Model.

  FIG. 7B shows a timing chart of test pattern capture in the LoS test corresponding to the two-pattern test. In the LoS test, first, the scan clock is applied for the cycle corresponding to the scan path length in the scan shift mode, thereby shifting in the first pattern of the two pattern test from the scan input and simultaneously shifting out the response to the two pattern test. To do. Next, another cycle of the scan clock is applied in the scan shift mode. Here, the value set in the scan FF is the second pattern of the two-pattern test. Then, SE is set to 0 (normal operation mode) and a normal clock is applied for one cycle. Here, the value loaded in the FF becomes a response to the two-pattern test. However, the period from the last scan clock application to the application of the normal clock must be equal to the normal clock. The test is performed by repeating this.

Below, the seed production | generation model which concerns on each embodiment of this invention shown in FIGS. 4-7 is demonstrated still in detail.
First, the XOR network will be described.
FIG. 8 is a diagram illustrating a sample circuit having a three-stage LFSR, the number of external inputs of 2, and a scan path length of 3. In the figure, 81 is a three-stage LFSR, 82 is a CUT, 83 is a combinational circuit portion of the CUT 82, and 84 is a scan path of the CUT 82. The LFSR is composed of XOR and FF. Accordingly, when the state information of the scan path 84 is developed in terms of time, the circuit under test can be considered as a combinational circuit without FF. Therefore, each scan FF at a certain time and the value of the external input can be expressed as a seed function.

  9 shows that the seeds of the LFSR 81 in FIG. 8 are (FF0, FF1, FF2) = (S0, S1, S2), and each FF ( (SFF0, SFF1, SFF2) values are developed in terms of time as described above and expressed only by seeds. As shown in the figure, the value of the seed input to the LFSR 81 and the value of the external input to the combinational circuit portion 83 have a dependency, and therefore this relationship can be expressed in the logic circuit. A structure in which the structure of the LFSR and the scan path is expanded in this way is called an XOR network. FIG. 10 shows an XOR network 101 formed based on the input / output relationship of FIG.

  FIG. 11 is a diagram showing a seed generation model configured by connecting the XOR network 101 shown in FIG. 10 to the combinational circuit portion 83 of the CUT, and the base model shown in FIG. 4 is applied to the sample circuit of FIG. Is. Thus, by extracting only the combinational circuit portion 83 of the CUT and connecting the XOR network 101 to its input, the same operation as the scan BIST circuit in the test mode can be simulated, and ATPG is applied to this model. Thus, the seed can be directly obtained. As a result, it is not necessary to generate a test with don't care, and the number of patterns can be suppressed as compared with the conventional method. In addition, it is not necessary to perform a fault simulation again in order to check how many faults can be detected by the seed generated in the process of generating seeds. Therefore, there is also an advantage that the seed generation time can be reduced. These points are evaluated experimentally. The effectiveness of the method of the present invention will be introduced as a result of evaluation by an experiment using an ITC'99 benchmark circuit in an experimental example described later.

  FIG. 12 is a diagram showing a sample circuit having a three-stage LFSR, an external input number of 2, and a scan path length of 3, and has one stuck-at fault in the combinational circuit portion. FIG. 13 shows an example in which a seed for a target failure is generated by a seed generation model formed for the circuit of FIG. FIG. 14 shows an example of test generation and seed conversion according to the conventional method, and shows a case where the test pattern: (0, X, X, 1, 1) cannot be converted into a seed.

  In order to facilitate the understanding of the present invention, various definitions such as scan BIST: built-in self-test method, LFSR: linear feedback shift register (LFSR), and examples related to the present invention will be described below. Will be described.

  FIG. 15A shows a combinational circuit, and FIG. 15B shows a sequential circuit. A circuit that can be expressed as a combination of an input value, an output value, and an internal state value of 0 or 1 is called a logic circuit. The logic circuit can be further classified into a combinational circuit (a) and a sequential circuit (b). In the combinational circuit, the output value of the circuit is determined only by the input value at that time, and in the sequential circuit, it is not determined only by the input value but depends on the internal state of the circuit. As shown in FIG. 15A, the combinational circuit is composed of only a combinational circuit portion 152. PI and PO represent external input and external output, respectively. As shown in FIG. 15B, the sequential circuit includes a state storage portion configured by a combinational circuit portion 152 and a plurality of flip-flops (FF) 155. In the sequential circuit, the output is determined by the value of the input applied at that time and the value of the internal state. The internal state changes to the internal state at the next time depending on the input and the internal state at that time. In this embodiment, the D-type flip-flop 166 shown in FIG. 16 is handled. The FF 166 has a data input (D), a data output (Q), and a clock input (CLK), and takes in data by a clock signal.

  If there are physical defects in the elements that make up the circuit, the circuit will not operate correctly. Such physical defects are called circuit failures. Faults are treated as fault models that model the effects of circuit faults. A failure model in which the logic function of a logic circuit changes to another logic function due to a failure is called a logic (static) failure. A typical static fault model is a stuck-at-fault. The stuck-at fault is a fault in which the value of the signal line in the circuit is fixed to 1 or 0. A fault that is fixed at 1 is called 1 stuck-at fault (stack-at-1, sa-1). The fixed fault is referred to as 0 stuck-at fault (stack-at-0, sa-0). As an example of a stuck-at fault, consider the circuit shown in FIG.

  In the AND circuit 177 of FIG. 17, when 1 is applied to each of the signal lines x and y, if there is no failure, 1 is output to the signal line z, but if sa-0 exists on x 0 is output. In addition to the stuck-at fault, many models such as a bridge fault, a delay fault, and a transistor fault are considered as fault models.

  Checking whether a logic circuit is manufactured as designed is called “testing”. The test consists of two processes, test generation and test application. The test generation assumes a failure, and sets (activates) a value opposite to the failure value for the failure location. Find the test pattern that propagates the value to the external output. In the test execution, the test pattern obtained by the test generation is applied to the circuit, and the output response is compared with the expected value to determine whether or not there is a failure.

  For example, consider test generation of a circuit in which the signal line F shown in FIG. 18 is sa-0. A and B become 1 to activate sa-0. In order to propagate the value as an error signal to an external output, it is necessary to set G to 0 and I to 1. To set G to 0, either C or D is 0, the other is don't care (X), and E is 0 to set I to 1. From the above, it can be seen that one of the test patterns for detecting sa-0 of the signal line F is (A, B, C, D, E) = (1, 1, 0, X, 0).

  Test evaluation measures include failure detection rate and failure detection efficiency. The failure detection rate is the number of failures detected among the target failures, and is expressed by Equation 1.

  The fault detection efficiency indicates how many faults that were identified as faults that could not be detected by the I / O support, called redundant faults, in addition to how many faults were detected. It is a ratio and is expressed by Equation 2.

  FIG. 19 shows an example of a scan-designed FF. One design for testability is scan design. In the scan design, a scan input (scan in) is provided so that the FF 191 can be directly input from the outside, and the data input (Din) and the scan input during normal operation are switched by the multiplexer (MUX) 192 so that the FF 191 can be input. . The output of the FF 191 can be observed from the scan output (scan out). If a scan input / output terminal is prepared for each FF 191, an extra terminal is required twice as many as the FF 191, which is not practical. Therefore, the FF 191 is connected in a row so that it can operate as a shift register. A set of FFs designed for scanning in this way is called a scan path.

  FIG. 20 shows an example of a sequential circuit designed by scanning. In the scan-designed sequential circuit, the FF 191 can be operated as a shift register, so that each FF 191 can be easily set to an arbitrary state and at the same time the state can be observed. Therefore, the problem of test generation of a scan-designed circuit can be handled as a problem of a combinational circuit.

FIG. 21 shows an example of the LFSR.
As a built-in self-test (BIST) test pattern generation circuit, a linear feedback shift register (LFSR: linear feed-shift shift register) is mainly used. In the illustrated LFSR model, when ci = 0, there is no feedback to XOR, and when ci = 1, there is feedback to XOR. The feedback position to XOR can be expressed by a polynomial, and the polynomial is called a characteristic polynomial. The characteristic polynomial of LFSR in FIG.

  When a primitive polynomial is used in this equation, all patterns except for all zero patterns can be generated pseudo-randomly. Accordingly, a pseudo-random test or an exhaustive test in which a pattern other than all 0 is applied can be performed using the LFSR.

  In the LFSR shown in FIG. 21, the FF value at the next time t + 1 can be expressed by the following equation 4 using the FF value at a certain time t and the characteristic polynomial.

  As an example of the LFSR, FIG. 22 shows a 3-bit LFSR. Table 1 shows the operation results when the value of FF at time 0 is used as a seed and the values are set as (FF0, FF1, FF2) = (0, 1, 0).

  From the results in Table 1, it can be seen that patterns other than all 0 can be generated.

  There is a built-in self-test (BIST, built-in self-test) method as a design method for simplifying the external test apparatus. In the BIST system, a circuit that generates a test pattern and a circuit that checks an output response to the test pattern are used, and the pattern generation circuit mainly uses LFSR.

  FIG. 23 shows a schematic diagram of the BIST. In BIST, a test pattern is generated by the pattern generation circuit 230, applied to the circuit 231 to be inspected, and the output is compared with an expected value by a response analyzer (MISR) 231, thereby determining whether or not there is a failure and a failure state. Check. As the pattern generation circuit 230, for example, the above LFSR is used.

  FIG. 24 shows a BIST of a scan designed circuit. Reference numeral 244 denotes an LFSR as a pattern generator, 246 denotes a combinational circuit portion in the sequential circuit, 248 denotes a scan path composed of FFs in the sequential circuit, and 250 denotes a MISR as a response analyzer. In this BIST, the LFSR 244 is moved until the value is satisfied in the scan path 248, and the value of the scan path 248 and the value of PI at that time are applied to the combinational circuit portion 246 of the circuit to be inspected to perform a pseudo random test. . In the present invention, the BIST having this structure is used as the BIST model of the present application as shown in FIG.

  A problem with BIST is that it is difficult to detect a random pattern tolerance failure. As an example, a circuit in which the signal line E in FIG. 25 is sa-0 is shown. The pattern for detecting a failure needs to be a pattern in which all four inputs are 1, but in the case of a 4-bit LFSR, the probability that this pattern is generated is 1/15. Of the patterns that can be generated by the LFSR, a failure that can be detected with only a limited number of patterns is called a random pattern tolerance failure. It is known that resetting the seed of the LFSR (referred to as reseeding) is effective for detecting a random pattern tolerance failure by BIST.

  In the pseudo-random pattern test by LFSR, generally, there is a dependency of the value between FFs in a scan path, or between an external input and a scan path. One technique for reducing this dependency is to use a phase shifter. The phase shifter is a circuit created using XOR arranged at the output of the LFSR, and changes the order of patterns generated by the LFSR. Further, as with the phase shifter, there is a method using a random inversion circuit as a technique for reducing the dependency between FFs, external inputs, and scan paths.

  A schematic diagram of an example of a BIST configuration in the case of using a phase shifter is shown in FIG. In FIG. 26A, reference numeral 200 denotes a phase shifter that functions to change the order of patterns generated by the LFSR 1 as described above.

  A schematic diagram of an example of a BIST configuration in the case of using a random inversion circuit is shown in FIG. The BIST includes a circuit to be inspected (CUT) 2, a scan path enabling the scan, and a first pattern generation circuit 1 for forming a test pattern supplied to the scan path. The random inversion circuit uses a pattern generated by a second pattern generation circuit 1b provided separately from the first pattern generation circuit 1 to change a pattern generated by the first pattern generation circuit 1 The pattern control circuit includes an inversion logic unit 266 that can invert the logic of the output value of the first pattern generation circuit 1 and the inversion logic unit using a pattern generated by the second pattern generation circuit 1b. An inverting control circuit 268 capable of controlling the operation of 266 is included, and the output signal of the inverting logic unit 266 is supplied to the circuit under test 2. Specifically, whether the value generated by the first pattern generation circuit 1b is inverted is determined by the number of 1 values generated by the second pattern generation circuit 1b and the value of the inversion condition setting REG270. The random inversion circuit includes the second pattern generation circuit 1b, the inversion logic unit 266, the inversion control circuit 268, and the inversion condition setting REG270.

  FIGS. 26C and 26D show a seed generation model corresponding to the BIST model with a phase shifter shown in FIG. FIG. 26C shows a seed generation model with a phase shifter for static faults, in which a phase shifter group 200a is inserted between the XOR network 10 and the combinational circuit portion 20 with respect to the base model shown in FIG. Have. The phase shifter group 200a is a circuit in which the phase shifter 200 shown in FIG. 26A is copied for the scan path length and arranged in parallel. Strictly speaking, the phase shifter group 200a in FIGS. 26C and 26D is obtained by deleting the phase shifter 200 shown in FIG. 26A and the XOR connected to the PI of the phase shifter 200 (connected to SI). This is a circuit in which the scan path length minus one is copied. FIG. 26D is a seed generation model with a phase shifter for a delay fault LoC test. In the seed generation model shown in FIG. 5A, a phase shifter group 200a is connected to the output of the XOR network 10. It has a configuration.

  FIGS. 26E and 26F show a seed generation model corresponding to the BIST model with a random inversion circuit shown in FIG. FIG. 26E shows a seed generation model with a random inversion circuit for static faults. The second XOR network 10a, inversion logic circuit group 266a, and inversion control circuit group 268a are compared to the base model shown in FIG. Is provided. The inversion logic circuit group 266a is a circuit in which the inversion logic unit 266 shown in FIG. 26B is copied for the scan path length and arranged in parallel. Similarly, the inversion control circuit group 268a is connected to the inversion control circuit 268 in the scan path. This is a circuit that is copied for a long time and arranged in parallel. The second XOR network 10a is configured by expanding the LFSR constituting the second pattern generation circuit 1b by the time corresponding to the scan path length of the scan FF. The first seed input to the (first) XOR network 10 is the seed of the first pattern generation circuit 1 in FIG. 26B, and the second seed input to the second XOR network 10a. Becomes a seed input to the second pattern generation circuit 1b of FIG.

  FIG. 26F shows a seed generation model with a random inversion circuit for a delay fault LoC test. The seed generation model shown in FIG. 5A has a second XOR network 10a and an inversion control circuit group 268a. In this configuration, a random inversion circuit group including an inversion logic circuit group 266a is added. As in the model of FIG. 26E, the seed input to the (first) XOR network 10 is the seed of the first pattern generation circuit 1, and the seed of the second XOR network 10a is the second pattern. It becomes a seed for the generation circuit 1b.

Hereinafter, the seed generation model for detecting a delay fault shown in FIGS. 5A to 7B will be described in more detail.
[Delayed fault model and test method]
With the recent increase in VLSI speed, not only logic failures but also delay failures, which are failure models related to timing, are becoming more important. A delay fault is a fault model in which a signal cannot be propagated within a specified time due to a delay of a gate or a signal line, resulting in a malfunction. Delay faults include transition faults, gate delay faults, and path delay faults. In the following description, transition faults are targeted, but the present invention is not limited to this.

  FIG. 27 shows an example of transition failure. Assuming that a transition fault is caused by a delay fault in a certain signal line in the circuit, it is assumed that a delay sufficiently large to be observed by an external output or FF occurs regardless of the path through which the delay propagates. There are two types of transition faults: rising transition faults with delayed signal rise and falling transition faults with delayed delay.

  In the transition fault test, first, the value of a signal at a target location is set, and then the value is changed, propagated to an external output or FF, and the response is observed. For example, a pattern that sets the signal line of the first pattern to 0 (low) is applied, and a pattern that sets the signal line to 1 (high) is applied to the second pattern to propagate to the external output or FF. If a change in value is observed, a rising transition failure of the signal line can be detected. Such a test method is called a two-pattern test.

  There are a LoC method and a LoS method as representative methods for performing a two-pattern test at an actual speed (at-speed) in a scan designed circuit. In the LoC test, the first pattern is set by the scan operation, and then the second pattern is set at the actual speed and the response is stored in the FF by the system clock (FIG. 28). This operation is called capture. The first pattern is set in consideration of using the internal state for the signal set in the second pattern FF. FIG. 29 shows a time expansion model in which the operation of the LoC method test is expanded for each time. The LoC timing chart shown in FIG. 28 corresponds to the timing chart for explaining the operation of the delay fault LoC test seed generation model 1 shown in FIG.

  FIG. 30 shows a basic timing chart of the delay fault test by the LoS method. This timing chart is basically the same as the timing chart (FIG. 7B) for explaining the operation of the delay fault LoS test seed generation model according to the embodiment of the present invention shown in FIG. Therefore, the details of the operation of the LoS system test can be the same as those described in the description section of FIGS. 7 (A) and 7 (B).

Delayed fault seed generation model 1
FIG. 31 shows a seed generation model 1 for delay faults. FIG. 32 shows a delay of the control signal m1 of the multiplexer of the seed generation circuit in the LoC method test. The delay fault seed generation model 1 in FIG. 31 is another embodiment of the delay fault seed generation model in FIG.

  In order to generate a two-pattern test for the LoC method test, it is necessary to consider two times. For this purpose, a circuit is added to the scan enable terminal and the scan FF of the target circuit, and the XOR network 10 is connected. An OR gate and FF are sequentially added and connected to the scan enable terminal, the output of the added FF is branched, a NOT gate is added, and this is used as another input of the OR gate. These OR gate, FF and NOT gate form a timing generation circuit.

  In addition, a multiplexer is added to the output of the scan FF. The multiplexer control signal is the output of the FF added to the scan enable. The input of the multiplexer is an external input connecting the XOR network and an output from the scan FF. By adding a circuit, the XOR network 10 can be selected as the PPI for the first pattern and the scan FF can be selected for the second pattern in the two-pattern test.

  In the case of a BIST configuration using a phase shifter and a random inversion circuit, a LoC delay fault seed generation model corresponding to them is required. These models are as described above with reference to FIGS. 26D and 26F.

Delayed fault seed generation models 2 and 3
FIG. 6 shows a delay fault seed generation model 2 and FIG. 7A shows a delay fault seed generation model 3 for LoS test.

  According to the LFSR seed generation method of the present invention using the seed generation model (base model) for static faults and the seed generation models 1 to 3 for delay faults described above, seed generation is impossible with the seed generation model. It is assured that the fault (which has been found to have no seed) cannot be detected by the original BIST circuit. Therefore, the failure detection capability of the BIST mechanism can be known. Further, without converting the test pattern once generated into a seed, by providing a constraint on test generation, a seed can be directly generated using a test generation tool. In the conventional method, test generation and seed conversion work are repeated until seed conversion is possible. Therefore, in order to obtain the same failure detection rate as that in the proposed method, it is considered that test generation is repeated many times and takes time.

[Evaluation]
First, the effectiveness of the proposed method by the seed generation model for static faults is shown by experiments.
Table 2 shows the experimental environment. An ITC '99 benchmark circuit was used as an experiment target circuit, and a seed generation experiment was conducted for a random pattern resistance fault (RPRF). RPRF applies a 10,000 pattern and sets it as an undetected failure. Table 3 shows the circuit characteristics of the ITC'99 benchmark circuit.

  In Table 3, #PIs, #POs, #Gates, and #FFs represent the number of external inputs, the number of external outputs, the number of gates, and the number of FFs, respectively.

  For the benchmark circuit b_19, circuits in which the number of scan paths is divided into 6, 13, and 22 are prepared, and circuit names are expressed as b19_scan6, b19_scan13, and b19_scan22, respectively.

  The experimental method is shown below. First, a 10,000 pseudo random pattern is generated by LFSR with an appropriate seed, and a failure simulation is performed on the circuit to be inspected with the generated pattern. Next, as a result of fault simulation, faults that have not been detected are determined as random pattern tolerance faults (RPRF), and seeds are obtained for those faults using the conventional method and the proposed method, respectively. Compare seed generation time and number of seeds. Moreover, the case where a phase shifter was added to the LFSR was also evaluated. For test generation in this experiment, the abort time was set to 10 seconds. The abort time is the upper limit of the time taken to generate one pattern. The LFSR used was the case where the random inverting circuit was not attached and the first pattern generating circuit when the LFSR was attached, and the 100 stage LFSR was used as the second pattern generating circuit of the random inverting circuit. In addition, the phase shifter with the phase shifter is designed so that the input of each scan path is shifted in phase by more than the scan path length so that the same partial sequence generated from the LFSR does not enter a plurality of scan paths. The conversion to seeds in the conventional method employs a method of solving SAT, and MiniSAT is used as the SAT solver.

  Table 4 shows the result of failure simulation with 10,000 pseudo-random patterns using LFSR.

When seeds were generated by the conventional method and the proposed method for undetected faults in Table 4, the results shown in Table 5 were obtained.

  In the experiment, it was confirmed that the conventional method could not convert a part of the test generated pattern into a seed and the failure detection rate was lowered. Also, from Table 5, the fault detection rate was higher with the proposed method for all circuits. It can be seen that the proposed method is superior to most circuits in terms of seed generation time.

  Next, the conventional method and the proposed method when a phase shifter is added to the LFSR will be considered. Table 6 shows the result of failure simulation using a 10,000 pseudo random pattern using an LFSR with a phase shifter.

  Table 7 shows the results of seed generation by the conventional method and the proposed method for the undetected faults in Table 6.

  From Table 7, it can be seen that, even when a phase shifter is added, the proposed method can obtain seeds at a higher speed in most circuits, and the number of seeds can be smaller than that of the conventional method. Furthermore, it can be seen that the proposed method is superior in terms of failure detection rate.

  Next, a conventional method and a proposed method when a random inverting circuit is attached to the LFSR will be considered. Table 8 shows the result of a failure simulation using a 10,000 pseudo-random pattern using an LFSR with a random inversion circuit.

  Table 9 shows the results of seed generation by the conventional method and the proposed method for the undetected faults in Table 8.

  Next, the effectiveness of the proposed method using the seed generation model 1 for delay faults is shown by experiments. The circuits used in the experiment are ITC'99 benchmark circuits b14, b17, b18, b19, b20, b21, and b22. The experimental environment is the same as shown in Table 2.

  The following Table 10 to Table 15 describe the evaluation of seed quality by the seed generation model 1 for delay fault. Tables 10 and 11 show the evaluation environment and circuit characteristics of the benchmark circuits b14, b17, b18, b19, b20, b21, and b22.

  Table 11 shows seed generation target failures. The number of undetected failures after application of the initial pseudo-random pattern is shown.

  Table 12 shows the experimental results for the seed quality alone. Here, the undetected failure after applying the 10,000 pseudo-random pattern is the seed generation target.

In Table 12,
Result of failure simulation when developing one pattern from each seed% FC:% FC,% FE: ATPG report at the time of seed generation.

  Table 13 shows test generation with don't care and seed conversion, and undetected faults after the application of 10,000 pseudo-random patterns are seed generation targets. The loss of failure detection rate due to failure to convert to seed by conventional method is shown.

  Table 14 shows the cumulative failure detection rate / detection efficiency. This result shows a case including 10,000 pseudo random pattern application. Undetected failures after application of 10,000 pseudo-random patterns are seed generation targets.

  Tables 15 to 20 and FIGS. 33 to 36 below show experimental results of seed development quality of seeds generated using the seed generation model 1 for delay faults.

  Table 15 shows the experimental results of seed quality (128 pattern development). In this experiment, the seeds are rearranged so that the rise of the detection rate is the earliest, seed generation target faults (only representative faults), all faults for b21, and undetected faults after application of 10,000 (10k) pseudorandom patterns B19 was regarded as an undetected failure after applying a 50,000 (50k) pseudo-random pattern.

  Table 16 shows the seed generation status.

  FIG. 33 shows the transition of the detection rate for all b21 failures.

  The experimental results in Table 16 show the detection rate transition for all failures of b21. From this table, the maximum detection rate that can be achieved by the conventional method is 86%, and in the proposed method, the number of seeds required to reach the same detection rate can be reduced by 12% (test time is reduced by 12%).

  The experimental result shown in FIG. 34 shows the transition of the detection rate with respect to the undetected failure after application of the 10k pseudo-random pattern of b21.

  The experimental results in Table 18 show the transition of the detection rate with respect to undetected faults after application of the b21 10k pseudo-random pattern. The maximum detection rate achieved by the conventional method was 85%, and the proposed method was able to reduce the number of seeds required to reach the same detection rate by 44% (test time was reduced by 44%).

  The experimental result shown in FIG. 35 is a diagram showing the transition of the detection rate with respect to the undetected fault after applying the 50k pseudo-random pattern of b19.

  The experimental result shown in Table 19 shows the transition of the detection rate for the undetected failure after applying the bk pseudo-random pattern of b19. The maximum detection rate that can be achieved by the conventional method is 65%, and in the proposed method, the number of seeds required to reach this detection rate can be reduced by 25% (test time is reduced by 25%).

  The experimental results shown in FIG. 36 show the transition of the detection rate for the undetected failure after applying the bk 50k pseudo-random pattern of b19.

  The experimental result shown in Table 19 shows the transition of the detection rate for the undetected failure after applying the bk pseudo-random pattern of b19. In this experiment, it takes time to rearrange all seeds, so only 5,000 (5k) seeds that were generated first were used.

  Table 20 shows that the proposed method is significant even when only the 5k seeds generated at the beginning are used. The maximum detection rate that could be reached by the conventional method was 56%, and the number of seeds required to reach this detection rate by the proposed method could be reduced by 28% (test time was reduced by 28%).

1 LFSR
2 Circuit under test (CUT)
3 Response compressor (MISR)
10 XOR network 20 Combinational circuit part 30 Scan FF
40 multiplexer 50 timing generation circuit

Claims (17)

Forming a seed generation model for scan BIST;
Each step of generating a LFSR seed by performing test generation of a target fault on the formed seed generation model,
The seed generation model includes an XOR network configured by expanding the LFSR of the scan BIST by a time corresponding to the scan path length in the scan FF of the circuit to be inspected, and a combinational circuit part of the circuit to be inspected. A scan BIST LFSR seed generation method having a configuration in which the XOR network output is connected.   The method according to claim 1, wherein the seed generation model is a LFSR seed generation method for a scan BIST, in which a phase shifter group is connected between the XOR network and a combinational circuit portion of the circuit under test.   2. The method according to claim 1, wherein the seed generation model includes a random inverting circuit group connected between the XOR network and a combinational circuit portion of the circuit under test.   4. The method according to claim 3, wherein each of the random inverting circuits of the random inverting circuit group includes an inverting logic circuit inserted between the XOR network and a combinational circuit portion of the circuit under test, and a second XOR. A scan BIST LFSR seed generation method comprising: a network; and an inversion control circuit for controlling an operation of the inversion circuit using an output of a second XOR network.   5. The method according to claim 1, wherein the target fault is a static fault.   2. The method according to claim 1, wherein the seed generation model further includes a multiplexer for temporally switching the XOR network output and the scan FF output and inputting the output to the combinational circuit portion, and timing for switching the multiplexer. A method for generating a LFSR seed for a scan BIST.   7. The method of claim 6, wherein the seed generation model further comprises a phase shifter group connected to the XOR network output, the output of the phase shifter group being input to a combinational circuit portion of the circuit under test and the multiplexer. LFSR seed generation method for scan BIST.   7. The method of claim 6, wherein the seed generation model further comprises a random inverting circuit group connected to the XOR network output, the output of the random inverting circuit group being a combinational circuit portion of the circuit under test and the multiplexer. LFSR seed generation method of scan BIST input to   9. The method according to claim 8, wherein each of the random inverting circuits in the random inverting circuit group includes an inverting logic circuit inserted between the XOR network and a combinational circuit portion of the circuit under test, and a second XOR. A scan BIST LFSR seed generation method comprising: a network; and an inversion control circuit for controlling an operation of the inversion logic circuit using an output of a second XOR network.   2. The method of claim 1, wherein the seed generation model further comprises a second combinational circuit portion that is a duplicate of the combinational circuit portion, the input of the second combinational circuit portion being an output of the XOR network. And an output of the combinational circuit portion are connected to each other.   2. The method according to claim 1, wherein the seed generation model further includes a second XOR network configured by time-expanding the LFSR by the scan path length + 1 scan shift, the XOR network output, and the second XOR. A scan BIST LFSR seed generation method, comprising: a multiplexer for switching a network output in time and inputting the output to the combinational circuit portion; and a timing generator for controlling a switching timing of the multiplexer.   12. The method according to claim 6, wherein the target fault is a delay fault.   The method according to claim 1, wherein the test generation of the target fault is performed using an automatic test pattern generation tool. Procedure for forming an XOR network by expanding the LFSR of the scan BIST for the scan path length in the scan FF of the circuit to be inspected to form an XOR network, and forming the seed generation model by connecting the XOR network to the combinational circuit portion of the circuit to be inspected When,
A storage medium for storing a program for causing a computer to execute a test generation of a target failure on the seed generation model and generate a seed of the LFSR. An XOR network formed by expanding the LFSR of the scan BIST by the time corresponding to the scan path length in the scan FF of the circuit to be inspected, and a combinational circuit portion of the circuit to be inspected by temporally switching between the XOR network output and the scan FF output A step of forming a seed generation model by a multiplexer applied to and a timing generator for controlling a switching timing of the multiplexer;
A storage medium for storing a program for causing a computer to execute a test generation of a target failure with respect to the seed generation model and form a seed of the LFSR. An XOR network constructed by expanding the LFSR of the scan BIST by the time corresponding to the scan path length in the scan FF of the circuit to be inspected, a combinational circuit part of the circuit to be inspected, and a second combinational circuit part replicating the combinational circuit part Connecting the XOR network output to an input of the combinational circuit portion and connecting the XOR network output and the combinational circuit portion output to an input of the second combinational circuit portion to form a seed generation model When,
A storage medium for storing a program for causing a computer to execute a test generation of a target failure with respect to the seed generation model and form a seed of the LFSR. An XOR network constructed by expanding the LFSR of the scan BIST by the time corresponding to the scan path length in the scan FF of the circuit to be inspected, the combinational circuit portion of the circuit to be inspected, and the LFSR by time expansion corresponding to the scan path length + 1 scan shift. A second XOR network configured as described above, a multiplexer that temporally switches the XOR network or the second XOR network output and applies it to the combinational circuit portion, and a timing generator that controls the switching timing of the multiplexer A procedure for forming a seed generation model;
A storage medium for storing a program for causing a computer to execute a test generation of a target failure with respect to the seed generation model and form a seed of the LFSR.

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