JP6388332B2 - Memory inspection system and memory inspection method - Google Patents

Description

The present invention relates to a memory inspection system and a memory inspection method .

In order to verify the operation of a manufactured memory device, operation verification using a memory aging system is generally performed (for example, Patent Document 1). The memory aging system is a so-called tester that repeatedly writes data to and reads data from a connected memory device to be inspected to verify whether the data is normally read or written. A predetermined control device is mounted on the memory aging device, and the operation verification is performed by the control device operating according to an operation verification program incorporated in advance.
In order to verify whether the memory device operates normally even in a high temperature environment (or low temperature environment), the memory aging system is operated in a high temperature environment or a low temperature environment. There is also.

JP 2003-014821 A

  However, when a test is performed in a special environment such as high temperature or low temperature using a memory aging system, the characteristics change due to the memory aging system itself being placed in a special environment, which is the inspection target. In some cases, the operation verification of the memory device could not be performed correctly.

An object of the present invention is made in view of the above problems, and is a memory inspection system and a memory inspection method capable of accurately inspecting a memory to be inspected even when placed in various environments. Is to provide.

  According to one aspect of the present invention, an address designation unit that outputs an address designation signal for designating an address to a memory, a latch signal output unit that outputs a first latch signal synchronized with the address designation signal, and the memory A data input unit for receiving an input of a data signal corresponding to the designated address; and a second latch signal obtained by delaying the first latch signal by a time corresponding to a delay time of the data signal with respect to the address designation signal. A memory test control device includes: a latch signal input unit that receives an input; and a data reading unit that reads data indicated by the data signal based on a timing specified by the second latch signal.

  In one embodiment of the present invention, the input of the first latch signal is received according to the above-described memory test control device, and the first latch signal is set in accordance with the delay time of the data signal with respect to the address designation signal. And a delay generation unit that outputs the second latch signal delayed by time.

  According to another aspect of the present invention, there is provided a step of outputting an address designation signal for designating an address to the memory, a step of outputting a first latch signal synchronized with the address designation signal, and the designation from the memory. Receiving an input of a data signal corresponding to the address, receiving an input of a second latch signal obtained by delaying the first latch signal by a time corresponding to a delay time of the data signal with respect to the address designation signal; Reading data indicated by the data signal based on timing designated by the second latch signal.

  According to another aspect of the present invention, there is provided an address designating unit for outputting an address designating signal for designating an address to a memory, and a latch for outputting a first latch signal synchronized with the address designating signal. A signal output means, a data input means for receiving an input of a data signal corresponding to the designated address from the memory, and the first latch signal is delayed by a time corresponding to a delay time of the data signal with respect to the address designation signal. In addition, the program functions as latch signal input means for receiving the input of the second latch signal and data reading means for reading the data indicated by the data signal based on the timing specified by the second latch signal.

According to the memory inspection system and the memory inspection method described above, it is possible to accurately inspect a memory to be inspected even when placed in various environments.

It is a figure which shows the function structure of the control apparatus for memory inspection which concerns on 1st Embodiment. It is a figure which shows the function structure of the memory test | inspection system which concerns on 1st Embodiment. It is the 1st figure explaining the function of the memory inspection system concerning a 1st embodiment. It is a 2nd figure explaining the function of the memory test | inspection system which concerns on 1st Embodiment. It is a figure which shows the function structure of the memory test | inspection system which concerns on 2nd Embodiment.

<First Embodiment>
Hereinafter, a first embodiment will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a functional configuration of the memory inspection control device according to the first embodiment.
The memory test control device 10 shown in FIG. 1 includes an address designating unit 101, a latch signal output unit 102, a data input unit 103, a latch signal input unit 104, and a data reading unit 105.
The address specifying unit 101 outputs an address specifying signal L1 for specifying an address to the memory to be inspected. Here, the “address” is information for specifying a storage location of data stored in the memory.
The latch signal output unit 102 outputs a first latch signal L1 synchronized with the address designation signal Sa. Here, “synchronize” means from high to low and from low to high so that the period of a predetermined clock signal that is a reference in a logic signal that takes a binary (High, Low) value coincides with the cycle. This means that the value transitions.
The data input unit 103 receives an input of the data signal Sd corresponding to the address specified by the address specification signal Sa from the memory to be inspected.
The latch signal input unit 104 uses the first latch signal L1 output from the latch signal output unit 102 as a delay time of the data signal Sd input to the data input unit 103 with respect to the address specifying signal Sa output from the address specifying unit 101. The input of the second latch signal L2 delayed by a time corresponding to is accepted. Here, the “delay time” is information indicating the degree of temporal deviation between the value transition timing in the addressing signal Sa and the value transition timing in the data signal Sd.
The data reading unit 105 reads the data indicated by the input data signal Sd based on the timing specified by the second latch signal L2.

FIG. 2 is a diagram illustrating a functional configuration of the memory inspection system according to the first embodiment.
As shown in FIG. 2, the memory inspection system 1 includes the above-described memory inspection control device 10, a connector 11, a delay generation unit 20, and buffers 201, 202, 203, and 204.
The memory inspection control device 10 is a logic circuit mounted on a test board of the memory inspection system 1 and is realized by, for example, a CPLD (Complex Programmable Logic Device). The memory inspection control device 10 which is a CPLD stores in advance an operation program for operation verification on the memory 3 to be inspected. The memory inspection control apparatus 10 verifies the soundness and reliability of the operation of the memory 3 by repeatedly reading and writing the memory 3 to be inspected according to the program.

The connector 11 is an interface that enables connection of the memory 3 to be inspected.
The delay generation unit 20 receives an input of the first latch signal L1 output from the memory test control device 10 (latch signal output unit 102) and delays the first latch signal L1 by a predetermined time. The signal L2 is output. Here, the time that the delay generating unit 20 delays corresponds to the delay time of the data signal Sd input to the data input unit 103 with respect to the address specifying signal Sa output from the address specifying unit 101. A specific configuration of the delay generation unit 20 will be described later.
The second latch signal L2 output from the delay generation unit 20 is input to the memory test control device 10 (latch signal input unit 104).

When the memory 3 to be inspected receives the input of the address designation signal Sa output from the memory inspection control device 10, the memory 3 reads the data stored at the location designated by the address indicated by the address designation signal Sa. Then, the memory 3 outputs a data signal Sd indicating the read data. The data signal Sd is input (returned) to the memory inspection control device 10 and used for soundness determination.
The address designation transmission wiring Pa is a wiring for transmitting the address designation signal Sa from the memory inspection control device 10 to the memory 3 to be inspected. The data transmission wiring Pd is a wiring for transmitting the data signal Sd from the memory 3 to the memory inspection control device 10. Each of the addressing transmission line Pa and the data transmission line Pd forms an address bus and a data bus each having a plurality of wirings bundled together (not shown in FIG. 2).

The buffers 201 to 204 are logic circuits that act as relays of logic signals, and include, for example, inverters formed by combining transistors. In general, a signal intensity (voltage) of a logic signal is attenuated due to a voltage drop while being transmitted through a transmission line. Therefore, by connecting one or a plurality of buffers (inverters) in series to the transmission line, the signal intensity of the logical signal transmitted through the transmission line is amplified and transmitted with the correct logical value.
As shown in FIG. 2, the buffers 201 and 202 are provided in series on the addressing transmission line Pa. The buffers 203 and 204 are provided in series on the data transmission line Pd.
Here, each of the buffers 201 to 204 is constituted by a bundle of a plurality of inverters, and is connected so as to correspond to each of the wirings constituting the address bus and the data bus. For example, the buffers 201 to 204 are constituted by a bundle of 32 inverters so as to be compatible with a 32-bit address bus and data bus. In the present embodiment, the plurality of inverters are all formed of transistors having the same structure. The “structure” of a transistor is a characteristic defined by the transistor manufacturing process, design size, and the like. That is, the transistors constituting each of the buffers 201 to 204 are manufactured with the same manufacturing process and the same design size at least within the range belonging to the bundle.

Next, a specific configuration of the delay generation unit 20 will be described in detail.
As shown in FIG. 2, the delay generator 20 is configured by a delay transmission line Pn. The delay transmission wiring Pn is a wiring that transmits the first latch signal L1 output from the latch signal output unit 102 and transmits the first latch signal L1 to the latch signal input unit 104. In the present embodiment, a signal obtained by transmitting the first latch signal L1 through the delay transmission line Pn is the above-described second latch signal L2.
As shown in FIG. 2, the delay transmission line Pn is formed so as to connect all the buffers 201 to 204 provided on the addressing transmission line Pa and the data transmission line Pd in series. Yes. Specifically, the delay transmission line Pn is routed so as to connect the latch signal output unit 102 of the memory inspection control device 10 and the buffer 201 along the addressing transmission line Pa. Further, the delay transmission wiring Pn is routed so as to connect the buffer 201 and the buffer 202, and the buffer 202 and the buffer 203 in order. Similarly, the delay transmission line Pn is routed so as to connect the buffer 203 and the buffer 204 and the buffer 204 and the latch signal input unit 104 of the memory inspection control device 10 along the data transmission line Pd. Is done.
Here, the delay transmission line Pn is at least one (1 bit) that is not used for transmission of the addressing signal Sa or the data signal Sd among the 32 (32 bit) inverters constituting each of the buffers 201 to 204. Is routed through the inverter.

3 and 4 are a first diagram and a second diagram, respectively, for explaining the function of the memory inspection system according to the first embodiment.
Next, functions of the memory inspection system 1 according to the first embodiment will be described in detail with reference to FIGS. 3 and 4.
FIG. 3 is a diagram illustrating functions of the memory inspection system according to the comparison of the memory inspection system 1 according to the first embodiment. FIG. 3 shows an address designation signal Sa output from the memory test control device mounted in the memory test system according to the comparison, a data signal Sd input to the memory test control device, and the memory test control device. The timing chart of the 1st latch signal L1 produced | generated internally is shown.
The control device for memory inspection according to the comparison reads the data indicated by the input data signal Sd based on the timing designated by the first latch signal L1.

  With reference to the upper part of FIG. 3, the operation in the case where the control device for memory inspection according to the comparison outputs the address designation signal Sa at normal temperature will be described. In this case, the memory 3 that has received the input of the address designation signal Sa outputs a data signal Sd corresponding to the address designation signal Sa to the memory test control device. Note that, at room temperature, the delay time of the data signal Sd with respect to the address designation signal Sa is very small, and here, description will be made assuming that there is substantially no delay.

As shown in the upper part of FIG. 3, the address designation signal Sa and the first latch signal L1 are output in synchronization with each other. Then, at normal temperature, the data signal Sd is input without causing a delay with respect to the addressing signal Sa, so that the data signal Sd is also substantially synchronized with the first latch signal L1.
Here, the control device for memory test according to the proportional relationship is configured to perform data transfer at the timing designated by the first latch signal L1, that is, at times T1, T2, T3, and T4 when the first latch signal L1 transits from Low to High. Data to be read is extracted from the signal Sd. Specifically, the logical value (High = 1, Low = 0) of the portion indicated by the white circle of the data signal Sd described in the upper part of FIG. 3 is read. According to the example shown in the upper part of FIG. 3, the read data read at times T1 to T4 is “0101”. As described above, at the normal temperature, the first latch signal L1 and the data signal Sd are shifted substantially in synchronization, so that the data stored in the memory 3 can be read normally.

  On the other hand, with reference to the lower part of FIG. 3, the case where the memory test control device outputs the address designation signal Sa at a high temperature will be described. Also in this case, the memory 3 that has received the input of the address designation signal Sa outputs a data signal Sd corresponding to the address designation signal Sa to the memory test control device. However, at a high temperature, the delay time of the data signal Sd with respect to the address designation signal Sa increases. Here, a description will be given assuming that a predetermined delay time td (see the lower part of FIG. 3) occurs.

The delay time td is mainly caused by the deterioration of the response characteristics of the buffers 201, 202, 203, and 204. That is, since the resistance value of a general transistor increases as the temperature increases, the delay time from when the input signal is applied as the inverter element to when the output signal is output increases.
Due to the deterioration of the response characteristics in the buffers 201 and 202, the time required to transmit the address designation signal Sa transmitted through the address transmission line Pa increases. Further, due to the deterioration of the response characteristics in the buffers 203 and 204, the time required for transmitting the data signal Sd transmitted through the data transmission line Pd increases. As described above, due to the accumulation of response delays in the buffers connected to the wirings through which the addressing signal Sa and the data signal Sd are transmitted, the data signal Sd is finally delayed by the delay time td with respect to the addressing signal Sa. Input with a delay.

As shown in the lower part of FIG. 3, the addressing signal Sa is output so as to be synchronized with the first latch signal L1 even at a high temperature. However, since the data signal Sd is input with a delay of the delay time td relative to the addressing signal Sa, the data signal Sd transitions at a timing shifted from the first latch signal L1 by the delay time td. .
Here, the control device for memory inspection related to the comparison extracts data to be read from the data signal Sd at the timings T1, T2, T3, and T4 designated by the first latch signal L1, similarly to the normal temperature. Specifically, the logical value of the portion indicated by the white circle of the data signal Sd described in the lower part of FIG. 3 is read. According to the example shown in the lower part of FIG. 3, the read data read at times T1 to T4 is “0010”. As described above, at the time of high temperature, the data signal Sd is shifted from the first latch signal L1 by the delay time td, so that the data stored in the memory 3 cannot be read normally. Then, although the memory 3 itself is normally operating at a high temperature, it is determined that the normal memory 3 is a defective product due to a reading error caused by the characteristic variation of the memory inspection system. Will be.

FIG. 4 is a diagram illustrating functions of the memory inspection system 1 according to the first embodiment. FIG. 4 shows an address designation signal Sa output from the memory inspection control device 10 installed in the memory inspection system 1, a data signal Sd input to the memory inspection control device 10, and is generated inside the memory inspection control device 10. 1 is a timing chart of the first latch signal L1 and the second latch signal L2 obtained by passing the first latch signal L1 through the delay generator 20 (delay transmission line Pn).
The memory inspection control device 10 (data reading unit 105) according to the first embodiment reads the data indicated by the input data signal Sd based on the timing specified by the second latch signal L2.

The operation when the memory test control device 10 (address specifying unit 101) according to the first embodiment outputs the address specifying signal Sa at room temperature will be described with reference to the upper part of FIG. In this case, the memory 3 that has received the input of the address designation signal Sa outputs a data signal Sd corresponding to the address designation signal Sa to the memory test control device 10. Note that, at room temperature, the delay time of the data signal Sd with respect to the address designation signal Sa is very small, and here, description will be made assuming that there is substantially no delay.
In the present embodiment, as described above, the latch signal output unit 102 outputs the internally generated first latch signal L1. The output first latch signal L1 is transmitted through the delay transmission line Pn and input to the latch signal input unit 104 as the second latch signal L2. However, since the delay time of the second latch signal L2 with respect to the first latch signal L1 is very small at room temperature, the description will be made assuming that there is substantially no delay.

As shown in the upper part of FIG. 4, the address designation signal Sa and the first latch signal L1 are output in synchronization with each other. Then, at normal temperature, the data signal Sd is input without delay with respect to the address designation signal Sa, and the second latch signal L2 is input without delay with respect to the first latch signal. Therefore, the data signal Sd and the second latch signal L2 are substantially synchronized with each other.
Here, the memory test control device 10 starts from the data signal Sd at the timing specified by the second latch signal L2, that is, at times T1, T2, T3, and T4 when the second latch signal L2 transits from Low to High. Extract the data to be read. Specifically, the logical value (High = 1, Low = 0) of the portion indicated by the white circle of the data signal Sd described in the upper part of FIG. 4 is read. According to the example shown in the upper part of FIG. 4, the read data read at times T1 to T4 is “0101”. In this way, at the normal temperature, the second latch signal L2 and the data signal Sd transition in a substantially synchronized manner, so that the data stored in the memory 3 can be read normally.

  On the other hand, a case where the memory inspection control device 10 (address specifying unit 101) according to the first embodiment outputs the address specifying signal Sa at a high temperature will be described with reference to the lower part of FIG. Also in this case, the memory 3 that has received the input of the address designation signal Sa outputs a data signal Sd corresponding to the address designation signal Sa to the memory test control device 10. However, at high temperatures, the delay time of the data signal Sd with respect to the addressing signal Sa increases mainly due to the deterioration of the response characteristics of the buffers 201-204. Here, description will be made assuming that a predetermined delay time td (see the lower part of FIG. 4) occurs.

  In the present embodiment, as shown in FIG. 2, the delay transmission line Pn is connected so that the buffers 201 to 204 provided on the addressing transmission line Pa and the data transmission line Pd are connected in series. Turned. Therefore, the second latch signal L2 output by transmitting the first latch signal L1 through the delay transmission line Pn has a predetermined delay time with respect to the first latch signal L1 due to the deterioration of the response characteristics in the buffers 201-204. Just delay.

  Here, in the memory inspection system 1 according to the present embodiment, the delay transmission line Pn is the same as the total number of buffers 201 to 204 provided on the addressing transmission line Pa and the data transmission line Pd. Buffer is provided. Further, a structure of a transistor constituting an inverter connected on the addressing transmission line Pa and a data transmission line Pd, and a structure of a transistor constituting an inverter connected on the delay transmission line Pn, Are configured to match. By doing so, the temperature characteristics of all the transistors constituting the buffers 201 to 204 are equalized, and therefore the response characteristics deteriorate in the buffers arranged on the addressing transmission line Pa and the data transmission line Pd. And the degree of deterioration of the response characteristics of the buffer arranged on the delay transmission line Pn coincide with each other. Accordingly, the delay time of the second latch signal L2 with respect to the first latch signal L1 is equivalent to the delay time td of the data signal Sd with respect to the addressing signal Sa (see the lower part of FIG. 4).

  As shown in the lower part of FIG. 4, the addressing signal Sa is output so as to be synchronized with the first latch signal L1 even at a high temperature. However, since the data signal Sd is input with a delay of the delay time td relative to the addressing signal Sa, the data signal Sd is shifted from High at a timing shifted from the first latch signal L1 by the delay time td. Transition from Low, Low to High. Further, since the second latch signal L2 is also input with a delay of the delay time td relative to the first latch signal L1, the second latch signal L2 is shifted from the first latch signal L1 by the delay time td. Transition from High to Low and from Low to High at the same timing (see the lower part of FIG. 4). As a result, the delay of the second latch signal L2 with respect to the data signal Sd is relatively zero.

The data reading unit 105 of the memory test control device 10 according to the first embodiment has a timing designated by the second latch signal L2, that is, a time at which the delayed second latch signal L2 transits from Low to High. At T1 ′, T2 ′, T3 ′, and T4 ′, data to be read is extracted from the data signal Sd. Here, the timings T1 ′, T2 ′, T3 ′, and T4 ′ are timings delayed by a delay time td from the timings T1, T2, T3, and T4 specified by the first latch signal L1, respectively.
Specifically, the logical value of the portion indicated by the white circle of the data signal Sd described in the lower part of FIG. 4 is read. According to the example shown in the lower part of FIG. 4, the read data read at times T1 ′ to T4 ′ is “0101”. As described above, the memory test system 1 according to the first embodiment transfers the data signal Sd, which is delayed by the delay time td with respect to the first latch signal L1, at a high temperature, to the first latch signal L1. Since reading is performed based on the second latch signal L2 delayed by the equivalent delay time td, the data stored in the memory 3 can be read normally.

  As described above, in the memory inspection system 1 according to the first embodiment, the latch signal (second latch signal L2) that intentionally causes the same delay as the signals used for the inspection (address designation signal Sa, data signal Sd). Therefore, the characteristic variation caused by the environmental temperature is canceled, and the data stored in the memory can be read correctly. Therefore, according to the memory inspection system 1 according to the first embodiment, it is possible to accurately inspect a memory to be inspected even when placed in various environments.

  In the memory inspection system 1 according to the present embodiment, the delay transmission line Pn includes a transmission line for the address designation signal Sa (address designation transmission line Pa) and a transmission line for the data signal Sd (data transmission). The same number of buffers as the total number of buffers provided on the wiring Pd) are provided. Thereby, the delay time of the second latch signal L2 with respect to the first latch signal L1 can be brought close to the delay time of the data signal Sd with respect to the address designation signal Sa. Therefore, the memory can be inspected with higher accuracy.

  In addition, the memory inspection system 1 according to the present embodiment is provided on the transmission line Pa for addressing and the structure of the transistors constituting the buffers provided on the transmission line Pd for data and the transmission line Pn for delay. The structure of the transistor that constitutes the buffer is configured to match. As a result, the temperature dependence of the response characteristics of the buffer provided on the addressing transmission line Pa and the data transmission line Pd and the buffer provided on the extension transmission line Pn are equal. . Therefore, the delay time of the second latch signal L2 with respect to the first latch signal L1 can be made closer to the delay time of the data signal Sd with respect to the address designation signal Sa.

  In the first embodiment, the delay transmission line Pn is arranged along the addressing transmission line Sa and the data transmission line Pd as far as possible in design. In this way, the temperature distribution generated in the addressing transmission line Sa and the data transmission line Pd and the temperature distribution generated in the delay transmission line Pn can be approximated. The delay time of the second latch signal L2 can be made closer to the delay time of the data signal Sd with respect to the address designation signal Sa.

  As described above, the memory inspection system 1 according to the first embodiment has been described in detail. However, a specific aspect of the memory inspection system 1 according to the present embodiment is not limited to the above-described one, and departs from the gist. It is possible to add various design changes and the like within the range not to be performed.

For example, in the memory inspection system 1 according to another embodiment, the number of buffers provided in the delay transmission line Pn is the total number of buffers provided on the addressing transmission line Pa and the data transmission line Pd. And the number need not necessarily be the same.
In the memory inspection system 1 according to another embodiment, the structure of the transistors constituting the buffers provided on the addressing transmission line Pa and the data transmission line Pd and the delay transmission line Pn are also provided. The structure of the transistor included in the provided buffer is not necessarily matched.
In other words, the number of buffers arranged on the delay transmission line Pn and the structure of the transistors constituting the buffers can be changed as long as the purpose of delaying the first latch signal by a desired delay time can be achieved. It is. For example, the delay transmission line Pn may have only one buffer. Even in this case, the delay transmission line Pn can delay the first latch signal by a predetermined delay time based on the one buffer.

  Further, in each of the above-described embodiments, the delay generation unit 20 has been described as being configured by the delay transmission wiring Pn having at least one buffer, but the other embodiments are not limited to this mode. For example, the delay generation unit 20 according to another embodiment may be configured by a delay generation logic circuit (delay logic circuit). Here, the delay logic circuit has a function of delaying and outputting the input logic signal (first latch signal L1) for a predetermined time.

<Second Embodiment>
Hereinafter, the second embodiment will be described in detail with reference to the drawings.
FIG. 5 is a diagram illustrating a functional configuration of the memory inspection system according to the second embodiment. In addition, about the same function structure as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
As shown in FIG. 5, the delay generation unit 20 of the memory inspection system 1 according to the second embodiment includes a delay transmission line Pn and an in-memory line Pm. Here, the in-memory wiring Pm is a signal wiring formed in the memory 3 to be inspected, and is electrically connected to the delay transmission wiring Pn via the connector 11.

  Specifically, the delay transmission line Pn according to the present embodiment includes the latch signal output unit 102 and the buffer 201 and the buffer 201 and the buffer 202 of the memory test control device 10 along the addressing transmission line Pa. Are sequentially connected to each other. The delay transmission line Pn is routed so as to connect the buffer 202 and the connection point X1 of the connector 11. Thereby, the delay transmission line Pn is electrically connected to the in-memory line Pm via the connection point X1.

The memory wiring Pm is arranged inside the memory 3 so as to electrically connect the connection point X1 of the connector 11 and the other connection point X2 of the connector 11 (see FIG. 5). The memory wiring Pm is connected to the delay transmission wiring Pn on the other side via the connection point X2. The other delay transmission line Pn is routed so as to connect the connection point X2 and the buffer 203, the buffer 203 and the buffer 204, and the buffer 204 and the latch signal input unit 104 along the data transmission line Pd. The
The first latch signal L1 output from the latch signal output unit 102 is input to the latch signal input unit 104 as the second latch signal L2 via the delay transmission wiring Pn and the in-memory wiring Pm arranged as described above. Is done.

  Here, the address designation signal Sa is input from the memory inspection system 1 to the memory 3 via the connector 11. Similarly, the data signal Sd is input from the memory 3 to the memory inspection system 1 via the connector 11. Therefore, when the electrical characteristics of the connector 11 have a predetermined temperature dependence, a delay may occur due to fluctuations in the electrical characteristics of the connector 11.

  However, according to the memory inspection system 1 according to the second embodiment, the delay transmission wiring Pn includes the connector 11 to which the memory 3 to be inspected is connected, and the in-memory wiring formed in the memory 3. It is routed through Pm. By doing in this way, the influence of the electrical characteristic of the connector 11 can be added to the delay time of the second latch signal L2 with respect to the first latch signal L1. Therefore, by reading data based on the second latch signal in which the influence of the electrical characteristics of the connector 11 is taken into account, the influence due to the fluctuation of the electrical characteristics that can occur in the connector 11 can be offset, and the memory 3 Can be read with higher accuracy.

  As described above, according to the memory inspection system 1 according to the second embodiment, the configuration of the transmission wiring for delaying the latch signal can be made closer to the configuration of the transmission wiring for transmitting the address specification signal Sa and the data signal Sd. As a result, the memory to be inspected can be inspected more accurately.

In each of the above-described embodiments, a program for realizing the function of the memory inspection control device 10 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read by a computer system. Each procedure is to be performed by executing. Here, each process of the memory inspection control device 10 described above is stored in a computer-readable recording medium in the form of a program, and the above-described various processes are performed by the computer reading and executing the program. Is called. Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, and the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.
In addition, each functional configuration of the memory inspection control device 10 may be provided across a plurality of devices connected via a network.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof, as long as they are included in the scope and gist of the invention.

DESCRIPTION OF SYMBOLS 1 Memory inspection system 10 Memory inspection control apparatus 101 Address designation part 102 Latch signal output part 103 Data input part 104 Latch signal input part 105 Data reading part 11 Connector 20 Delay generation part 201, 202, 203, 204 Buffer 3 Memory

Claims (4)

An address designating unit for outputting an address designating signal for designating an address to the memory;
A latch signal output unit for outputting a first latch signal synchronized with the address designation signal;
A data input unit for receiving an input of a data signal corresponding to the designated address from the memory;
A latch signal input unit for receiving an input of a second latch signal obtained by delaying the first latch signal by a time corresponding to a delay time of the data signal with respect to the addressing signal;
A data reading unit that reads data indicated by the data signal based on the timing specified by the second latch signal;
A memory inspection control device comprising:
A delay generator for receiving the input of the first latch signal and outputting the second latch signal obtained by delaying the first latch signal by a time corresponding to a delay time of the data signal with respect to the addressing signal;
With
The delay generator is
A transmission line for delay provided with one or more buffers,
The delay transmission wiring is
A memory inspection system in which the same number of buffers as the total number of buffers provided on the address specification signal transmission line and the data signal transmission line are provided . A structure of a transistor constituting a buffer provided on the transmission wiring of the addressing signal and a transmission line of the data signal; and a structure of a transistor constituting a buffer provided on the transmission wiring for delay; The memory inspection system according to claim 1 , wherein: The delay transmission wiring is
The memory inspection system according to claim 1 , wherein the memory is routed through a connector to which the memory is connected. Outputting an address designation signal for designating an address to the memory;
Outputting a first latch signal synchronized with the addressing signal;
Receiving an input of a data signal corresponding to the designated address from the memory;
Receiving an input of a second latch signal obtained by delaying the first latch signal by a time corresponding to a delay time of the data signal with respect to the addressing signal;
Reading the data indicated by the data signal based on the timing specified by the second latch signal;
A delay generation unit receives the input of the first latch signal and outputs the second latch signal obtained by delaying the first latch signal by a time corresponding to the delay time of the data signal with respect to the address designation signal. Steps,
Have
The delay generator is
A transmission line for delay provided with one or more buffers,
The delay transmission wiring is
The same number of buffers as the total number of buffers provided on the address signal transmission wiring and the data signal transmission wiring are provided.
Memory inspection method.

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