JP6370688B2 - Current balance control device, rectifier, and current balance control method - Google Patents

Description

  Embodiments described herein relate generally to a current balance control device, a rectifier, and a current balance control method.

  As an example of the configuration of a conventional rectifier using power semiconductors connected in parallel, a configuration of a thyristor rectifier using thyristors connected in parallel as shown in FIG. 11 will be described as an example. The thyristor rectifier is composed of U-phase, V-phase, W-phase, X-phase, Y-phase, and Z-phase as one bridge, and N bridges 103-1, 103-2, ..., 103-N connected in parallel. Has been.

  For example, the bridge 103-1 will be described. Generally, each of thyristors TU1, TV1, TW1, TX1, TY1, and TZ1 is connected with each of fuses FU1, FV1, FW1, FX1, FY1, and FZ1 in series for protection. The three-phase outputs of the three-phase AC power source 100 are the anode of the U-phase arm and the cathode of the X-phase arm, the anode of the V-phase arm and the cathode of the Y-phase arm, and the anode of the W-phase arm and the Z-phase arm of each bridge. It is connected to the cathode, and is converted into a DC voltage by an AC / DC converter comprising six arms controlled in phase. The gate circuits GU1, GV1, GW1, GX1, GY1, and GZ1 are connected to the gates of the thyristors TU1, TV1, TW1, TX1, TY1, and TZ1, respectively.

  The gate signal generator 101 controls the output timing of the six gate signals 201U, 201V, 201W, 201X, 201Y, and 201Z based on the synchronization signals 200R, 200S, and 200T applied from the three-phase AC power supply 100. Thereby, gate signals are simultaneously supplied to N gate circuits Gx1, Gx2,..., GxN (x = U, V, W, X, Y, Z) in the same phase in each bridge. , Current flows through N thyristors in the same phase at the same time.

  Here, the case where the U phase is conducted in each bridge will be described. IUN1, IU2,..., IUN are currents flowing through the U-phase thyristors TU1, TU2,..., TUN of each bridge, and IU is a total current obtained by adding these currents. Thus, the N thyristors TU1, TU2,..., TUN share the total current IU for each period of the three-phase AC power supply 100.

  However, each value of the output currents IU1, IU2,..., IUN is the difference in the voltage-current characteristics of each thyristor, the difference in the conductor impedance due to the different structural arrangement, or the current that flows in a divided manner to the conductor. The value may not be the same due to the difference in voltage drop due to Therefore, for example, in the excitation system of the power generation plan IV, when the semiconductor elements used in the rectifier are used in parallel connection as described above due to the current capacity, the current is supplied to each element connected in parallel due to variations in element characteristics. Does not flow evenly, the current of a specific element increases, and there is a problem that the lifetime is consumed.

Therefore, conventionally, thyristors TU1, TU2, · · ·, TUN of voltage - and the current characteristics are used by selecting as close as possible, it and devised so that the conductor structure in symmetrical arrangement, or, Detect thyristors TU1, TU2,..., TUN having a large energization current, and perform control to stop the gate signal of the corresponding thyristor once a plurality of times (for example, Patent Document 1), or thyristor TU1, TU2,..., UN having a large energization current is detected, and control for delaying the output timing of the gate signal of the corresponding thyristor is performed (for example, Patent Document 2), so that the current can be shared as much as possible. Evenly.

JP 2007-325328 A JP 2011-172405 A

  In the prior art, in order to achieve current balance when power semiconductors are used in parallel, even if power semiconductors with generally similar characteristics are selected and used or the conductor structure is devised, the current sharing varies The current unbalance rate, which is one of the indices representing the degree of the current, may be 30% or more, which accelerates the deterioration of the power semiconductor having a high current sharing rate. The current unbalance rate here means the degree to which the current value of the output current flowing through each power semiconductor deviates from a predetermined reference value. More specifically, the current unbalance rate is represented by the ratio of the maximum energization current or the minimum energization current with respect to the average value of the energization current of the power semiconductor. For example, when the energization currents of N power semiconductors are IU1, IU2,..., IUN, the average value of the energization currents is represented by (IU1 + IU2 +... + IUN) / N. The current unbalance rate of 30% means that the maximum energized current value falls within the range of + 30% with respect to the average value of the energized current, and the minimum energized current value with respect to the average value of the energized current. It means entering the range of -30%.

  Further, in the prior art, it is the limit to suppress the current unbalance rate to about 30%, and it is difficult to satisfy the recent requirement for the current unbalance rate to be 10% or less. Moreover, since power semiconductors are selected and purchased and the structure of conductors is limited, it also hinders cost reduction of rectifiers.

  In addition, when the gate signal output control technique as shown in Patent Document 1 and Patent Document 2 is used, it is necessary to specify in advance a setting value that takes into account the characteristics of each power semiconductor, the bridge configuration, and the like that have been measured in advance. In addition, when the characteristics of the power semiconductor used or the bridge configuration changes due to a failure of the power semiconductor, the control may not be continued unless the setting is changed. Further, if the setting is incorrect, output current hunting or output current decrease may occur, resulting in control failure.

  A problem to be solved by the present invention is a current balance control device capable of realizing highly accurate current balance control between power semiconductors connected in parallel without selecting power semiconductors connected in parallel according to electrical characteristics. , A rectifier, and a current balance control method.

A current balance control device in which a plurality of power semiconductors that alternately repeat energization and pause are connected in parallel, and the current balance control device includes control means. The control means checks whether or not there is a deviation from a predetermined current value range among a plurality of output currents output from a plurality of power semiconductors at a constant cycle. The corresponding power semiconductor gate is driven and controlled so that the most deviating output current falls within a predetermined current value range. The control means diagnoses the balance of the plurality of output currents output from the plurality of power semiconductors for each period, and the phase control angle command means for periodically outputting the phase control angle command signals to the plurality of power semiconductors, In accordance with a phase control angle command signal, current balance diagnosis means for outputting a current balance control signal for suppressing or promoting the most deviating output current so that the most deviating output current falls within the range, And a gate signal generating means for periodically supplying a gate signal corresponding to the current balance control signal to the corresponding power semiconductor.

  According to the present invention, highly accurate current balance control between power semiconductors connected in parallel can be realized without selecting power semiconductors connected in parallel according to electrical characteristics.

The figure which shows the structural example of the rectifier provided with the current balance control apparatus which concerns on 1st Embodiment. The figure which shows an example of the output current waveform and total output current waveform of each power semiconductor obtained by the current balance control process performed in the current balance control apparatus of the embodiment. The flowchart which shows the procedure of the current balance control process performed in the current balance control apparatus of the embodiment. The figure which shows the structural example of the thyristor rectifier provided with the current balance control apparatus which concerns on 2nd Embodiment. The figure which shows the more detailed structural example of the current balance control apparatus of the embodiment. The figure which shows the structural example of the current balance diagnostic part provided in the current balance control apparatus of the embodiment. The figure which shows the structural example of the current output identification part provided in the current balance control apparatus of the embodiment. The figure which shows an example of the input waveform in the current output identification part provided in the current balance control apparatus of the embodiment. The figure which shows the structural example of the reference value calculating part provided in the current balance control apparatus of the embodiment. The figure which shows an example of the output current waveform of each U-phase thyristor obtained by the current balance control process performed in the current balance control apparatus of the embodiment, and the total output current waveform of the U phase. The figure which shows the structural example of the thyristor rectifier by a prior art.

Hereinafter, embodiments will be described with reference to the drawings.
In the following, the description will focus on the parts different from the conventional configuration shown in FIG. Elements common to those in FIG. 11 are denoted by the same reference numerals, and redundant description is omitted.
(First embodiment)
First, the first embodiment will be described with reference to FIGS. 1 to 3.
FIG. 1 is a diagram illustrating an example of a configuration of a rectifier including the current balance control device according to the first embodiment.

  The current balance control device 10 is a current of N power semiconductors T1, T2,..., TN that are connected in parallel and alternately repeat energization and rest included in the rectifier used in the excitation system of the power generation plan IV. It is a device that controls the balance. The power semiconductor here is a semiconductor element such as a thyristor, IEGT, or IGBT.

  The current balance control device 10 checks whether there is a deviation from a predetermined current value range among a plurality of output currents output from the power semiconductors T1, T2,. When there is a deviation, the control function of driving and controlling the gate of the corresponding power semiconductor so that the most deviating output current is within the predetermined current value range is provided.

  The current balance control device 10 includes a phase control angle command unit 300, a current balance diagnosis unit 301, and gate signal generation units 302-1, 302-2, ..., 302-N. The power semiconductors T1, T2,..., TN are connected in parallel. In addition, each of the power semiconductor gate circuits G1, G2,..., GN is attached to each gate of the power semiconductors T1, T2,.

  The phase control angle command unit 300 performs control to periodically generate and collectively supply a phase control angle command signal 400 that instructs a phase control angle with respect to the power semiconductors T1, T2,. The phase control angle command unit 300 outputs the phase control angle command signal 400 to the gate signal generation units 302-1, 302-2, ..., 302-N.

  The current balance diagnosis unit 301 diagnoses the balance of the output currents of the power semiconductors T1, T2,. More specifically, the current balance diagnosis unit 301 has a predetermined current among a plurality of output currents I1, I2,..., IN output from the power semiconductors T1, T2,. The current balance is diagnosed by checking whether there are any deviations from the range of values.

  Based on the diagnosis result, the current balance diagnosis unit 301 drives and controls the gate of the corresponding power semiconductor so that the most deviated output current falls within a predetermined current value range when there is a deviation. Current control signals 401-1, 401-2,..., 401 -N that instruct the power semiconductors T 1, T 2,. Output. More specifically, the current balance diagnostic unit 301 is configured to determine the number of N power semiconductors T1, T2,... TN based on power semiconductor constraint conditions (for example, represented by a current unbalance rate). Diagnose the balance of the output current output from each, and based on the diagnosis results, for example, current balance control to reduce the amount of current for power semiconductors that deviate most from the constraints and have the highest current share The output value of any of the signals 401-1, 401-2,..., 401-N is lowered and output to the gate signal generators 302-1, 302-2,. One of the current balance control signals 401-1, 401-2,..., 401 -N for increasing the amount of current for the power semiconductor that is most deviated from the constraint condition and has the lowest current sharing ratio. Increase output value Gate signal generating unit 302-1 and 302-2, ..., and outputs to one of the 302-N.

  Each of the gate signal generators 302-1, 302-2,..., 302-N periodically follows the phase control angle indicated by the phase control angle command signal 400 and the current balance control signals 401-1, 401. ,..., 401-N corresponding to the N gate signals 402-1, 402-2,..., 402-N are generated, and the generated gate signals 402-1, 402-2, ..., 402-N is output to the power semiconductor gate circuits G1, G2, ..., GN.

  The power semiconductor gate circuits G1, G2,..., GN are gate signals 402-1 and 402-2 output from the N gate signal generators 302-1, 302-2,. ,..., 402-N are received, the gates of the power semiconductors T1, T2,... TN are driven, and the power semiconductors T1, T2,. Thereby, the power semiconductor output currents I1, I2,..., IN flow through the arms including the power semiconductors T1, T2,..., TN, and the power semiconductor output total current I, which is the sum of these currents, is obtained. .

Next, with reference to FIG. 2, the outline of the current balance control operation of the current balance control device 10 in the first embodiment will be described.
Here, it is assumed that the current unbalance rate that defines the constraint condition is 10%. In this case, for example, a current value 10% larger than a predetermined current value (reference value) is set as an upper limit value, and a current value 10% smaller than the reference value is set as a lower limit value.

  The power semiconductors T1, T2,..., TN have variations in electrical characteristics, and the balance between the power semiconductor output currents I1, I2,.

  Now, suppose that the current sharing ratio of each power semiconductor T1, T2,..., TN is the largest in the power semiconductor T1, the next largest in the power semiconductor T2, and the smallest in the power semiconductor TN.

  At this time, the current balance diagnosis unit 301 diagnoses the current balance of the power semiconductors T1, T2,. The current balance diagnosis unit 301 determines that the output current I1 of the power semiconductor T1 is the maximum current value that deviates most from the upper and lower limit values of the constraint conditions, and for the power semiconductor T1 that has the highest current sharing ratio The current balance control signal 401-1 for decreasing the output current I <b> 1 is output in the second cycle, that is, the second cycle. Thereby, in period 2, the output current I1 of the power semiconductor T1 decreases, and the decrease in the output current I1 is shared by the power semiconductors T2 to TN, so that the power semiconductor output total current I is obtained. The output value of the current balance control signal 401-1 of the power semiconductor T <b> 1 is retained after the period 2 and is output at the same value as long as the output current value of the power semiconductor T <b> 1 does not depart from the constraint condition again. The output current I1 is continuously suppressed.

  Similarly, the current balance diagnosis unit 301 diagnoses the current balance of the power semiconductors T1, T2,. The current balance diagnosis unit 301 determines that the output current IN of the power semiconductor TN is the minimum current value that is most deviated from the upper and lower limit values of the constraint conditions, and for the power semiconductor TN having the lowest current sharing ratio In the third cycle, the current balance control signal 401-N for increasing the output current IN is output. As a result, the output current IN of the power semiconductor TN increases, and the current sharing ratio of the power semiconductors T1 and T2 corresponding to the increase of the output current IN decreases. The output value of the current balance control signal 401-N of the power semiconductor TN is maintained even after the period 3 and is output at the same value as long as the output current IN of the power semiconductor TN does not depart from the constraint condition again. The output current IN is continuously promoted. It can be seen that in the cycle N, which is the Nth cycle, the output current I1 of the power semiconductor T1 to the output current IN of the power semiconductor TN fall within the range of the constraint condition.

Next, an example of the procedure of the current balance control process in the first embodiment will be described with reference to FIG.
The current balance control device 10 diagnoses the current balance of the power semiconductors T1, T2, ..., TN based on the output currents I1, I2, ..., IN (step S301). More specifically, the current balance control device 10 determines whether there is an output current that deviates from a predetermined current value range based on the diagnosis result. When there is an output current that deviates from the predetermined current value range (YES in step S303), the current balance control device 10 most deviates from the output current that deviates from the predetermined current value range. More specifically, the output current is reduced when the most deviating output current exceeds the upper limit value of the predetermined current value range so that the output current is within the predetermined current value range. On the other hand, if the most deviating output current is below the lower limit value of the predetermined current value range, the output current is increased so that the output current is within the predetermined current value range. The power semiconductor gate corresponding to the most deviating output current is driven and controlled so as to fall within the value range (step S305). On the other hand, when there is no output current that deviates from the predetermined current value range (NO in step S303), the current balance control device 10 maintains the current control state as it is.

  Thereafter, the process returns to step S301, and the same processing is repeated in the next cycle.

  As described above, according to the first embodiment, in each cycle, the current balance control is performed on the power semiconductor whose output current is most deviated from the constraint condition, and the output current of the power semiconductor is adjusted. Thus, it is possible to suppress variation in the average output current of each power semiconductor. As a result, it is possible to realize a highly accurate current balance between the parallel power semiconductors without considering the electrical characteristics and the conductor structure of the power semiconductors connected in parallel.

  Further, by controlling the gate pulse output to each element so that the current amount falls within the set range, current imbalance between elements can be suppressed. In addition, in a rectifier in which a plurality of power semiconductors are connected in parallel, output current can be controlled according to the current sharing of each power semiconductor, and current balance between the power semiconductors can be realized.

  In addition, when there is an output current that deviates from the upper and lower limit values of the constraint conditions for each period, it is only necessary to control one power semiconductor, so that cooperative control between the power semiconductors is not required.

In addition, it is possible to provide a low-cost rectifier while satisfying recently required constraints.
(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS.
In the following description, it is assumed that the output current of the power semiconductors connected in parallel is in an unbalanced state as shown in period 1 of FIG. Hereinafter, a case where a thyristor is used as the power semiconductor will be described, but IEGT or IGBT may be used instead of the thyristor.

  Unlike the first embodiment, the current balance control device 10 according to the second embodiment assumes a large-capacity thyristor rectifier having a plurality of phases as one bridge. Also, the current balance control device 10 in the second embodiment differs from the conventional technique as shown in FIG. 11 in that a gate signal including control for suppressing or promoting the output current of each thyristor instead of the gate signal generator 101. Is provided.

4 and 5 are diagrams illustrating a configuration example of a thyristor rectifier including the current balance control device according to the second embodiment.
The main circuit portion of the current balance control device 10 includes one thyristor TU1, TV1, TW1, TX1, TY1, and TZ1, fuse FU1, respectively for the U phase, V phase, W phase, X phase, Y phase, and Z phase. A bridge including FV1, FW1, FX1, FY1, and FZ1, and gate circuits GU1, GV1, GW1, GX1, GY1, and GZ1 is provided. In the current balance control device 10, N bridges 103-1, 103-2,..., 103-N are connected in parallel to this bridge, and a three-phase AC that supplies power to these N bridges. A power supply 100 is provided.

  The current balance control device 10 is also provided with a phase control angle command unit 501, a current balance diagnosis unit 502, a U-phase gate signal generation unit 504U, and a current detection that detects the output current of each P-side thyristor. , 503-NP, and current detectors 503-1N, 503-2N,... That detect the output current of each N-side thyristor provided in each bridge. 503-NN.

  The U-phase thyristor will be described below, but the same applies to the V-phase, W-phase, X-phase, Y-phase, and Z-phase thyristors. The operation when the U phase is conducted in each bridge of the current balance control device 10 will be described.

  The phase control angle command unit 501 receives phase control angle command signals 602U, 602V, 602W, 602X, 602Y, and 602Z for instructing the phase control angles for the thyristors TU1, TU2,. Output in batches periodically.

  The current balance diagnosis unit 502 diagnoses the current balance of each thyristor based on the P-side thyristor current detection signals IP1, IP2,..., IPN or the N-side thyristor current detection signals IN1, IN2,. . Details of the current balance diagnosis unit 502 will be described later.

  The U-phase gate signal generation unit 504U periodically according to the R-phase synchronization signal 200R applied from the three-phase AC power supply 100 and the U-phase phase control angle command signal 602U output from the phase control angle command unit 501. U-phase thyristor gate signals 601U-1, 601U-2,... Corresponding to U-phase current balance control signals 600U-1, 600U-2,. 601U-N is output.

Here, the correspondence relationship between the current balance control device 10 according to the second embodiment and the current balance control device 10 according to the first embodiment will be described.
U-phase thyristor TU1 corresponds to power semiconductor T1. U-phase thyristor TU2 corresponds to power semiconductor T2. The U-phase thyristor TUN corresponds to the power semiconductor TN. The gate circuit GU1 for the U-phase thyristor TU1 corresponds to the power semiconductor gate circuit G1. U-phase thyristor gate circuit GU2 corresponds to power semiconductor gate circuit G2. U-phase thyristor gate circuit GUN corresponds to power semiconductor gate circuit GN. The phase control angle command unit 501 corresponds to the phase control angle command unit 300. The current balance diagnosis unit 502 corresponds to the current balance diagnosis unit 301. U-phase thyristor gate signal generator 504U-1 corresponds to gate signal generator 302-1. U-phase thyristor gate signal generator 504U-2 corresponds to gate signal generator 302-2. The U-phase thyristor gate signal generator 504U-N corresponds to the gate signal generator 302-N. The U-phase phase control angle command signal 602U corresponds to the phase control angle command signal 400.

  The current balance control signal 600U-1 of the U-phase thyristor TU1 corresponds to the current balance control signal 401-1 of the power semiconductor T1. The current balance control signal 600U-2 of the U-phase thyristor TU2 corresponds to the current balance control signal 401-2 of the power semiconductor T2. The current balance control signal 600U-N of the U-phase thyristor TUN corresponds to the current balance control signal 401-N of the power semiconductor TN.

  The gate signal 601U-1 of the U-phase thyristor TU1 corresponds to the gate signal 402-1 of the power semiconductor T1. The gate signal 601U-2 of the U-phase thyristor TU2 corresponds to the gate signal 402-2 of the power semiconductor T2. The gate signal 601U-N of the U-phase thyristor TUN corresponds to the gate signal 402-N of the power semiconductor TN. The output current IU1 of the U-phase thyristor TU1 corresponds to the output current I1 of the power semiconductor T1. Output current IU2 of U-phase thyristor TU2 corresponds to output current I2 of power semiconductor T2. The output current IUN of the U-phase thyristor TUN corresponds to the output current IN of the power semiconductor TN. U-phase thyristor output total current IU corresponds to power semiconductor output total current I.

Next, a configuration example of the current balance diagnosis unit 502 will be described with reference to FIG.
The current balance diagnosis unit 502 includes a current output identification unit 505, a U-phase thyristor difference calculation unit 509U1, a U1-phase delay control angle setting unit 512U1 +, a U1-phase advance control angle setting unit 512U1-, a U-phase thyristor control angle command value synthesis unit 513U1. , U-phase failure detection unit 514U, comparison unit 515, U1-phase previous value holding unit 516U1, reference value calculation unit 517, and the like.

  The current output identification unit 505 is output from the U-phase thyristor gate signals 601U-1, 601U-2,..., 601U-N output from the U-phase gate signal generation unit 504U and the V-phase gate signal generation unit 504V. V-phase thyristor gate signals 601V-1, 601V-2,..., 601V-N, and W-phase thyristor gate signals 601W-1, 601W-2,. , 601W-N and thyristor current detection signals IP1, IP2,..., IPN detected by current detectors 503-1P, 503-2P,. Identifies whether the signals IP1, IP2, ..., IPN are U-phase output currents IU1, IU2, ..., IUN output from the U-phase thyristor. .

  Current output identifying unit 505 outputs U-phase output currents IU1, IU2,..., IUN to U-phase failure detection unit 514U and reference value calculation unit 517.

  The U-phase failure detection unit 514U detects U-phase output currents IU1, IU2,..., IUN to detect thyristors that have failed and the current output is stopped, and U-phase thyristor failure signals 611U1, 611U2,. 611UN is output to the reference value calculation unit 517 and the comparison unit 515.

  The reference value calculation unit 517 selects a thyristor to be subjected to current balance control using the U-phase output currents IU1, IU2,..., IUN and the U-phase thyristor failure signals 611U1, 611U2,. Therefore, a U-phase thyristor output current upper / lower limit value 606 is output, which is centered on the reference value of the U-phase thyristor output current necessary for this. A specific method for calculating the U-phase thyristor output current upper and lower limit value 606 by the reference value calculation unit 517 will be described later.

  The U-phase thyristor difference calculation unit 509U1 calculates the U-phase thyristor output current difference value 607U1 based on the U-phase thyristor output current IU1 and the U-phase thyristor output current upper / lower limit value 606, and calculates the calculated U-phase thyristor output current difference value 607U1. Is output to the comparison unit 515. Similarly, U-phase thyristor difference calculation units 509U2 to 509UN output U-phase thyristor output current difference values 607U2 to 607UN to comparison unit 515, respectively.

  The comparison unit 515 compares the U-phase thyristor output current difference values 607U1, 607U2,..., 607UN, detects the one having the largest absolute value, and selects the U-phase thyristor to be controlled as the U-phase thyristor TU1, TU2. , ..., determined from TUN.

  Here, a case where the absolute value of the U-phase thyristor output current difference value 607U1 is larger than the absolute values of the other thyristor output current difference values 607U2 to 607UN will be described. Comparison unit 515 detects U-phase thyristor TU1 as a control target. Then, when the U-phase thyristor output current difference value 607U1 is a positive value, the comparison unit 515 sends the plus-side U-phase thyristor control execution signal 608U1 + to the U1-phase delay control angle setting unit 512U1 + and the U1-phase previous value holding unit 516U1. Output to. On the other hand, when the U-phase thyristor output current difference value 607U1 is a negative value, the comparison unit 515 holds the minus-side U-phase thyristor control execution signal 608U1- with the U1-phase advance control angle setting unit 512U1- and the U1-phase previous value. To the unit 516U1.

  Further, when any of the U-phase thyristor failure signals 611U1, 611U2,..., 611UN is received, the comparison unit 515 stops the control execution signal 608 of the thyristor corresponding to the received U-phase thyristor failure signal 611. For example, when the comparison unit 515 receives the U-phase thyristor failure signal 611U1, the plus-side U-phase thyristor control execution signal 608U1 + and the minus-side U-phase thyristor control execution signal of the thyristor TU1 corresponding to the received U-phase thyristor failure signal 611U1. 608U1- is stopped.

  When the positive U-phase thyristor control execution signal 608U1 + is input, U1-phase delay control angle setting unit 512U1 + outputs U1-phase delay control angle command value 609U1 + to U-phase thyristor control angle command value synthesis unit 513U1. On the other hand, when the negative U phase thyristor control execution signal 608U1- is input, the U1 phase advance control angle setting unit 512U1- sends the U1 phase advance control angle command value 609U1- to the U phase thyristor control angle command value synthesis unit 513U1. Output.

  Note that the control angle values set by the U1-phase delay control angle setting unit 512U1 + and the U1-phase advance control angle setting unit 512U1- are fixed values (+ α and -α), respectively. Further, the fixed values (+ α and −α) may be values that are used to keep the amount of current of the thyristor to be controlled within the predetermined range, for example. Further, the absolute value of the control angle value set by the U1 phase lag control angle setting unit 512U1 + may be different from the absolute value of the control angle value set by the U1 phase advance control angle setting unit 512U1-. .

  The U-phase thyristor control angle command value synthesis unit 513U1 synthesizes the U1-phase delay control angle command value 609U1 + and the U1-phase advance control angle command value 609U1- and, based on the synthesis result, the U1-phase control angle command value 610U1 as the U1-phase previous time. The data is output to the value holding unit 516U1.

  When the positive U-phase thyristor control execution signal 608U1 + or the negative U-phase thyristor control execution signal 608U1- is input, the U1-phase previous value holding unit 516U1 sets U1 to the previous value of the U-phase thyristor current balance control signal 600U-1. A value obtained by adding the phase control angle command value 610U1 is output as a U-phase thyristor current balance control signal 600U-1. Further, when neither the plus side U-phase thyristor control execution signal 608U1 + nor the minus side U-phase thyristor control execution signal 608U1- is input, the U1-phase previous value holding unit 516U1 last time the U-phase thyristor current balance control signal 600U-1. Output the value.

Next, a more detailed configuration example of the current output identification unit 505 will be described with reference to FIG.
The current output identification unit 505 includes a U1 phase synchronization interval identification unit 510U1, a V1 phase synchronization interval identification unit 510V1, a W1 phase synchronization interval identification unit 510W1, a U1 phase detection signal average value calculation unit 511U1, and a V1 phase detection signal average value calculation unit 511V1. And W1 phase detection signal average value calculation section 511W1.

  The U-phase thyristor gate signal 601U-1 and the V-phase thyristor gate signal 601V-1 input to the current balance diagnosis unit 502 are input to the U1-phase synchronization section identification unit 510U1.

  When a value is input to the set side (S side), the U1 phase synchronization section identification unit 510U1 holds the previous value until a value is input to the reset side (R side). Therefore, when the U-phase thyristor gate signal 601U-1 is output from the U-phase thyristor gate signal generation unit 504U-1, the U1-phase synchronization section identification unit 510U1 next outputs the V-phase thyristor gate signal 601V-1. Until this time, the U1-phase synchronization section signal 603U-1 is continuously output.

  Similarly, when the V-phase thyristor gate signal 601V-1 and the W-phase thyristor gate drive signal 601W-1 are input, the V1-phase synchronization section identification unit 510V1 outputs the V1-phase synchronization section signal 603V-1. W1 phase synchronization section identification section 510W1 outputs W1 phase synchronization section signal 603W-1 when W phase thyristor gate signal 601W-1 and U phase thyristor gate signal 601U-1 are input to W1 phase synchronization section identification section 510W1. To do.

  The current output identification unit 505 uses the synchronization interval signal 603U-1, the synchronization interval signal 603V-1, and the synchronization interval signal 603W-1 to generate a P-side thyristor in the interval in which the U1-phase synchronization interval signal 603U-1 is output. The current detection signal IP1 is extracted.

  The U1-phase detection signal average value calculation unit 511U1 calculates the average value of the P-side thyristor current detection signal IP1 in the U1-phase synchronization interval. The U1-phase detection signal average value calculation unit 511U1 outputs the calculated average value as a U-phase thyristor output current IU1 for each cycle. Similarly, although not shown, the U-phase detection signal average value calculation units 511U2 to 511UN calculate the average value of the P-side thyristor current detection signal IP2 to the average value of IPN, respectively, and the U-phase thyristor output currents IU2 to IU2 Output as IUN for each period.

Next, an example of the input signal waveform identified by the current output identifying unit 505 will be described with reference to FIG.
As shown in FIG. 8, when the synchronization interval signal 603U-1 is on, the synchronization interval signal 603V-1 and the synchronization interval signal 603W-1 are off. Similarly, when the synchronization interval signal 603V-1 is on, the synchronization interval signal 603U-1 and the synchronization interval signal 603W-1 are off. When the synchronization interval signal 603W-1 is on, the synchronization interval signal 603U-1 and the synchronization interval signal 603V-1 are off. IP1 illustrated in FIG. 8 indicates an average value of the P-side thyristor current detection signal IP1 that is an input signal when any one of the synchronization interval signals 603U-1, 603V-1, and 603W-1 is on. .

Next, a detailed configuration example of the reference value calculation unit 517 will be described with reference to FIG.
The U-phase thyristor output currents IU 1, IU 2,..., IUN are input to an average value calculation unit 506 provided in the reference value calculation unit 517. The average value calculation unit 506 outputs the U-phase output current average value 604 calculated using the output currents IU1, IU2,..., IUN of the U-phase thyristors to the upper and lower limit value calculation unit 508. When the average value calculation unit 506 receives any of the U-phase thyristor failure signals 611U1, 611U2,..., 611UN, the average value calculation unit 506 corresponds to the number of the received U-phase thyristor failure signals 611U1, 611U2,. The internal parameter for calculating the U-phase output current average value 604 is changed according to the number of failed thyristors. For example, when three thyristors are out of order, the average value calculation unit 506 is obtained by subtracting 3 from the number of target thyristors in order to obtain the U-phase output current average value 604. Change to

  The upper and lower limit value calculation unit 508 uses the constraint condition setting value 605 and the U phase output current average value 604 output from the constraint condition setting unit 507 to calculate the upper and lower limit values of the U phase thyristor output current according to a certain constraint condition equation. calculate. The constraint condition setting value 605 is a value set based on, for example, the current unbalance rate. For example, when the current unbalance rate is 10%, the upper and lower limit value calculation unit 508 uses the U-phase output current average value 604 as a reference value, sets the current value 10% larger than the reference value as the upper limit value, The current value 10% smaller than the value is calculated as the lower limit value. Further, the upper and lower limit value calculation unit 508 calculates, for example, the calculated upper limit value and lower limit value as the range of the current balance ratio. The upper / lower limit value calculation unit 508 outputs the calculated U-phase thyristor output current upper / lower limit value 606.

FIG. 10 shows the current balance control results of the U-phase output currents IU1, IU2,..., IUN.
In the first period (period 1), the U-phase thyristor output current upper and lower limit value 606 is calculated using the output currents IU1, IU2,..., IUN and the constraint condition setting value 605. Then, comparison section 515 compares the difference between U-phase thyristor output current upper / lower limit value 606 and each of output currents IU1, IU2, ..., IUN. Then, it can be seen that the output current IU1 is the maximum current value that deviates from the upper and lower limit value 606 of the U-phase thyristor output current.

  Next, in the second cycle (cycle 2), the output current IU1 is decreased by outputting the U1-phase control angle command value 610U1 set in the direction of delaying the phase with respect to the output current IU1. At the same time, the comparison unit 515 compares the output currents IU1, IU2,..., IUN with respect to the difference between the U-phase thyristor output current upper and lower limit values 606, and the output current IUN becomes the U-phase thyristor output current upper and lower It can be seen that the minimum current value deviates from the value 606.

  In the third period (period 3), the UN phase control angle command value 610UN set in the direction of advancing the phase with respect to the output current IUN is output, the output current IUN increases, and the output current IU1 It is output in a state where the previous value of phase control angle command value 610U1 is held. For this reason, the control on the output current IU1 is continued, so that the output current IU1 decreases.

  As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained in each of the U phase, V phase, W phase, X phase, Y phase, and Z phase. Further, it is possible to control the output current of the thyristor that is most deviated from the range based on the constraint condition, and to suppress variations in the average output current of each phase thyristor. Further, it is possible to control the output current of the thyristor according to the current sharing, and to suppress the variation of the average output current of each phase thyristor. Thereby, it is possible to realize a highly accurate current balance between the parallel thyristors without selecting the thyristors connected in parallel according to the electrical characteristics.

  Further, it is possible to delay the gate pulse of the thyristor bearing a current larger than the upper limit value and advance the gate pulse of the thyristor bearing a current smaller than the lower limit value.

  In addition, a set value necessary for current balance control can be automatically calculated. Specifically, the upper and lower limit values can be automatically calculated by designating a constraint condition in which the current unbalance rate between the elements is 10%, for example.

  In addition, even under conditions where a thyristor failure or the like occurs, it is possible to perform stable current balance control between thyristors with high accuracy by automatically changing setting values such as parameters.

  The same effect can be obtained by using IEGT or IGBT as the power semiconductor instead of the thyristor.

  In the first embodiment and the second embodiment, each component can be realized by hardware or software. For example, the current balance control device 10 shown in FIG. 1 may be realized by hardware, and the phase control angle command unit 300 may be realized by software.

  Further, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, all the constituent elements shown in the embodiment or some constituent elements may be deleted. Furthermore, you may combine suitably the component covering different embodiment.

DESCRIPTION OF SYMBOLS 100 ... Three-phase alternating current power supply, 101 ... Gate signal generation part, 103-1 ... Bridge, 200R ... R phase synchronous signal, 300 ... Phase control angle command part, 301 ... Current balance diagnostic part, 302-1 ... Gate signal generation part , 500 ... Gate signal generator, 501 ... Phase control angle command part, 502 ... Current balance diagnostic part, 503-1P ... P-side current detector, 504U ... U-phase gate signal generator, 504U-1 ... U-phase thyristor gate Signal generation unit, 505 ... current output identification unit, 506 ... average value calculation unit, 507 ... constraint condition setting unit, 508 ... upper / lower limit value calculation unit, 509U1 ... U-phase thyristor difference calculation unit, 510U1 ... U1-phase synchronization section identification unit 511U1... U1 phase detection signal average value calculation unit, 512U1 +... U1 phase delay control angle setting unit, 512U1... U1 phase advance control angle setting unit, 513U1. Star control angle command value synthesis unit, 514U: U phase failure detection unit, 515 ... comparison unit, 516U1 ... U1 phase previous value holding unit, 517 ... reference value calculation unit, FU1 ... U phase fuse, G1 ... power semiconductor gate circuit, GU1 ... U-phase thyristor gate circuit, I ... power semiconductor output total current, IU ... U-phase thyristor output total current, T1 ... power semiconductor, TU1 ... U-phase thyristor.

Claims (8)

A current balance control device for controlling the current balance of a plurality of parallel-connected power semiconductors that alternately repeat energization and pause,
Check whether there is any deviation from the range of the predetermined current value among the plurality of output currents output from the plurality of power semiconductors at a certain period. Control means for driving and controlling the gate of the corresponding power semiconductor so that the output current is within the range of the predetermined current value ,
The control means includes
Phase control angle command means for periodically outputting a phase control angle command signal to the plurality of power semiconductors;
The balance of a plurality of output currents output from the plurality of power semiconductors is diagnosed for each period, and the most deviating output current is suppressed or promoted, so that the most deviating output current falls within the range. Current balance diagnostic means for outputting a current balance control signal for
A current balance control device comprising: a gate signal generation unit that periodically supplies a gate signal corresponding to the current balance control signal to a corresponding power semiconductor according to the phase control angle command signal . A plurality of bridges including the plurality of power semiconductors are connected in parallel with six U-phase, V-phase, W-phase, X-phase, Y-phase, and Z-phase as one bridge,
A current detecting means for detecting an output current of the power semiconductor connected in parallel in the same phase;
The current balancing means for diagnosing said current detecting means in response to the detected output current to generate the gate signal including a control to suppress the output current unbalance of each power semiconductor of the same phase, so that consists claimed Item 2. The current balance control device according to Item 1 . The phase control angle command means collectively outputs the phase control angle command signal to each in-phase power semiconductor,
The current balance diagnosis means outputs a current balance control signal that decreases the output current for a power semiconductor having the highest current sharing ratio and increases the output current for a power semiconductor having the lowest current sharing ratio,
The gate signal generating means, wherein in accordance with the phase control angle command signal, the current balance control signal to generate a gate signal corresponding to the current balance control device according to claim 2 that is configured to. The current balance diagnosis means includes
Current output identification means for identifying the output phase of the output current detected by the current detection means;
Based on the in-phase output current identified by the current output identification means, a failure detection means for detecting a failed power semiconductor and outputting a failure detection signal;
A reference value calculation means for calculating a reference value of the in-phase output current based on the output current of each in-phase power semiconductor identified by the current output identification means and the failure detection signal generated by the failure detection means;
A difference calculating means for calculating a difference between an output current of each power semiconductor in the same phase and the reference value;
Comparing means for comparing each difference between the power semiconductors in the same phase, detecting the largest absolute value of the difference, and determining the power semiconductor to be controlled;
Current balance phase control angle setting means for setting a phase control angle for the power semiconductor to be controlled and outputting a lead control angle command signal or a delay control angle command signal;
Control angle command value synthesizing means for synthesizing the advance control angle command signal or the delay control angle command signal output from the current balance phase control angle setting means for each cycle, and outputting the control angle command value as a control angle command value;
When the advance control angle command signal or the delay control angle command signal is not output from the control angle command value synthesizing means, the previous value is held and the advance control angle command signal or the delay control angle command signal is output. A previous value holding means for outputting, as a current balance control signal, a value obtained by adding the advance control angle command signal or the delay control angle command signal to the previous value;
Further comprising Ru claim 2 current balance control device according to. The current output identification means includes
Synchronization section identifying means for identifying a synchronization section of each phase based on the gate signal generated by the gate signal generating means;
Based on the current detection signal of the output current detected by the current detection means and the identification signal of the synchronization interval identified by the synchronization interval identification means, a detection signal average that calculates and outputs an average value of the current detection signal Value calculation means;
Further comprising Ru claim 4 current balance control device according to. The reference value calculating means includes
Based on the output current of each in-phase power semiconductor and the failure detection signal, average value calculating means for calculating the average output current value of each in-phase power semiconductor;
Restriction condition setting means for setting a current unbalance rate that defines a restriction condition of the output current of each power semiconductor in the same phase;
Upper and lower limit value calculating means for calculating upper and lower limit values centered on the reference value based on the output current average value and the current imbalance rate;
Further comprising Ru claim 4 current balance control device according to. A rectifier comprising the current balance control device according to any one of claims 1 to 6 . A current balance control device for controlling a current balance of a plurality of power semiconductors connected in parallel that alternately repeat energization and pause, and a current balance control method,
When the control means checks whether or not there is a deviation from a predetermined current value range among the plurality of output currents output from the plurality of power semiconductors at a constant cycle, and there is a deviation , Driving and controlling the gate of the corresponding power semiconductor so that the most deviating output current falls within the range of the predetermined current value ,
The phase control angle command means of the control means periodically outputs a phase control angle command signal to the plurality of power semiconductors,
The current balance diagnosing means of the control means diagnoses the balance of the plurality of output currents output from the plurality of power semiconductors for each period, and suppresses or promotes the most deviating output current to make the most deviating. Output a current balance control signal so that the output current is within the range,
A current balance control method in which a gate signal corresponding to the current balance control signal is periodically supplied to a corresponding power semiconductor by a gate signal generation unit of the control unit in accordance with the phase control angle command signal .

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