JP6367108B2 - Pseudo random number generator - Google Patents

Description

  The present invention relates to a pseudorandom number generator using a ferroelectric memory element.

  As a conventional pseudo random number generation device, as disclosed in Patent Document 1, for example, a plurality of pseudo random number generation circuits are connected in series, and a random number is sequentially generated from a set initial value by a plurality of pseudo random number generation circuits. It is known that pseudorandom numbers are generated by generating and output to the outside.

JP2013-64898A

  In the conventional pseudo-random number generation device, the number of pseudo-random number generation circuits is determined in advance, so that the pseudo-random number generated from the set initial value can be easily guessed, which may cause a problem in security.

  The present invention provides a pseudo-random number generator capable of improving security.

  The pseudo-random number generation device of the present invention includes a first register that holds first random number data while a power supply voltage that is equal to or higher than a drive voltage is supplied, and the first random number that is stored in the first register. A first arithmetic circuit that generates second random number data based on the data; a second register that holds the second random number data while the power supply voltage equal to or higher than the drive voltage is supplied; A first ferroelectric memory that holds the first random number data during a period in which the power supply voltage equal to or higher than the drive voltage is not supplied to the first register; and the power supply voltage equal to or higher than the drive voltage is stored in the second register And a second ferroelectric memory for holding the second random number data during a period during which the second random number data is not supplied.

  According to the pseudo random number generation device of the present invention, security can be improved.

1 shows a pseudorandom number generator 1 according to an embodiment of the present invention. 3 is a timing chart showing the operation of the pseudorandom number generator 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The numerical values, circuits, etc. described below can be selected as appropriate without departing from the spirit of the present invention.

  [Embodiment]

  FIG. 1 shows a pseudorandom number generator 1 according to an embodiment of the present invention. The pseudo random number generation device 1 includes a control unit CP, a register RG1 as a fourth register, a register RG2 as a first register, a register RG3 as a second register, and a register RG4 as a third register. A register unit RGP, an arithmetic unit OP1 having an arithmetic circuit OP1 as a first arithmetic circuit, and an arithmetic circuit OP2 as a second arithmetic circuit, and a non-volatile, strong ferroelectric memory as a fourth ferroelectric memory. A ferroelectric memory unit FMP including a dielectric memory FM1, a first ferroelectric memory FM2, a second ferroelectric memory FM3, and a third ferroelectric memory FM4 is provided. . Although there are other nonvolatile memories such as an EEPROM, the ferroelectric memory is advantageous in terms of power saving as compared with other memories.

  Further, a power supply voltage VDD of, for example, 5V is supplied to each of the control unit CP, the register unit RGP, the operation unit OPP, and the ferroelectric memory unit FMP of the pseudorandom number generation device 1.

  Here, the control unit CP uses, for example, a voltage of 1.5 V generated by stepping down the power supply voltage VDD by means such as a regulator as its drive voltage. Further, the calculation unit OPP uses, for example, a voltage of 1.5 V generated by stepping down the power supply voltage VDD by means of a regulator or the like as its drive voltage. Further, the register unit RGP uses, for example, a voltage of 1.5 V generated by stepping down the power supply voltage VDD by means such as a regulator as its drive voltage. Further, the ferroelectric memory unit FMP uses, for example, a voltage of 1.5 V generated by stepping down the power supply voltage VDD by means such as a regulator as its drive voltage.

  The controller CP is connected to the arithmetic circuits OP1 and OP2 of the arithmetic unit OPP, and controls the arithmetic circuits OP1 and OP2 of the arithmetic unit OPP by the control signal CPO. The arithmetic unit OPP is driven when the control signal CPP is at a high level H, for example, and is stopped when the control signal CPP is at a low level L.

  The control unit CP is connected to the ferroelectric memories FM1 to FM4 of the ferroelectric memory unit FMP, and controls the ferroelectric memories FM1 to FM4 of the ferroelectric memory unit FMP by the control unit CPM. . The ferroelectric memory unit FMP is driven when the control signal CPM is at a high level H, for example, and is stopped when the control signal CPM is at a low level L.

  In FIG. 1, the control unit CP and the arithmetic circuits OP1 and OP2 of the arithmetic unit OPP are connected by one wiring. However, the control unit CP and the arithmetic circuits OP1 and OP2 of the arithmetic unit OPP are connected to each other. The wiring to be connected may be independent. In FIG. 1, the control unit CP and each of the ferroelectric memories FM1 to FM4 of the ferroelectric memory unit FMP are connected by a single wiring, but the control unit CP and each of the ferroelectric memories FM1 to FM1 are shown. The wiring connecting FM4 may be independent.

  The register RG1 is connected to the ferroelectric memory FM1, the register RG2, and the register RG4. The register RG1 holds the random number data RD1 as the first random number data while the power supply voltage VDD is supplied at the driving voltage or higher. The random number data is composed of, for example, an 8-bit bit string. In the present embodiment, the register RG1 holds the random number data RD1. However, the register RG1 may hold data set from the outside of the pseudorandom number generator 1.

  The register RG2 is connected to the register RG1, the ferroelectric memory FM2, and the arithmetic circuit OP1. The register RG2 holds the random number data RD1 while the power supply voltage VDD is supplied at the self drive voltage or higher. In the present embodiment, the register RG2 holds the random number data RD1. However, the register RG2 may hold data set from the outside of the pseudorandom number generator 1.

  The register RG3 is connected to the ferroelectric memory FM3, the arithmetic circuit OP1, and the arithmetic circuit OP2. The register RG3 holds the random number data RD2 as the second random number data while the power supply voltage VDD is supplied at or above its own driving voltage. In the present embodiment, the register RG3 holds the random number data RD2. However, the register RG3 may hold data set from the outside of the pseudo random number generation device 1.

  The register RG4 is connected to the arithmetic circuit OP2, the ferroelectric memory FM4, and the register RG1. The register RG4 holds the random number data RD3 while the power supply voltage VDD is supplied at the self drive voltage or higher. In the present embodiment, the register RG4 holds the random number data RD3. However, the register RG4 may hold data set from the outside of the pseudorandom number generator 1. The register RG4 outputs the random number data RD3 as output data to the outside of the pseudo random number generation device 1.

  The arithmetic circuit OP1 generates random number data RD2 as second random number data based on the random number data RD1 output from the register RG2 when the control signal CPO supplied from the control unit CP is at the high level H, and registers Output to RG3. Here, the arithmetic circuit OP1 may generate the random number data RD2 by shifting the random number data RD1 by, for example, two digits, and the present invention is not limited to this, and various operations can be used.

  The arithmetic circuit OP2 generates random number data RD3 as third random number data based on the random number data RD2 output from the register RG2 when the control signal CPO supplied from the control unit CP is at the high level H, Output to RG4. Here, the arithmetic circuit OP2 may generate the random number data RD3 by shifting the random number data RD2 by, for example, two digits, and the present invention is not limited to this, and various operations can be used.

  The ferroelectric memory FM1 is composed of a nonvolatile ferroelectric capacitor. When the control signal CPM supplied from the control unit CP is at the high level H, the random number data RD1 held in the register RG1 is stored. Store.

  The ferroelectric memory FM2 is composed of a nonvolatile ferroelectric capacitor. When the control signal CPM supplied from the controller CP is at a high level H, the random number data RD1 held in the register RG2 is stored. Store.

  The ferroelectric memory FM3 is composed of a nonvolatile ferroelectric capacitor. When the control signal CPM supplied from the controller CP is at a high level H, the random number data RD2 held in the register RG3 is stored. Store.

  The ferroelectric memory FM4 is composed of a nonvolatile ferroelectric capacitor. When the control signal CPM supplied from the control unit CP is at the high level H, the random number data RD3 held in the register RG4 is stored. Store.

  FIG. 2 is a timing chart showing the operation of the pseudorandom number generator 1. The pseudo random number generation device 1 performs normal operation in a period A after time t0 to t2 and time t6, and ferroelectrically stores the random number data held in the registers RG1 to RG4 of the register unit RGP in a period B from time t2 to t3. A data storing operation is performed to store in each of the ferroelectric memories FM1 to FM4 of the body memory unit FMP, and the power supply voltage VDD does not reach the driving voltage of each component of the pseudorandom number generator 1 in the period C from time t3 to t5. Data read operation in which the random number data stored in each of the ferroelectric memories FM1 to FM4 of the ferroelectric memory unit FMP is read to each of the registers RG1 to RG4 of the register unit RGP in the period D from time t5 to t6. I do.

  Note that the times t0 to t6 in FIG. 2 are common to each signal waveform. As for each signal waveform, it is assumed that the signal waveform up to the previous time is maintained unless otherwise specified.

  The pseudorandom number generation device 1 performs a normal operation at times t0 to t1. The normal operation is an operation in which the arithmetic circuit OPP generates random number data based on the random number data held in the register unit RGP and outputs the generated random number data to the outside as, for example, random number data RD3.

  At time t0 to t1, the power supply voltage VDD is 5 V, for example. Further, the control signal CPO is at a high level H, and the control signal CPM is at a low level L.

  At time t1, the power supply is turned off and the power supply voltage VDD starts to decrease. At this time, the control unit CP, the calculation unit OPP, and the register unit RGP continue normal operation because the power supply voltage VDD is equal to or higher than its own drive voltage.

  At time t2, the power supply voltage VDD falls below the threshold voltage Vref1 as the first threshold voltage of 3.5 V set in the control unit CP, for example. When the control unit CP detects this, the control unit CP outputs a high level control signal CPM to the ferroelectric memory unit FMP. Thereby, the pseudo random number generation device 1 starts a data storage operation.

  At time t3, the power supply voltage VDD falls below the threshold voltage Vref2 as the second threshold voltage of 1.5V that is the driving voltage of the register unit RGP. As a result, the random number data held in the register unit RGP is lost. However, the random number data held in the register unit RGP is already stored in the nonvolatile ferroelectric memory unit FMP at the time t3 by the data storing operation started from the time t2, and the power supply higher than the drive voltage Even in the period C in which the voltage VDD is not supplied to the register unit RGP, the voltage VDD is held in the ferroelectric memory unit FMP. Therefore, according to the pseudo-random number generation device 1, even when the power supply voltage VDD drops below the drive voltage corresponding to the threshold voltage Vref2 of the register unit RGP, the random number data held in the register unit RGP Is not lost from the pseudo-random number generator 1.

  At time t4, the power supply is turned on and the power supply voltage VDD starts to rise. At this time, the control unit CP, the calculation unit OPP, and the register unit RGP are in a stopped state because the power supply voltage VDD is equal to or lower than the drive voltage corresponding to the threshold voltage Vref2 of its own.

  At time t5, the power supply voltage VDD exceeds the threshold voltage Vref2 of 1.5 V set in the control unit CP, for example. When the control unit CP detects this, the control unit CP outputs a high level control signal CPM to the ferroelectric memory unit FMP. Thereby, the pseudo random number generation device 1 starts the data reading operation.

  When the control unit CP detects that the power supply voltage VDD is equal to or higher than the threshold voltage Vref1 at time t6, the control unit CP controls the output of the random number data RD3 from the register RG4 to the outside. At this time, the random number data RD3 is generated by the pseudorandom number generator 1 before the power is turned off and the power supply voltage VDD becomes equal to or lower than the drive voltage corresponding to the threshold voltage Vref2 of each configuration of the pseudorandom number generator 1. Random number data generated based on the random number data. For this reason, the random number data RD3 generated and output by the pseudo random number generation device 1 according to the present invention is the initial value after the power supply voltage VDD rises due to factors such as turning on the power as in the conventional pseudo random number generation device 1. Compared to random number data generated by performing random number generation on a value a predetermined number of times, it is much more difficult to guess.

  As described above, according to the pseudo random number generation device 1 of the present invention, security can be improved.

  In the embodiment of the present invention, the exchange of random number data between the register unit RGP and the ferroelectric memory unit FMP when the power supply voltage VDD is increased or decreased as the power is turned on / off is described. However, the exchange of random number data between the register unit RGP and the ferroelectric memory unit FMP is not limited to that caused by a change in the power supply voltage VDD. That is, for example, even when the power supply voltage VDD does not vary and does not actually decrease or increase, the random number held in the register unit RGP by outputting the high-level control signal CPM from the control unit CP. Data can be written in the ferroelectric memory unit FMP, and random number data stored in the ferroelectric memory unit FMP can be held in the register unit RGP.

  In the embodiment of the present invention, the configuration in which the random number data RD3 is output from the register RG4 as the output data from the pseudorandom number generator 1 is described. However, the random number data RD3 is directly output from the arithmetic circuit OP2 to the pseudorandom number generator. 1 may be configured to be output as output data from 1.

  According to the pseudo-random number generation apparatus according to the present invention, security can be improved, and thus industrial applicability is extremely high.

1 Pseudorandom number generator CP control unit CPM, CPO control signal FMP ferroelectric memory unit FM1, FM2, FM3, FM4 ferroelectric memory OPP operation unit RD1, RD2, RD3 Random number data RGP register unit RG1, RG2, RG3, RG4 Register VDD Power supply voltage

Claims (6)

A first register for holding first random number data while a power supply voltage equal to or higher than the drive voltage is supplied;
A first arithmetic circuit that generates second random number data based on the first random number data stored in the first register;
A second register for holding the second random number data while the power supply voltage equal to or higher than the drive voltage is supplied;
A first ferroelectric memory that holds the first random number data during a period in which the power supply voltage equal to or higher than the drive voltage is not supplied to the first register;
A second ferroelectric memory that holds the second random number data during a period in which the power supply voltage equal to or higher than the driving voltage is not supplied to the second register;
A pseudo-random number generator characterized by comprising: The first random number data held in the first register is controlled to be stored in the first ferroelectric memory, and the second random number data held in the second register is stored in the first register. 2 to store in the ferroelectric memory,
The second random number data stored in the second ferroelectric memory is controlled to hold the first random number data stored in the first ferroelectric memory in the first register. 2. The pseudorandom number generation device according to claim 1, further comprising a control unit that performs control for holding the second register in the second register. The controller is
When the power supply voltage supplied to the first register and the second register is lower than the first threshold voltage from when the power supply voltage is equal to or higher than the first threshold voltage, The first random number data held in the register is controlled to be stored in the first ferroelectric memory, and the second random number data held in the second register is changed to the second ferroelectric data. Control to store in the body memory,
From the case where the power supply voltage supplied to the first register and the second register is a second threshold voltage lower than the first threshold voltage, the second threshold voltage The first random number data stored in the first ferroelectric memory is controlled to be held in the first register, and stored in the second ferroelectric memory. The pseudo-random number generation device according to claim 2, wherein the second random number data is controlled to be stored in the second register. A second arithmetic circuit for generating third random number data based on the second random number data stored in the second register;
A third register for holding the third random number data while the power supply voltage equal to or higher than the drive voltage is supplied;
A third ferroelectric memory that holds the third random number data during a period in which the power supply voltage equal to or higher than the drive voltage is not supplied to the third register;
The pseudo-random number generator according to claim 1, wherein the pseudo-random number generator is provided.   The pseudorandom number generation device according to claim 4, wherein the third random number data generated by the second arithmetic circuit is output to the outside. A fourth register for holding the first random number data and outputting the first random number data to the first register while a power supply voltage equal to or higher than a drive voltage is supplied;
A fourth ferroelectric memory that holds the first random number data during a period in which the power supply voltage equal to or higher than the drive voltage is not supplied to the fourth register;
The pseudorandom number generator according to claim 1, wherein the pseudorandom number generator is provided.

Images