JP6365695B2 - Signal processing apparatus and signal processing method - Google Patents

Description

  The present invention relates to a signal processing device and a signal processing method, and more particularly to a signal processing device and a signal processing method capable of reducing power consumption.

  A coherent optical transmission system capable of high-capacity and high-speed communication has been put into practical use. In a coherent optical transmission system, a coherent optical receiver is used to demodulate signal light.

  FIG. 10 is a block diagram showing a configuration of a general coherent optical receiver 800. The coherent optical receiver 800 includes a front end 801, an analog-digital converter (ADC) 802, a local oscillation light source 803, and a digital signal processor (DSP) 900. The local oscillation light source 803 is a light source, for example, a semiconductor laser. The front end 801 outputs a beat signal between the local oscillation light and the signal light output from the local oscillation light source 803 as an analog reception signal. The front end 801 has a known configuration including, for example, a beam splitter, a 90-degree hybrid, and a photodiode. The analog reception signal is converted into a digital reception signal by the ADC 802. The digital received signal is input to the DSP 900. The DSP 900 outputs data obtained by performing arithmetic processing on the digital reception signal as reception data. The DSP 900 also performs error correction on the digital received signal. In a coherent optical transmission system, an error correction code called an LDPC (low density parity check) code may be used.

  FIG. 11 is a block diagram showing a configuration of a general DSP 900 used in the coherent optical receiver 800. The DSP 900 includes a demodulation unit 901, an error correction unit 902, and a framer 903. The demodulator 901 performs symbol determination on the digital reception signal input from the ADC 802 and generates digital data. The error correction unit 902 corrects an error in the demodulated digital data. The framer 903 converts the digital data into received data having a frame of a predetermined format and outputs the received data.

  In relation to the present invention, Patent Document 1 describes a decoding apparatus that decodes an LDPC code in units of frames.

Japanese Patent Laying-Open No. 2005-064735 (paragraph [0135], FIG. 15)

  The error correction unit 902 performs error correction processing on the input digital data. The error correction unit 902 consumes constant power regardless of the load. For this reason, the DSP 900 described in FIGS. 10 and 11 has a problem of high power consumption and a large amount of heat generation. Further, the DSP 900 has a problem that the design cost and the parts cost for driving and cooling the DSP 900 are high. On the other hand, if the scale of the error correction unit 902 is reduced in order to reduce power consumption, the necessary error correction capability may not be ensured.

Against this background, there is a need for a technique for achieving both reduction in power consumption and securing error correction capability in a DSP. However, Patent Document 1 does not disclose such a technique.
(Object of invention)
An object of the present invention is to provide a signal processing device and a signal processing method capable of achieving both reduction of power consumption and ensuring of error correction capability.

  A signal processing apparatus according to the present invention includes: an error correction unit in which a plurality of calculation units that perform error correction of an input signal are connected in series; an error correction unit that is connected in parallel; and the calculation unit for the signal Control means for controlling the operating state of each of the correction blocks based on the number of error corrections.

  The signal processing method of the present invention performs error correction of a signal input by an error correction unit in which a correction block in which a plurality of calculation units are connected in series is connected in parallel, and the signal in any of the calculation units The operation state of each of the correction blocks is controlled based on the number of error corrections.

  The signal processing device and the signal processing method of the present invention have an effect that it is possible to achieve both reduction of power consumption and securing of error correction capability.

It is a block diagram which shows the structure of the signal processing apparatus of 1st Embodiment. It is a block diagram which shows the structure of the error correction part of a signal processing apparatus. It is a block diagram which shows the structure of a correction block. It is a graph which shows the example of the number of error corrections of a calculating part. It is a figure which shows the example of the operation state of the correction block when the load of an error correction part is small. It is a figure which shows the example of the operation state of the correction block in case the load of an error correction part is large. It is a figure which shows the other example of the operation state of a correction block. It is a flowchart which shows the example of control of the error correction part by a control part. It is a block diagram which shows the structure of the coherent optical receiver of 2nd Embodiment. It is a block diagram which shows the structure of a general coherent optical receiver. It is a block diagram which shows the structure of the common signal processor (DSP) used with a coherent optical receiver.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration of a signal processing device 100 according to the first embodiment. The signal processing apparatus 100 of the present embodiment is a signal processing processor (digital signal processor, DSP) mounted on an optical receiver. A digital received signal is input to the signal processing apparatus 100. The digital reception signal is a signal obtained by digitizing an analog reception signal obtained by photoelectrically converting signal light at the front end of the optical receiver by the ADC. The digital received signal includes phase information of phase-modulated signal light. The signal processing apparatus 100 demodulates the digital received signal, corrects the error, puts it on a frame of a predetermined format, and outputs it as received data.

  The signal processing apparatus 100 includes a demodulation unit 101, an error correction unit 102, a framer 103, and a control unit 104. The demodulator 101 performs symbol determination on the digital reception signal input from the ADC and converts it into digital data. The error correction unit 102 corrects digital data errors. The framer 103 converts the digital data into frame data of a predetermined format and outputs it as received data. The demodulator 101 is sometimes called a de-mapper. Since the configurations and operations of the demodulator 101 and the framer 103 are known, detailed description thereof will be omitted.

  The control unit 104 controls the operation of each unit of the signal processing device 100. The control unit 104 may control the operation of the signal processing device 100 by executing a program as a central processing unit (CPU). The program is recorded on a fixed recording medium provided inside or outside the signal processing apparatus 100. The recording medium is, for example, a semiconductor memory, a magnetic fixed disk, or an optical disk, but is not limited thereto. In FIG. 1, the control unit 104 is described as a block independent of the demodulation unit 101, the error correction unit 102, and the framer 103. However, the function of the control unit 104 may be included in any of the functions of the demodulation unit 101, the error correction unit 102, and the framer 103. The control unit 104 may be provided outside the signal processing apparatus 100 and may remotely control the demodulation unit 101, the error correction unit 102, and the framer 103.

  In the present embodiment, the error correction unit 102 performs digital data error correction using soft-decision forward error correction (SD-FEC). An error correction code called a low density parity check (LDPC) code is used as an error correction code for digital data. The LDPC code can be decoded at high speed by parallel processing.

  FIG. 2 is a block diagram illustrating a configuration of the error correction unit 102 included in the signal processing apparatus 100. The error correction unit 102 includes N (N is a natural number) correction blocks 301 to 30N. The error correction unit 102 performs error correction on the digital data input from the demodulation unit 101, and outputs the corrected digital data to the framer 103.

  The error correction unit 102 performs error correction using correction blocks 301 to 30N connected in parallel. For example, the error correction unit 102 divides digital data in time according to the number of correction blocks in operation, and distributes the data so that the amount of data input to each of the correction blocks in operation is equal. Perform block load balancing. However, the load distribution procedure for the correction block is not particularly limited. The error correction unit 102 combines the digital data output from each correction block in time series order and outputs the combined data to the framer 103. The control unit 104 may control such distribution, division, and combination of digital data with respect to the error correction unit 102. In this case, the control unit 104 dynamically distributes the digital data only to the correction block being operated. In this embodiment, digital data is not input to a correction block that is not operating.

  FIG. 3 is a block diagram showing a configuration of the correction block 301 included in the error correction unit 102. In FIG. 3, the correction block 301 is described as an example, but the other correction blocks 302 to 30N have the same configuration. The correction block 301 includes M (M is a natural number) arithmetic units 401 to 40M. The arithmetic units 401 to 40M are connected in series inside the correction block 301. Hereinafter, a case where any of the correction blocks 301 to 30N includes M arithmetic units will be described. However, the number M of the calculation units may not be the same in each of the correction blocks 301 to 30N.

  First, error correction processing is performed on the digital data input from the demodulation unit 101 in the calculation unit 401. If an error remains as a result of the error correction processing in the calculation unit 401, the calculation unit 402 further performs error correction. As described above, the correction block 301 performs error correction processing on the digital data using the M arithmetic units, and outputs the processed digital data to the framer 103. Similarly, the other correction blocks 302 to 30N included in the error correction unit 102 also perform error correction processing on the digital data, and output the processed digital data to the framer 103.

  The correction block 301 shown in FIG. 3 further has a function of outputting the number of error corrections in the arithmetic units 401 to 40M to the control unit 104. The number of error corrections is, for example, the number of error corrections of each arithmetic unit per fixed time or the number of error corrections per fixed amount of data, but is not limited thereto. The control unit 104 collects the number of error corrections of the calculation units 401 to 40M for each of the correction blocks 301 to 30N.

  FIG. 4 is a graph illustrating an example of the number of error corrections of the arithmetic units 401 to 40M included in the correction block 301. The vertical axis in FIG. 4 indicates the number of error corrections of the arithmetic units 401 to 40M, and the horizontal axis indicates the number of stages of the arithmetic units. The number of error corrections is an arbitrary scale. The number of stages in the calculation unit is a number in which the input side of digital data is 1, and the output side (final stage) is M, and corresponds to the calculation units 401, 402,.

  In the example of FIG. 4, the arithmetic units 401 to 403 close to the input of the correction block 301 have a relatively large number of error corrections, and the arithmetic units close to the output of the correction block 301 have a small number of error corrections. This is because the error of the received data generally decreases as it approaches the output of the correction block due to a plurality of error correction processes in the arithmetic unit.

  In the error correction unit 102, when there are many errors in the received data and the number of error corrections is large as a result, the load of error correction processing in the error correction unit 102 is large. In this case, it is necessary to operate many correction blocks. However, when there are few errors in the received data, an error correction process with a required quality can be executed without operating many correction blocks. In the present embodiment, the control unit 104 controls the operation state of the correction blocks 301 to 30N based on the number of error corrections of the arithmetic units 401 to 40M output from the correction blocks 301 to 30N.

  Specifically, when the number of error corrections in the last calculation unit (calculation unit 40M in FIG. 3) of a certain correction block is less than the first threshold, the control unit 104 determines the error of the correction block including the calculation unit. Stop the correction process. The control unit 104 distributes digital data to correction blocks for which error correction processing has not been stopped, and does not distribute digital data to correction blocks for which error correction processing has been stopped. Hereinafter, “stopping (or operating) the error correction processing of the correction block” is simply referred to as “stopping (or operating) the correction block”. The control unit 104 may operate or stop each correction block by executing or stopping power supply for each correction block. Note that the control unit 104 may continue the distribution of digital data to correction blocks with sufficiently few errors and stop only error correction processing of the correction blocks.

  For example, when the number of error corrections in the calculation unit 40M of the correction block 302 is less than the first threshold, the control unit 104 stops the correction block 302. Then, the control unit 104 continues the digital data error correction processing by parallel processing using the remaining correction blocks 301 and 303 to 30N. As described above, the control unit 104 can suppress the power consumption of the error correction unit 102 by stopping the correction blocks having a small number of error corrections (that is, the load of error correction is small).

  FIG. 5 is a diagram illustrating an example of an operation state of the correction blocks 301 to 30N when the load of the error correction unit is small. In FIG. 5, the stopped correction blocks are indicated by broken lines. The number of error corrections output from the operation unit 40M at the last stage of the correction block 301 shown in FIG. 5 is equal to or greater than the first threshold. Then, the number of error corrections output from the last-stage arithmetic unit 40M of each of the correction blocks 302 to 30N is less than the first threshold value. Therefore, the control unit 104 operates the correction block 301 and stops the correction blocks 302 to 30N. By stopping the correction block with a small load among the correction blocks 301 to 30N, power consumption and heat generation of the error correction unit 102 are suppressed.

  On the other hand, when the number of error corrections in the last operation unit of a certain correction block exceeds the second threshold, the control unit 104 gives an instruction to start error correction processing to one of the stopped correction blocks. The second threshold is greater than the first threshold. For example, in FIG. 5, when the number of error corrections of the calculation unit 40M of the correction block 301 exceeds the second threshold while the correction block 302 is stopped, the control unit 104 starts the operation of the correction block 302. Then, the control unit 104 continues digital data error correction processing by parallel processing using the correction blocks 301 and 302. As described above, when the load of the correction process for the correction block being operated increases, the control unit 104 ensures the necessary error correction capability by resuming the operation of the stopped correction block. Note that the number of correction blocks whose operations are started simultaneously may not be one.

  In a state where a plurality of correction blocks are stopped, in any of the correction blocks in operation, if the number of error corrections in the last-stage arithmetic unit exceeds the second threshold, the control unit 104 defines in advance A correction block for starting the operation may be selected based on the determined priority. The control unit 104 starts the operation of, for example, the correction block that has been stopped in the past among the correction blocks that have been stopped.

  FIG. 6 is a diagram illustrating an example of an operation state of the correction blocks 301 to 30N when the load of error correction processing is large. The load of the operation unit at the last stage of each of the correction blocks 301 to 30N illustrated in FIG. 6 is greater than or equal to the first threshold value. In this case, the control unit 104 operates all of the correction blocks 301 to 30N. In this way, the error correction processing capability of the error correction unit 102 is ensured.

  FIG. 7 is a diagram illustrating another example of the operation state of the correction blocks 301 to 30N. In the example of FIG. 7, the correction blocks 304 to 30N are stopped because the number of error corrections of the last-stage arithmetic unit has become less than the first threshold in the past. On the other hand, the number of error corrections in the last calculation unit of the correction blocks 301 to 303 is not less than the first threshold and not more than the second threshold. As a result, the correction blocks 301 to 303 operate and the correction blocks 304 to 30N are stopped. Since the number of error corrections in the last calculation unit of the correction blocks 301 to 303 is less than or equal to the second threshold, the control unit 104 does not instruct the correction blocks 304 to 30N to start the operation.

  The number of error corrections used for determining the load of error correction processing is not limited to the number of error corrections of the last-stage arithmetic unit 40M. For example, the control unit 104 corrects the correction based on the comparison result between the first and second threshold values and the total, average value, or maximum value of the number of error corrections of the plurality of arithmetic units located in the last stage and the preceding stage. An increase or decrease in the error correction load of the block may be determined. Further, the control unit 104 calculates the total, average value, or maximum value of the number of error corrections of all the calculation units 401 to 40M for each correction block, and based on the comparison result between these values and the first and second threshold values. Thus, an increase or decrease in error correction load of the correction block may be determined.

  As described above, the control unit 104 controls the operation state of each correction block based on the number of error corrections in any of the arithmetic units. Specifically, the control unit 104 dynamically changes the number of correction blocks to be operated from 1 to N based on the comparison result between the number of error corrections of the arithmetic unit and a predetermined threshold value.

  FIG. 8 is a flowchart illustrating an example of control of the error correction unit 102 by the control unit 104. The procedure of steps S11 to S15 is started at the start of the operation of the correction blocks 301 to 30N, and is performed in parallel with the correction blocks 301 to 30N being operated. The control unit 104 collects the number of error corrections P output from the calculation units 401 to 40M included in the correction blocks 301 to 30N, respectively (Step S11 in FIG. 8).

  The control unit 104 determines whether or not the error correction number P is less than the first threshold (S12). The first threshold is a threshold for determining whether or not to stop the operation of the correction block because the error correction processing load is low. As described above, as the error correction number P, the error correction number of the arithmetic unit 40M at the last stage (M stage) of each correction block may be used. When the error correction number P is less than the first threshold, it is determined that the load of error correction processing in the correction block in which the error correction number P is output is small. In this case, the control unit 104 stops the correction block including the arithmetic unit that has output the error correction number P (S13). The power consumption of the error correction unit 102 is suppressed by stopping the correction block. The correction block stopped in step S13 is stopped until an operation start instruction is received from the control unit 104 in step S15 described below. For this reason, the flow of FIG. 8 with respect to the said correction block is once complete | finished after step S13. The control unit 104 instructs the correction block whose operation is to be restarted to start the procedure from step S15. When the correction block stopped in step S13 receives an operation start instruction from the control unit 104, the correction block resumes operation (S15 to S11).

  In step S13, there is a possibility that all the correction blocks of the error correction unit 102 are stopped due to the stop of the correction block. In such a case, the control unit 104 does not have to stop the correction block regardless of the determination result of step S12.

  If the error correction number P is greater than or equal to the first threshold value in step S12, the control unit 104 determines whether or not the error correction number P exceeds the second threshold value (S14). The second threshold value is a threshold value for determining whether to start the operation of another correction block that is stopped because the load of error correction processing is high, and is larger than the first threshold value. As in step S12, as the error correction number P, the error correction number of the operation unit 40M at the last stage of each correction block may be used. When the error correction number P exceeds the second threshold, it is determined that the error correction processing load of the correction block in which the error correction number P is output is high. In this case, the control unit 104 selects one or more stopped correction blocks and starts the operation of the selected correction block (S15). As described above, the control unit 104 selects a correction block whose operation is to be restarted based on, for example, a predetermined priority order. When the error correction number P is equal to or smaller than the second threshold value in step S14, the control unit 104 does not instruct the stopped correction block to start the operation.

  When the error correction number P is equal to or greater than the first threshold value, the operation of the correction block in which the error correction number P is output and the control unit 104 regardless of the comparison result with the second threshold value in step S14. The collection of the number of error corrections P of the correction block according to is continued. That is, after steps S14 and S15, the flow returns to step S11. The procedure shown in FIG. 8 is also executed in the correction block that receives the operation start instruction from the control unit 104 in step S15. Thus, the error correction processing capability of the error correction unit 102 is ensured by resuming the operation of the stopped correction block when the error correction processing load increases.

  In step S15, when all of the correction blocks 301 to 30N included in the error correction unit 102 have already been operated, the correction block cannot be operated any more. In such a case, the control unit 104 does not have to control other correction blocks regardless of the determination result of step S14.

  As described above, the signal processing apparatus 100 according to the first embodiment dynamically changes the number of correction blocks to be operated based on the number of error corrections in the arithmetic unit. As a result, the signal processing apparatus 100 has an effect that it is possible to achieve both reduction of power consumption of the signal processing apparatus and ensuring of error correction capability.

(Minimum configuration of the first embodiment)
The effects of the signal processing apparatus 100 of the first embodiment can also be obtained by a signal processing apparatus that includes only the error correction unit 102 and the control unit 104. That is, referring to FIG. 1 and FIG. 2, the signal processing apparatus with the minimum configuration includes an error correction unit 102 and a control unit 104. The error correction unit 102 includes correction blocks 301 to 30N connected in parallel. The correction blocks 301 to 30N are configured by connecting a plurality of arithmetic units 401 to 40M that perform error correction of an input signal in series. The control unit 104 controls the operation state of the correction blocks 301 to 30N based on the number of error corrections in the arithmetic units 401 to 40M for the signals input to the correction blocks 301 to 30N.

  The signal processing apparatus having such a configuration can also dynamically change the number of correction blocks to be operated based on the number of error corrections of the arithmetic unit. Therefore, the signal processing device with the minimum configuration also has an effect that both the error correction capability of the signal processing device can be ensured and the power consumption can be reduced.

(Second Embodiment)
FIG. 9 is a block diagram illustrating a configuration of an optical receiver 200 according to the second embodiment of this invention. The optical receiver 200 includes a front end 201, an analog-digital converter (ADC) 202, a local oscillation light source 203, and a signal processing device 204. The local oscillation light source 203 is a light source such as a semiconductor laser. The front end 201 outputs a beat signal of local light and signal light output from the local oscillation light source 203 as an analog reception signal. The front end 201 is configured using, for example, a known 90-degree hybrid. The analog reception signal is converted into a digital reception signal by the ADC 202. The digital received signal is input to the signal processing device 204. The signal processing device 204 has the same configuration and function as the signal processing device 100 described in the first embodiment. The signal processing device 204 outputs data obtained by performing arithmetic processing on the digital reception signal output from the ADC 202 as reception data.

The optical receiver 200 of the second embodiment includes the signal processing device 100 described in the first embodiment as the signal processing device 204. That is, the optical receiver 200 dynamically changes the number of correction blocks to be operated based on the number of error corrections of the arithmetic unit of the signal processing device 204. As a result, the optical receiver 200 has an effect that it is possible to achieve both reduction in power consumption of the signal processing device and securing of error correction capability.

  In the above embodiments, the embodiments in which the present invention is applied to a coherent optical receiver have been described. However, the present invention can be applied to apparatuses other than the coherent optical receiver. That is, the signal processing apparatus 100 described in the first embodiment can reduce the power consumption of an apparatus that requires error correction processing. In each embodiment, a low density parity check (LDPC) code is used as an error correction code, and the error correction unit performs error correction of digital data using soft decision forward error correction (SD-FEC). did. However, the error correction code and the error correction determination procedure are not limited to these.

  In addition, although embodiment of this invention can be described also as the following additional remarks, it is not limited to these.

[Appendix 1]
An error correction means in which a correction block in which a plurality of arithmetic means for performing error correction of an input signal are connected in series is connected; and
Control means for controlling the operating state of each of the correction blocks based on the number of error corrections in any of the arithmetic means for the signal;
A signal processing apparatus comprising:

[Appendix 2]
The arithmetic means outputs the error correction number to the control means,
The control means includes
Calculate the correction processing load of the correction block based on the number of error correction obtained from each of the arithmetic means,
Stopping a correction block whose load is less than a first threshold;
The signal processing apparatus described in the supplementary note 1 characterized by the above.

[Appendix 3]
If the load exceeds a second threshold greater than the first threshold, any one of the stopped correction blocks is activated;
The signal processing apparatus described in Appendix 2 characterized by the above.

[Appendix 4]
The load is the number of error corrections of one arithmetic means selected from the arithmetic means included in the one correction block in operation. The load is described in any one of appendices 1 to 3 Signal processing device.

[Appendix 5]
The signal processing apparatus according to appendix 4, wherein the selected one arithmetic means is an arithmetic means arranged at the last stage of the arithmetic means connected in series in the correction block. .

[Appendix 6]
The load is an average value of the number of error corrections of a plurality of arithmetic means selected from the arithmetic means included in one of the correction blocks in operation. Signal processing apparatus.

[Appendix 7]
The load is a maximum value of the number of error corrections of a plurality of the calculation means selected from the calculation means included in one correction block in operation. The described signal processing device.

[Appendix 8]
Demodulating means for performing symbol determination of the input digital received signal, converting the digital received signal into digital data and inputting the digital data to the error correcting means;
A framer that converts the signal output from the error correction means into a frame of a predetermined format and outputs it as received data;
The signal processing device according to any one of appendices 1 to 7, further comprising:

[Appendix 9]
A front end that converts the signal light into an analog received signal and outputs it;
Analog-to-digital conversion means for converting the analog reception signal into a digital reception signal;
The signal processing device according to appendix 7, which receives the digital reception signal and outputs the reception data;
With optical receiver.

[Appendix 10]
An error correction means in which a correction block in which a plurality of arithmetic means are connected in series is connected in parallel performs error correction of the input signal,
Controlling the operation state of each of the correction blocks based on the number of error corrections for the signal in any of the computing means;
Signal processing method.

[Appendix 11]
In the computer of the signal processing device,
A procedure for correcting an error of an input signal by an error correction means in which a correction block having a plurality of arithmetic means connected in series is connected in parallel;
A procedure for controlling the operating state of each of the correction blocks based on the number of error corrections for the signal in any of the computing means;
A program for running

[Appendix 12]
further,
Outputting the number of error corrections to the control means;
Calculate the correction processing load of the correction block based on the number of error correction obtained from each of the arithmetic means,
Stopping a correction block whose load is less than a first threshold;
The signal processing method according to attachment 10.

[Appendix 13]
further,
If the load exceeds a second threshold greater than the first threshold, any one of the stopped correction blocks is activated;
The signal processing method described in appendix 12.

[Appendix 14]
further,
A procedure for outputting the error correction number to the control means;
A procedure for calculating a correction processing load of the correction block based on the number of error corrections acquired from each of the arithmetic means;
Stopping a correction block whose load is less than a first threshold;
The program described in appendix 11 to be executed.

[Appendix 15]
further,
A procedure for operating any of the stopped correction blocks when the load exceeds a second threshold greater than the first threshold;
The program described in appendix 14, wherein

  As mentioned above, although this invention was demonstrated with reference to embodiment, this invention is not limited to said embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2015-018978 for which it applied on February 3, 2015, and takes in those the indications of all here.

DESCRIPTION OF SYMBOLS 100,204 Signal processing apparatus 101 Demodulation part 102 Error correction part 103 Framer 104 Control part 200 Optical receiver 201,801 Front end 202,802 Analog-digital converter (ADC)
203 Local Oscillation Light Source 301-30N Correction Block 401-40M Arithmetic Unit 800 Coherent Optical Receiver 900 Signal Processor (DSP)

Claims (9)

An error correction means in which a correction block in which a plurality of arithmetic means for performing error correction of an input signal are connected in series is connected; and
Control means for controlling the operating state of each of the correction blocks based on the number of error corrections in any of the arithmetic means for the signal;
With
The arithmetic means outputs the error correction number to the control means,
The control means includes
Calculate the correction processing load of the correction block based on the number of error correction obtained from each of the arithmetic means,
Stopping a correction block whose load is less than a first threshold;
The load is the number of error corrections of one arithmetic means selected from the arithmetic means included in one correction block in operation,
The selected one computing means is a computing means arranged at the last stage of the computing means connected in series in the correction block,
Signal processing device. An error correction means in which a correction block in which a plurality of arithmetic means for performing error correction of an input signal are connected in series is connected; and
Control means for controlling the operating state of each of the correction blocks based on the number of error corrections in any of the arithmetic means for the signal;
With
The arithmetic means outputs the error correction number to the control means,
The control means includes
Calculate the correction processing load of the correction block based on the number of error correction obtained from each of the arithmetic means,
Stopping a correction block whose load is less than a first threshold;
The load is an average value of the number of error corrections of a plurality of calculation means selected from the calculation means included in one correction block in operation.
Signal processing device. An error correction means in which a correction block in which a plurality of arithmetic means for performing error correction of an input signal are connected in series is connected; and
Control means for controlling the operating state of each of the correction blocks based on the number of error corrections in any of the arithmetic means for the signal;
With
The arithmetic means outputs the error correction number to the control means,
The control means includes
Calculate the correction processing load of the correction block based on the number of error correction obtained from each of the arithmetic means,
Stopping a correction block whose load is less than a first threshold;
The load is a maximum value of the number of error corrections of the plurality of arithmetic means selected from the arithmetic means included in one correction block in operation.
Signal processing device. If the load exceeds a second threshold greater than the first threshold, any one of the stopped correction blocks is activated;
The signal processing device according to claim 1, wherein the signal processing device is a signal processing device . Demodulating means for performing symbol determination of the input digital received signal, converting the digital received signal into digital data and inputting the digital data to the error correcting means;
A framer that converts the signal output from the error correction means into a frame of a predetermined format and outputs it as received data;
The signal processing apparatus according to claim 1, further comprising: A front end that converts the signal light into an analog received signal and outputs it;
Analog-to-digital conversion means for converting the analog reception signal into a digital reception signal;
The signal processing apparatus according to claim 5, wherein the digital reception signal is input and the reception data is output.
With optical receiver . An error correction means in which a correction block in which a plurality of arithmetic means are connected in series is connected in parallel performs error correction of the input signal,
Based on the number of error corrections for the signal in any of the computing means, control the operating state of each of the correction blocks,
Outputting the number of error corrections by the computing means;
Calculating a correction processing load of the correction block based on the number of error corrections output from each of the arithmetic means;
Stopping a correction block whose load is less than a first threshold;
A signal processing method comprising:
The load is the number of error corrections of one arithmetic means selected from the arithmetic means included in one correction block in operation,
The selected one arithmetic means is an arithmetic means arranged at the last stage of the arithmetic means connected in series in the correction block.
Signal processing method . An error correction means in which a correction block in which a plurality of arithmetic means are connected in series is connected in parallel performs error correction of the input signal,
Based on the number of error corrections for the signal in any of the computing means, control the operating state of each of the correction blocks,
Outputting the number of error corrections by the computing means;
Calculating a correction processing load of the correction block based on the number of error corrections output from each of the arithmetic means;
Stopping a correction block whose load is less than a first threshold;
A signal processing method comprising:
The load is an average value of the number of error corrections of a plurality of calculation means selected from the calculation means included in one correction block in operation.
Signal processing method . An error correction means in which a correction block in which a plurality of arithmetic means are connected in series is connected in parallel performs error correction of the input signal,
Based on the number of error corrections for the signal in any of the computing means, control the operating state of each of the correction blocks,
Outputting the number of error corrections by the computing means;
Calculating a correction processing load of the correction block based on the number of error corrections output from each of the arithmetic means;
Stopping a correction block whose load is less than a first threshold;
A signal processing method comprising:
The load is a maximum value of the number of error corrections of the plurality of arithmetic means selected from the arithmetic means included in one correction block in operation.
Signal processing method .

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