JP6363686B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  Conventionally, a "pachislot" comprising a plurality of reels each having a plurality of symbols arranged on each surface, a start switch, a stop switch, a stepping motor provided for each reel, and a controller. A game machine called is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as “start operation”) after a game medium such as a medal or coin has been inserted into the gaming machine, and the rotation of all reels is detected. Outputs a signal requesting start. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the stop control of the reel rotation based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and the symbol combination related to the winning is displayed, a privilege corresponding to the symbol combination is given to the player. Examples of privileges granted to a player include payout of game media (medals, etc.), re-game (replay) operation in which internal lottery processing is performed again without consuming game media, and game media payout opportunities. The operation of a bonus game that increases can be mentioned.

  The above-mentioned gaming machine is usually equipped with a main control circuit in which a circuit (main control circuit) for controlling the main gaming operation of the gaming machine such as determination of an internal winning combination, rotation and stop of each reel, determination of presence / absence of winning is implemented. A board and a sub-control board on which a circuit (sub-control circuit) for controlling a rendering operation mainly by displaying an image is mounted. Then, a command is transmitted from the main control board to the sub control board, and the operation of the sub control board is controlled.

  By the way, in the gaming machine having such a configuration, an advantageous gaming state can be obtained by erasing a command transmitted from the main control circuit to the sub-control circuit by short-circuiting the power supply wiring in the gaming machine by, for example, a metal member during the game. The fraudulent act of generating (an act called “got”) has become a big problem. For example, when a replay is continuously won a predetermined number of times (when a command including replay winning information is continuously sent a predetermined number of times from the main control circuit to the sub-control circuit), a predetermined privilege is given to the player. In a gaming machine having a function, when a role other than replay wins in a situation where replays are continuously won, if the power supply wiring is short-circuited by the goto action at that timing, the command including the winning information is deleted. In this case, the replay continuous winning state is maintained, and a predetermined privilege can be obtained illegally.

  Therefore, conventionally, various techniques for detecting and preventing the above-described goto action have been proposed (see, for example, Patent Document 1). Japanese Patent Application Laid-Open No. H10-228561 proposes a technique for holding the history within a standby time from the detection of a power-off operation (power-off operation) to the power-off processing. In this technology, after the power is restored, the administrator checks the history and manually changes the settings of the gaming machine by operating the power supply manually. It is possible to easily determine whether the setting has been changed.

JP 2006-068241 A

  As described above, conventionally, there has been proposed a technique for detecting a goto action of erasing a command transmitted from a main control circuit to a sub control circuit by short-circuiting (instantaneously interrupting) a power supply wiring in the gaming machine. However, in this technical field, it is desired to develop a goto detection technique that can more easily detect the presence or absence of such a got action and that can detect a goto action of various patterns.

  The present invention has been made in order to meet this demand, and an object of the present invention is to provide a goto detection function capable of more easily detecting the presence or absence of a goto action and detecting a goto action of various patterns. It is providing the game machine provided with.

  In order to solve the above problems, the present invention provides a gaming machine having the following first configuration.

Control means (for example, a sub-control circuit 70 described later) for executing control relating to the game;
Power supply monitoring means for monitoring the power supply voltage supplied to the control means (for example, a power interruption detection circuit 90 described later);
Storage means (for example, SRAM 74 described later) capable of maintaining and storing the stored information;
Display means for displaying predetermined information (for example, a liquid crystal display device 10 described later),
The power supply monitoring means monitors the lowering of the power supply voltage supplied to the control means and outputs an interrupt signal to the control means when the power supply voltage falls below a predetermined power supply voltage. Have
The control means is processed by the interrupt processing means for performing predetermined processing based on the interrupt signal from the interrupt signal generating means, and by the interrupt processing means at a predetermined cycle (for example, 100 msec described later). Monitoring means for monitoring
First generation information (for example, “POWER DOWN” and “POWER UP” to be described later) indicating that the interrupt signal has occurred is different from the first generation information, and a plurality of the first generation information A plurality of types of second generation information (for example, “POWER ERR1” to “POWER ERR3” described below), which are information respectively associated with a plurality of types of generation modes of the generation information,
It said interrupt processing means stores the previous SL first generation information Ho及 beauty date information in the storage means,
It said monitoring means, on the basis of the above stored in the storage means the first occurrence information and the date and time information, a plurality of the first second occurrence information one predetermined corresponding to the occurrence mode of occurrence information A gaming machine characterized in that it can be displayed on the display means instead of a plurality of the first occurrence information .

In the gaming machine of the present invention, the generation mode of the plurality of first generation information includes the number of generations of the first generation information and the generation period of the plurality of first generation information. Also good.

  According to the gaming machine of the present invention, it is possible to more easily detect the presence or absence of an error event that occurs when a goto action is performed, and it is also possible to detect goto actions of various patterns.

It is a figure for demonstrating the functional flow of the game machine (pachislot) in one Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the symbol display area and effective line of the game machine in one Embodiment of this invention. It is a front view which shows the external appearance structure of the liquid crystal display device vicinity of the game machine in one Embodiment of this invention. It is a schematic sectional drawing of the display panel unit vicinity of the game machine in one Embodiment of this invention. It is a figure which shows the structure of the display panel of the game machine in one Embodiment of this invention. It is a figure for demonstrating the structure of the left infrared sensor provided in the left decoration panel and its back surface side of the gaming machine in one Embodiment of this invention. It is a block diagram which shows the whole structure of the circuit with which the game machine in one Embodiment of this invention is provided. It is a block diagram which shows the internal structure of the sub control circuit in one Embodiment of this invention. It is a figure which shows the area | region image of the sub ROM of the sub control circuit in one Embodiment of this invention. It is a figure which shows the area | region image of the sub RAM of the sub control circuit in one Embodiment of this invention. It is a figure which shows an example of the structure of the error information log | history storage area in the sub-RAM of one Embodiment of this invention. It is a figure which shows an example of the content of the data stored in the error information log | history storage area in one Embodiment of this invention. It is a figure which shows an example of the content of the data stored in the error information log | history storage area in one Embodiment of this invention. It is a figure which shows an example of the structure of the ring buffer area | region for communication log collection in sub-RAM of one Embodiment of this invention. It is a figure which shows an example of the structure of the communication error preservation | save buffer area | region in the sub-RAM of one Embodiment of this invention. It is a figure which shows the area | region image of the backup RAM (SRAM) of the sub control circuit in one Embodiment of this invention. It is a figure which shows the data format of the transmission / reception command between the sub control circuit and subdevice in one Embodiment of this invention. It is a figure which shows the content of the transmission / reception data between the sub control circuit and subdevice in one Embodiment of this invention. It is a figure which shows an example of the subdevice communication check table (subdevice communication data consistency check table) in one Embodiment of this invention. It is a figure which shows the example of an error alert | report at the time of RAM destruction in the gaming machine of one Embodiment of this invention. It is a figure which shows the example of a display of the menu screen of the liquid crystal display device in the game machine of one Embodiment of this invention. It is a figure which shows an example of the confirmation screen of an error information log | history in the gaming machine of one Embodiment of this invention. It is a figure which shows an example of the confirmation screen of an error information history when not using the registration edit process of the error information history of this invention. It is a figure which shows an example of the confirmation screen of an error information log | history in the gaming machine of one Embodiment of this invention. It is a figure which shows the format of the transmission information contained in the two-dimensional code used in order to manage error information in the game machine of one Embodiment of this invention. It is a figure which shows the relationship between the code number of the received command used in the gaming machine of one embodiment of the present invention, the type, and the parameter. It is a figure for demonstrating the recording image of the information of the two-dimensional code when the COM error generate | occur | produces in the gaming machine of one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the table at the time of the bonus action | operation in one Embodiment of this invention. It is a figure which shows the transition flow of RT game state controlled by the main control circuit of the game machine in one Embodiment of this invention. It is a figure which shows an example of RT transition table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table determination table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table (for non-bonus operation | movement) in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table for RB (regular bonus) 1 game state in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table for RB2 game states in one Embodiment of this invention. It is a figure which shows an example of the internal winning combination determination table for bonuses in one Embodiment of this invention. It is a figure which shows an example of the internal winning combination determination table for a small combination and replay in one Embodiment of this invention. It is a figure which shows an example of the stop table in one Embodiment of this invention. It is a figure which shows an example of the drawing priority order table A in one Embodiment of this invention. It is a figure which shows an example of the drawing priority order table B in one Embodiment of this invention. It is a figure which shows an example of the internal winning combination storing area in one Embodiment of this invention. It is a figure which shows an example of the display combination storage area in one Embodiment of this invention. It is a figure which shows an example of the carryover combination storage area in one Embodiment of this invention. It is a figure which shows an example of the game state flag storage area in one Embodiment of this invention. It is a figure which shows one storage example of the symbol storage area A (in non-RB) of the gaming machine in one embodiment of the present invention. It is a figure which shows one storage example of the symbol storage area B (in RB) of the game machine in one Embodiment of this invention. It is a figure which shows an example of the navigation mode transfer lottery table A in one Embodiment of this invention. It is a figure which shows an example of the navigation mode transfer lottery table B in one Embodiment of this invention. It is a figure which shows an example of the navigation mode transfer lottery table C in one Embodiment of this invention. It is a figure which shows an example of the navigation game state transfer waiting | standby number lottery table in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 transfer waiting | standby number lottery table in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition game number lottery table A in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition game number lottery table B in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition game number lottery table C in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition game number lottery table D in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition lottery mode lottery table A in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition lottery mode lottery table B in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition lottery mode lottery table C in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 addition lottery mode lottery table D in one Embodiment of this invention. It is a figure which shows an example of the navigation set number lottery table in one Embodiment of this invention. It is a figure which shows an example of the navigation game state 3 navigation game number addition lottery table in one Embodiment of this invention. It is a figure which shows an example of the navigation game number special addition lottery table in one Embodiment of this invention. It is a figure which shows an example of the billy get challenge generation lottery table in one Embodiment of this invention. It is a figure which shows an example of the billy get challenge control counter lottery table in one Embodiment of this invention. It is a figure which shows an example of the billy get challenge correct answer lottery table in one Embodiment of this invention. It is a figure which shows an example of the lottery table at the time of no billy get challenge selection in one Embodiment of this invention. It is a flowchart which shows an example of the reset interruption process in one Embodiment of this invention. It is a flowchart which shows an example of the bonus action | operation monitoring process in one Embodiment of this invention. It is a flowchart which shows an example of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows an example of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows an example of the reel stop control process in one Embodiment of this invention. It is a flowchart which shows an example of the display combination search process in one Embodiment of this invention. It is a flowchart which shows an example of RT control processing in one Embodiment of this invention. It is a flowchart which shows an example of the bonus end check process in one Embodiment of this invention. It is a flowchart which shows an example of the bonus operation | movement check process in one Embodiment of this invention. It is a flowchart which shows an example of the interruption process by control of main CPU in one Embodiment of this invention. It is a flowchart which shows an example of the effect registration process by control of the sub CPU in one Embodiment of this invention. It is a flowchart which shows an example of the production content determination process in one Embodiment of this invention. It is a flowchart which shows an example of the process at the time of start command reception in one Embodiment of this invention. It is a flowchart which shows an example of the process at the time of start command reception in one Embodiment of this invention. It is a flowchart which shows an example of the process in BB in one Embodiment of this invention. It is a flowchart which shows an example of lottery processing in BB4 in one Embodiment of this invention. It is a figure which shows the example of a change of LED brightness at the time of the display panel unit presentation in one Embodiment of this invention. It is a flowchart which shows an example of the billy get challenge process in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state 3 addition game number and lottery mode lottery process in one Embodiment of this invention. It is a flowchart which shows an example of the ART at the time of the ART first hit in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state transfer process in waiting state in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state transition process in the navigation game state 1 in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state transition process in the navigation game state 2 in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state transition process in the navigation game state 2 in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state 3 transition process in the navigation game state 2 in one Embodiment of this invention. It is a flowchart which shows an example of a navigation game state transition process in the navigation game state 3 in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game number addition process in one Embodiment of this invention. It is a flowchart which shows an example of the billy get challenge lottery process in one Embodiment of this invention. It is a flowchart which shows an example of the billy get challenge determination process in one Embodiment of this invention. It is a flowchart which shows an example of the navigation game state transfer process in one Embodiment of this invention. It is a flowchart which shows an example of the process at the time of the display command reception in one Embodiment of this invention. It is a flowchart which shows an example of the process at the time of the bonus end command reception in one Embodiment of this invention. It is a flowchart which shows an example of the main board | substrate communication reception interruption process in one Embodiment of this invention. It is a flowchart which shows an example of the main board | substrate communication task in one Embodiment of this invention. It is a flowchart which shows an example of the main board | substrate communication reception data log preservation | save process in one Embodiment of this invention. It is a flowchart which shows an example of the main board | substrate communication reception data log temporary area | region storage process in one Embodiment of this invention. It is a flowchart which shows an example of the main board | substrate communication error log | history data storage process in one Embodiment of this invention. It is a flowchart which shows an example of the main board | substrate communication reception command check process in one Embodiment of this invention. It is a flowchart which shows an example of the COM error check process in one Embodiment of this invention. It is a flowchart which shows an example of the power activation process of the sub CPU in one Embodiment of this invention. It is a flowchart which shows an example of the power interruption interruption process of the sub CPU in one Embodiment of this invention. It is a flowchart which shows an example of the mother task in one Embodiment of this invention. It is a flowchart which shows an example of the RTC control task in one Embodiment of this invention. It is a flowchart which shows an example of the sub RAM management process in one Embodiment of this invention. It is a flowchart which shows an example of the backup creation process in one Embodiment of this invention. It is a flowchart which shows an example of the communication control task between subdevices in one Embodiment of this invention. It is a flowchart which shows an example of the subdevice command reception process in one Embodiment of this invention. It is a flowchart which shows an example of the subdevice communication return process in one Embodiment of this invention. It is a flowchart which shows an example of the reception time process of the subdevice communication in one Embodiment of this invention. It is a flowchart which shows an example of the process at the time of the scaler control command reception in one Embodiment of this invention. It is a flowchart which shows an example of the subdevice reception data determination process in one Embodiment of this invention. It is a flowchart which shows an example of the scaler control setting process in one Embodiment of this invention. It is a flowchart which shows an example of the sub device communication disconnection process in one Embodiment of this invention. It is a flowchart which shows an example of the subdevice serial reception interruption process in one Embodiment of this invention. It is a flowchart which shows an example of the fraud monitoring process task in one Embodiment of this invention. It is a flowchart which shows an example of the electric power failure abnormality fraud determination process in one Embodiment of this invention. It is a flowchart which shows an example of the scaler control main task in one Embodiment of this invention. It is a flowchart which shows an example of the sub control reception process in one Embodiment of this invention. It is a flowchart which shows an example of the resolution conversion LSI setting process in one Embodiment of this invention. It is a flowchart which shows an example of the sub control transmission process in one Embodiment of this invention. It is a flowchart which shows an example of the operation state determination process in one Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine (pachinko) in a modification. It is an external appearance front view of the game machine in a modification. It is a disassembled perspective view of the game machine in a modification. It is a front view which shows the structure of the game board of the game machine in a modification. It is a block diagram which shows the whole structure of the circuit with which the game machine in a modification is provided.

  Hereinafter, a pachi-slot showing an embodiment of a gaming machine according to the present invention will be described with reference to the drawings.

<Function flow>
First, a functional flow of a pachislot according to an embodiment of the present invention will be described with reference to FIG. In the pachislot machine of this embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as game media.

  When a player inserts a medal into the pachislot and operates the start lever, one value (hereinafter, random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. By determining the internal winning combination, a combination of symbols that permits display along an after-mentioned effective line (winning determination line) is determined. The types of symbol combinations are those related to “winning” that gives the player benefits such as medal payout, re-game operation, bonus game operation, etc., and other so-called “losing” And are provided.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do.

  The pachislot is basically controlled to stop the rotation of the corresponding reel within a specified time (190 msec) from when the stop button is pressed. In this specification, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”, and when the specified period is 190 msec (maximum delay time), the maximum number (maximum) Set the number of sliding pieces to 4 symbols.

  The reel stop control means, when the internal winning combination permitting display of the symbol combination related to the winning is determined, the symbol combination normally follows the effective line within a specified time of 190 msec (four symbols). Stop the reel rotation so that it is displayed as much as possible. In addition, the reel stop control means stops the rotation of the reel using a specified time so that the combination of symbols that are not permitted to be displayed by the internal winning combination is not displayed along the active line.

  As described above, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the active line is related to winning. Then, when the winning determination means determines that the combination of symbols related to winning is made, a privilege such as a medal payout is given to the player. In the pachislot, the above-described series of operations are performed as a single game (unit game).

  In the pachislot, among the above-described series of operations, for example, an image display operation by a liquid crystal display device, a light output operation by various lamps, an audio output operation by a speaker, or a combination of these operations is used. Various productions are performed. Such a production operation is performed as follows.

  First, when the start lever is operated, a random number value for performance (hereinafter referred to as a random number value for performance) is extracted separately from the random number value used for determining the internal winning combination. When the effect random number value is extracted, the effect content determination means determines the effect content to be executed this time from lots of effect contents associated with the internal winning combination by lottery.

  When the content of the effect is determined, the effect executing means executes the corresponding effect in conjunction with each opportunity such as the start of reel rotation, the stop of rotation of each reel, or the determination of the presence or absence of a prize. In this way, in the pachislot machine, the player has the opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) by executing the production contents associated with the internal winning combination. It is possible to improve the player's interest.

  Although the pachislot of this embodiment is not shown in FIG. 1, during the above game flow, the power supply wiring in the pachislot is short-circuited (instantaneous interruption) to erase the command transmitted from the main control circuit to the sub-control circuit. A means (function) for detecting an action is also provided. Note that this embodiment proposes a goto detection technique that can determine not only whether or not a goth act has been performed, but also the types of goth acts with different patterns.

<Pachislot structure>
[Overall structure]
Next, with reference to FIG. 2, the structure of the pachislot in this embodiment will be described. FIG. 2 is a perspective view showing an external structure of the pachislot machine 1 of the present embodiment.

  As shown in FIG. 2, the pachi-slot 1 includes a cabinet 1a that houses reels, circuit boards, and the like, and a front door 1b that is attached to the cabinet 1a so as to be openable and closable. Note that the pachi-slot 1 includes a lock mechanism that locks or unlocks the front door 1b with respect to the cabinet 1a with the front door 1b closed.

  The locking / unlocking of the locking mechanism is performed by inserting the door key 2 into the door key hole 1c provided in the front door 1b and rotating the door key 2. The door key 2 also has a reset function for electrically resetting the pachi-slot 1 in addition to the operation of the lock mechanism. For example, when the door key 2 is inserted into the door key hole 1c, the door key 2 can be rotated to the right to open and close the front door 1b. By rotating the door key 2 to the left, a main control circuit 60 (described later) can be opened. And the like are electrically reset.

  Inside the cabinet 1a, three reels 3L, 3C, 3R (variable display means) are provided, and the three reels 3L, 3C, 3R are arranged in a row in a horizontal direction (a direction perpendicular to the rotation direction of the reels). Is done. Hereinafter, the reels 3L, 3C, and 3R are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel (display row) includes a cylindrical reel body and a translucent sheet material attached to the peripheral surface (circumferential surface) of the reel body. A plurality of (for example, 21) symbols are continuously drawn on the surface of the sheet material along the circumferential direction of the reel body. The configuration of symbols drawn on each reel will be described later with reference to a symbol arrangement table (see FIG. 29 described later).

  A liquid crystal display device 10 (display means) is provided at the front center of the front door 1b. The liquid crystal display device 10 displays the number of medals stored (credited), or displays the number of medals paid out when winning is established.

  Further, on the display screen of the liquid crystal display device 10, three symbol display areas 4L, 4C, and 4R (hereinafter referred to as the left symbol display respectively) for transparently displaying the symbols drawn on the left reel 3L, the middle reel 3C, and the right reel 3R. Area 4L, middle symbol display area 4C, and right symbol display area 4R). That is, each symbol display area provided on the display screen serves as a symbol display window drawn on the reel. The transmittance in each symbol display area can be changed.

  Then, the liquid crystal display device 10 displays a frame image having a predetermined shape surrounding the three symbol display areas 4L, 4C, and 4R, and a predetermined image corresponding to the contents of effects described later. In other words, in the present embodiment, an image is displayed using the entire display screen of the liquid crystal display device 10 and an effect is executed.

  Each symbol display area is provided at a position overlapping the corresponding reel arrangement area when viewed from the front side (player side) of the pachi-slot 1 and is positioned in front of the corresponding reel (player side). To be provided. Therefore, the symbol drawn on the corresponding reel provided behind the symbol display area can be viewed through the symbol display area.

  Further, in this embodiment, each reel is controlled by a main control circuit 60 (see FIG. 8 described later) so as to rotate at a constant speed (for example, 80 revolutions / minute), and the symbols drawn on each reel are controlled. Fluctuates with the rotation of the reel within the corresponding symbol display area. Each reel is connected to a corresponding stepping motor described later (any of stepping motors 49L, 49C, 49R in FIG. 8 described later) via a gear having a predetermined reduction ratio. And in this embodiment, when the rotation of the corresponding reel provided behind each symbol display area stops, three symbols arranged in succession among a plurality of symbols drawn on each reel. Is configured to display. That is, in the frame of each symbol display area, the upper, middle and lower areas are provided for each reel, and one symbol can be displayed in each area.

  Here, FIG. 3 shows a schematic configuration of each symbol display area on the display screen of the liquid crystal display device 10. As shown in FIG. 3, symbols are displayed in a 3 × 3 arrangement form in the left symbol display area 4L, the middle symbol display area 4C, and the right symbol display area 4R of the display screen of the liquid crystal display device 10. . In this embodiment, in the symbols displayed in the 3 × 3 arrangement, a pseudo line set from the left symbol display area 4L of the left reel 3L to the right symbol display area 4R of the right reel 3R is displayed. , It is defined as a line for determining whether or not a prize is won (hereinafter referred to as an effective line).

  In this embodiment, five types of effective lines are set. Specifically, as shown in FIG. 3, a line (cross) is set across the upper area A of the left symbol display area 4L, the middle area E of the middle symbol display area 4C, and the lower area I of the right symbol display area 4R. Down line), the lower symbol area G of the left symbol display area 4L, the lower symbol area H of the middle symbol display area 4C and the lower symbol area I of the right symbol display area 4R (bottom line), the left symbol display area 4L. A line (cross-up line) set over the lower stage area G, the middle stage area E of the middle symbol display area 4C and the upper stage area C of the right symbol display area 4R, the middle stage area D of the left symbol display area 4L, and the middle symbol display A line (center line) set over the middle area E of the area 4C and the middle area F of the right symbol display area 4R, and the middle area D of the left symbol display area 4L and the lower area H of the middle symbol display area 4C. Fine right symbol display areas 4R in the upper area C in the over and set line (hereinafter, in RB special lines), and sets as the active line. Although not an effective line, a line extending over the upper area A of the left symbol display area 4L, the upper area B of the middle symbol display area 4C, and the upper area C of the right symbol display area 4R is hereinafter referred to as a top line.

  In this embodiment, when the gaming state is the big bonus state (hereinafter referred to as BB gaming state) or the regular bonus state (hereinafter referred to as RB gaming state), the number of inserted medals is two, and the special during RB Only lines are used as active lines. On the other hand, when the gaming state is a non-bonus state, four lines of a center line, a bottom line, a cross-up line, and a cross-down line are used as effective lines.

  The “regular bonus (RB)” is a so-called type 1 special bonus, and the “big bonus (BB)” is a feature continuous action device related to the first type special bonus. Yes, “RB” is activated continuously. In this embodiment, the number of medals inserted in the BB gaming state is two, and the number of medals inserted in the RB gaming state is three. Further, in the present embodiment, four types of states (BB1 gaming state to BB4 gaming state described later) are prepared as the BB gaming state, and two types of states (RB1 gaming state and RB2 gaming state described below) are prepared as the RB gaming state. ). In the present embodiment, an ordinary accessory called “single bonus (SB)” is also prepared as an accessory.

  In the present embodiment, the liquid crystal display device 10 includes a scaler function for enlarging an image to be displayed in order to enhance the effect. The details of the scaler function will be described later.

  An upper panel 11 is provided above the liquid crystal display device 10 of the front door 1b, and an upper panel LED (Light Emitting Diode) 101 (on the back side of the upper panel 11 (the side opposite to the player side) is provided. 9 described later) is provided. The upper panel LED 101 emits light according to the contents of the effect. In addition, the apparatus (lamp) which light-emits the upper panel 11 is not limited to LED, You may use another light-emitting device.

  Although not shown in FIG. 2, in this embodiment, a display panel unit 110, two decorative panels 121L and 121R, and two selection panels 151L and 151R described later are provided between the liquid crystal display device 10 and the upper panel 11. Etc. are provided (see FIG. 4 described later). The configuration of these panel members will be described in detail later.

  A lower panel 12 is provided below the liquid crystal display device 10 of the front door 1b, and a lower panel LED 102 (see FIG. 9 described later) is provided on the back side of the lower panel 12 (the side opposite to the player side). Is provided. The lower panel LED 102 emits light according to the contents of the effect. In addition, the apparatus (lamp) which makes the lower panel 12 light-emit is not limited to LED, You may use another light-emitting device.

  In addition, an operation unit portion 13 (pedestal portion) to which various operation buttons and the like operated by the player are attached is provided below the lower panel 12 of the front door 1b. In addition, the operation unit part 13 has the convex-shaped external shape which protruded on the outer side (player side), as shown in FIG. Various operation buttons, levers, and the like are arranged on the front surface and upper surface of the convex operation unit 13.

  Three stop buttons 20L, 20C, and 20R are arranged in a row in the horizontal direction substantially at the center of the front portion of the operation unit 13. Stop buttons 20L, 20C, and 20R are provided in association with the left reel 3L, middle reel 3C, and right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 20L, 20C, and 20R are referred to as a left stop button 20L, a middle stop button 20C, and a right stop button 20R, respectively.

  A start lever 21 is disposed on one side of the stop button on the front surface of the operation unit 13 (left side as viewed from the player side in FIG. 2). The start lever 21 is provided to start rotation of all reels.

  A C (Credit) / P (Pay) button 22 is provided near the side end of one of the upper surfaces of the operation unit 13 (left side as viewed from the player side in FIG. 2). The C / P button 22 is an operation button for switching the credit / payout of medals acquired by the player in the game. In the medal credit mode, when a combination related to paying out medals (hereinafter referred to as “small role”) wins (when a combination of symbols related to small roles is stopped and displayed on the active line), The corresponding medals are credited. On the other hand, in the medal payout mode, when a small combination wins, medals for the payout number corresponding to the win are paid out from a medal payout exit 15 described later.

  Further, a MAX bet button 23 is arranged on one side of the C / P button 22 (right side as viewed from the player side in FIG. 2). The MAX bet button 23 is provided to determine the number of coins to be inserted into one game from medals deposited inside the pachislot 1. When the player presses the MAX bet button 23, the maximum number of medals that can be inserted at that time is inserted among the credited medals.

  A selection button 24 is provided in the vicinity of the other side end portion of the upper surface portion of the operation unit portion 13 (right side as viewed from the player side in FIG. 2). The selection button 24 is used, for example, when a predetermined menu is selected on the menu screen displayed on the liquid crystal display device 10. Further, a determination button 25 is arranged on one side of the selection button 24 (right side as viewed from the player side in FIG. 2). The decision button 25 is used, for example, for an operation for determining a predetermined menu selected by operating the selection button 24 on the menu screen displayed on the liquid crystal display device 10.

  In the present embodiment, a medal slot 26 is provided on one side of the determination button 25 (right side as viewed from the player side in FIG. 2). The medal slot 26 is provided to accept a medal that is inserted into the pachislot 1 from the outside by the player. The medals accepted through the medal slot 26 are inserted into one game up to a predetermined number (for example, three), and the amount exceeding the predetermined number can be deposited inside the pachislot machine 1 (so-called Credit function). In the present embodiment, the door key hole 1c described above is provided on one side of the medal slot 26 (right side as viewed from the player side in FIG. 2).

  Furthermore, a light-transmitting waist panel 14 is provided below the operation unit portion 13 of the front door 1b, and a waist panel LED 103 is provided on the back side of the waist panel 14 (the side opposite to the player side). (See FIG. 9 described later). This waist panel LED 103 emits light according to the contents of the performance. In addition, the apparatus (lamp) which light-emits the waist panel 14 is not limited to LED, You may use another light-emitting device.

  Further, at the lower part of the waist panel 14 of the front door 1b, a medal payout port 15, a medal tray 16, speakers 17L and 17R (audio output unit) and the like are provided.

  The medal payout port 15 guides medals discharged by driving a medal payout device 40 (hereinafter referred to as a hopper 40; see FIG. 8 described later) to the outside. The medal tray 16 stores medals discharged from the medal payout opening 15. The two speakers 17L and 17R are arranged so that the medal payout opening 15 is sandwiched between them, and output sound such as sound effects corresponding to the contents of the effects, effects such as music, and notification sounds.

[Configuration around the LCD]
Next, a configuration around the liquid crystal display device 10 will be described with reference to FIG. FIG. 4 is a front view showing a configuration around the liquid crystal display device 10 of the front door 1b.

  In the pachi-slot 1 of the present embodiment, as shown in FIG. 4, a display panel unit 110, two decorative panels 121 </ b> L and 121 </ b> R (hereinafter, left decorative panel) are provided between the display screen of the liquid crystal display device 10 and the upper panel 11. 121L and right decorative panel 121R) and two selection panels 151L and 151R (hereinafter referred to as left selection panel 151L and right selection panel 151R).

  Specifically, a display panel unit 110, a left selection panel 151L, and a right selection panel 151R are provided on the upper part of the liquid crystal display device 10. At this time, the left selection panel 151L is arranged on one side (left side as viewed from the player side in FIG. 4) of the display panel unit 110, and on the other side (right side as viewed from the player side in FIG. 4). A right selection panel 151R is arranged.

  In addition, a left decorative panel 121L and a right decorative panel 121R are provided on the upper portion of the display panel unit 110. At this time, the left decorative panel 121L is disposed on one side (left side as viewed from the player side in FIG. 4) of the upper portion of the display panel unit 110, and the other side (right side as viewed from the player side in FIG. 4). The right decorative panel 121R is arranged in the part.

(1) Configuration of Display Panel Unit Here, the configuration of the display panel unit 110 will be described with reference to FIG. FIG. 5 is a schematic sectional view of the vicinity of the display panel unit 110 of the front door 1b.

  As shown in FIG. 5, the display panel unit 110 includes four display panels 110a, 110b, 110c, and 110d having high light transmittance and excellent light guiding properties, and four LEDs 111, 112, 113, and 114. Have. The four display panels 110a to 110d are arranged at a predetermined distance from each other along the direction from the front side to the back side of the front door 1b. At this time, the display panels are arranged so that the light transmission surfaces of the display panels face each other. The four LEDs 111 to 114 are attached to the upper end surfaces (upper side surfaces) of the four display panels 110a to 110d, respectively.

  A pattern of a predetermined character is drawn on each of the four display panels 110a to 110d. And it is the structure which a player can visually recognize the design of a corresponding display panel by light-emitting predetermined LED. At this time, the symbols drawn on each display panel are configured to be clearly visible to the player as the brightness of the corresponding LED increases.

  Here, FIG. 6A to FIG. 6D show examples of symbols drawn on each display panel. 6A is a symbol drawn on the display panel 110d, FIG. 6B is a symbol drawn on the display panel 110c, and FIG. 6C is a symbol drawn on the display panel 110b. FIG. 6D shows a pattern drawn on the display panel 110a.

  In the present embodiment, as shown in FIGS. 6A to 6D, the symbols of the characters drawn on each display panel are the same. However, the size of the character design drawn on the display panel is different for each display panel, and the design is drawn on the display panel so that the character design becomes larger when the position of the display panel is closer to the player. .

  6A to 6D, for example, from the LED 114 provided on the display panel 110d farthest from the player, the LED 113 provided on the display panel 110c, the LED 112 provided on the display panel 110b, Further, when the brightness of the LEDs 111 provided on the display panel 110a is increased in this order (when the LEDs are made to emit light), that is, the display panel 110d located farthest from the player is positioned closest to the player. When the display panel is made to emit light sequentially toward the arranged display panel 110a, it seems to the player that the character approaches the player. On the other hand, for example, from the LED 111 provided on the display panel 110a located closest to the player, the LED 112 provided on the display panel 110b, the LED 113 provided on the display panel 110c, and the LED 114 provided on the display panel 110d. When the brightness is increased in this order (when the LED is turned on), it seems to the player that the character is moving away from him. The luminance control of the four LEDs 111 to 114 is executed by a sub CPU 71 (see FIG. 9 described later) of the sub control circuit 70 described later.

  In addition, when changing the brightness | luminance of LED111-114 in order as mentioned above, it is preferable to control the brightness | luminance of LED111-114 suitably so that a pattern may not become difficult to see. For example, when the luminance of a predetermined LED is increased, it is preferable to decrease the luminance of the LED whose luminance has been increased before that.

  In the example shown in FIGS. 6A to 6D, the character design of the display panel 110a located closest to the player is drawn largest, and the character design of the display panel 110d arranged farthest from the player is made smallest. Although the example to draw was demonstrated, this invention is not limited to this. The character design of the display panel 110a located closest to the player may be drawn the smallest, and the character design of the display panel 110d arranged farthest from the player may be drawn the largest.

  Furthermore, in the pachi-slot 1 of the present embodiment, a liquid crystal display device is separately provided on the back side of the display panel unit 110, or the display screen of the liquid crystal display device 10 is enlarged, and the player passes through the display panels 110a to 110d. You may make the image which this liquid crystal display device displays be visible.

(2) Configuration of decorative panel Next, with reference to FIGS. 7A and 7B, the configuration of the left decorative panel 121L and the left infrared sensor 120L provided on the back side thereof will be described. 7A is a front perspective view of the left decorative panel 121L, and FIG. 7B is a diagram illustrating an operation state of the left infrared sensor 120L provided on the back side of the left decorative panel 121L.

  As shown in FIG. 7A, the left infrared sensor 120L is provided on the back side of the left decorative panel 121L. The left infrared sensor 120L is a so-called reflective infrared sensor, and has an infrared beam output function and a light receiving function of an infrared beam reflected from a detection target. Then, the left infrared sensor 120L detects whether or not a detection target (for example, a player's hand) exists in the output direction of the infrared beam based on the received infrared beam, or whether or not the object is approaching. be able to.

  In this embodiment, as shown in FIG. 7B, the left infrared sensor 120L outputs an infrared beam (arrow AR) toward the left selection panel 151L, and is there a player's hand or the like near the left selection panel 151L? Detect whether or not. At this time, if a player's hand or the like is present near the left selection panel 151L, the left infrared sensor 120L detects an infrared beam reflected from the player's hand or the like.

  Although not shown and described here, the right infrared sensor 120R is also disposed on the back side of the right decorative panel 121R. At this time, the arrangement of the right decorative panel 121R and the right infrared sensor 120R is configured to be symmetrical to the arrangement of the left decorative panel 121L and the left infrared sensor 120L.

  Similarly to the left infrared sensor 120L, the right infrared sensor 120R is configured by a reflective infrared sensor, outputs an infrared beam toward the right selection panel 151R, and a player's hand exists near the right selection panel 151R. Whether or not is detected.

  In the present embodiment, the left infrared sensor 120L and the right infrared sensor 120R do not always operate and operate when a predetermined effect is executed.

  In the present embodiment, an example in which a reflective infrared sensor is used as a sensor for determining whether or not a detection target such as a player's hand exists near each selection panel has been described. It is not limited. Any sensor can be used as long as it can determine whether or not a detection target such as a player's hand exists near each selection panel. Furthermore, in this embodiment, each selection panel may be configured with a touch sensor.

<Configuration of circuits provided in pachislot>
Next, with reference to FIG.8 and FIG.9, the structure of the circuit with which the pachislot 1 in this embodiment is provided is demonstrated. FIG. 8 is a block configuration diagram of the entire circuit included in the pachislot machine 1, and FIG. 9 is a block configuration diagram illustrating an internal configuration of the sub control circuit.

  As shown in FIG. 8, the pachislo 1 includes a main control circuit 60 (main control means), a sub control circuit 70 (sub control means), and peripheral devices (actuators) electrically connected to these circuits. .

[Configuration of main control circuit and its peripheral devices]
The main control circuit 60 is a circuit that controls operations essential to games such as determination of an internal winning combination and reel rotation control. The main control circuit 60 is mainly composed of a microcomputer 30 mounted on a circuit board (main board). As other components, the main control circuit 60 includes a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, a sampling circuit 37, a lamp driving circuit 45, and a display unit driving circuit 48, as shown in FIG. A hopper driving circuit 41 and a payout completion signal circuit 51.

  The microcomputer 30 includes a main CPU (Central Processing Unit) 31, a main ROM (Read Only Memory) 32 and a main RAM (Random Access Memory) 33.

  As shown in FIG. 8, a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37 are connected to the main CPU 31 (main control unit). The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The main CPU 31 executes a control program based on the generated clock pulse. The random number generator 36 generates a random number in a predetermined range (for example, 0 to 65535). Then, the sampling circuit 37 extracts one value from the generated random numbers.

  In the main ROM 32, control programs for various processes (see FIGS. 69 to 78 to be described later) executed by the main CPU 31, various data tables (see FIGS. 29 to 42 to be described later), and various controls for the sub control circuit 70. Data and the like for transmitting a command (command) are stored.

  The main RAM 33 is provided with a storage area (see FIGS. 43 to 48 described later) for storing various data such as an internal winning combination determined by execution of the control program, various flags necessary for control, and the like.

  Connected to the input section of the microcomputer 30 are various switches, sensors, and various circuits that generate input signals that trigger the output of control signals to various circuits and various peripheral devices. Specifically, a stop switch 20S, a start switch 21S, a C / P switch 22S, a MAX bet switch 23S, a medal sensor 26S, a reel position detection circuit 50, and a payout completion signal circuit 51 are connected to the microcomputer 30 via an input / output port. Connected to the input. The main CPU 31 receives input signals from these various switches and controls the operation of peripheral devices such as the stepping motors 49L, 49C, 49R.

  The stop switch 20S detects that each of the left stop button 20L, the middle stop button 20C, and the right stop button 20R has been pressed (stop operation) by the player. The stop switch 20S outputs a stop signal to the microcomputer 30 for instructing to stop the rotation of the reel that has been operated to stop. The start switch 21S detects that the start lever 21 has been operated by the player (start operation), and outputs a start signal instructing the start of the game to the microcomputer 30.

  The C / P switch 22S detects that the C / P button 22 has been pressed by the player (credit mode / payout mode switching operation), and outputs a signal for switching the mode to the microcomputer 30. When the credit mode is switched to the payout mode, a signal for instructing the payout of medals credited to the pachislot 1 is output to the microcomputer 30.

  The MAX bet switch 23S detects that the MAX bet button 23 has been pressed by the player, and outputs a signal instructing insertion of a medal from a credited medal to the microcomputer 30.

  The medal sensor 26S detects that a medal inserted into the medal insertion slot 26 has passed through the selector, and outputs a signal indicating that a medal has been inserted to the microcomputer 30.

  The reel position detection circuit 50 detects, for each reel, a reel index indicating that the reel has made one turn by an optical sensor having a light emitting portion and a light receiving portion, and outputs a signal for detecting the position of the symbol on each reel. Occur.

  The payout completion signal circuit 51 manages the detection of medals performed by the medal detection unit 40S provided in the hopper 40, and checks whether or not the medals discharged from the hopper 40 have reached a predetermined payout number. The payout completion signal circuit 51 completes payout of medals when the number of medals detected by the medal detection unit 40S (the number of medals paid out from the hopper 40) reaches the designated number. A signal is generated to indicate this. Thereby, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

  Peripheral devices whose operations are controlled by the microcomputer 30 include three stepping motors 49L, 49C, 49R, a WIN lamp 6, a BET lamp 7, a payout number display unit 8, a credit display unit 9, and a hopper 40. Various drive circuits for controlling the operation of these peripheral devices are connected to the output section of the microcomputer 30. Specifically, the motor drive circuit 39, the lamp drive circuit 45, the display unit drive circuit 48, and the hopper drive circuit 41 are connected to the output unit of the microcomputer 30 via the input / output port.

  The motor drive circuit 39 controls driving of three stepping motors 49L, 49C, 49R provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively. Thereby, the rotation operation and the stop operation of each reel are performed.

  Each of the three stepping motors 49L, 49C, 49R has a configuration in which the momentum is proportional to the number of output pulses, and the rotation axis can be stopped at a specified angle. The driving force of each stepping motor is transmitted to the corresponding reel via a gear having a predetermined reduction ratio. Each time one pulse is output to each stepping motor, the corresponding reel rotates at a constant angle.

  The main CPU 31 detects the reel index of each reel and then counts the number of times a pulse has been output to the corresponding stepping motor, so that the rotation angle of each reel (specifically, how many symbols the reel has) Only managed).

  Here, the management of the rotation angle of each reel will be specifically described. The number of pulses output to each stepping motor is counted by a pulse counter (not shown) provided in the main RAM 33. Each time the output of a predetermined number of pulses (for example, 16 times) necessary for rotation of one symbol is counted by the pulse counter, the value of the symbol counter (not shown) provided in the main RAM 33 is set to “1”. "Is added. A symbol counter is provided for each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detection circuit 50.

  That is, in this embodiment, the number of symbols that have fluctuated in the rotation operation after the reel index detection is managed by managing the value of the symbol counter. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  In the present embodiment, the maximum number of sliding symbols in the game is set to 4 symbols. Therefore, for example, when the left stop button 20L is pressed, the symbols positioned on the effective line of the left reel 3L and the symbols existing in the range up to four points can be stopped on the effective line. It becomes a design.

  In the present embodiment, as will be described later, a symbol arrangement table is provided for associating the rotation position of each reel with the symbol drawn on the outer peripheral surface of the reel, and this symbol arrangement table is stored in the main ROM 32. Is done. The symbol arrangement table is provided for each code number from “00” to “20”, which is sequentially given at a certain rotation pitch of each reel with reference to the position where the reel index is output. It is the table which matched with the symbol code which identifies the kind of symbol provided in this way. The symbol arrangement table will be described in detail later with reference to the drawings.

  The lamp driving circuit 45 controls the operations of the WIN lamp 6 and the BET lamp 7. The display unit drive circuit 48 controls the operations of the payout number display unit 8 and the credit display unit 9. The hopper drive circuit 41 controls the operation of the hopper 40. Thereby, the medal accommodated in the hopper 40 is paid out.

[Outline of main CPU operation]
Next, an outline of main operations (functions) related to the game controlled by the main CPU 31 will be described. The detailed processing contents of the control by the main CPU 31 will be described later with reference to various processing flowcharts.

  First, each time a unit game (one game) is started, the main CPU 81 performs an internal lottery process (described later with reference to FIG. 71 and FIG. 71) based on a random number value for lottery stored in the main RAM 33. 72), an internal winning combination is determined. At this time, the main CPU 31 determines an internal winning combination based on a random number value and an internal lottery table described later (see FIGS. 35 to 37 described later). The random number value for lottery is extracted (generated) by the random number generator 36 and the sampling circuit 37 when the start signal is output from the start switch 21S, and is stored in the random value storage area of the main RAM 33.

  In this embodiment, a configuration example in which a random number value for lottery is generated using a random number generator 36 and a random number sampling circuit 37 provided outside the main CPU 31 will be described. However, the present invention is not limited to this. A random number value for lottery may be generated on the operation program of the main CPU 31. In this case, the random number generator 36 and the sampling circuit 37 may be used as a backup device for random value generation operation or may be omitted.

  Next, after the rotation speed of each reel reaches a constant speed, when a stop signal is output from the corresponding stop switch by the player's stop operation for a predetermined reel, the main CPU 31 outputs the stop signal (stop operation of the stop operation). Based on the detection timing) and the determined internal winning combination, a control signal for controlling the stop of the reel that has been operated to stop is output to the motor drive circuit 39. Then, the motor drive circuit 39 drives and controls the corresponding stepping motor based on this control signal, and stops the rotation of the corresponding reel. That is, the main CPU 31 stops the rotation of each reel based on the internal winning combination and the detection timing of the stop operation.

  At this time, in the present embodiment, the main CPU 31 performs internal processing within the range from the symbol positioned on the active line to the symbol positioned ahead by the maximum number of sliding symbols (four frames) when the stop operation is performed. The reels are controlled to stop so that the symbols related to the winning combination stop on the active line. Specifically, the main CPU 31 first plays an internal winning combination within a symbol range from a symbol positioned on the active line to a symbol ahead of four frames when a player's stop operation is performed on a predetermined reel. It is determined whether or not a symbol related to establishment exists. If there is a symbol related to the establishment of the internal winning combination within the range of the symbol, the main CPU 31 displays the corresponding reel so that the symbol related to the establishment of the internal winning combination is stopped and displayed on the active line. The number of sliding pieces is determined and the reel is stopped.

  In the reel stop control by the main CPU 31 described above, there are a plurality of symbols related to the establishment of the internal winning combination within the range from the symbol positioned on the effective line to the symbol four frames ahead when the stop operation is performed. If it exists (when a plurality of internal winning combinations are duplicated), the main CPU 31 determines the number of sliding symbols so that the symbol related to the internal winning combination with higher priority is stopped and displayed on the active line. Then, the reel is stopped. In the present embodiment, basically, the internal winning combination with the highest priority is a role related to replay (replay), and the internal winning combination with the next highest priority is the payout of medals. (Hereinafter referred to as “small role”). The priority order of the internal winning combination relating to the bonus (“BB”, “RB”) is set to be lower than the priority order of the small combination.

  Next, when all the reels are stopped, the main CPU 31 searches for the corresponding display combination (winning combination) based on the combination of symbols stopped and displayed on the active line, that is, the establishment / A failure determination process is performed. The display combination search process is performed based on a symbol combination table (described later, see FIG. 30) stored in the main ROM 32.

  When it is determined that the internal winning combination is won by the display combination searching process, the main CPU 31 gives the player a privilege corresponding to the winning combination (for example, paying out a medal). The operation of the pachi-slot 1 is controlled. Specifically, for example, when it is determined by the display combination search process that the combination of symbols related to the small combination is stopped and displayed on the active line, the main CPU 31 outputs a control signal to the hopper drive circuit 41, thereby The hopper 40 is driven, and the number of medals corresponding to the winning small combination is paid out. If it is determined that the combination of symbols related to the small combination is stopped and displayed on the active line, if the medal payout mode is switched to the credit mode by the C / P switch 22S, the winning small combination The medal payout number corresponding to is added to the credit counter of the main RAM 33.

  The main CPU 31 also obtains various information obtained during the various processes (for example, random number values for lottery, gaming state, internal winning combination, number of payouts, bonus carryover status, setting values, etc., various counters, And various control flags) are stored (set) in a predetermined storage area of the main RAM 33. Further, the main CPU 31 transmits a part of the information to the sub control circuit 70 by including it in various commands. The sub control circuit 70 performs various processes such as determination and execution of effect data based on various commands (for example, a start command described later) transmitted from the main control circuit 60. In the present embodiment, the sub control circuit 70 does not input commands, information, or the like to the main control circuit 60, and communication is performed in one direction from the main control circuit 60 to the sub control circuit 70.

[Sub-control circuit configuration]
As shown in FIGS. 8 and 9, the sub control circuit 70 is connected to the main control circuit 60, and is mainly based on commands (predetermined data) transmitted from the main control circuit 60 and input signals from various switches. Then, processing such as determination and execution of the production contents using video, sound, light and the like is performed.

  As shown in FIG. 9, the sub control circuit 70 includes a sub CPU 71 (sub control unit), sub ROM 72, DRAM (Dynamic RAM) 73 (hereinafter referred to as sub RAM 73), SRAM (Static RAM) 74 (hereinafter referred to as backup RAM 74). ), GPU (Graphics Processing Unit) 75, VRAM (Video RAM) 76, A / D (Analog to Digital) converter 77, amplifier 78, and power interruption detection circuit 90 (voltage monitoring unit). The sub ROM 72, the sub RAM 73, the backup RAM 74, the GPU 75, the A / D converter 77, and the power interruption detection circuit 90 are connected to the sub CPU 71, the VRAM 76 is connected to the GPU 75, and the amplifier 78 is connected to the A / D converter 77. Is done.

  The sub-control circuit 70 includes an RTC (Real Time Clock) 70 a (hereinafter referred to as a built-in RTC 70 a) that is a dedicated clocking circuit provided in the sub CPU 71, and an external RTC 70 b that is connected to the sub CPU 71. Further, the sub control circuit 70 has a battery 70c connected to the SRAM 74 and the external RTC 70b. The external RTC 70b is a backup timing circuit for the built-in RTC 70a. The operations of the internal RTC 70a and the external RTC 70b are managed by an RTC control task shown in FIG.

  The sub CPU 71 is composed of a CPU, and mainly performs video, sound, and light output control (effect control) in accordance with a control program stored in the sub ROM 72 in accordance with a command transmitted from the main control circuit 60. . Further, the sub CPU 71 has not only an effect control function but also, for example, various error monitoring functions. Various error monitoring functions (means) included in the sub CPU 71 will be described in detail later.

  The sub ROM 72 basically has a program storage area and a data storage area.

  Various control programs executed by the sub CPU 71 are stored in the program storage area. The control program stored in the program storage area includes, for example, a main board communication task for controlling communication with the main control circuit 60, a production random number value, and production content (production data) determination. An effect registration task for performing registration, a drawing control task for controlling display of an image by the liquid crystal display device 10 based on the determined content of the effect, a lamp control task for controlling light output from various LEDs, and a speaker 17L , 17R includes a program such as a voice control task for controlling voice output.

  In the data storage area, for example, a storage area for storing various data tables, a storage area for storing effect data constituting various effects, a storage area for storing animation data relating to creation of video, and sound data relating to BGM and sound effects And various storage areas such as a storage area for storing lamp data relating to a light on / off pattern. The configuration of various storage areas provided in the sub ROM 72 will be described in detail later.

  The sub RAM 73 has a storage area for registering the determined contents of the effect (effect data), a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 60, and the like. The configuration of various storage areas provided in the sub RAM 73 will be described in detail later.

  The backup RAM 74 is a storage device that backs up predetermined data in the sub RAM 73. For example, data copied to the sub RAM 73 is backed up in the backup RAM 74 when the power is turned on. The configuration of various storage areas provided in the backup RAM 74 will be described in detail later.

  The GPU 75 performs processing for displaying an image on the liquid crystal display device 10 based on an image display command received from the sub CPU 71. Data necessary for processing performed by the GPU 75 is expanded in the VRAM 76 at the time of activation. The GPU 75 generates image data based on the data expanded in the VRAM 76 and supplies the image data to the liquid crystal display device 10.

  As a result, an image corresponding to the effect data determined by the sub CPU 71 is displayed on the display screen of the liquid crystal display device 10. As described above, the pachislot machine 1 of the present embodiment has a scaler function, and a scaler control board 80 described later is provided in order to realize the scaler function. Therefore, in this embodiment, the size of the original image of the image displayed on the display screen of the liquid crystal display device 10 can be selected by this scaler function.

  The VRAM 76 has two frame buffer areas, a write image data area and a display image data area. The write image data area stores image data generated by the GPU 75, and the display image data area is the liquid crystal display device 10. Stores image data to be displayed on the screen. Note that the GPU 75 sequentially displays the image data on the liquid crystal display device 10 by alternately switching the two frame buffers (that is, switching the bank).

  The A / D converter 77 converts the digital audio data selected by the sub CPU 71 based on the effect data into analog audio data, and outputs the converted analog audio data to the amplifier 78. The amplifier 78 amplifies the analog audio data input from the A / D converter 77 based on the volume adjusted by a volume adjusting knob (not shown) provided in the pachislot 1, and the speakers 17L and 17R. Send to. As a result, sound corresponding to the effect data determined by the sub CPU 71 is output from the speakers 17L and 17R.

  The power interruption detection circuit 90 monitors a decrease in the power supply voltage supplied to the sub control circuit 70. When the power interruption detection circuit 90 detects the occurrence of power interruption (for example, the power supply voltage has dropped to 4.5 V), the power interruption detection circuit 90 outputs the power interruption detection signal to the sub CPU 71 as an interrupt signal. To do. Note that, when an interrupt signal is input from the external interrupt port (NMI), the sub CPU 71 executes a power interruption interrupt process described later with reference to FIG.

[Configuration of peripheral device of sub-control circuit]
As shown in FIGS. 8 and 9, the sub control circuit 70 is connected not only to the main control circuit 60 but also to the door key switch 2S, the selection switch 24S, the determination switch 25S, the setting key switch 27S, and the sub device group 100. In the present embodiment, the sub control circuit 70 determines effect data based on various commands transmitted from the main control circuit 60, input information from the selection switch 24S and the determination switch 25S, and the like. Then, the sub control circuit 70 outputs the determined effect data to various sub devices in the sub device group 100. As a result, a predetermined effect is executed by the subdevice.

(1) Configuration of Various Switches The door key switch 2S detects that the door key 2 is rotated in the counterclockwise direction (counterclockwise direction) when viewed from the player side, and outputs a detection signal to the sub CPU 71. . In the present embodiment, the error of the pachi-slot 1 is reset by rotating the door key 2 in the left rotation direction. When the door key 2 is rotated clockwise (clockwise direction), the front door 1b can be opened and closed as described above.

  The setting key switch 27S detects that a setting key (not shown) has been operated to operate a game setting value, and outputs a detection signal to the sub CPU 71.

  The selection switch 24S detects whether or not the player has pressed the selection button 24. The selection switch 24S displays a signal corresponding to the selection operation content of the player, for example, a display mode (for example, indicating which item is selected from a plurality of selectable items displayed on the menu screen or the like) , An icon) is moved to the sub CPU 71.

  The decision switch 25S detects whether or not the player has pressed the decision button 25. Then, the determination switch 25S outputs a signal corresponding to the determination operation content of the player, for example, a signal indicating that the player has selected an item in the selected state to the sub CPU 71. That is, the player can select a predetermined item by pressing the selection button 24 on the menu screen or the like until the predetermined item to be selected is selected, and then pressing the predetermined item with the decision button 25. .

(2) Configuration of Sub-Device Group Next, the configuration content of the sub-device group 100 including various sub-devices connected to the sub-control circuit 70 and controlled by the sub-control circuit 70 will be described.

  In the present embodiment, the sub device group 100 includes two speakers 17L and 17R, an upper panel LED 101, a lower panel LED 102, a waist panel LED 103, and four LEDs 111 to 11 in the display panel unit 110, as shown in FIG. 114, left infrared sensor 120L and right infrared sensor 120R. Since the configuration of these sub devices is as described above, description of these sub devices is omitted here.

  The subdevice group 100 includes a serial communication relay board 79, a scaler control board 80, and the liquid crystal display device 10. Note that the configuration of the sub device group 100 is not limited to the example shown in FIG. For example, a touch sensor module, a camera module, and the like may be included in the sub device group 100.

  The serial communication relay board 79 is connected to the sub CPU 71. At this time, the serial communication relay board 79 is connected to the sub CPU 71 (sub control circuit 70) by a UART (Universal Asynchronous Receiver Transmitter), and data is transmitted and received between them.

  The scaler control board 80 is connected to the serial communication relay board 79 and the GPU 75, and the liquid crystal display device 10 is connected to the scaler control board 80. That is, the liquid crystal display device 10 is connected to the sub CPU 71 via the scaler control board 80 and the serial communication relay board 79. If the scaler control board 80 is not provided in the sub device group 100, the liquid crystal display device 10 is connected to the sub CPU 71 via the GPU 75.

  In FIG. 9, the sub CPU 71 and the serial communication relay board 79 are connected by a single wiring line for the sake of simplicity, but actually, the control line and the data line are separately provided. Is provided. Furthermore, each of the control line and the data line is also composed of an input line and an output line provided separately from each other. Note that between the devices connected to the data line, the transmission terminal (TxD terminal) and the reception terminal (RxD terminal) of the data line are connected to each other.

[Outline of sub CPU effect control]
The sub CPU 71 mainly performs display control of the liquid crystal display device 10, output control of the speakers 17L and 17R, light emission control of various LEDs (101 to 103, 111 to 114), and the like based on a program stored in the sub ROM 72. The production control is performed.

  Specifically, the sub CPU 71 receives various commands and the like from the main control circuit 60 and stores various information included in the commands in the sub RAM 73. Since all information related to the state of the main control circuit 60 is transmitted by a command, the sub control circuit 70 can determine the state of the main control circuit 60 one by one. The sub CPU 71 executes the program while referring to the game state information, the internal winning combination information, etc. stored in the sub RAM 73, so that the liquid crystal display device 10, the speakers 17L, 17R, the various LEDs 101-103, 111-114, etc. The contents of the production to be performed by the sub device are determined.

  When determining the effect data and the like, the sub CPU 71 executes a random number acquisition program stored in the sub ROM 72 to acquire a random value for determining the effect data and the like. However, when the random number generator and the sampling circuit are provided in the sub control circuit 70 as in the main control circuit 60, this processing is not necessary.

  Next, the sub CPU 71 controls the liquid crystal display device 10 via the GPU 75 based on the determined effect data, and controls the sound output from the speakers 17L and 17R and the light emission of the various LEDs 101 to 103 and 111 to 114. .

  The LED 101 for the upper panel, the LED 103 for the lower back panel, and the LED 102 for the lower panel are each actually composed of a plurality of LEDs, and each of these LEDs is inserted into a port (not shown) provided individually. Controlled by output processing. That is, the light emission of the LED connected to each port can be individually controlled.

[Configuration of sub ROM]
Next, the internal configuration of the sub ROM 72 (cartridge ROM) will be described with reference to FIG. FIG. 10 is a diagram showing the configuration of various data areas provided in the sub ROM 72.

  As shown in FIG. 10, the sub ROM 72 has an OS area 72a for storing an operating system (hereinafter referred to as OS), a sub control program storage area 72b for storing a program executed by the sub CPU 71, and game data initialization setting data. Area 72c, clerk operation initial setting data area 72d, various program table area 72e for storing various tables, program management data area 72f, image data (still image / moving image) area 72g, sound data area 72h, and accessory movable A data area 72i is provided.

  The sub-control program storage area 72b is based on the inter-board communication process for controlling communication with the device driver and the main control circuit 60, the effect registration process for determining the contents of the effect, and the registered LED data. LED control task for controlling light output from various LEDs, sound control task for controlling sound output from speakers 17L and 17R based on registered sound data, and liquid crystal based on registered animation data A program for executing a drawing control task or the like for performing video display control by the display device 10 is stored.

  The various program table areas 72e include an effect lottery table (not shown), an error code table of a sub-control circuit 70 described later (see FIG. 13 described later), and an error code table of a sub device described later (described later FIG. 14). Various tables such as a sub device communication check table (see FIG. 20 described later) described later are stored.

  The program management data area 72f stores various types of information such as magic codes and program versions. For example, animation data called character object data is stored in the image data (still image / moving image) area 72g. In the sound data area 72h, for example, audio data such as BGM (Back-Ground Music) and sound effects are stored. Furthermore, LED control data, such as a lighting pattern of light, is memorize | stored in the accessory movable data area 72i, for example.

[Configuration of sub-RAM]
Next, the internal configuration of the sub RAM 73 (DRAM) will be described with reference to FIG. FIG. 11 is a diagram showing the configuration of various data areas provided in the sub RAM 73.

  As shown in FIG. 11, the sub RAM 73 includes a sub control game data area 73a, a sub control game data sum value area 73b, a work area 73c, a staff operation setting data area 73d, an error information history storage area 73e (error information storage section). ), A communication log collection ring buffer area 73f and a communication error storage buffer area 73g are provided. The sub RAM 73 is also provided with another work area 73h.

  In the sub-control game data area 73a, data stored in the sub-RAM 73 is stored out of information including game data related to the progress of the game. In the sub-control game data sum value area 73b, a check-sum value (4 bytes) for the game data stored in the sub-control game data area 73a is stored. The work area 73c stores various data necessary for various processes. The clerk operation setting data area 73d stores clerk operation setting data corresponding to setting items on the menu screen displayed on the display screen of the liquid crystal display device 10.

  The sub control game data area 73a and the work area 73c are used as temporary work storage means when the sub CPU 71 executes each program. Further, the sub-control game data area 73a includes, for example, commands transmitted from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counter values, from 4 bytes to 8 bytes. Information such as an arbitrary magic code and various flags is stored.

  The error information history storage area 73e includes various error detection functions (such as a communication error detection means 71a, a procedure detection means 71b, a data corruption detection means 71c, a sub device error, which will be described later) provided in the power failure detection circuit 90 and the sub CPU 71. All error information detected by the detecting means 71h etc. is stored.

  Specifically, in the error information history storage area 73e, an error detected by a communication error detection unit 71a described later is stored as a COM error, and an error detected by a procedure detection unit 71b described later is stored as a procedure abnormality error. Is done. In the error information history storage area 73e, an error detected by a data destruction detection unit 71c described later is stored as a data destruction error, and an error detected by a sub device error detection unit 71h described later is stored as a scaler error. The Further, the error detected by the power failure detection circuit 90 is stored as a power failure error in the error information history storage area 73e. In the present embodiment, error codes are sequentially stored in the error information history storage area 73e, thereby creating error history information.

  Here, the configuration of the error information history storage area 73e and the contents of various error codes stored in the error information history storage area 73e will be described in more detail with reference to FIGS. FIG. 12 is a diagram showing the configuration of the error information history storage area 73e. FIG. 13 is a table showing the contents of error codes related to the sub control circuit 70, and is a table showing the types of error codes transmitted from the main control circuit 60 to the sub control circuit 70 and their contents. FIG. 14 is a table showing the contents of error codes related to the sub devices included in the sub device group 100, and is a table showing the types of error codes transmitted from the sub device group 100 to the sub control circuit 70 and their contents. is there.

  In the error information history storage area 73e, as shown in FIG. 12, a data set (a set of an error code (“ERROR CODE”), an error occurrence date (“occurrence”), and an error release date (“release”)) is set. The error information history is stored below. The error information history storage area 73e has a configuration capable of storing 128 error information histories (data sets).

  The error code stored in the error information history storage area 73e is 1-byte data. When the error code is related to the sub control circuit 70, a predetermined error code is stored in the error code area in the error information history storage area 73e from the various error codes defined in FIG. Stored.

  For example, when a communication error occurs, an error code corresponding to “COM ERROR (COM ERR ALM)” in FIG. 13 is stored in the error code area in the error information history storage area 73e. For example, when an operation procedure error occurs, a predetermined error code corresponding to “procedure abnormality (BLS 123PE)” in FIG. 13 is stored in the error code area in the error information history storage area 73e. . Further, for example, when a data destruction error occurs, a predetermined error code corresponding to “MEM ERR ALM” in FIG. 13 is stored in the error code area in the error information history storage area 73e. The Further, for example, when a power failure error occurs, “main body (POWER DOWN)” and “short-term power failure abnormality (POWER ERR1)” to “long-term power failure abnormality (POWER ERR3)” in FIG. Is stored in the error code area in the error information history storage area 73e.

  If the error code is related to the sub-device, a predetermined error code is stored in the error code area in the error information history storage area 73e from among the various error codes defined in FIG. The

  For example, if the sub device ID does not exist, a predetermined error code corresponding to “sub device ID error (SD COM DVC)” in FIG. 14 is stored in the error code area in the error information history storage area 73e. The For example, when the sub-device is reset, a predetermined error code corresponding to “reset occurrence (SD RST)” in FIG. 14 is stored in the error code area in the error information history storage area 73e. . For example, if the data size of the scaler control board 80 exceeds 256 bytes, a predetermined error code corresponding to “data size error (SD COM SIZ)” in FIG. 14 is stored in the error information history storage area. It is stored in the error code area in 73e. For example, when communication between the sub CPU 71 and the sub device is interrupted or resumed, an error code corresponding to “communication disconnection (SCL DSC)” or “communication restart (SCL RSM)” in FIG. It is stored in the error code area in the error information history storage area 73e. Further, for example, when the luminance, contour, or interpolation setting is abnormal for the scaler control board 80, “brightness setting abnormality (SCL SET ERR1)”, “contour setting abnormality (SCL SET ERR2)” or “interpolation” in FIG. The error code corresponding to “setting error (SCL SET ERR3)” is stored in the error code area in the error information history storage area 73e.

  In each of the error occurrence date and time and the error release date and time stored in the error information history storage area 73e, “year” data is 2-byte data, “month” data is 1-byte data, and “day” data is 1-byte data, “minute” data is 1-byte data, and “second” data is 1-byte data.

  Next, FIG. 15 shows the configuration of the communication log collection ring buffer area 73f. As shown in FIG. 15, the communication log collection ring buffer area 73f includes 256 sets of command and parameter data sets and one buffer index (“0” to “255”) corresponding to each data set. Are stored as appropriate, and these data function as a ring buffer.

  FIG. 16 shows the configuration of the communication error storage buffer area 73g. The communication error storage buffer area 73g stores 1024 data groups including 256 sets of command and parameter data sets and one buffer index ("0" to "255") corresponding to each data set. The The communication error storage buffer area 73g stores one buffer selection index indicating which buffer index is selected from the buffer indexes ("1" to "1024") of the 1024 data groups. .

[Configuration of backup RAM]
Next, an internal configuration of the backup RAM 74 will be described with reference to FIG. FIG. 17 is a diagram showing the configuration of various data areas provided in the backup RAM 74.

  As shown in FIG. 17, the backup RAM 74 includes a first backup data area 74a, a first backup data sum value area 74b, a second backup data area 74c that is a mirroring of the first backup data area 74a, and a second backup data sum. A value area 74d, an attendant backup data area 74e, an attendant backup data sum value area 74f, and an error information history storage area 74g are provided.

  As described above, in the present embodiment, the first backup data area 74 a and the second backup data area 74 c are provided in the single backup RAM 74. Here, “mirroring” means copying data, and is not limited to copying data to another storage. In addition, any magic code consisting of 4 bytes to 8 bytes is provided in each of the first backup data area 74a and the second backup data area 74c.

[Data format of send / receive data]
Next, with reference to FIGS. 18 and 19, the format of various data to be transmitted and received and the contents of the transmitted and received data in communication between the sub CPU 71 and the sub device will be described.

  FIG. 18 is a diagram illustrating an example of a transmission / reception command data format. In FIG. 18, “STX” indicates a start text, and “ADR” indicates a transmission source ID and a transmission destination ID. In FIG. 18, “CMD” indicates a command, “DATA1” to “DATA256” indicate a data group of 256 bytes at maximum corresponding to the command, “ETX” indicates an end text, and “SUM” indicates an end text. Indicates the sum value up to.

  FIG. 19 is a table showing the contents of each data from “STX” to “SUM” in the transmission / reception command data format defined in FIG. For example, in “ADR” in the transmission / reception command data, the ID “01h” of the scaler control board 80 is indicated as the transmission source, the ID “02h” of the sub CPU 71 is indicated as the transmission destination, and “82h” is indicated as “CMD”. Is displayed, and “DATA1” or the like indicates a program version, it indicates that transmission / reception command data indicating a parameter request for a predetermined program version has been transmitted from the scaler control board 80 to the sub CPU 71. .

[Subdevice communication check table]
Here, with reference to FIG. 20, the subdevice communication check table (subdevice communication data consistency check table) stored in the various program table areas 72e will be described. The sub-device communication check table is used, for example, in processing such as a later-described scaler control command reception process (see FIG. 118 described later).

  The sub device communication check table is used by the sub CPU 71 to determine whether the command type and command packet size of the data received from the scaler control board 80 are correct. For example, the sub CPU 71 determines whether “CMD1” is an activation parameter request of “81h” as “determination 1” based on the subdevice communication check table, and whether the DATA size of the command is 2 bytes. Judge that. Then, when the “determination 1” ends, the sub CPU 71 proceeds to a determination process of “determination 2”.

[Error monitoring function of sub CPU]
Next, contents of various error management functions (means) included in the sub CPU 71 in the pachi-slot 1 of the present embodiment will be described.

  As shown in FIG. 9, the sub CPU 71 serves as an error monitoring unit, such as a communication error detection unit 71a, a procedure detection unit 71b, a data destruction detection unit 71c, an error information registration unit 71d, and a received data log storage unit 71e. Error information history display means 71f, two-dimensional code conversion means 71g, and sub-device error detection means 71h.

  The communication error detection means 71a detects that an error has occurred in the communication process between the main control circuit 60 and the sub control circuit 70 by executing a COM error check process (see FIG. 107 described later).

  The procedure detecting means 71b executes a main board communication reception command check process (see FIG. 106, which will be described later), and a game progresses in a procedure different from the normal game operation procedure, that is, an abnormal operation procedure. Is detected.

  The data destruction detection means 71c executes a main board reception data BCC (Block Check Character) check process (BCC check process in the sub control game data storage area) during the main board communication task of the sub CPU 71 shown in FIG. Thus, data destruction of the sub-control game data area 73a (see FIG. 11) of the sub-RAM 73, in particular, commands received from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters In addition, data destruction such as various flags is detected.

  The error information registration unit 71 d stores an error code corresponding to the detected error in the error information history storage area 73 e of the sub-RAM 73 when an error occurrence is detected by various error detection units.

  Specifically, for example, when the occurrence of a communication error is detected by the communication error detection means 71a, the error information registration means 71d corresponds to the “COM error” in FIG. 13 in the error information history storage area 73e. Error code ("COM ERR ALM" error code) is stored. Further, for example, when the occurrence of a procedure abnormality error is detected by the procedure detection unit 71b, the error information registration unit 71d stores a predetermined error code (for example, “procedure abnormality”) in the error information history storage area 73e. , "BLS 123PE" error code). Further, for example, when data destruction (sum abnormality error) is detected in the sub-control game data area 73a by the data destruction detection means 71c, the error information registration means 71d is stored in the error information history storage area 73e in FIG. The error code corresponding to the “sum error” (error code of “MEM ERR ALM”) is stored. Furthermore, for example, when an error in the luminance setting abnormality of the scaler control board 80 is detected by a sub device error detection unit 71h described later, the error information registration unit 71d stores the error information history storage region 73e in FIG. An error code (error code of “SCL SET ERR1”) corresponding to the “brightness setting abnormality” of the scaler is stored.

  Further, the error information registering unit 71d detects the power interruption by the power interruption detection circuit 90, and when the power interruption detection signal is input to the sub CPU 71, the error code corresponding to the power interruption in FIG. DOWN "error code) is stored in the error information history storage area 73e.

  Furthermore, the error information registration unit 71d performs a predetermined number of times or more in a predetermined period (short-term, medium-term or long-term), for example, by a goto action, as will be described later in the power failure abnormality fraud determination process (see FIG. 124). When a power interruption (instantaneous interruption) occurs, an error code corresponding to the number of interruptions (instantaneous interruptions) corresponding to the number of occurrences of the interruption occurs as one error code ("Short-term interruption occurrence ( "POWER ERR1)" to "Long-term power failure occurrence (POWER ERR3)"), and the collected error codes are stored in the error information history storage area 73e.

  The reception data log storage unit 71e collects information about a reception log (hereinafter also referred to as a communication log) by executing a main board communication reception data log storage process (see FIG. 103 described later). Further, the received data log storage unit 71e executes a main board communication received data log temporary area storage process (see FIG. 104 described later) in the process, thereby performing a communication log collection ring buffer area in the sub RAM 73. Only one communication log is temporarily stored in 73f. The reception data log storage unit 71e executes main board communication error history data storage processing (see FIG. 105 described later) when a communication error is detected by the communication error detection unit 71a. The communication error storage buffer area 73g of the sub RAM 73 stores up to 1024 communication logs related to communication errors (hereinafter referred to as communication error logs).

  The error information history display means 71 f displays various past error information histories stored in the error information history storage area 73 e of the sub RAM 73 on the liquid crystal display device 10 when a predetermined operation is performed on the door key 2. The error information history display operation by the error information history display means 71f will be described in detail later.

  The two-dimensional code conversion means 71g is a communication error log related to a communication error stored in the communication error storage buffer area 73g of the sub RAM 73 when the occurrence of a communication error is detected by the communication error detection means 71a. A domain of an external data management server (not shown) as a transmission destination is converted into a two-dimensional code as transmission information. Then, the two-dimensional code conversion unit 71g outputs the generated two-dimensional code data to the error information history display unit 71f. As will be described later, the two-dimensional code is displayed on the error information history confirmation screen by the error information history display means 71f (see FIG. 23 described later).

  The sub device error detection means 71h detects whether a communication error or other error has occurred between the sub CPU 71 and the sub device (such as the scaler control board 80).

  For example, errors detected by the sub device error detection means 71h executing a sub device command reception process (see FIG. 115 described later) described later are stored in the error information history storage area 73e by the error information registration means 71d. The At this time, the detected error is stored, for example, as an error code (error code of “SD COM STX”) whose head is not STX or not received by ETX according to the content of the error, for example. This error code is included in the error information history stored in the error information history storage area 73e.

[Error information display operations]
Here, various display operations of error information by the sub CPU 71 will be described.

(1) Display screen of error information In the present embodiment, when the data of the sub RAM 73 is destroyed due to some cause such as gore action, for example, on the display screen of the liquid crystal display device 10 under the control of the sub control circuit 70, A notification is given that the game cannot be continued because of an abnormality in the RAM data. FIG. 21 shows an example of the notification.

  For example, if some or all of the data received from the main control circuit 60, such as command, effect data information, gaming state information, internal winning combination information, display combination information, various counters, various flags, etc. are deleted, As shown in FIG. 21, a warning “RAM data abnormal game cannot be continued. Please change the setting” is displayed on the display screen of the liquid crystal display device 10 to notify that an error has occurred. In the present embodiment, the warning text is displayed in a portion other than the symbol display areas 4L, 4C, and 4R in the display screen of the liquid crystal display device 10. By performing such notification, an effect of suppressing the goto action can be expected.

(2) Menu Screen Display Operation In the present embodiment, for example, when a predetermined operation (for example, an operation corresponding to the opening operation of the front door 1b) is performed on the door key 2 by a clerk (hall manager) of a game shop A menu screen for performing operations such as changing various settings of the pachi-slot 1 is displayed on the ideographic screen of the liquid crystal display device 10. FIG. 22 shows an example of the menu screen.

  In the example of the menu screen shown in FIG. 22, for example, various menus listed on the menu screen by the hall manager (in the example of FIG. 22, “time setting”, “guide option”, “setting change / confirmation history”, “error” To set / change / confirm the selected menu by selecting and determining a predetermined menu from “information history”, “monitoring history”, “warning display setting”, “automatic volume adjustment function”) Is displayed.

(3) Error Information History Confirmation Screen In this embodiment, the error information history confirmation screen is displayed by selecting and determining the “error information history” menu on the menu screen shown in FIG. FIG. 23 shows a configuration example of an error information history confirmation screen displayed on the pachi-slot 1 of the present embodiment.

  As shown in FIG. 23, error information histories that occurred in the past are displayed in time series on the error information history confirmation screen. At this time, the latest error information history is displayed in the uppermost column (error number “1” column) on the confirmation screen. In the present embodiment, each error information history is displayed as a data set of “error content”, “occurrence date / time” of error, and “release date / time” of error. An error code corresponding to an error generated from the various error codes described with reference to FIGS. 13 and 14 is displayed in the “error content” column in the error information history confirmation screen.

  In this embodiment, when a predetermined error information history is selected on the error information history confirmation screen, a two-dimensional code corresponding to the selected error information history is displayed at a predetermined position in the confirmation screen. The For example, in the example shown in FIG. 23, the error information history “COM ERR ALM” is selected, and the two-dimensional code 300 corresponding to the error information history is displayed in the free area on the right side of the list of error information history.

  In the present embodiment, the communication error information is converted into the two-dimensional code 300 only when the occurrence of a communication error is detected by the sub CPU 71. Therefore, since the two-dimensional code is not generated more than necessary, the control can be simplified. The configuration of the two-dimensional code 300 will be described in detail later.

  In addition, in the example of the error information history confirmation screen shown in FIG. 23, the meaning of the error content related to the error code “BLS 123PE” described in the column of the error number “10” will be briefly described. In the operation procedure corresponding to “BLS 123PE”, the procedure of “L” and “S” representing the start of rotation of the reel by the lever operation is usually performed after the procedure of “B” representing the insertion operation of medals and the like, and the first reel. The procedure of “1” representing the stop operation of “2”, the procedure of “2” representing the stop operation of the second reel, the procedure of “3” representing the stop operation of the third reel, and the procedure of “P” representing the payment operation The game ends in order.

  However, in the example shown in FIG. 23, in the description of “error content”, the number “1” is circled. This means that the procedure for stopping the first reel has been missed. In addition, as a method for indicating the procedure of the missed operation, a method of changing a character color, changing a typeface, or making a character line thick may be used in addition to enclosing with a circle.

(4) Display Mode of Power Failure Error On the error information history confirmation screen shown in FIG. 23, as shown in the columns of error numbers “1” to “4”, a short period of 23 seconds (10 June 2012 10 From "9:46" to June 1, 2012 10: 10: 9), "POWER DOWN" (power failure) and "POWER UP" (power recovery) error code repeated twice. . That is, it shows that the power supply interruption has occurred twice in a short time.

  As a main cause of frequent interruptions in a short period of time as described above, a goto action called clear goto that erases a transmission command between the main control circuit 60 and the sub control circuit 70 can be considered. Therefore, when the error information history of “POWER DOWN” and “POWER UP” is simply displayed repeatedly for such a momentary disconnection due to the goto action, if the goto action period becomes relatively long, the error information The history confirmation screen is filled with repeated error information histories of “POWER DOWN” and “POWER UP”. An example is shown in FIG.

  As shown in FIG. 24, when the error information history confirmation screen is filled with repeated display of “POWER DOWN” and “POWER UP”, the start time and end time of goto action and the number of goto actions are grasped. It becomes difficult to do. That is, simply repeating the history display of “POWER DOWN” and “POWER UP” makes it difficult to grasp at a glance the error information related to the goto action. Therefore, in the present embodiment, when a power interruption (instantaneous power interruption) occurs more than a predetermined number of times within a predetermined period, the error information history of “POWER DOWN” and “POWER UP” is repeatedly displayed for the number of power interruptions. (Error information related to power interruption) is collected and displayed in one error information history.

  Furthermore, in the present embodiment, when power interruptions ("POWER DOWN") occur more than a predetermined number of times in each of the three types of periods: short-term (second unit), medium-term (minute unit), and long-term (time unit). Displays the error information history (repetition of “POWER DOWN” and “POWER UP”) related to power interruptions for the number of power interruptions that occurred within a predetermined period in one error information history. . More specifically, when power interruption occurs 5 times or more in 30 seconds (short term), when power interruption occurs 10 times or more in 10 minutes (medium term), or for 4 hours (long term) When power interruption occurs 30 times or more, the error event in each case is displayed as one error information history instead of repeatedly displaying “POWER DOWN” and “POWER UP”.

  At this time, on the error information history confirmation screen, an error code corresponding to each error event, that is, “POWER ERR1” (“short-term power” in various error codes shown in FIG. One of the following error codes is displayed: “POWER ERR2” (“Middle term power failure”) and “POWER ERR3” (“Long term power failure”). Furthermore, together with the error code, the occurrence time (occurrence date and time) of the first interruption (“POWER DOWN”) and the occurrence time (“POWER DOWN”) of the last interruption (“POWER DOWN”) (Release date and time) is also displayed. An example is shown in FIG.

  In the example of the error information history confirmation screen shown in FIG. 25, five or more times of electric power are used during 28 seconds from 10:08:32 on June 1, 2012 to 10: 9: 02 on June 1, 2012. It is an example of a display when a disconnection occurs. In this example, an error information history corresponding to the occurrence of such a power failure abnormality is displayed in the column of error number “1”. Specifically, an error code of “POWER ERR1” indicating an error of “short-term power failure abnormality” is displayed in “error content”, and “2012/06/01 10:08” is displayed in “occurrence date”. : 32 ”is displayed, and“ 2012/06/01 10:09: 00 ”is displayed in“ Release date and time ”.

  Thus, on the error information history confirmation screen, an error event that is considered to be an error caused by a go-to action is displayed in one error information history, so that the error information history confirmation screen is displayed as “POWER DOWN” and “POWER UP”. ”Is not buried, and the presence / absence and number of goto acts and the period during which the goto act was performed can be confirmed at a glance. Furthermore, in the present embodiment, the occurrence of power interruption abnormalities is monitored in three different periods: short-term (second unit), medium-term (minute unit), and long-term (hour unit). It can be detected, and the deterrent effect of goto action is obtained.

  In the present embodiment, as a determination condition for the presence or absence of an error event due to the goto action, 5 or more interruptions occur in 30 seconds (short term), 10 or more interruptions occur in 10 minutes (medium period), and 4 An example of using three types of determination conditions for occurrence of power interruptions of 30 times or more in time (long term) will be described, but the present invention is not limited to this, for example, for the pattern type of the goto action to be detected (monitored) Accordingly, the determination condition can be arbitrarily changed. For example, the condition for the determination period may be changed, the condition for the number of occurrences of power interruption may be changed, or both conditions may be changed together. Furthermore, the types of determination conditions are not limited to three, and the number of determination conditions may be more or less than three.

(5) Configuration of two-dimensional code In the present embodiment, the two-dimensional code 300 displayed on the error information history confirmation screen is information transmitted to an information processing apparatus for analysis provided outside the pachislot 1. . By transmitting the two-dimensional code 300 to the information processing device for analysis, the cause of the error can be analyzed and specified by an external information processing device, and the analysis result is used for the subsequent improvement of the pachislot 1 or the like. Can be used. Although not shown, in this error information transmission process, the error information of the two-dimensional code 300 is once read by, for example, an attendant's portable terminal or the like, and the data management server of the external information processing apparatus from the portable terminal or the like. Sent to.

  Here, the transmission information included in the two-dimensional code 300 will be described with reference to FIG. FIG. 26 is a diagram illustrating a format of transmission information included in the two-dimensional code 300.

  The transmission information included in the two-dimensional code 300 is composed of information consisting of 192 bytes, as shown in FIG. Note that the transmission information has a general-purpose configuration so that not only the pachislot machine 1 of this embodiment but also error information recorded by other types of pachislot machines can be transmitted.

  The domain of the data management server (not shown) and data indicating a request to the data management server are set in the 0th to 28th bytes of the transmission information. A case unique code for identifying the pachislot 1 is set in the 29th to 39th bytes of the transmission information. The area from the 40th byte to the 61st byte of the transmission information is a spare area. The transmission information generation time is set in the 62nd to 67th bytes of the transmission information. A model code indicating the type of pachislot 1 is set in the 68th to 71st byte areas of the transmission information.

  A type number is set in the 72nd to 73rd byte areas of the transmission information. In this case, information “3FH” is set in both the 72nd and 73rd byte areas. Information indicating the type of error is set in the area of the 74th to 75th bytes of the transmission information. Error information is set in the 76th to 188th bytes of the transmission information. A checksum is set in the area from the 189th byte to the 191st byte of the transmission information.

  Note that the error information set in the 76th to 188th bytes of the transmission information includes a command type consisting of one character (6 bits). When the command type is accompanied by a parameter, a parameter consisting of two characters (12 bits) is added after the one-character command type.

  FIG. 27 shows a table example of command types and parameters included in the transmission information. In the command type and parameter table shown in FIG. 27, not only the correspondence between the received command data in each received command and the type and parameter, but also the received command data in the previous received command, the type and parameter, The correspondence is also shown.

  Further, the information included in the transmission information is not limited to this example. For example, the transmission information may include information related to the player's game record.

  As described above, in the present embodiment, the sub CPU 71 creates the two-dimensional code 300 only when a communication error occurs. Here, a recording image of information of the two-dimensional code 300 when a COM error (communication error) occurs will be described with reference to FIGS. 28A to 28C. The numerical values in FIGS. 28A to 28C are the number of characters of data, “1” character data indicates a command type, and “2” character data indicates a parameter for the immediately preceding command.

  First, consider a case where a communication error occurs, for example, accidentally during a normal game (in the example of FIG. 28A, a COM error occurs between “first stop” and “second stop”). In this case, as shown in FIG. 28A, the data recorded as error information in the two-dimensional code 300 causes a communication error (COM error) during normal processing, and normal processing is performed again immediately after that. It will be executed.

  Next, consider a case where a communication error has occurred due to a go-to action and the pachislot 1 has been changed in setting. In this case, the data placed as error information on the two-dimensional code 300 is the one whose setting has been changed immediately after the occurrence of a communication error (COM error) as shown in FIG. 28B. Further, consider a case where a communication error occurs and continuous transmission is performed by lever operation. In this case, as shown in FIG. 28C, the data that is put as the error information in the two-dimensional code 300 includes the lever operation as the command type and the winning combination as the parameter immediately after the occurrence of the communication error (COM error). It will be a thing.

(6) Error Information History Display Operation Next, an outline of a series of operations from the error detection process to the error information history display process under the control of the sub CPU 71 will be described.

  In the present embodiment, when the occurrence of a communication error is detected by the communication error detection means 71a, the error information registration means 71d stores an error code corresponding to the communication error in the error information history storage area 73e of the sub RAM 73. . The received data log storage unit 71e stores the communication log in the communication log collection ring buffer area 73f and also stores the communication error log in the communication error storage buffer area 73g.

  If an error other than a communication error is detected by the procedure detection means 71b, the data destruction detection means 71c or other error detection means other than the communication error detection means 71a, the error information registration means 71d Is stored in the error information history storage area 73 e of the sub-RAM 73. The received data log storage unit 71e stores the communication log in the communication log collection ring buffer area 73f without storing the communication log in the communication error storage buffer area 73g.

  When a predetermined operation is performed on the door key 2 by an attendant or the like, the error information history display means 71f displays the error information history stored in the error information history storage area 73e on the display screen of the liquid crystal display device 10. To display. In this embodiment, two methods of normal operation and simple operation by an attendant are adopted as a method for displaying the error information history confirmation screen as shown in FIGS. 23 and 25 on the liquid crystal display device 10. Yes.

  In the normal operation, first, the clerk rotates the door key 2 clockwise to release the lock mechanism of the front door 1b. Next, the clerk operates the setting key to turn on the setting key switch 27S, and displays the menu screen shown in FIG. 22 on the display screen of the liquid crystal display device 10. Then, the clerk operates the operation keys to select the “error information history” item in the menu. In the normal operation, the error information history confirmation screen as shown in FIGS. 23 and 25 is displayed on the display screen of the liquid crystal display device 10 by such an operation procedure.

  On the other hand, in the simple operation, the clerk rotates the door key 2 counterclockwise to reset the error, and holds the state for a certain time (for example, 5 seconds or more). In the simple operation, the error information history confirmation screen as shown in FIG. 23 and FIG. 25 is displayed on the display screen of the liquid crystal display device 10 by such an operation procedure.

  The error information history registration editing process (aggregation process) that is performed when power interruptions ("POWER DOWN") occur frequently (when power failure occurs) is performed by, for example, the error information registration unit 71d of the sub CPU 71. Done. The present invention is not limited to this, and the means for performing the above-described error information history registration / editing process may be provided separately from the error information registration means 71d. Further, the specific contents of the error information history registration / editing process described above will be described in detail in the flowcharts of the processes related to the fraud monitoring process task shown in FIGS. 123 and 124 described later.

<Configuration of data table stored in main ROM>
Next, with reference to FIGS. 29 to 42, the structure of various data tables stored in the main ROM 32 and necessary for controlling various game operations will be described.

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table includes positions of symbols in the rotation directions of the left reel 3L, the middle reel 3C, and the right reel 3R, and data (hereinafter referred to as symbol codes) for specifying the type of symbols arranged at each position. Define the correspondence.

  In the symbol arrangement table, when a reel index is detected, the position of the symbol arranged in the middle area within the frame of each symbol display area is defined as “0”. Then, in each reel, the value corresponding to the symbol counter in the order of advance in the reel rotation direction (the direction from symbol position “20” in FIG. 29 toward symbol position “0”) with reference to symbol position “0” is as follows: Symbol positions “0” to “20” are assigned to the symbols.

  That is, by referring to the symbol counter values (“0” to “20”) and the symbol arrangement table, the types of symbols displayed in the upper, middle, and lower regions within the frame of each symbol display region Can be specified. For example, when the value of the symbol counter corresponding to the left reel 3L is “7”, the upper, middle, and lower regions in the frame of the left symbol display area 4L have “don 1” at the symbol position “8”, respectively. , Symbols corresponding to “bell 1” at symbol position “7” and “replay” at symbol position “6” are displayed.

[Design combination table]
Next, the symbol combination table will be described with reference to FIG. The symbol combination table defines a correspondence relationship between a symbol combination predetermined according to the type of privilege, a display combination (storage area), and a payout number.

  Note that FIG. 30 shows a combination of symbols that trigger the transition of a gaming state (RT gaming state) to be described later (“up 2nd 1” to “up 2nd 3” described in the contents column of the display combination in FIG. 30). , “Push order bell failure 1” to “push order bell failure 4”, “SB spilled eyes 1” to “SB spilled eyes”). Hereinafter, the combination of symbols that trigger the transition of the gaming state (RT gaming state) is also referred to as a transitional combination.

  In the present embodiment, the combination of symbols displayed by the left reel 3L, the middle reel 3C and the right reel 3R along the effective line matches the symbol combination specified in the symbol combination table (excluding the above transition combination). When winning, it is determined to be a prize. When it is determined that a prize is won, the player is given benefits such as a medal payout, a re-game operation, and a bonus game operation. If the symbol combination displayed along the active line does not match any of the symbol combinations defined in the symbol combination table, it is a so-called “lost”. That is, in this embodiment, the symbol combination corresponding to “losing” is not defined in the symbol combination table, thereby defining the symbol combination “losing”. Note that the present invention is not limited to this, and the item “losing” may be provided in the symbol combination table to directly define “losing”. Further, the symbol “ANY” in the symbol combination table shown in FIG. 30 represents an arbitrary symbol drawn on the corresponding reel.

  Various data described in the display combination column in the symbol combination table is data for identifying a symbol combination displayed along the active line. “Data” in the display combination column is represented by 1-byte data, and a unique symbol combination (content of display combination) is assigned to each bit in the data.

  The “storage area” data in the display combination column is data for designating a later-described display combination storage area (see FIG. 44 described later) in which information on the corresponding display combination is stored. In the present embodiment, seven display combination storage areas (display combination storage area 1 to display combination storage area 7) are provided. In the present embodiment, display combinations having the same bit pattern (1-byte data pattern) and having different contents are managed as different display combinations depending on the “storage area”.

  The numerical value described in the payout number column in the symbol combination table represents the number of medals to be paid out to the player. In the combination of symbols to which a numerical value of 1 or more is given as the “paid-out number” data, the same number of medals are paid out. In the present embodiment, when the number of inserted medals is 2, for example, when any one of “Bell” to “BB medium use combination 5” in the symbol combination table shown in FIG. 30 is determined as the display combination. Ten medals are paid out. On the other hand, when the number of inserted medals is 3, when one of “bell” to “control combination 3” in the symbol combination table shown in FIG. A predetermined number (one of 1, 2, 4 and 6) of medals is paid out in accordance with the above.

  In the present embodiment, combinations of symbols relating to replay (replay) as a display combination, for example, “normal lip”, “up 1 step lip 1” to “up 2 step lip 2” shown in the symbol combination table of FIG. ”And“ control lip 1 ”to“ control lip 3 ”, when one of the symbol combinations is determined, the re-game is performed. Furthermore, when one of “BB1” to “BB4” is determined as the display combination, the big bonus game is activated, and when “SB” is determined as the display combination, the single bonus game is activated. .

[Bonus operating table]
Next, the bonus operation time table will be described with reference to FIG. The bonus operation time table is stored in a later-described game state flag storage area (see FIG. 46 described later) provided in the main RAM 33, a bonus end number counter, a game possible number counter, and a winning possible number counter provided during the bonus game. Define the data.

  The game state flag is data for identifying the type of bonus game being operated. In the present embodiment, four types of big bonuses (“BB1” to “BB4”), two types of regular bonuses (“RB1”, “RB2”), and a single bonus (“SB”) are used as bonus games. Provide. Each game state flag is assigned to each bonus. Note that the present embodiment is not limited to this, and for example, a common gaming state flag may be given to four types of big bonuses (“BB1” to “BB4”).

  Note that “RB” is continuously operated when “BB” is operated, but “RB1” is continuously operated when “BB1” to “BB3” is operated in this embodiment, and “RB2” is continuously operated when “BB4” is operated. Operate.

  The numerical value of the bonus end number counter stipulated in the bonus operation time table is data indicating the number of medals to be paid out (specified number) that triggers the end of the bonus game. In the present embodiment, the operations of “BB1” to “BB3” are finished when the medals of more than the specified number “270” are paid out, and the operation of “BB4” is set to the specified number “60”. The process ends when more medals are paid out.

  Specifically, first, the numerical value of the “bonus end number counter” defined in the bonus operation time table is actually stored in the bonus end number counter. Next, after the BB operation, every time a medal is paid out, the value of the bonus end number counter is subtracted. Then, the operation of “BB” is terminated on condition that the value of the bonus end number counter is less than “0” (negative value).

  The game possible number counter is data for managing the number of remaining games that can be played at the time of RB operation, that is, the so-called game possible number (12 times in the present embodiment). The winning possible number counter is data for managing the number of remaining games that can display a combination of symbols related to winning at the time of RB operation, so-called winning possible number (8 times in the present embodiment). It is.

[Game state transition flow]
Next, with reference to FIG. 32, the transition flow of the gaming state in the present embodiment will be described. As shown in FIG. 32, main game states managed by the main control circuit 60 include “general game state”, “RT1 game state” (RT: replay time), “RT2 game state”, and “RT3 game state”. , “RT4 gaming state” and “BB gaming state” (generic name of “BB1 gaming state” to “BB4 gaming state”). Note that, between these gaming states, the winning probability of replay and / or the type of replay to be won differ from each other. Although not shown, the game state managed by the main control circuit 60 operates in the “SB game state” in which only one game coexists with the other game states, or “BB1 game state” to “BB3 game state”. There is an “RB2 gaming state” that operates in “RB1 gaming state” and “BB4 gaming state”.

  In the present embodiment, in the game in the “general game state”, the symbol combination related to “SB spilled eyes” (any one of “SB spilled eyes 1” to “SB spilled eyes 12” in the symbol combination table shown in FIG. 30). When (transfer role) is stopped and displayed on the active line, the gaming state transitions from the “general gaming state” to the “RT1 gaming state”.

  In the game of “RT1 gaming state”, when the symbol combination related to “Raise 1st stage lip 1” is stopped and displayed on the active line, the gaming state transitions from “RT1 gaming state” to “RT2 gaming state”. . Further, in the game of “RT1 gaming state”, the symbol combination related to “push order bell failure” (any one of “push order bell failure 1” to “push order bell failure 4” in the symbol combination table shown in FIG. 30). Is stopped on the active line, the gaming state transitions from “RT1 gaming state” to “general gaming state”.

  In a game of “RT2 gaming state”, “Raise 2 stage lip” (“Raise 2 stage lip 1” or “Raise 2 stage lip 2” in the symbol combination table shown in FIG. 30) or “Raise second stage” ( When the symbol combination related to “any one of“ 2nd raised 1 ”to“ 3 raised 2 ”in the symbol combination table in FIG. 30) is stopped and displayed on the active line, the gaming state is“ RT gaming state ”. To “RT3 gaming state”. Further, in the game of “RT2 gaming state”, when the symbol combination related to “SB spilling” is stopped and displayed on the active line, the gaming state transitions from “RT2 gaming state” to “RT1 gaming state”. Furthermore, in the game of “RT2 gaming state”, when the symbol combination related to “push order bell failure” is stopped and displayed on the active line, the gaming state transitions from “RT2 gaming state” to “general gaming state”. To do.

  In the game of “RT3 gaming state”, when the symbol combination related to “SB spilling” is stopped and displayed on the active line, the gaming state transitions from “RT3 gaming state” to “RT1 gaming state”. In addition, in the game of “RT3 gaming state”, when the symbol combination related to “push order bell failure” is stopped and displayed on the active line, the gaming state transitions from “RT3 gaming state” to “general gaming state”. To do.

  In any of the “general gaming state” and “RT1 gaming state” to “RT3 gaming state”, the combination related to “BB” (any one of “BB1” to “BB4”) is determined as an internal winning combination. In this case, the gaming state transitions from any one of “general gaming state” and “RT1 gaming state” to “RT3 gaming state” to “RT4 gaming state”. Further, in the game of “RT4 gaming state”, when the symbol combination related to “BB” (any one of “BB1” to “BB4”) is stopped and displayed on the active line, the gaming state is “RT4 gaming state”. ”To“ BB gaming state ”(any one of“ BB1 gaming state ”to“ BB4 gaming state ”). Further, in the “BB gaming state”, when a prescribed number (270 or 60) of medals are paid out (when “BB” ends), the gaming state transitions from the “BB gaming state” to the “general gaming state”. .

[RT transition table]
Here, FIG. 33 shows an RT transition table in which transition forms of the gaming state (RT gaming state) described in FIG. 32 are summarized. The RT transition table defines a correspondence relationship between a combination of symbols (transfer role) that becomes a trigger for transition and the control content of the game state flag. This RT transition table is used when the gaming state flag is updated in an RT control process (described later with reference to FIG. 75) executed by the main control circuit 60.

  Specifically, when the symbol combination related to any of “push order bell failure 1” to “push order bell failure 4” is stopped and displayed on the active line, all the game state flags are turned off. Thus, the “general gaming state” is activated. Further, when the symbol combination related to any one of “SB spilled eyes 1” to “SB spilled eyes 12” is stopped and displayed on the active line, the RT1 gaming state flag is turned on. In addition, when the symbol combination related to “up 1 step lip 1” is stopped and displayed on the active line, the RT2 gaming state flag is turned on. In addition, when the symbol combination related to any one of “Raising 2 stage Lip 1”, “Raising 2 stage Lip 2” and “Raising second eye 1” to “Raising second eye 3” is stopped and displayed on the effective line The RT3 gaming state flag is turned on.

  Each transition combination (display combination) defined in the RT transition table of FIG. 32 is a case where a predetermined combination is determined as an internal winning combination, as will be described in detail later, and a predetermined predetermined combination. The reel stop operation is performed according to the stop operation sequence of the reel, the reel stop operation is performed in a stop operation sequence different from the predetermined stop operation sequence, or the reel stop operation is performed at an appropriate timing. This is a display combination that may be stopped and displayed on the active line if there is not.

[Internal lottery table determination table]
Next, the internal lottery table determination table will be described with reference to FIG. The internal lottery table determination table is an internal lottery table used for determining the on / off information of the game state flag in each gaming state and the internal lottery process in the internal lottery process described later (see FIGS. 71 and 72 described later). And the number of lottery times.

  For example, when only the SB gaming state flag and the RT1 gaming state flag are “1 (ON state)”, that is, when the “SB gaming state” and the “RT1 gaming state” are operating together. “In-SB RT1 gaming state internal lottery table” is selected as the internal lottery table, and “49” is selected as the number of lotteries. Further, for example, when all the game state flags are “0 (off state)”, that is, when the game state is “general game state”, the “internal lottery table for general game state” is used as the internal lottery table. Is selected, and “49” is selected as the number of lotteries.

[Internal lottery table]
Next, the internal lottery table will be described with reference to FIGS.

  The internal lottery table is a table that is referred to when performing an internal lottery in an internal lottery process (see FIGS. 71 and 72 described later), that is, when determining an internal winning combination. The internal lottery table defines the correspondence between the data pointer and the lottery value when this data pointer is determined in various winning numbers.

  The data pointer is data acquired as a result of lottery performed with reference to the internal lottery table, and designates an internal winning combination specified by an internal winning combination determination table described later (see FIGS. 38 and 39 described later). It is data for. There are two types of data pointers: a small role / replay data pointer and a bonus data pointer.

  FIG. 35 is an internal lottery table that is referred to when the gaming state (RT gaming state) is any one of “general gaming state” and “RT1 gaming state” to “RT4 gaming state”. FIG. 36 is an internal lottery table that is referred to when the gaming state is any one of “BB1 gaming state” to “BB3 gaming state” (“RB1 gaming state”). FIG. 37 is an internal lottery table that is referred to when the gaming state is “BB4 gaming state” (“RB2 gaming state”).

  In the internal lottery tables shown in FIGS. 35 to 37, the right column of the “winning number” column shows the abbreviation of the internal winning combination corresponding to the data pointer. Further, on the right side of each internal lottery table shown in FIG. 36 and FIG. 37, it stops on one of the top line (upper stage), center line (middle stage) and bottom line (lower stage) corresponding to the data pointer. The name (stop form) of the symbol combination which can be displayed is shown.

  36. For example, “don XX tempered slip” described in the stop type table in FIG. 36 means “don” on the line corresponding to “XX” (on the top line if “upper”) in the stop operation of each reel. When the stop operation is performed at a timing at which the symbol (design “Don 1” or “Don 2” in FIG. 29) can be stopped and displayed, the first and second stop operation operations will display “Don” on the corresponding line. The symbol “design” is stopped and displayed, but in the third stop operation, the “don symbol” is not stopped and displayed on the corresponding line.

  For example, in the “RB1 gaming state”, when “25” (winning number “2”) is determined as the data pointer for the small role / replay, the stop type becomes “Do n’t lower tempered”. In this stop type, when the stop operation is performed on the left reel 3L and the middle reel 3C at a timing at which “Don symbol” can be stopped and displayed on the lower zone of the left reel 3L and the lower zone of the middle reel 3C. In the lower area of the left reel 3L and the lower area of the middle reel 3C, the “don symbol” is stopped and displayed. In the lower region of the right reel 3R, the right reel is displayed at a timing at which the “don symbol” can be stopped and displayed. Even when the stop operation is performed on the 3R, the “don symbol” is not stopped and displayed in the lower area of the right reel 3R.

  On the other hand, “per don XX template” in the stop type table in FIG. 36 means “don symbol” on the line corresponding to “XX” (on the top line if “upper”) in the reel stop operation. When a stop operation is performed at a timing when can be stopped, “Don Symbol” is stopped and displayed in all symbol display areas on the corresponding line (“Don Symbol”-“Don Symbol”-“Don Symbol”). This means a stop type in which the symbol combination “symbol” is stopped and displayed.

  For example, in the “RB1 gaming state”, when “28” (winning number “5”) is determined as the small role / replay data pointer, the stop type becomes “per don't lower tempo”. In this stop type, the left reel 3L, the middle reel 3C, and the right reel at the timing at which “Don symbols” can be stopped and displayed in the lower area of the left reel 3L, the lower area of the middle reel 3C, and the lower area of the right reel 3R. When the stop operation is performed on 3R, “Don symbol” is stopped and displayed in all symbol display areas on the bottom line (“Don symbol”-“Don symbol”-“Don symbol” symbol combination) Is stopped).

  Here, the contents of the internal lottery process in this embodiment will be briefly described. In the internal lottery process, first, a random value extracted from a predetermined numerical range (for example, 0 to 65535) is sequentially subtracted by a lottery value defined corresponding to each winning number. Next, it is determined (internal lottery) whether the result of the subtraction has become negative (whether a so-called “digit” has occurred). When the result of subtraction becomes negative (a “digit” occurs) at a predetermined winning number, it means that the winning number is won, and the data point assigned to the corresponding winning number is acquired.

  For example, in the “general gaming state”, when the extracted random number value is “1500” and the internal lottery table shown in FIG. 35 is referred to, the main CPU 31 first determines the winning number “1” from “1500”. The lottery value “1000” corresponding to is subtracted. In this case, the subtraction result (1500−1000 = 500) is positive.

  Next, the main CPU 31 subtracts the lottery value “2100” corresponding to the winning number “2” from the subtracted value “500”. In this case, the subtraction result (500-2100 = -1600) is negative. Therefore, the main CPU 31 determines (acquires) the winning number “2” as the internal winning combination, that is, “13” as the small combination / replay data pointer, and determines “0” as the bonus data pointer.

  In the above internal lottery processing method, the larger the numerical value defined as the lottery value, the higher the probability that assigned data (that is, data pointer) is determined. The winning probability of each winning number can be expressed by “the lottery value specified for each winning number / the number of all random numbers that may be extracted (random denominator: 65536)”.

  In the present embodiment, various lottery processes using lottery values are performed in addition to the internal lottery process described above, as will be described later. However, these lottery processing methods are the same as the above-described internal lottery processing methods. A lottery table is provided for each lottery process, and a predetermined lottery value is appropriately defined in the lottery table according to an item (for example, a winning number) that may be selected by lottery. As described above, in the present embodiment, the lottery processing methods other than the internal lottery processing are the same as the above-described internal lottery processing methods, and thus description thereof is omitted.

[Internal winning combination determination table]
Next, with reference to FIGS. 38 and 39, the internal winning combination determination table will be described. In the present embodiment, two types of internal winning combination determination tables for bonuses and replays (FIG. 39) are prepared as internal winning combination determination tables for bonuses (FIG. 38) and small winning combination / replay internal winning combination determination tables (FIG. 39).

  The internal winning combination determination table defines the correspondence between the data pointer and the internal winning combination. That is, when the data pointer is determined, the internal winning combination data is uniquely acquired by the internal winning combination determination table. The internal winning combination determination table is referred to when an internal winning combination is determined based on the data pointer in an internal lottery process (see FIGS. 71 and 72 described later).

  “Internal winning combination” in the internal winning combination determination table is data for identifying a combination of symbols of the left reel 3L, the middle reel 3C, and the right reel 3R that are permitted to be displayed along the active line. The “internal winning combination” is represented by 1-byte data in the same way as the “display combination” in the symbol combination table shown in FIG. 30, and a unique symbol combination is assigned to each bit in the 1-byte data. Assigned. When the data pointer is “0”, the content of “internal winning combination” is “losing”, but this is for all the display combinations related to the winnings defined by the symbol combination table shown in FIG. Indicates that symbol combination display is not permitted.

(1) Bonus internal winning combination determination table FIG. 38 is a diagram showing a configuration of the bonus internal winning combination determination table. The bonus internal winning combination determination table defines internal winning combinations related to the operation of the bonus game for each of the bonus data pointers “1” to “5”.

  In the bonus internal winning combination determination table, “◯” indicates an internal winning combination to be won in the acquired bonus data pointer. For example, when “1” is acquired as the bonus data pointer, “BB1” is won as the internal winning combination.

  For example, when “5” is determined as the bonus data pointer, “SB” is won as the internal winning combination. In this case, when the stop operation is performed on the three reels in the predetermined stop order, the combination of symbols related to “SB” is stopped and displayed on the effective line, but the stop operation is performed in the predetermined stop order. When the operation is not performed, the combination of symbols relating to any one of “SB spilled eyes 1” to “SB spilled eyes 12” is stopped and displayed on the active line.

(2) Small winning combination / replay internal winning combination determination table FIG. 39 is a diagram showing a configuration of a small winning combination / replay internal winning combination determining table. The small winning combination / replay internal winning combination determining table defines the small winning combination and replay winning combination for each of the small combination / replay data pointers “1” to “31”. That is, the small winning combination / replay internal winning combination determination table defines a correspondence relationship between the small winning combination / replay data pointer and the internal winning combination relating to the payout of medals or the internal winning combination relating to the replay operation. In addition, the symbol “◯” in the small winning combination / replay winning symbol determination table indicates the internal winning combination to be won in the acquired small winning combination / replay data pointer.

  For example, when “2” is determined as the data pointer for small combination / replay, the replay combination related to “normal lip 1” and “up 1-step lip 1” is won as an internal winning combination. In this case, only when the stop operation is performed in the order of the left reel 3L, the right reel 3R, and the middle reel 3C, the combination of symbols related to “up 1 step lip 1” is stopped and displayed on the active line. . On the other hand, when the stop operation is performed in the other order, the combination of symbols related to “normal lip 1” is stopped and displayed on the active line.

  Further, for example, even when any one of “3” to “6” is determined as the small role / replay data pointer, as in the case where the small role / replay data pointer “2” is acquired, “ Raising one-step lip 1 ”and“ normal lip 1 ”are commonly used in common (see FIG. 39). In this case, the order of the stop operation in which the combination of symbols related to “up 1 step lip 1” is stopped and displayed on the active line is predetermined for each data pointer, and the stop operation is performed in a predetermined order. When it is performed, the symbol combination related to “Raising 1-step lip 1” is stopped and displayed on the active line, but when the stop operation is performed in the other order, the symbol combination related to “normal lip 1” is displayed. The combination is stopped on the active line.

  Specifically, when the small role / replay data pointer “3” is acquired, only when the stop operation is performed in the order of the left reel 3L, the right reel 3R, and the middle reel 3C, The combination of symbols related to “Step Lip 1” is stopped and displayed on the active line.

  When the small role / replay data pointer “4” is acquired, only when the stop operation is performed in the order of the middle reel 3C, the left reel 3L, and the right reel 3R, "Is stopped and displayed on the active line.

  In addition, when the small pointer / replay data pointer “5” is acquired, only when the stop operation is performed in the order of the middle reel 3C, the right reel 3R, and the left reel 3L, "Is stopped and displayed on the active line.

  Further, when the small role / replay data pointer “6” is acquired, the combination of symbols related to “raising 1-step lip 1” is performed only when the first stop operation is performed on the right reel 3R. Is stopped on the active line.

  For example, when “7” is determined as the data pointer for the small role / replay, “normal lip 1”, “up 1 step lip 1”, “up 2 step lip 1”, “up 2 step lip” 2 ”and“ Control Lip 1 ”to“ Control Lip 3 ”are duplicated (see FIG. 39).

  In this case, only when the first stop operation is performed on the left reel 3L, “raised 2-step lip 1”, “raised 2-step lip 2”, “raised 2-step lip 1”, “raised-second sight” The combination of symbols relating to either “2” or “raised second eye 3” is stopped and displayed on a predetermined active line. In the present embodiment, when “up 2nd 1”, “up 2nd 2” or “up 2nd 3” is stopped and displayed on a predetermined effective line, “normal lip 1” or “ “Raised 1-step lip 1” is stopped and displayed on another active line. On the other hand, when the stop operation is performed in the other order, the combination of symbols related to “normal lip 1” is stopped and displayed on the active line.

  Further, for example, even when any one of “8” to “11” is determined as the small role / replay data pointer, as in the case where the small role / replay data pointer “7” is acquired, “ The “normal lip 1”, “raising 1-step lip 1”, “raising 2-step lip 1”, and “raising 2-step lip 2” are commonly duplicated (see FIG. 39). And in this case, the combination of symbols related to “Raise 2 stage Lip 1”, “Raise 2 stage Lip 2”, “Raise 2 eye 1”, “Raise 2 eye 2” or “Raise 2 eye 3” is effective. The order of the stop operation to be stopped and displayed on the line is predetermined for each data pointer, and when the stop operation is performed in a predetermined order, the combination of symbols related to any of these is stopped and displayed on the active line However, when the stop operation is performed in the other order, the combination of symbols related to “normal lip 1” is stopped and displayed on the active line.

  Specifically, when the small role / replay data pointer “8” is acquired, only when the stop operation is performed in the order of the middle reel 3C, the left reel 3L, and the right reel 3R, The combination of symbols related to any one of “Step Lip 1”, “Raise 2 Step Lip 2”, “Raise 2 Eye 1”, “Raise 2 Eye 2” and “Raise 2 Eye 3” is stopped and displayed on the active line. .

  Further, when the small role / replay data pointer “9” is acquired, only when the stop operation is performed in the order of the middle reel 3C, the right reel 3R, and the left reel 3L, ”,“ Raise 2 stage Lip 2 ”,“ Raise second eye 1 ”,“ Raise second eye 2 ”and“ Raise second eye 3 ”are stopped and displayed on the active line.

  In addition, when the small role / replay data pointer “10” is acquired, only when the stop operation is performed in the order of the right reel 3R, the left reel 3L, and the middle reel 3C, ”,“ Raise 2 stage Lip 2 ”,“ Raise second eye 1 ”,“ Raise second eye 2 ”and“ Raise second eye 3 ”are stopped and displayed on the active line.

  Furthermore, when the small role / replay data pointer “11” is acquired, only when the stop operation is performed in the order of the right reel 3R, the middle reel 3C, and the left reel 3L, ”,“ Raise 2 stage Lip 2 ”,“ Raise second eye 1 ”,“ Raise second eye 2 ”and“ Raise second eye 3 ”are stopped and displayed on the active line.

  For example, when “12” is determined as the data pointer for the small role / replay, “bell” and “control combination 1” to “control combination 3” are duplicated (see FIG. 39). In this case, regardless of the stop operation order, the “bell 1” symbol (the combination of symbols related to the display combination “bell”) is stopped and displayed in the middle area of the middle reel 3C. When the “bell 1” symbol is stopped and displayed in the middle area of the middle reel 3C, the “bell 1” symbol (“bell 2” symbol) − “bell” is displayed on any of the center line, the cross-up line, and the cross-down line. The symbol combination “1” symbol- “bell 1” symbol is stopped and displayed.

  When “13” is determined as the data pointer for the small role / replay, “bell” is won (see FIG. 39). In this case, only when the stop operation is performed in order of the left reel 3L, the middle reel 3C, and the right reel 3R, the “bell 1” symbol (the combination of symbols relating to the “bell”) is displayed in the middle area of the middle reel 3C. ) Is stopped.

  On the other hand, when the stop operation is performed in the other order, the combination of symbols related to any of “push order bell failure 1” to “push order bell failure 4” is stopped and displayed on the active line. When the combination of symbols related to any of “push order bell failure 1” to “push order bell failure 4” is stopped on the active line, the “bell 1” symbol (“bell 2” is displayed on the bottom line. "Symbol)-" bell 1 "symbol-" bell 1 "symbol combination is stopped and displayed.

  Further, for example, even when any one of “14” to “17” is determined as the small role / replay data pointer, as in the case where the small role / replay data pointer “13” is acquired, “ “Bell” is a common winning combination (see FIG. 39). Also in this case, the order of the stop operation in which the “bell 1” symbol (the symbol combination related to the display combination “bell”) is stopped and displayed on the active line in the middle area of the middle reel 3C is predetermined for each data pointer. When the stop operation is performed in a predetermined order, the “Bell 1” symbol is stopped and displayed in the middle area of the middle reel 3C. The combination of symbols related to any of “order bell failure 1” to “push order bell failure 4” is stopped and displayed on the active line.

  Specifically, when the small role / replay data pointer “14” is acquired, only when the stop operation is performed in the order of the left reel 3L, the right reel 3R, and the middle reel 3C, the middle reel 3C The “bell 1” symbol is stopped and displayed in the middle area.

  When the small role / replay data pointer “15” is acquired, the “bell 1” symbol is displayed in the middle area of the middle reel 3C only when the first stop operation is performed on the middle reel 3C. Is stopped.

  In addition, when the small role / replay data pointer “16” is acquired, the middle area of the middle reel 3C is used only when the stop operation is performed in the order of the right reel 3R, the left reel 3L, and the middle reel 3C. The “Bell 1” symbol is stopped and displayed.

  Further, when the small role / replay data pointer “17” is acquired, the middle area of the middle reel 3C is only when the stop operation is performed in the order of the right reel 3R, the left reel 3L, and the middle reel 3C. The “Bell 1” symbol is stopped and displayed.

  As described above, in this embodiment, in the internal lottery table (see FIG. 35), the abbreviated small role / replay pointers ("2" to "11", " 13 ”to“ 17 ”), the suggested pushing order is a so-called correct pushing order, and the game state is advantageous for the player by performing the stop operation in accordance with the pushing order. Such a combination of symbols is stopped and displayed on the active line.

  For example, when the small role / replay pointer “2” (abbreviation “left middle right bell”) is acquired, the stop operation is performed in the order of the left reel 3L, the middle reel 3C, and the right reel 3R. Only, the “bell 1” symbol is stopped and displayed in the middle area of the middle reel 3C, and in the other pressing order, the “bell 1” symbol is stopped and displayed in the lower area of the middle reel 3C. In the former stop operation, payout of 4 medals × 3 effective lines = 12 medals is given, and in the latter stop operation, payout of 4 medals × 1 effective line = 4 medals is given.

[Stop table]
Next, the stop table will be described with reference to FIG. The stop table shown in FIG. 40 is a stop table that is referred to when the middle reel 3C is stopped for the first time when the small role / replay data pointer “15” is acquired.

  In the stop table, line data and stop data corresponding to symbol positions “0” to “20” are defined. The symbol position defined in the stop table is a symbol position located in the middle area of the symbol display area when a stop operation is detected, and is a symbol position at which the reel rotation stop operation is started. .

  Although not shown here, in this embodiment, a small role / replay data pointer and a plurality of stop tables corresponding to the stop operation order of the player are prepared.

  For example, when “5” is determined as the bonus data pointer, only when the stop operation is performed in the order of the right reel 3R, the left reel 3L, and the middle reel 3C, the “SB spilling point 1” to “ A stop table in which the number of sliding symbols is specified so that none of the SB spilled eyes 12 "is stopped and displayed on the active line is selected. On the other hand, when the stop operation is performed in an order other than this, when the stop operation is performed on each reel at the timing when the symbol combination related to “SB” is not stopped and displayed, “SB spill 1 ”To“ SB spilled eyes 12 ”is selected a stop table in which the number of sliding symbols is specified such that the combination of symbols is stopped and displayed on the active line.

[Pull-in priority table]
Next, with reference to FIGS. 41 and 42, the pull-in priority table will be described. The pull-in priority table A shown in FIG. 41 is a pull-in priority table used in normal times (including during BB) or when a stop operation is performed in a predetermined stop order (so-called “push order correct answer”). Yes, the pull-in priority table B shown in FIG. 42 is a pull-in priority table used when a stop operation is performed in an order other than the predetermined stop order (so-called “push order incorrect answer”).

  Each pull-in priority table has a plurality of internal winning combinations in the case where a plurality of internal winning combinations are overlapped and the symbol combinations related to the plurality of internal winning combinations can be stopped and displayed (drawn) on the active line. Specifies the ranking of internal winning combinations that are stopped and displayed as a display combination with priority from among the winning combinations. Each pull-in priority table is used to search whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols obtained based on the stop table.

  In the present embodiment, basically, the priority order is the replay combination, small combination, and bonus from the highest priority. However, among the small roles, the higher the number of payouts, the higher the priority (in the case of JAC1 (7 in BB), this is given priority). Further, in this embodiment, a plurality of types of replay roles are prepared, and the priority order of each replay role varies depending on the conditions such as the correct answer / incorrect answer in the above-described push order. One of the pull-in priority table B is used.

  As described above, the pull-in priority table A shown in FIG. 41 is referred to at the normal time (including during BB) or at the so-called “push order correct answer”. In this case, the priority order of each replay combination is “higher two-step lip 1”, “higher two-step lip 2”> “higher one-step lip 1”> “normal lip 1”> “control lip 1 ”to“ Control Lip 3 ”.

  On the other hand, at the so-called “push order incorrect answer”, the pull-in priority table B shown in FIG. 42 is referred to. In this case, the priority order of each replay combination is “normal lip 1”> “up two-step lip 1”, “up two-step lip 2”, “up one-step lip 1”> “control lip from the highest priority. 1 ”to“ Control Lip 3 ”.

  In addition, although not shown, when two or more symbol combinations (transitional combinations) relating to the transition of the RT gaming state are simultaneously stopped and displayed, it is also determined in advance which transition combination is to be prioritized. In the present embodiment, the priority order of each migrating role is “higher two-step lip 1”, “higher two-step lip 2”, “higher two-step 1” to “higher two-step 3”> “higher one”. Step lip 1 ”>“ SB spilled eye 1 ”to“ SB spilled eye 12 ”>“ push order bell failure 1 ”to“ push order bell failure 4 ”.

<Configuration of storage area provided in main RAM>
Next, the configuration of various storage areas provided in the main RAM 33 will be described with reference to FIGS.

[Internal winning combination storage area, display combination storage area, carryover combination storage area]
First, the configuration of the internal winning combination storing area, the display combination storing area, and the carryover combination storing area will be described with reference to FIGS. FIG. 43 is a diagram showing a configuration example of the internal winning combination storing area in the present embodiment, FIG. 44 is a diagram showing a configuration example of the display winning combination storing area in the present embodiment, and FIG. It is a figure which shows the structural example of the carryover combination storage area | region in this embodiment.

  The internal winning combination storing area is a data area for storing (storing) information of the internal winning combination and is composed of internal winning combination storing areas 1 to 5 as shown in FIG. Each internal winning combination storing area is composed of a data area of 1 byte (8 bits). Then, by storing the data of “0” or “1” in the area of bits “0” to “7” in each internal winning combination storing area, the information of the internal winning combination won internally is stored. Specifically, when data “1” is stored in a predetermined bit in a predetermined internal winning combination storing area, it indicates that the internal winning combination corresponding to the predetermined bit is won. On the other hand, when all the bits of the internal winning combination storing area are “0”, the content of the internal winning combination is “lost”.

  The display combination storage area is a data area for storing (storing) information of the display combination, and includes display combination storage areas 1 to 7 as shown in FIG. In the present embodiment, information on the transition combination that triggers the transition of the RT state is also stored in the display combination storage area. Each display combination storage area is composed of a 1-byte (8-bit) data area. Then, by storing the data “0” or “1” in the bit “0” to “7” area in each display combination storage area, the display combination corresponding to the symbol combination stopped and displayed on the active line is displayed. Alternatively, information on the transition role is stored. Specifically, when data “1” is stored in a predetermined bit in a predetermined display combination storing area, a combination of symbols related to the combination corresponding to the predetermined bit is displayed on the active line. Show. On the other hand, when all the bits in the display combination storage area are “0”, the symbol combination related to winning, the symbol combination related to the operation of the bonus game, the symbol combination related to the RT state transition trigger, etc. are not displayed on the active line. It shows that.

  The carryover combination storage area is a data area for storing (storing) information of bonuses carried over (carryover combination), and is composed of a data area of 1 byte (8 bits) as shown in FIG. Then, by storing the data “0” or “1” in the area of bits “0” to “3” in the carryover combination storage area, the information of the carryover combination is stored. Specifically, when data “1” is stored in a predetermined bit in the carryover combination storage area, it indicates that the carryover combination corresponding to the predetermined bit is a bonus currently carried over. Note that the data of the carryover combination stored in the carryover combination storage area is held without being cleared until the symbol combination related to the carryover combination is displayed on the active line.

[Game state flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. The gaming state flag storage area is a data area for storing on / off information of each gaming state flag, and is configured by a gaming state flag storage area 1 and a gaming state flag storage area 2 as shown in FIG.

  Each gaming state flag storage area is composed of a 1-byte (8-bit) data area. In the present embodiment, a bonus game type is assigned to each bit of the gaming state flag storage area 1, and an RT type is assigned to each bit of the gaming state flag storage area 2. When “1” is stored in a predetermined bit in the game state flag storage area, it indicates that a bonus game or RT corresponding to the predetermined bit is being operated. Further, when all the data of each bit in the gaming state flag storage area is “0”, it indicates that the gaming state is the general gaming state.

[Design storage area]
Next, the configuration of the symbol storage area will be described with reference to FIGS. 47 and 48. FIG. In the present embodiment, as the symbol storage area, the symbol storage area A when “RB” is inactive (when the gaming state is other than the RB gaming state), and the symbol storage area B when “RB” is activated Is provided.

  FIG. 47 is a configuration example of the symbol storage area A when “RB” is not operated, and the symbol position data at the time of the stop operation of each reel (the symbols of the symbols located in the middle area of each symbol display area at the time of the stop operation) It is a figure which shows the structural example of the symbol storage area A in case a symbol position data) is "0". On the other hand, FIG. 48 shows a configuration example of the symbol storage area B when the “RB” is operated, and the symbol position data when the left reel 3L, the middle reel 3C and the right reel 3R are stopped are “9”, It is a figure which shows the structural example of the symbol storage area B in the case of "8" and "9". In each symbol storage area, the symbol position of each reel stopped and displayed on the effective line is stored.

  When “RB” is not activated, the effective line is the center line, bottom line, cross down line, and cross up line. Therefore, in the symbol storage area A when “RB” is not activated, symbol position data is stored for each effective line. Is done.

  For example, in the example shown in FIG. 47, since the symbol position data at the time of the stop operation of each reel is “0”, the “red 7” symbol is displayed in the middle area of the symbol display area of each reel constituting the center line. A symbol code corresponding to (symbol position “0”) is stored. In this case, the symbol code corresponding to the “replay” symbol (design symbol position “20”) is stored in the lower area of the left symbol display area 4L of the left reel 3L, which forms the bottom line, and the middle reel 3C The symbol code corresponding to the “cherry 1” symbol (symbol position “20”) is stored in the lower area of the middle symbol display area 4C, and “bell 1” is stored in the lower area of the right symbol display area 4R of the right reel 3R. A symbol code corresponding to the symbol (symbol position “20”) is stored. In this case, the symbol code corresponding to the “wave” symbol (symbol position “1”) is stored in the upper area of the left symbol display area 4L of the left reel 3L constituting the cross down line. A symbol code corresponding to the “red 7” symbol (symbol position “0”) is stored in the middle symbol display region 4C of 3C, and “bell 1” is displayed in the lower symbol region of the right symbol display region 4R of the right reel 3R. The symbol code corresponding to the symbol (symbol position “20”) is stored. In this case, the symbol code corresponding to the “replay” symbol (symbol position “20”) is stored in the lower area of the left symbol display area 4L of the left reel 3L constituting the cross-up line. A symbol code corresponding to the “red 7” symbol (symbol position “0”) is stored in the middle symbol display region 4C of 3C, and “cherry 1” is displayed in the upper symbol region of the right symbol display region 4R of the right reel 3R. The symbol code corresponding to the symbol (symbol position “1”) is stored.

  On the other hand, since the effective line is only the special line during RB when “RB” is activated, the symbol position data of the symbol stopped and displayed on the special line during RB is stored in the symbol storage area B when “RB” is activated. The For example, in the example shown in FIG. 48, the symbol position data at the time of the stop operation of the left reel 3L, the middle reel 3C and the right reel 3R are “9”, “8” and “9”, respectively. In the middle area of the left symbol display area 4L of the left reel 3L, a symbol code corresponding to the “don 2” symbol (symbol position “9”) is stored, and the middle symbol display area 4C of the middle reel 3C In the lower area, a symbol code corresponding to the “cherry 2” symbol (symbol position “7”) is stored, and in the upper area of the right symbol display area 4R of the right reel 3R, a “replay” symbol (symbol position “10”) is stored. ") Is stored.

<Configuration of data table stored in sub-ROM>
Next, the configuration of various lottery tables stored in the sub ROM 72 will be described. In addition, lottery values are defined in each lottery table described below (for each table depending on conditions), and a predetermined lottery process is performed by the same method as the lottery process using the internal lottery table described above. . In each lottery table described below, lottery values are defined so that the sum of lottery values is “65536”.

[Navigation mode transition lottery table]
First, the configuration of various navigation mode transition lottery tables will be described with reference to FIGS. 49 to 51. The navigation mode transition lottery table is a lottery table that is used when the navigation mode of the transfer destination is determined by lottery (see the start command reception process in FIGS. 81 and 82 described later). In this embodiment, five types of “0” to “4” are prepared as navigation modes. In this embodiment, three types of navigation mode transition lottery table A, navigation mode transition lottery table B, and navigation mode transition lottery table C are prepared as navigation mode tables.

  Note that “navigation” in the present specification refers to a function of notifying the player of information that would be advantageous to the player. Also, in this specification, a period during which “navigation” is performed is referred to as AT (Assist Time), and the transition of the navigation mode from “0” to “1” to “4” is determined as AT winning (or ART). That's what it means.

  FIG. 49 is a diagram showing a configuration example of the navigation mode transition lottery table A. In the navigation mode transition lottery table A, the lottery value of the destination navigation mode is defined in accordance with the current navigation mode and the value of the small role / replay data pointer. FIG. 50 is a diagram illustrating a configuration example of the navigation mode transition lottery table B. In the navigation mode transition lottery table B, the lottery value of the destination navigation mode is defined according to the current navigation mode and the value of the bonus data pointer. 49 and 50, the same navigation mode as the current navigation mode may be determined as the destination navigation mode (that is, the navigation mode does not change).

  FIG. 51 is a diagram showing a configuration example of the navigation mode transition lottery table C. The navigation mode transition lottery table C is a navigation mode transition lottery table that is referred to when the number of navigation games becomes zero. In this case, a lottery value is defined for each of the case where the navigation mode shifts to the mode “0” and the case where the current mode is maintained.

[Navi gaming state transition standby number lottery table]
Next, the navigation game state transition standby number lottery table will be described with reference to FIG. FIG. 52 is a diagram showing a configuration example of the navigation game state transition standby number lottery table in the present embodiment.

  The navigation game state transition standby number lottery table is a lottery table used when determining the number of navigation game state transition standbys (see the process at the time of receiving a start command in FIGS. 81 and 82 described later). In the present embodiment, a lottery value for the number of waiting states for navigation game state transition is defined for each of the three types of states. Specifically, as shown in FIG. 52, when non-BB simultaneous winning ("A" state in the figure), BB simultaneous winning ("B" state in the figure), and when the number of navigation games becomes 0 In each state (“C” in the figure), lottery values for the number of waiting states for various navigation game state transitions are defined. At the time of lottery, the lottery value defined in the corresponding status column is referred to.

  Here, the various navigation game states prepared in the pachi-slot 1 of this embodiment are demonstrated easily. In the present embodiment, four types of navigation game states of the navigation game state 0 to the navigation game state 3 are prepared as the navigation game state. The navigation game state 0 is a game state in which navigation is not performed, and the navigation game state 1 to the navigation game state 3 are game states in which navigation is performed. In the navigation game state 1 or the navigation game state 3, the value of the navigation game number counter provided in the sub RAM 73 is not subtracted, and in the navigation game state 2, the value of the navigation game number counter is subtracted. The number of remaining games in the navigation game states 1 to 3 is managed by the navigation game number counter and the navigation set number counter provided in the sub RAM 73, and the value of the navigation game number counter has changed from “1” to “0”. Even in this case, if the value of the navigation set number counter is “1” or more, “50” is further set in the navigation game number counter.

  In the present embodiment, when the navigation mode shifts from “0” to any one of “1” to “4”, the navigation gaming state also shifts from the navigation gaming state 0 to the navigation gaming state 1 or the navigation gaming state 2. . At this time, the navigation game state shifts after the number of games (unit game number) of the navigation game state transition standby number determined by the lottery process using the navigation game state transition standby number lottery table has elapsed. Therefore, as a transition form of the navigation game state, there is a form in which the navigation game state transitions after a predetermined number of games (navigation game state transition standby number) elapses. There is also a case where the waiting number of waiting for the navigation game state transition is 0).

[Navigation game state 3 transition waiting number lottery table]
Next, the navigation game state 3 transition standby number lottery table will be described with reference to FIG. FIG. 53 is a diagram showing a configuration example of the navigation game state 3 transition standby number lottery table in the present embodiment.

  The navigation game state 3 transition standby number lottery table is a lottery table used when determining the navigation game state 3 transition standby number (refer to the navigation game state 3 transition process during the navigation game state 2 in FIG. 93 described later). In the navigation game state 3 transition standby number table, a lottery value is defined according to a value of a navigation game number counter, which will be described later. Specifically, the lottery value is separately defined when the value of the navigation game number counter is “5” or less and when the value of the navigation game number counter is “6” or more. If the value of the navigation game number counter is “6” or more, as shown in FIG. 53, the small role / replay data pointer is one of “18” to “21”, and the navigation The navigation game state 3 transition standby number table is set so that the lottery value when winning the game state 3 addition game lottery is different from the lottery value in other cases.

[Navi gaming state 3 addition game number lottery table]
Next, with reference to FIGS. 54 to 57, the navigation game state 3 addition game number lottery table will be described. The navigation game state 3 addition game number lottery table is a lottery table used when determining the number of navigation game state 3 addition games (see, for example, the number of navigation game state 3 addition games and lottery mode lottery processing in FIG. 87 described later). . In the present embodiment, four types of lottery tables (navigation game state 3 addition game number lottery tables AD) are prepared as the navigation game state 3 addition game number lottery tables.

  FIG. 54 is a diagram showing a configuration example of the navigation game state 3 addition game number lottery table A in the present embodiment, and FIG. 55 shows a configuration example of the navigation game state 3 addition game number lottery table B in the present embodiment. FIG. FIG. 56 is a diagram showing a configuration example of the navigation game state 3 addition game number lottery table C in the present embodiment, and FIG. 57 shows one example of the navigation game state 3 addition game number lottery table D in the present embodiment. It is a figure which shows the example of a structure.

  In the navigation game state 3 added game number lottery tables A to C, as shown in FIGS. 54 to 56, the current navigation mode, the value of the small role / replay pointer and / or the value of the bonus data pointer are displayed. Accordingly, lottery values for various types of navigation game state 3 addition games are defined. In addition, as shown in FIG. 57, the navigation game state 3 addition game number lottery table D defines the correspondence between the various navigation game state 3 addition game numbers and the lottery values regardless of the current navigation mode. Each lottery value is commonly used for all current navigation modes.

[Navi gaming state 3 addition lottery mode lottery table]
Next, the navigation game state 3 addition lottery mode lottery table will be described with reference to FIGS. The navigation game state 3 addition lottery mode lottery table is a lottery table used when determining the navigation game state 3 addition lottery mode (see, for example, the number of navigation game state 3 addition lottery and lottery mode lottery processing in FIG. 87 described later). . In the present embodiment, four types of lottery tables (navigation game state 3 addition lottery mode lottery tables AD) are prepared as the navigation game state 3 addition lottery mode lottery table.

  58 is a diagram showing a configuration example of the navigation game state 3 addition lottery mode lottery table A in the present embodiment, and FIG. 59 is a configuration example of the navigation game state 3 addition lottery mode lottery table B in the present embodiment. FIG. FIG. 60 is a diagram showing a configuration example of the navigation game state 3 addition lottery mode lottery table C in the present embodiment, and FIG. 61 shows an example of the navigation game state 3 addition lottery mode lottery table D in the present embodiment. It is a figure which shows the example of a structure.

  In the navigation game state 3 addition lottery mode lottery table A and the navigation game state 3 addition lottery mode lottery table D, as shown in FIGS. 58 and 61, various navigation game state 3 addition lottery tables are selected according to the current navigation mode. A lottery value for the mode is defined. In the navigation game state 3 addition lottery mode lottery table B, as shown in FIG. 59, lottery values for various navigation game state 3 addition lottery modes are defined in accordance with the current navigation mode and the value of the bonus data pointer. . In the navigation game state 3 addition lottery mode lottery table C, as shown in FIG. 60, lottery values of various navigation game state 3 addition lottery modes according to the values of the current navigation mode and the small role / replay data pointer. Is stipulated.

[Navigation set number lottery table]
Next, a navigation set number lottery table will be described with reference to FIG. FIG. 62 is a diagram showing a configuration example of a navigation set number lottery table in the present embodiment.

  The navigation set number lottery table is a lottery table used when determining the number of navigation sets (refer to the ART initial hit processing in FIG. 88 described later). In the navigation set number lottery table, lottery values for various navigation set numbers (“0” to “3”) are defined. In this embodiment, as shown in FIG. 62, various navigations used when “BB3” is won (determined as an internal winning combination) and there is a game stop for performance (a lock effect described later). Two kinds of lottery values, that is, lottery values for the number of sets and lottery values for various numbers of navigation sets used in other cases are defined in the navigation set number lottery table.

[Navigation gaming state 3 navigation game number addition lottery table]
Next, the navigation game state 3 navigation game number addition lottery table will be described with reference to FIG. FIG. 63 is a diagram showing a configuration example of the navigation game state 3 navigation game number addition lottery table in the present embodiment.

  The navigation game state 3 navigation game number addition lottery table is a lottery table used when the navigation game state 3 navigation game number addition lottery is performed (see the navigation game number addition process in FIG. 95 described later). In the navigation game state 3 navigation game number addition lottery table, the navigation game state 3 addition lottery mode, the value of the small role / replay pointer and / or the bonus data pointer, and the game state The winning / non-winning lottery value of the 3 Navi game number adding lottery is defined.

[Navi game number special addition lottery table]
Next, the navigation game number special addition lottery table will be described with reference to FIG. FIG. 64 is a diagram showing a configuration example of the navigation game number special addition lottery table in the present embodiment.

  The navigation game number special addition lottery table is a lottery table used when determining the number of navigation games to be added in the navigation game number special addition lottery (see the navigation game number addition process in FIG. 95 described later). In the navigation game number special addition lottery table, the value of the navigation game state 3 continuation counter or the lottery value of the number of navigation games to be added according to the type of “BB” determined as the internal winning combination is defined.

[Billy get challenge occurrence lottery table]
Next, the billy get challenge occurrence lottery table will be described with reference to FIG. FIG. 65 is a diagram showing a configuration example of the billy get challenge occurrence lottery table in the present embodiment.

  The billy get challenge occurrence lottery table is a lottery table that is used when the billy get challenge occurrence lottery is performed (see the lottery process in BB4 in FIG. 84 described later). In the billy get challenge occurrence lottery table, lottery values are defined in accordance with the current navigation mode, presence / absence of production game stop, and on / off of the billy get challenge success flag.

  Here, an event called “Billy get challenge” will be described. “Billy get challenge” is an event that is performed by a player when a predetermined condition is satisfied. Specifically, the “Billy get challenge” is a game when a “Billy get challenge effect” is displayed on the display screen of the liquid crystal display device 10, for example, “Choose left or right”. The person holds his hand near the left selection panel 151L or the right selection panel 151R (hereinafter referred to as a selection operation) until the third stop operation is performed, and this selection operation is the left infrared sensor 120L or the right infrared sensor 120R. It is performed by detecting.

  At this time, when the correct answer (“left”, “right”, “both”) determined by the billy get challenge correct answer lottery performed in advance matches the “left” or “right” selected by the player (the correct answer is In the case of “both”, it is determined that both match), “Billy get challenge” is successful, and the navigation mode is increased.

  Further, in the present embodiment, even if the player does not perform the selection operation described above, if the winning is determined by the lottery when no billy get challenge selection is performed in advance, the “Billy get challenge” is set. Considered successful. If the player's selection (“Left” or “Right”) does not match the correct answer (when the player holds his / her hand in a direction different from the correct answer), a lottery will be awarded when no billy get challenge is selected. Even so, the “Billy Get Challenge” will fail.

  In the present embodiment, the example in which it is determined whether or not the player's selection operation has been performed before the third stop operation is performed in the “Billy get challenge” is described, but the present invention is not limited to this. . The end timing of the selection period can be arbitrarily set. For example, the end timing of the selection period can be set until the first stop operation is performed, the second stop operation is performed, or a predetermined predetermined time. It may be set until time elapses. In addition, the start timing of the selection period can be arbitrarily set. For example, the start timing of the selection period may be set after the start operation is performed, after the first stop operation is performed, or the like. . Furthermore, the period for determining whether or not the player's selection operation has been performed may be an arbitrary period during one unit game, or an arbitrary period over a plurality of unit games (for example, start of a unit game) From the operation to the third stop operation of the next unit game).

[Billy get challenge control counter lottery table]
Next, the billy get challenge control counter lottery table will be described with reference to FIG. FIG. 66 is a diagram showing a configuration example of the billy get challenge control counter lottery table in the present embodiment.

  The billy get challenge control counter lottery table is a lottery table that is used when the billy get challenge control counter lottery is performed (see the billy get challenge lottery process in FIG. 96 described later). In the billy get challenge control counter lottery table, lottery values are defined in accordance with the presence / absence of the effect game stop and the value of the small role / replay pointer or the value of the bonus data pointer.

[Billy get challenge correct lottery table]
Next, the billy get challenge correct lottery table will be described with reference to FIG. FIG. 67 is a diagram showing a configuration example of the billy get challenge correct lottery table in the present embodiment.

  The billy get challenge correct lottery table is a lottery table used when determining the correct answer (“left”, “right”, “both”) at the time of “billy get challenge” (see the billy get challenge process in FIG. 86 described later). It is. In the billy get challenge correct lottery table, lottery values are defined according to the situation when the “billy get challenge” is generated.

  Specifically, as shown in FIG. 67, when the gaming state is not the RB gaming state, or when the gaming state is the RB gaming state and there is no staging game stop, the correct answer is “left” or “right ”Is determined, and the probability that each correct answer is determined is“ 32768/65536 (= 50%) ”. On the other hand, when the gaming state is the RB gaming state and there is a production stop, one of “Left”, “Right” and “Both” (“Left” or “Right” is correct) is determined as the correct answer. Is done. In this case, the probability of determining “left” or “right” as the correct answer is “31744/65536”, and the probability of determining “both” as the correct answer is “2048/65536”.

[Lottery table when no billy get challenge is selected]
Next, with reference to FIG. 68, the lottery table without the billy get challenge selection will be described. FIG. 68 is a diagram showing a configuration example of a lottery table when no billy get challenge is selected in the present embodiment.

  When no billy get challenge is selected, the lottery table is used when the player does not select either “left” (left selection panel 151L) or “right” (right selection panel 151R) in the “Billy get challenge” (Billy get challenge). It is a lottery table used when determining whether or not to win (when there is no selection) (see the billy get challenge process in FIG. 86 described later). In the lottery table when no billy get challenge is selected, a lottery value is defined according to the result of the billy get challenge correct lottery performed based on the billy get challenge correct lottery table.

  In this embodiment, as shown in the lottery table when no billy get challenge is selected in FIG. 68, even when there is no billy get challenge selected (when the player does not perform the selection operation), When the result is “left” or “right”, it is configured to win with a probability of 50%. Further, when the result of the billy get challenge correct lottery is “both”, the winning combination is made with a probability of 100%.

<Description of main control circuit operation>
Next, the contents of various control processes executed by the main CPU 31 of the main control circuit 60 using a program will be described with reference to FIGS. Various tables necessary for various processes of the main CPU 31 described below are stored in the main ROM 32, and various control flags, various control counters, various storage areas, and the like are provided in the main RAM 33.

[Reset interrupt processing]
First, a reset interrupt process performed by the main CPU 31 will be described with reference to FIG. FIG. 69 is a flowchart illustrating a procedure of reset interrupt processing performed by the main CPU 31 in the present embodiment. The main CPU 31 generates a reset interrupt by turning on the power and applying a voltage to the reset terminal. Based on the occurrence of the reset interrupt, the main CPU 31 uses a program stored in the main ROM 32 to execute the following. The reset interrupt process described in the above is performed.

  First, the main CPU 31 clears a designated storage area (not shown) of the main RAM 33 (S1). Specifically, the main CPU 31 erases data in the writable area of the main RAM 33 used in the previous game, writes parameters necessary for the current game in the writable area of the main RAM 33, The start address designation processing for the game sequence program is performed.

  Next, the main CPU 31 performs a bonus operation monitoring process (S2). Details of the bonus operation monitoring process will be described later with reference to FIG. 70 described later.

  Next, the main CPU 31 performs medal acceptance / start check processing (S3). In the medal acceptance / start check process, the insertion number counter is updated by checking the medal sensor 26S, the MAX bet switch 23S, etc., the input check of the start switch 21S, and the like. Further, the main CPU 31 validates the valid line (winning determination line) through the medal acceptance / start check process.

  Next, the main CPU 31 extracts a random value and stores the extracted random value in a random value storage area (S4). Specifically, the main CPU 31 acquires one value (random value) randomly extracted by the random number generator 36 and the sampling circuit 37 from the range “0” to “65535”, and the acquired random value Is stored in the random value storage area.

  Next, the main CPU 31 performs an internal lottery process (S5). Specifically, the main CPU 31 refers to the internal lottery table determination table (see FIG. 34), the internal lottery table (see FIGS. 35 to 37), and the internal winning combination determination table (see FIGS. 38 and 39), and S4 The internal winning combination is determined based on the random number value extracted in. Details of the internal lottery process will be described later with reference to FIGS. 71 and 72 described later.

  Next, the main CPU 31 transmits start command data to the sub-control circuit 70 (S6). The start command includes game state information, internal winning combination information (information regarding a small combination / replay data pointer, bonus data pointer and internal winning combination storing area), carryover state information indicating whether or not a bonus carryover state, Various information such as a lock flag is included.

  Next, the main CPU 31 determines whether or not the lock flag is on (S7). In S7, when the main CPU 31 determines that the lock flag is not on (when S7 is No), the main CPU 31 performs the process of S9 described later. On the other hand, when the main CPU 31 determines in S7 that the lock flag is on (in the case where S7 is Yes), the main CPU 31 turns off the lock flag and performs a lock effect for 5 seconds (stopping the game for production). Is executed (S8). In the lock effect performed in S8, an effect of delaying the start of reel rotation is performed.

  After the process of S8 or when S7 is No, the main CPU 31 requests the start of rotation of all reels (S9). By the process of S9, the rotation start process and the acceleration control process of the three reels 3L, 3C, 3R are performed.

  Next, the main CPU 31 performs a constant speed waiting process for reel rotation (S10). In this process, the main CPU 31 stands by until the rotational speed of each reel reaches a predetermined rotational speed.

  Next, the main CPU 31 performs a reel stop control process (S11). In this process, the main CPU 31 stops the rotation of the corresponding reel based on a stop signal or the like transmitted from the stop switch 20S by the stop operation of the player. Details of the reel stop control process will be described later with reference to FIG. 73 described later.

  Next, the main CPU 31 performs a display combination search process (S12). In this process, the main CPU 31 determines the display combination and the number of payouts based on the combination of symbols displayed on the active line when the rotation of all reels is stopped. The details of the display combination search process will be described later with reference to FIG. 74 described later.

  Next, the main CPU 31 performs RT control processing (S13). In this process, the main CPU 31 manages the RT gaming state. Details of the RT control process will be described later with reference to FIG. 75 described later.

  Next, the main CPU 31 transmits display command data to the sub-control circuit 70 (S14). The display command includes various types of information such as display combination information indicating a display combination and payout number information indicating a payout number.

  Next, the main CPU 31 performs medal payout processing (S15). Specifically, the main CPU 31 controls driving of the hopper 40 by the hopper driving circuit 41 to pay out medals based on information on the number of payouts in the payout mode, and based on information on the payout number in the credit mode. To update the value of a credit counter (not shown).

  Next, the main CPU 31 determines whether or not a bonus is being operated (S16). Specifically, the main CPU 31 determines whether the gaming state is any one of the BB1 gaming state to the BB4 gaming state and the SB gaming state.

  When the main CPU 31 determines in S16 that the bonus operation is not being performed (when S16 is No), the main CPU 31 performs a process of S18 described later. On the other hand, when it is determined in S16 that the main CPU 31 is operating the bonus (when S16 is Yes), the main CPU 31 performs a bonus end check process (S17). In this process, the main CPU 31 checks whether or not to end the operation of the bonus game with reference to various counters for managing the end timing of the bonus game. The details of the bonus end check process will be described later with reference to FIG.

  After the process of S17 or when S16 is No, the main CPU 31 performs a bonus operation check process (S18). In this process, the main CPU 31 checks whether or not to start the operation of the bonus game and whether or not to replay (replay). The details of the bonus operation check process will be described later with reference to FIG. 77 described later. When the bonus operation check process ends, the main CPU 31 returns the process to S1, and repeats the processes after S1.

  In the pachi-slot 1 of the present embodiment, the main CPU 31 executes the series of processes from S1 to S18 described above as processes in one game (one game), and executes the process in the next game when the process in S18 is completed. The process is returned to the process of S1.

[Bonus activation monitoring process]
Next, with reference to FIG. 70, the bonus operation monitoring process performed in S2 in the flowchart of the reset interrupt process (see FIG. 69) will be described. FIG. 70 is a flowchart showing the procedure of the bonus operation monitoring process in the present embodiment.

  First, the main CPU 31 determines whether or not the gaming state is the BB gaming state (any of BB1 gaming state to BB4 gaming state) (S21). In this process, the main CPU 31 refers to the gaming state flag storage area (see FIG. 46) to grasp the current gaming state.

  In S21, when the main CPU 31 determines that the gaming state is not the BB gaming state (when S21 is No), the main CPU 31 ends the bonus operation monitoring process, and resets the process (see FIG. 69). Move to S3. On the other hand, when the main CPU 31 determines in S21 that the gaming state is the BB gaming state (when S21 is Yes), the main CPU 31 is in the RB gaming state (RB1 gaming state or RB2 gaming state). It is determined whether or not there is (S22).

  In S22, when the main CPU 31 determines that the gaming state is the RB gaming state (when S22 is Yes), the main CPU 31 ends the bonus operation monitoring process, and resets the process (see FIG. 69). ) To S3. On the other hand, when the main CPU 31 determines in S22 that the gaming state is not the RB gaming state (when S22 is No), the main CPU 31 corresponds to the type of BB based on the bonus operating time table (see FIG. 31). RB operation processing is performed (S23).

  In the process of S23, when the gaming state is any of the BB1 gaming state to the BB3 gaming state, the main CPU 31 operates the bonus game “RB1”, and when the gaming state is the BB4 gaming state, The main CPU 31 operates the bonus game “RB2”. After the process of S23, the main CPU 31 ends the bonus operation monitoring process, and moves the process to S3 of the reset interrupt process (see FIG. 69).

[Internal lottery processing]
Next, with reference to FIGS. 71 and 72, the internal lottery process performed in S5 in the flowchart of the reset interrupt process (see FIG. 69) will be described. 71 and 72 are flowcharts showing the procedure of the internal lottery process in the present embodiment.

  First, the main CPU 31 determines an internal lottery table and the number of lotteries corresponding to the gaming state (S31). Specifically, the main CPU 31 refers to the gaming state flag storage area (see FIG. 46), grasps the current gaming state, and sets the current gaming state based on the internal lottery table determination table (see FIG. 34). The type of the corresponding internal lottery table and the number of lotteries are determined.

  Next, the main CPU 31 obtains a random value stored in the random value storage area, and sets the random value as a winning / non-winning determination random value (S32). Then, the main CPU 31 sets “1” as the initial value of the winning number (S33).

  Next, the main CPU 31 refers to the internal lottery table (see FIGS. 35 to 37) and acquires a lottery value corresponding to the winning number (S34). Then, the main CPU 31 subtracts the lottery value from the determination random number value, and sets the subtraction result as the determination random number value (S35). Specifically, the main CPU 31 subtracts the lottery value acquired in the process of S34 from the random number value for determination stored in the random number value storage area for determination (not shown), and uses the subtraction result (subtracted value) for determination. The determination random number value stored in the random value storage area is updated.

  Next, the main CPU 31 determines whether or not a digit has occurred in the subtraction process of S35, that is, whether or not the subtraction result has become a negative value (S36).

  In S36, when the main CPU 31 determines that no digit is generated (the calculation result is 0 or more) (when S36 is No), the main CPU 31 decrements the value of the number of lotteries by “1”. “1” is added to the value of the number (S37). Next, the main CPU 31 determines whether or not the number of lotteries is “0” (S38).

  When the main CPU 31 determines in S38 that the number of lotteries is not “0” (when S38 is No), the main CPU 31 returns the process to S34 and repeats the processes after S34. The main CPU 31 repeats the series of processes from S34 to S38 until the number of lotteries becomes “0” or a digit is generated.

  On the other hand, when the main CPU 31 determines that the number of lotteries is “0” in S38 (when S38 is Yes), the main CPU 31 sets the small data / replay data pointer and the bonus data pointer to “ “0” is set (S39). Then, after the process of S39, the main CPU 31 performs the process of S41 described later.

  Here, returning to the processing of S36 again, in S36, when the main CPU 31 determines that a digit has occurred (the calculation result is less than 0) (when S36 is Yes), the main CPU 31 determines the winning number. Based on this, a small role / replay data pointer and a bonus data pointer are acquired (S40).

  Then, after the processing of S39 or S40, the main CPU 31 refers to the small winning combination / replay internal winning combination determining table (see FIG. 39), and acquires information of the internal winning combination based on the small winning combination / replay data pointer. (S41). Next, the main CPU 31 updates the internal winning combination storing area (see FIG. 43) based on the information of the internal winning combination acquired in S41 (S42).

  Next, the main CPU 31 determines whether or not the data stored in the carryover combination storage area (see FIG. 45) is “00000000” (S43).

  When the main CPU 31 determines in S43 that the data stored in the carryover combination storage area is not “00000000” (when S43 is No), the main CPU 31 performs the process of S50 described later. On the other hand, when the main CPU 31 determines in S43 that the data stored in the carryover combination storage area is “00000000” (when S43 is Yes), the main CPU 31 determines whether the bonus internal winning combination determination table ( Referring to FIG. 38), information on the internal winning combination is acquired based on the bonus data pointer (S44).

  Next, after the processing of S44, the main CPU 31 determines whether or not “SB” is an internal winning combination (S45).

  In S45, when the main CPU 31 determines that “SB” is an internal winning combination (when S45 is Yes), the main CPU 31 determines that the internal winning combination storing area (see FIG. 43) is based on the information of “SB”. ) Is updated (S46). Then, after the process of S46, the main CPU 31 performs a process of S50 described later. On the other hand, when the main CPU 31 determines in S45 that “SB” is not an internal winning combination (when S45 is No), the main CPU 31 determines whether or not “BB” is an internal winning combination ( S47).

  In S47, when the main CPU 31 determines that “BB” is not an internal winning combination (when S47 is No), the main CPU 31 performs a process of S50 described later. On the other hand, in S47, when the main CPU 31 determines that “BB” is an internal winning combination (when S47 is Yes), the main CPU 31 determines that the carryover combination storage area (FIG. 45) is based on the information of “BB”. Reference) is updated (S48). After the process of S48, the main CPU 31 turns on the RT4 gaming state flag (S49).

  After the processing of S46 or S49, or when S43 or S47 is No, the main CPU 31 performs a logical OR operation between the data in the carryover combination storage area and the data in the internal winning combination storage area 1, and the calculation result is internally stored. Store in the winning combination storage area 1 (S50). Next, the main CPU 31 determines whether or not the gaming state is the RB2 gaming state (S51).

  In S51, when the main CPU 31 determines that the gaming state is not the RB2 gaming state (when S51 is No), the main CPU 31 ends the internal lottery process, and resets the process (see FIG. 69). Move to S6. On the other hand, when the main CPU 31 determines in S51 that the gaming state is the RB2 gaming state (when S51 is Yes), the main CPU 31 performs a lock lottery with a probability of 1/64 (S52). Then, the main CPU 31 determines whether or not a lock lottery has been won (S53).

  When the main CPU 31 determines in S53 that it has not won the lock lottery (when S53 is No), the main CPU 31 ends the internal lottery process and the process is reset interrupt process (see FIG. 69) S6. Move to. On the other hand, when it is determined in S53 that the main CPU 31 has won the lock lottery (when S53 is Yes), the main CPU 31 turns on the lock flag (S54). Then, after the process of S54, the main CPU 31 ends the internal lottery process and moves the process to S6 of the reset interrupt process (see FIG. 69).

  As described above, in the present embodiment, the main CPU 31 performs lottery of an internal winning combination by repeatedly executing the processes of S34 to S38. Specifically, the main CPU 31 sequentially subtracts the lottery values specified for each winning number in the internal lottery table from the extracted random number values (or updated determination random number values), and a digit is generated by this subtraction process. In such a case, a small combination / replay data pointer and bonus data pointer corresponding to the winning number at that time are acquired, and an internal winning combination is determined based on each acquired data pointer and the internal winning combination determination table. decide.

  In this embodiment, when the gaming state is the RB2 gaming state, a lock lottery is performed with a probability of 1/64 in S52, but during normal gaming (general gaming state, RT1 gaming state to RT3 gaming state) ) May be configured to perform lock lottery. Further, in the lock lottery, when a specific small combination (for example, a small combination with a small combination / replay data pointer of “18” to “22”) or a bonus (“BB1” to “BB4”) is won internally. A lottery value (winning probability) may be set so that the winning probability is high.

[Reel stop control process]
Next, with reference to FIG. 73, the reel stop control process performed in S11 in the flowchart of the reset interrupt process (see FIG. 69) will be described. FIG. 73 is a flowchart showing the reel stop control process in the present embodiment.

  First, the main CPU 31 sets “3” in the stop button non-operating counter (S61). The stop button non-operating counter is a counter for managing the number of stop buttons whose stop operation has not been detected. Next, the main CPU 31 obtains a stop table (see FIG. 40) corresponding to the internal winning combination (data pointer) (S62).

  Next, the main CPU 31 determines whether or not a valid stop button has been pressed (S63). An effective stop button is a stop button that has not been stopped.

  When the main CPU 31 determines in S63 that the effective stop button has not been pressed (in the case where S63 is No), the main CPU 31 repeats the process of S63 and the effective stop button is pressed. Wait until. On the other hand, when the main CPU 31 determines in S63 that a valid stop button has been pressed (in the case where S63 is Yes), the main CPU 31 invalidates the operation of the corresponding stop button (S64).

  Next, the main CPU 31 reselects a stop table corresponding to the operation stop button (stop order) (S65). Next, the main CPU 31 sets “5” as the number of checks (S66).

  Next, the main CPU 31 refers to the pull-in priority table (see FIGS. 41 and 42) and based on the internal winning combination, the main CPU 31 has the highest priority within the range of the number of checks from the symbol position corresponding to the symbol counter value. A high symbol position is searched (S67).

  Next, the main CPU 31 determines the number of sliding pieces based on the stop table, the symbol position corresponding to the value of the symbol counter, and the search result, and sets the planned stop position of the reel (S68). Next, the main CPU 31 transmits a reel stop command to the sub-control circuit 70 (S69). The reel stop command includes information such as the type information of the stopped reel, stop start position information indicating the stop start position, and slip piece number information indicating the number of slide pieces.

  Next, the main CPU 31 refers to the symbol arrangement table (see FIG. 29), acquires the symbol code based on the stop reel, the planned stop position, and the gaming state, and stores the symbol code information in the symbol storage area (FIGS. 47 and 48) (S70). Next, the main CPU 31 determines whether or not there is a stop button whose operation is valid (S71).

  In S71, when the main CPU 31 determines that there is a stop button whose operation is valid (when S71 is Yes), the main CPU 31 returns the process to S63 and repeats the processes after S63. The processing after S63 is repeated until the main CPU 31 has no stop button for which the operation is effective. In S71, when the main CPU 31 determines that there is no stop button for which the operation is effective (when S71 is No), the main CPU 31 ends the reel stop control process, and resets the process (see FIG. 69).

[Indicator search process]
Next, with reference to FIG. 74, the display combination search process performed in S12 in the flowchart of the reset interrupt process (see FIG. 69) will be described. FIG. 74 is a flowchart showing the procedure of the display combination search process in the present embodiment.

  First, the main CPU 31 clears the data stored in the display combination storage area (see FIG. 44) (S81).

  Next, the main CPU 31 designates the head address of the symbol storage area (see FIGS. 47 and 48) (S82). Specifically, the main CPU 31 designates the address corresponding to the center line as the head address when the gaming state is a gaming state other than the RB gaming state, and RB when the gaming state is the RB gaming state. Specify the address corresponding to the medium special line as the start address.

  Next, the main CPU 31 designates the head address of the symbol combination table (see FIG. 30) (S83). Specifically, the main CPU 31 designates the address corresponding to the column “BB1” in the symbol combination table as the head address.

  Next, the main CPU 31 compares the symbol combination specified in the symbol combination table with the symbol combination corresponding to the data stored in the symbol storage area (S84). Then, the main CPU 31 determines whether or not both match as a result of the comparison processing (S85).

  When the main CPU 31 determines in S85 that the two do not match (when S85 is No), the main CPU 31 performs the process of S89 described later. On the other hand, when the main CPU 31 determines that the two match in S85 (in the case of Yes determination in S85), the main CPU 31 refers to the symbol combination table (see FIG. 30) and displays the storage area type and the display combination. The indicated data is acquired (S86).

  After the processing of S86, the main CPU 31 performs a logical OR operation between the data in the display combination storage area corresponding to the data indicating the storage area type acquired in S86 and the data indicating the display combination acquired in S86, and the calculation result Is stored in the display combination storing area (S87). Next, the main CPU 31 refers to the symbol combination table, acquires payout number data, and adds the acquired payout number value to the payout number counter (S88).

  After the processing of S88, or when S85 is No, the main CPU 31 designates an address corresponding to the next display combination defined in the symbol combination table (S89). That is, in this process, the display combination address in the symbol combination table to be compared (searched) in the comparison process in S84 is updated. Next, the main CPU 31 determines whether or not the data stored at the address in the symbol combination table designated in the process of S89 is an “end code” (S90).

  In S90, when the main CPU 31 determines that the data stored at the address specified in the process of S89 is not an “end code” (when S90 is No), the main CPU 31 returns the process to S84. , S84 and subsequent steps are repeated. On the other hand, when the main CPU 31 determines in S90 that the data stored at the address specified in the processing of S89 is an “end code” (when S90 is Yes), the main CPU 31 It is determined whether or not a search has been performed for a line, that is, whether or not the processing of S84 to S90 has been performed for all active lines (S91).

  When the main CPU 31 determines in S91 that all the effective lines have not been searched (when S91 is No), the main CPU 31 designates an address corresponding to the next effective line stored in the symbol storage area. (S92). That is, in this process, the address of the effective line that is the display target search target is updated. Next, the main CPU 31 returns the process to S83 and repeats the processes after S83. Note that the processes of S83 to S92 are repeated until the display combination search process is completed for all the active lines.

  In S91, when the main CPU 31 determines that the search has been performed for all active lines (when S91 is Yes), the main CPU 31 ends the display combination search process and resets the process (see FIG. 69).

[RT control processing]
Next, the RT control process performed in S13 in the flowchart of the reset interrupt process (see FIG. 69) will be described with reference to FIG. FIG. 75 is a flowchart showing the procedure of RT control processing in the present embodiment.

  First, the main CPU 31 determines whether “BB” is being carried over (whether the gaming state is the RT4 gaming state) (S101).

  In S101, when the main CPU 31 determines that “BB” is being carried over (in the case where S101 is Yes), the main CPU 31 ends the RT control process and resets the process (see FIG. 69). Move to S14. On the other hand, when the main CPU 31 determines that “BB” is not being carried over in S101 (when S101 is No), the main CPU 31 determines whether “BB” is in operation (S102). .

  In S102, when the main CPU 31 determines that “BB” is in operation (when S102 is Yes), the main CPU 31 ends the RT control process and resets the process (see FIG. 69). Move to S14. On the other hand, when the main CPU 31 determines that “BB” is not in operation in S102 (when S102 is No), the main CPU 31 refers to the RT transition table (see FIG. 33) and stops on the active line. The gaming state flag is updated based on the displayed symbol combination (S103). In this process, the game state flag is updated when the symbol combination (display combination) that is stopped and displayed on the active line is a transition combination that triggers the transition of the RT state, but with other symbol combinations The game state flag is not updated.

  After the process of S103, the main CPU 31 ends the RT control process, and moves the process to S14 of the reset interrupt process (see FIG. 69).

[Bonus end check process]
Next, with reference to FIG. 76, the bonus end check process performed in S17 in the flowchart of the reset interrupt process (see FIG. 69) will be described. FIG. 76 is a flowchart showing the procedure of bonus end check processing in the present embodiment.

  First, the main CPU 31 determines whether or not “BB” is in operation (S111).

  In S111, when the main CPU 31 determines that “BB” is not in operation (when S111 is No), the main CPU 31 turns off the SB gaming state flag (S112). After the process of S112, the main CPU 31 ends the bonus end check process, and moves the process to S18 of the reset interrupt process (see FIG. 69).

  On the other hand, when the main CPU 31 determines that “BB” is operating in S111 (when S111 is Yes), the main CPU 31 determines whether or not the value of the bonus end number counter is “0”. (S113).

  When the main CPU 31 determines in S113 that the value of the bonus end number counter is “0” (in the case where S113 is Yes), the main CPU 31 performs a bonus end time process (S114). Specifically, the main CPU 31 turns off the BB gaming state flag and the RB gaming state flag that are on. Next, the main CPU 31 transmits a bonus end command to the sub-control circuit 70 (S115). After the process of S115, the main CPU 31 ends the bonus end check process, and moves the process to S18 of the reset interrupt process (see FIG. 69).

  On the other hand, when the main CPU 31 determines in S113 that the value of the bonus end number counter is not “0” (when S113 is No), the main CPU 31 subtracts “1” from the value of the possible game number counter. (S116). Next, the main CPU 31 determines whether or not the display combination is a small combination (S117).

  In S117, when the main CPU 31 determines that the display combination is not a small combination (when S117 is No), the main CPU 31 performs a process of S119 described later. On the other hand, when the main CPU 31 determines in S117 that the display combination is a small combination (when S117 is Yes), the main CPU 31 subtracts “1” from the value of the winning possible number counter (S118).

  After the processing of S118, or when S117 is No, the main CPU 31 determines whether or not the value of the winning possible number counter or the value of the possible gaming number counter is “0” (S119).

  When the main CPU 31 determines in S119 that the value of the winning number counter or the value of the number of possible games counter is not “0” (when S119 is No), the main CPU 31 ends the bonus end check process, and the process Is transferred to S18 of the reset interrupt process (see FIG. 69). On the other hand, when the main CPU 31 determines in S119 that the value of the winning number counter or the value of the possible game number counter is “0” (when S119 is Yes), the main CPU 31 performs processing at the end of RB. (S120). Specifically, the main CPU 31 performs processing such as turning on an RB gaming state flag that is on.

  After the process of S120, the main CPU 31 ends the bonus end check process, and moves the process to S18 of the reset interrupt process (see FIG. 69).

[Bonus activation check process]
Next, with reference to FIG. 77, the bonus operation check process performed in S18 in the flowchart of the reset interrupt process (see FIG. 69) will be described. FIG. 77 is a flowchart showing the procedure of the bonus operation check process in the present embodiment.

  First, the main CPU 31 determines whether or not the display combination is “BB” (any one of “BB1” to “BB4”) (S131).

  In S131, when the main CPU 31 determines that the display combination is “BB” (in the case where S131 is Yes), the main CPU 31 performs a bonus operation process (S132). In this process, the main CPU 31 refers to the bonus operating time table (see FIG. 31) and turns on the gaming state flag corresponding to the gaming state to be activated (any of the BB1 gaming state to the BB4 gaming state). The value of the bonus end number counter in the gaming state to be operated specified in the table is set in the bonus end number counter. Next, the main CPU 31 turns off the RT4 gaming state flag and clears the data in the carryover combination storage area (S133). After the process of S133, the main CPU 31 performs a process of S136 described later.

  On the other hand, when the main CPU 31 determines in S131 that the display combination is not “BB” (in the case where S131 is No), the main CPU 31 determines whether or not the display combination is “SB” (S134). .

  When the main CPU 31 determines in S134 that the display combination is “SB” (in the case where S134 is Yes), the main CPU 31 performs a bonus operation process (S135). In this process, the main CPU 31 refers to the bonus operating time table (see FIG. 31) and turns on the SB gaming state flag.

  After the processing of S133 or S135, the main CPU 31 transmits a bonus start command to the sub control circuit 70 (S136). The bonus start command includes information indicating the type of bonus to be started. After the process of S136, the main CPU 31 ends the bonus operation check process, and moves the process to S1 of the reset interrupt process (see FIG. 69).

  On the other hand, when the main CPU 31 determines that the display combination is not “SB” in S134 (when S134 is No), the main CPU 31 determines whether or not the display combination is a combination related to “replay”. (S137).

  When the main CPU 31 determines in S137 that the display combination is not a “replay” combination (in the case where S137 is No), the main CPU 31 ends the bonus operation check process, and resets the process (see FIG. 69)). On the other hand, when the main CPU 31 determines in S137 that the display combination is a combination related to “replay” (when S137 is Yes), the main CPU 31 copies the value of the insertion number counter to the automatic insertion number counter. (S138). When a value is set in the automatic insertion number counter, the number of medals corresponding to the value is automatically inserted in the medal acceptance / start check process in S3 of the next game (the player's medal is not reduced). .

  After the process of S138, the main CPU 31 ends the bonus operation check process and moves the process to S1 of the reset interrupt process (see FIG. 69).

[Interrupt processing under the control of the main CPU (1.1173 msec)]
Next, with reference to FIG. 78, an interrupt process by the control of the main CPU 31 will be described. FIG. 78 is a flowchart showing the procedure of interrupt processing under the control of the main CPU 31 in the present embodiment. Note that the interrupt process under the control of the main CPU 31 is an interrupt process performed at predetermined intervals (1.1173 msec in the present embodiment).

  First, the main CPU 31 interrupts the program being executed before calling the interrupt process under the control of the main CPU 31, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the main RAM 33. (S141). In this process, when the interrupt process under the control of the main CPU 31 is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the point of interruption. To be done.

  Next, the main CPU 31 performs an input port check process (S142). Specifically, the main CPU 31 checks input signals from various switches such as the MAX bet switch 23S.

  Next, the main CPU 31 performs a reel control process (S143). Specifically, when there is a reel rotation start request in the reset interrupt process (see FIG. 69), the main CPU 31 starts rotation of the three reels 3L, 3C, and 3R in the process of S143. Control to rotate at a constant speed. If the number of sliding symbols is determined in the reel stop control process (see FIG. 73) and the expected stop position of the reel is determined, the main CPU 31 determines the value of the symbol counter of the corresponding reel in the process of S143. When the value becomes the same as the value indicating the planned stop position, control is performed to stop the reel. For example, when the value indicating the scheduled stop position is “4”, the main CPU 31 controls to stop the corresponding reel when the symbol counter value becomes “4” in the process of S143. I do.

  Next, the main CPU 31 performs a lamp driving process (S144). Next, the main CPU 31 refers to the information saved in the predetermined area of the main RAM 33 in the process of S141, and restores the register (S145). When the process of S145 ends, the main CPU 31 ends the interrupt process and continuously executes the program interrupted by the occurrence of the interrupt process.

<Explanation of operation of various effects by sub-control circuit>
Next, with reference to FIGS. 79 to 100, the contents of processes (tasks) related to various effects executed by the sub CPU 71 of the sub control circuit 70 using a program will be described. Various tables necessary for various processes of the sub CPU 71 described below are stored in the sub ROM 72, and various control flags, various control counters, various storage areas and the like are provided in the sub RAM 73 and the like.

[Production registration process performed by sub CPU]
First, the effect registration process performed by the sub CPU 71 will be described with reference to FIG. FIG. 79 is a flowchart showing the procedure of the effect registration process in the present embodiment.

  First, the sub CPU 71 sets a period of 4 msec for the effect registration process (S151). Next, the sub CPU 71 extracts a message from the message queue (S152). Next, the sub CPU 71 determines whether or not there is a message in the message queue (S153).

  In S153, when the sub CPU 71 determines that there is no message in the message queue (when S153 is No), the sub CPU 71 performs the process of S157 described later. On the other hand, when the sub CPU 71 determines in S153 that there is a message in the message queue (if S153 is Yes), the sub CPU 71 copies the game information from the message (S154). In this process, for example, various data such as an internal winning combination, a type of reel that has stopped rotating, a display combination, and a game state flag specified by parameters are copied to a predetermined storage area provided in the sub-RAM 73.

  Next, the sub CPU 71 performs effect content determination processing (S155). In this processing, the sub CPU 71 performs processing such as determining the content of effects and registering effect data according to the type of the received command. Details of the effect content determination process will be described later with reference to FIG.

  Next, the sub CPU 71 performs a backup creation process (S156). Specifically, the sub CPU 71 creates backup data from the sub RAM 73 to the SRAM 74. Details of the backup creation process will be described later with reference to FIG. 113 described later.

  After the processing of S156, or when S153 is No, the sub CPU 71 registers animation data (S157). Specifically, the sub CPU 71 registers animation data based on the effect data registered in the effect content determination process. By this processing, an image is displayed on the liquid crystal display device 10. That is, the sub CPU 71 transmits an image display command to the GPU 75 based on the effect data determined in the effect content determination process.

  The GPU 75 selects appropriate image data from the image data expanded in the VRAM 76 based on the received image display command, determines the display position and size of the image data, and stores the image data in the VRAM 76. Is stored in one frame buffer area (write image data area or display image data area). Further, the GPU 75 performs a bank switching process for switching the display image data area and the write image data area every predetermined cycle (1/30 second). In the bank switching process, the GPU 75 outputs the image data stored in the write image data area to the liquid crystal display device 10, replaces the display image data area with the write image data area, and then displays it. Write image data.

  Next, the sub CPU 71 registers sound data (S158). Specifically, the sub CPU 71 registers sound data based on the effect data determined in the effect content determination process. By this process, sound is output from the speakers 17L and 17R.

  Next, the sub CPU 71 registers LED data (S159). Specifically, the sub CPU 71 registers LED data based on the effect data determined in the effect content determination process. By this processing, the various LEDs 101 to 103 and 111 to 114 provided in the sub device group 100 are turned on or off as appropriate according to the contents of the effects.

  Next, the sub CPU 71 waits until the 4 msec period set in S151 ends (S160). After the process of S160, the sub CPU 71 returns the process to S152 and repeats the processes after S152.

[Production content decision processing]
Next, with reference to FIG. 80, the effect content determination process performed in S155 in the flowchart of the effect registration process (see FIG. 79) will be described. FIG. 80 is a flowchart showing the procedure of effect content determination processing in the present embodiment.

  First, the sub CPU 71 determines whether or not a start command has been received (S171).

  In S171, when it is determined that the sub CPU 71 has received the start command (when S171 is Yes), the sub CPU 71 performs a start command reception process (S172). Details of the start command reception process will be described later with reference to FIGS. 81 and 82 described later. Next, the sub CPU 71 registers effect data at the start of the game (S173). After the process of S173, the sub CPU 71 ends the effect content determination process, and moves the process to S156 of the effect registration process (see FIG. 79).

  On the other hand, when it is determined in S171 that the sub CPU 71 has not received the start command (S171 is No), the sub CPU 71 determines whether or not a reel stop command has been received (S174).

  When it is determined in S174 that the sub CPU 71 has received the reel stop command (when S174 is Yes), the sub CPU 71 performs a billy get challenge determination process (S175). The details of the billy get challenge determination process will be described later with reference to FIG. 97 described later. Next, the sub CPU 71 registers effect data at the time of reel stop according to the type of the operation stop button or the like (S176). Then, after the process of S176, the sub CPU 71 ends the effect content determination process and moves the process to S156 of the effect registration process (see FIG. 79).

  On the other hand, when it is determined in S174 that the sub CPU 71 has not received the reel stop command (when S174 is No), the sub CPU 71 determines whether or not a display command has been received (S177).

  When it is determined in S177 that the sub CPU 71 has received the display command (in the case where S177 is Yes), the sub CPU 71 performs a display command reception process (S178). Details of the display command reception process will be described later with reference to FIG. 99 described later. After the process of S178, the sub CPU 71 ends the effect content determination process, and moves the process to S156 of the effect registration process (see FIG. 79).

  On the other hand, when it is determined in S177 that the sub CPU 71 has not received the display command (when S177 is No), the sub CPU 71 determines whether or not a BET command has been received (S179).

  When it is determined in S179 that the sub CPU 71 has received the BET command (S179 is YES), the sub CPU 71 registers the effect data for the BET according to the number of inserted sheets (S180). Then, after the process of S180, the sub CPU 71 ends the effect content determination process, and moves the process to S156 of the effect registration process (see FIG. 79).

  On the other hand, when it is determined in S179 that the sub CPU 71 has not received the BET command (S179 is No), the sub CPU 71 determines whether or not a bonus start command has been received (S181).

  When it is determined in S181 that the sub CPU 71 has received the bonus start command (when S181 is Yes), the sub CPU 71 registers bonus start effect data (S182). After the process of S182, the sub CPU 71 ends the effect content determination process, and moves the process to S156 of the effect registration process (see FIG. 79).

  On the other hand, when it is determined in S181 that the sub CPU 71 has not received the bonus start command (when S181 is No), the sub CPU 71 determines whether or not a bonus end command has been received (S183).

  When it is determined in S183 that the sub CPU 71 has not received the bonus end command (when S183 is No), the sub CPU 71 ends the effect content determination process, and the process is S156 of the effect registration process (see FIG. 79). Move to.

  On the other hand, when it is determined in S183 that the sub CPU 71 has received the bonus end command (when S183 is Yes), the sub CPU 71 performs a bonus end command reception process (S184). The details of the bonus end command reception process will be described later with reference to FIG. Next, the sub CPU 71 registers bonus end effect data (S185). Then, after the process of S185, the sub CPU 71 ends the effect content determination process and moves the process to S156 of the effect registration process (see FIG. 79).

[Start command reception processing]
Next, with reference to FIG. 81 and FIG. 82, the start command reception process performed in S172 in the flowchart of the effect content determination process (see FIG. 80) will be described. FIG. 81 and FIG. 82 are flowcharts showing the procedure of start command reception processing in this embodiment.

  First, the sub CPU 71 determines whether “BB” (any one of “BB1” to “BB4”) is operating (S191).

  In S191, when the sub CPU 71 determines that “BB” is in operation (in the case where S191 is Yes), the sub CPU 71 performs processing during BB (S192). Details of the BB processing will be described later with reference to FIG. 83 described later. Then, after the process of S192, the sub CPU 71 performs the process of S210 described later.

  On the other hand, when the sub CPU 71 determines that “BB” is not operating in S191 (when S191 is No), the sub CPU 71 determines whether or not the BB carryover flag is on (S193). ). Note that the BB carryover flag is determined from the unit game next to the unit game in which “BB” (any one of “BB1” to “BB4”) is internally won as the display combination. During the period up to the unit game (period in which “BB” is in the carryover state), the game is turned on.

  In S193, when the sub CPU 71 determines that the BB carryover flag is on (when S193 is Yes), the sub CPU 71 performs the process of S210 described later.

  On the other hand, in S193, when the sub CPU 71 determines that the BB carryover flag is not on (when S193 is No), the sub CPU 71 performs the navigation game state 3 addition game number and lottery mode lottery processing (S194). ). Details of the number of navigation game state 3 addition games and lottery mode lottery processing will be described later with reference to FIG. 87 described later.

  Then, after the processing of S194, the sub CPU 71 refers to the navigation mode transition lottery table A (see FIG. 49), and performs the navigation mode transition lottery based on the current navigation mode, data pointer, and the like (S195). Next, the sub CPU 71 determines whether or not the current unit game is a unit game won in “BB” (“BB1” to “BB4”) (whether or not it is a BB win game) (S196).

  In S196, when it is determined that the sub CPU 71 is not a BB win game (when S196 is No), the sub CPU 71 performs a process of S198 described later. On the other hand, when it is determined in S196 that the sub CPU 71 is a BB winning game (when S196 is Yes), the sub CPU 71 refers to the navigation mode transition lottery table B (see FIG. 50) to determine the current navigation mode. Then, the navigation mode transition lottery is performed based on the bonus data pointer and the presence or absence of the effect game (S197).

  After the processing of S197, or when S196 is No, the sub CPU 71 determines whether the navigation mode has shifted from “0” to “1” to “4” as a result of the navigation mode transition lottery in S195 or S197. It is determined whether or not (S198).

  In S198, when the sub CPU 71 determines that the navigation mode has shifted from “0” to any one of “1” to “4” (when S198 is Yes), the sub CPU 71 performs the ART initial hit processing. Perform (S199). Details of the ART initial hit processing will be described later with reference to FIG. 88 described later. Next, the sub CPU 71 determines whether or not the current unit game is a BB winning game (S200).

  In S200, when it is determined that the sub CPU 71 is a BB winning game (when S200 is Yes), the sub CPU 71 performs a process of S210 described later. On the other hand, when it is determined in S200 that the sub CPU 71 is not the BB winning game (when S200 is No), the sub CPU 71 refers to the navigation game state transition standby number lottery table (see FIG. 52) and shifts to the navigation game state. The lottery of the waiting number is performed, and the winning number of waiting for the navigation game state transition is set in the navigation game state transition standby counter (S201). Then, after the process of S201, the sub CPU 71 performs a process of S210 described later.

  Here, returning to the processing of S198 again, in S198, when the sub CPU 71 determines that the navigation mode has not shifted from “0” to “1” to “4” (S198 is No determination). In this case, the sub CPU 71 determines whether or not the value of the navigation game state transition standby counter is “1” or more (S202).

  In S202, when the sub CPU 71 determines that the value of the navigation game state transition standby counter is “1” or more (in the case where S202 is Yes), the sub CPU 71 performs a navigation game state transition process during the standby state ( S203). The details of the waiting state navigation game state transition process will be described later with reference to FIG. 89 described later. Then, after the process of S203, the sub CPU 71 performs a process of S210 described later.

  On the other hand, when the sub CPU 71 determines in S202 that the value of the navigation game state transition standby counter is not equal to or greater than “1” (when S202 is No), the sub CPU 71 indicates that the navigation game state is the navigation game state 1. Whether or not (S204).

  In S204, when the sub CPU 71 determines that the navigation game state is the navigation game state 1 (when S204 is Yes), the sub CPU 71 performs a navigation game state transition process during the navigation game state 1 (S205). Details of the navigation game state transition process during the navigation game state 1 will be described later with reference to FIG. 90 described later. Then, after the processing of S205, the sub CPU 71 performs processing of S210 described later.

  On the other hand, in S204, when the sub CPU 71 determines that the navigation game state is not the navigation game state 1 (when S204 is No), the sub CPU 71 determines whether the navigation game state is the navigation game state 2 or not. (S206).

  In S206, when the sub CPU 71 determines that the navigation game state is the navigation game state 2 (when S206 is Yes), the sub CPU 71 performs a navigation game state transition process during the navigation game state 2 (S207). The details of the navigation game state transition process during the navigation game state 2 will be described later with reference to FIGS. 91 and 92 described later. Then, after the process of S207, the sub CPU 71 performs the process of S210 described later.

  On the other hand, when the sub CPU 71 determines that the navigation game state is not the navigation game state 2 in S206 (when S206 is No), the sub CPU 71 determines whether the navigation game state is the navigation game state 3 or not. (S208).

  In S208, when the sub CPU 71 determines that the navigation game state is the navigation game state 3 (when S208 is Yes), the sub CPU 71 performs a navigation game state transition process during the navigation game state 3 (S209). The details of the navigation game state transition process during the navigation game state 3 will be described later with reference to FIG. 94 described later. Then, after the processing of S209, the sub CPU 71 performs processing of S210 described later. On the other hand, when the sub CPU 71 determines that the navigation game state is not the navigation game state 3 in S208 (when S208 is No), the sub CPU 71 performs the process of S210 described later.

  After S192, S201, S203, S205, S207, or S209, if S193 or S200 is Yes, or if S208 is No, the sub CPU 71 performs a billy get challenge lottery process (S210). Details of the billy get challenge lottery process will be described later with reference to FIG. 96 described later.

  Next, the sub CPU 71 determines whether or not the navigation game state is one of the navigation game state 1 to the navigation game state 3 and the “push order” is an internal winning combination (S211).

  In S211, when the sub CPU 71 determines that the determination condition of S211 is not satisfied (when S211 is No), the sub CPU 71 ends the process at the time of receiving the start command, and the process is effect content determination process (see FIG. 80). To S173. On the other hand, when it is determined in S211 that the sub CPU 71 satisfies the determination condition of S211 (when S211 is Yes), the sub CPU 71 performs navigation effect data (navigation for establishing a role that is advantageous to the player). The effect data to be performed) is registered (S212). Then, after the process of S212, the sub CPU 71 ends the process at the time of receiving the start command, and moves the process to S173 of the effect content determination process (see FIG. 80).

[BB processing]
Next, with reference to FIG. 83, the BB in-process performed in S192 in the flowchart of the start command reception process (see FIGS. 81 and 82) will be described. FIG. 83 is a flowchart showing the procedure of the BB in-process in this embodiment.

  First, the sub CPU 71 determines whether or not the gaming state is the BB gaming state 4 (S221).

  In S221, when the sub CPU 71 determines that the gaming state is the BB gaming state 4 (when S221 is Yes), the sub CPU 71 performs a lottery process during BB4 (S222). Details of the lottery process during BB4 will be described later with reference to FIG. 84 described later. Then, after the process of S222, the sub CPU 71 ends the BB process, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S221 that the gaming state is not the BB gaming state 4 (when S221 is No), the sub CPU 71 determines whether or not to change the navigation mode based on the data pointer. The navigation mode is updated according to the determination result (S223). Specifically, the small role / replay pointer is “28” to “31” (the stop type is “Don middle tier alignment”, “Don lower tempai”, “Don upper tempai”, “Don middle tempei”) If it is, the sub CPU 71 increases the navigation mode by “1” (however, the upper limit is “4”), otherwise the sub CPU 71 does not change the navigation mode.

  Further, in the process of S223, the navigation mode may be raised in a plurality of stages when a specific condition is satisfied. As specific conditions, for example, “31” is determined from “28” to “31” as the small role / replay pointer, and any of “28” to “31” is selected as the small role / replay pointer. And the combination of “don-matched” symbols on a specific active line is stopped and displayed. Although not shown, the sub CPU 71 registers don-matched effect data when the “don symbol” is aligned in the upper (top line), middle (center line), or lower (bottom line).

  Next, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table C (see FIG. 56), and determines the number of navigation game state 3 addition games based on the current navigation mode and the small role / replay pointer data pointer. A lottery is performed (S224).

  Next, the sub CPU 71 determines whether or not the number of navigation game state 3 addition games of 5 games or more has been won in the lottery process of S224 (S225). When the sub CPU 71 determines in S225 that the number of navigation game state 3 addition games of 5 or more games is not won (the number of won games is 0) (when S225 is No), the sub CPU 71 , The process during BB is terminated, and the process proceeds to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S225 that the number of navigation game state 3 addition games of 5 games or more has been won (when S225 is Yes), the sub CPU 71 determines the navigation game state 3 addition lottery mode lottery table C. Referring to (see FIG. 60), the navigation game state 3 addition lottery mode is lottery based on the current navigation mode and the small role / replay data pointer (S226).

  Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in S224 with the navigation game state 3 addition lottery mode determined in S226, and stores data of the combination in the navigation game state 3 information. Store in an area (not shown) (S227).

  Next, the sub CPU 71 turns on the navigation game state 3 transition flag (S228). The navigation game state 3 transition flag is a flag indicating whether or not information is stored in the navigation game state 3 information storage area (when it is stored, it is turned on). Then, after the process of S228, the sub CPU 71 ends the process during BB, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  In the present embodiment, a maximum of 32 combinations of the number of navigation game state 3 addition games and the navigation game state 3 addition lottery mode can be stored in the navigation game state 3 information storage area. The information stored in the navigation game state 3 information storage area is processed by FIFO (First In, First Out) processing.

  Further, the number of combinations (number of combinations) of the navigation game state 3 addition game number and the navigation game state 3 addition lottery mode stored in the navigation game state 3 information storage area is displayed on the liquid crystal display device 10, and the player Can be grasped. Note that the process of notifying the number of pairs stored in the navigation game state 3 information storage area may be performed only when the navigation game state is the navigation game state 2. In this notification process, the value of the number of sets stored in the navigation game state 3 information storage area itself (that is, “5” for 5 sets) may be notified, or a part of the number of sets is notified. You may do it.

  For example, when the don-match production data described later is registered, or when the billy get challenge success production data described later is registered in the BB4 gaming state, the navigation gaming state 3 is stored in the navigation gaming state 3 information storage area. Since the combination of the number of added games and the navigation game state 3 added lottery mode is always stored, in these cases, only the number of sets for which the effect data is registered is displayed (notified) on the liquid crystal display device 10. It may be. In other words, only the number of pairs for which a confirmed effect (for example, a don-matched effect or a billy get successful effect) that allows the player to recognize the acquisition of the right to move from the navigation game state 2 to the navigation game state 3 is notified. You may do it.

  Further, when the number of rights to shift from the navigation game state 2 to the navigation game state 3 is 1 or more, it is preferable to notify that at least the number of rights is 1 or more. For example, when it is configured to notify only the number of sets for which the above-described finalized effect has been performed, the number of sets stored in the navigation game state 3 information storage area is “5”, and the finalized effect is once. If it is not performed, nothing will be notified. In such a case, at least the number of pairs stored in the navigation game state 3 information storage area is notified that it is “1” or more. Is preferred.

[BB4 lottery processing]
Next, with reference to FIG. 84, the BB4 lottery process performed in S222 in the flowchart for the BB process (see FIG. 83) will be described. FIG. 84 is a flowchart showing the procedure of the BB4 lottery process in the present embodiment.

  First, the sub CPU 71 refers to the billy get challenge occurrence lottery table (see FIG. 65), and determines the current navigation mode, presence / absence of effect game stop (on / off of the lock flag in the main control circuit 60), and billy get. A lottery for generating a billy get challenge is performed based on the challenge success flag (S231). Then, the sub CPU 71 determines whether or not the lottery process of S231 has been won (S232).

  In S232, when the sub CPU 71 determines that the lottery process of S231 has not been won (when S232 is No), the sub CPU 71 ends the BB4 lottery process and ends the BB process. On the other hand, in S232, when the sub CPU 71 determines that the lottery process of S231 has been won (when S232 is Yes), the sub CPU 71 performs a billy get challenge process (S233). Details of the billy get challenge process will be described later with reference to FIG. 86 described later.

  Next, the sub CPU 71 determines whether or not there is an effect game stop (the lock flag is in an on state) (S234). In S234, when the sub CPU 71 determines that there is no stop for the effect game (when S234 is No), the sub CPU 71 ends the BB4 lottery process and the BB process.

  On the other hand, when the sub CPU 71 determines in S234 that there is an effect game stop (when S234 is Yes), the sub CPU 71 registers display panel unit effect data (S235). After the process of S235, the sub CPU 71 ends the BB4 lottery process and also ends the BB process.

  Here, the contents of the display panel unit effect executed when the display panel unit effect data is registered in S235 of the above-described BB4 lottery process will be described with reference to FIG. 85 shows the temporal changes in the luminance of the LEDs 111 to 114 that cause the display panels 110a to 110d (corresponding to “fourth from the back” to “first from the back” in FIG. 85) to disappear, respectively. The time series change pattern of the brightness | luminance shown is shown.

  When the display panel unit effect data is registered in S235, the sub CPU 71 changes the luminance of the LEDs 111 to 114 according to the luminance time-series change pattern shown in FIG. In the time-series pattern of luminance change shown in FIG. 85, it appears to the player that the character is slowly approaching from the back first, and then the display panel 110a on the foremost side with the light extinction period in between. Flashes rapidly. In this embodiment, a player's expectation can be improved by performing such an effect.

[Billy Get Challenge Processing]
Next, with reference to FIG. 86, the billy get challenge process performed in S233 in the flowchart of the lottery process during BB4 (see FIG. 84) will be described. FIG. 86 is a flowchart showing the procedure of the billy get challenge process in the present embodiment.

  First, the sub CPU 71 refers to the billy get challenge correct lottery table (see FIG. 67), and performs the billy get challenge correct lottery based on the occurrence status of the “billy get challenge”, the gaming state, and whether or not there is a game stop for performance. (S241). Next, the sub CPU 71 refers to the lottery table without billy get challenge selection (see FIG. 68), and performs lottery without billy get challenge selection based on the result of the billy get challenge correct lottery performed in S241 (S242). .

  Next, the sub CPU 71 registers the billy get challenge effect described above (S243). With this process, immediately after the player presses the start lever 21, the billy get challenge effect is executed. Then, after the process of S243, the sub CPU 71 ends the billy get challenge process, and moves the process to S234 of the BB4 lottery process (see FIG. 84).

[Number of navigation game state 3 addition games and lottery mode lottery processing]
Next, with reference to FIG. 87, the navigation game state 3 addition game number and lottery mode lottery processing performed in S194 in the flowchart (see FIGS. 81 and 82) of the start command reception process will be described. FIG. 87 is a flowchart showing the procedure of the number of navigation game state 3 addition games and lottery mode lottery processing in the present embodiment.

  First, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table A (see FIG. 54) and adds the navigation game state 3 addition based on the current navigation mode, the small role / replay pointer, the bonus data pointer, and the like. The number of games is lottery (S251).

  Next, the sub CPU 71 determines whether or not the number of navigation game state 3 addition games of 5 games or more has been won by the lottery process of S251 (S252). In S252, when the sub CPU 71 determines that the number of navigation game state 3 addition games of 5 games or more has not been won (when S252 is No), the sub CPU 71 performs a process of S256 described later.

  On the other hand, when the sub CPU 71 determines in S252 that the number of navigation game state 3 addition games of 5 games or more has been won (when S252 is Yes), the sub CPU 71 determines the navigation game state 3 addition lottery mode lottery table A. Referring to FIG. 58, the navigation game state 3 addition lottery mode is lottery based on the current navigation mode (S253). Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in S251 with the navigation game state 3 addition lottery mode determined in S253, and stores data of the combination in the navigation game state 3 information. (S254). Then, the sub CPU 71 turns on the navigation game state 3 transition flag (S255).

  After the processing of S255, or when S252 is No, the sub CPU 71 determines whether or not the current unit game is a unit game in which “BB” (“BB1” to “BB4”) is won (BB winning game or not) (S256). In S256, when the sub CPU 71 determines that the game is not a BB winning game (when S256 is No), the sub CPU 71 ends the number of navigation game state 3 addition games and lottery mode lottery processing, and receives the start command. The process proceeds to S195 of the process (see FIGS. 81 and 82).

  On the other hand, when it is determined in S256 that the sub CPU 71 is a BB winning game (when S256 is Yes), the sub CPU 71 refers to the navigation game state 3 addition game number lottery table B (see FIG. 55), Based on the current navigation mode, bonus data pointer, and presence / absence of effect game stop, the number of navigation game state 3 addition games is determined (S257).

  Next, the sub CPU 71 determines whether or not the number of navigation game state 3 addition games of 5 games or more has been won by the lottery process of S257 (S258). In S258, when the sub CPU 71 determines that the number of navigation game state 3 addition games of 5 games or more has not been won (when S258 is No), the sub CPU 71 determines the number of navigation game state 3 addition games and lottery mode lottery. The process ends, and the process proceeds to S195 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S258 that the number of navigation game state 3 addition games of 5 games or more has been won (when S258 is Yes), the sub CPU 71 determines that the navigation game state 3 addition lottery mode lottery table B Referring to FIG. 59, the navigation game state 3 addition lottery mode is lottery based on the current navigation mode, the bonus data pointer, and the presence / absence of the effect game stop (S259). Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in S257 with the navigation game state 3 addition lottery mode determined in S259, and stores data of the combination in the navigation game state 3 information. (S260).

  Next, the sub CPU 71 turns on the navigation game state 3 transition flag (S261). Then, after the process of S261, the sub CPU 71 ends the number of navigation game state 3 added games and the lottery mode lottery process, and moves the process to S195 of the start command reception process (see FIGS. 81 and 82).

[ART first hit processing]
Next, with reference to FIG. 88, the ART initial hit process performed in S199 in the flowchart of the start command reception process (see FIGS. 81 and 82) will be described. FIG. 88 is a flowchart showing a procedure of ART hitting time processing in the present embodiment.

  First, the sub CPU 71 refers to the navigation set number lottery table (see FIG. 62) and determines the number of navigation sets (S271). Next, the sub CPU 71 sets the number of navigation sets determined in the lottery process of S271 in the navigation set number counter (S272).

  Next, the sub CPU 71 sets “50” to the value of the navigation game number counter (S273). Next, the sub CPU 71 subtracts “1” from the value of the navigation set number counter (S274). After the process of S274, the sub CPU 71 ends the ART initial hit process, and moves the process to S200 of the start command reception process (see FIGS. 81 and 82).

[Navi game state transition process during standby]
Next, with reference to FIG. 89, the standby state navigation game state transition process performed in S203 in the flowchart (see FIGS. 81 and 82) of the start command reception process will be described. FIG. 89 is a flowchart showing the procedure of the waiting state navigation game state transition process in the present embodiment.

  First, the sub CPU 71 determines whether or not the current unit game is a unit game that has won “BB” (“BB1” to “BB4”) during the digestion of the navigation game state transition standby counter (whether or not it is a BB winning game). Is determined (S281).

  When the sub CPU 71 determines in S281 that the navigation game state transition standby counter is not the BB winning game being digested (when S281 is No), the sub CPU 71 decrements the value of the navigation game state transition standby counter by “1”. (S282). Next, the sub CPU 71 determines whether or not the value of the navigation game state transition standby counter has become “0” (S283).

  In S283, when the sub CPU 71 determines that the value of the navigation gaming state transition standby counter is not “0” (when S283 is No), the sub CPU 71 ends the navigation gaming state transition processing in the standby state, Is shifted to S210 of the start command reception process (see FIGS. 81 and 82). On the other hand, in S283, when the sub CPU 71 determines that the value of the navigation gaming state transition standby counter is “0” (when S283 is Yes), the sub CPU 71 determines whether the RT gaming state is the RT3 gaming state. It is determined whether or not (S284).

  In S284, when the sub CPU 71 determines that the RT gaming state is not the RT3 gaming state (when S284 is No), the sub CPU 71 shifts the navigation gaming state from the next unit game to the navigation gaming state 1. Processing is performed (S285). Although the detailed description of this process is omitted, in this process, the sub CPU 71 turns on the navigation game state 1 flag, and if the navigation game state 1 flag is on at the start of the next unit game, The navigation game state is shifted to the navigation game state 1. Then, after the process of S285, the sub CPU 71 ends the navigation game state transition process during the standby state, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, in S284, when the sub CPU 71 determines that the RT gaming state is the RT3 gaming state (when S284 is Yes), the sub CPU 71 navigates from the next unit game to the navigation gaming state 2. Processing for shifting is performed (S286). In this processing, the sub CPU 71 turns on the navigation game state 2 flag, and shifts the navigation game state to the navigation game state 2 if the navigation game state 2 flag is on at the start of the next unit game. . Then, after the process of S286, the sub CPU 71 ends the navigation game state transition process during the standby state, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  Here, returning to the processing of S281 again, when it is determined in S281 that the sub CPU 71 is a BB winning game during digestion of the navigation game state transition standby counter (when S281 is Yes), the sub CPU 71 The navigation game state transition standby counter is cleared (S287). Next, the sub CPU 71 performs processing for shifting the navigation game state to the navigation game state 1 after the end of the BB (S288). In this process, the sub CPU 71 turns on the navigation game state 1 flag, and shifts the navigation game state to the navigation game state 1 if the navigation game state 1 flag is on after BB ends. After the process of S288, the sub CPU 71 ends the navigation game state transition process during the standby state, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

[Navigation gaming state transition processing during navigation gaming state 1]
Next, with reference to FIG. 90, the navigation game state transition process during the navigation game state 1 performed in S205 in the flowchart of the start command reception process (see FIGS. 81 and 82) will be described. FIG. 90 is a flowchart showing the procedure of the navigation game state transition process during the navigation game state 1 in this embodiment.

  First, the sub CPU 71 determines whether or not the current unit game is a unit game won in “BB” (“BB1” to “BB4”) (whether or not it is a BB win game) (S291).

  In S291, when the sub CPU 71 determines that the game is a BB winning game (when S291 is Yes), the sub CPU 71 performs a process for shifting the navigation game state to the navigation game state 1 after the end of the BB ( S292). In this process, the sub CPU 71 turns on the navigation game state 1 flag, and shifts the navigation game state to the navigation game state 1 if the navigation game state 1 flag is on after BB ends. After the process of S292, the sub CPU 71 ends the navigation game state transition process during the navigation game state 1, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S291 that the game is not a BB winning game (when S291 is No), the sub CPU 71 determines that the unit game (RT3) in which the current unit game has shifted from another game state to the RT3 game state. It is determined whether or not the game is a transition game (S293). In S293, when the sub CPU 71 determines that the current unit game is the RT3 transition game (when S293 is Yes), the sub CPU 71 performs the process of S295 described later.

On the other hand, in S293, when the sub CPU 71 determines that the current unit game is not an RT3 transition game (when S293 is No), the sub CPU 71 determines whether or not the player satisfies a specific condition without following the navigation. Is determined (S294). The specific condition is satisfied in the following cases (i) to (v).
(I) When the RT gaming state does not shift to the RT1 gaming state at the time of SB winning in the general gaming state (ii) The RT gaming state does not shift to the RT2 gaming state at the time of the push order lip 1 winning during the RT1 gaming state Case (iii) When the RT gaming state shifts to the general gaming state during the push order bell win in the RT1 gaming state or RT2 gaming state (iv) The RT gaming state shifts to the RT1 gaming state when SB winning during the RT2 gaming state (V) When the RT gaming state does not shift to the RT3 gaming state during the push order lip 2 win in the RT2 gaming state

  In S294, when the sub CPU 71 determines that the player does not follow the navigation and does not satisfy the specific condition (when S294 is No), the sub CPU 71 performs the navigation game state transition process during the navigation game state 1. The process is terminated, and the process proceeds to S210 of the start command reception process (see FIGS. 81 and 82). On the other hand, in S294, when the sub CPU 71 determines that the player does not follow the navigation and satisfies the specific condition (when S294 is Yes), the sub CPU 71 performs the process of S295 described later.

  If S293 or S294 is Yes, the sub CPU 71 determines whether or not the navigation game state 3 interruption flag is on (S295). The navigation game state 3 interruption flag is turned on when “BB” is won in the navigation game state 3, and after the end of the BB, the navigation game state shifts to the navigation game state 1, and then the navigation game state again. Cleared when returning to 3.

  In S295, when the sub CPU 71 determines that the navigation game state 3 interruption flag is not on (when S295 is No), the sub CPU 71 shifts the navigation game state from the next unit game to the navigation game state 2. For this purpose (S296). In this process, the sub CPU 71 turns on the navigation game state 2 flag, and shifts the navigation game state to the navigation game state 2 if the navigation game state 2 flag is on at the start of the next unit game. After the process of S296, the sub CPU 71 ends the navigation game state transition process during the navigation game state 1 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S295 that the navigation game state 3 interruption flag is on (when S295 is Yes), the sub CPU 71 changes the navigation game state from the next unit game to the navigation game state 3. Processing for shifting to (S297). In this process, the sub CPU 71 turns on the navigation game state 3 flag, and shifts the navigation game state to the navigation game state 3 if the navigation game state 3 flag is on at the start of the next unit game. After the process of S297, the sub CPU 71 ends the navigation game state transition process during the navigation game state 1 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

[Navigation Game State 2 Navi Game State Transition Process]
Next, with reference to FIG. 91 and FIG. 92, the navigation game state transition process in the navigation game state 2 performed in S207 in the flowchart (see FIG. 81 and FIG. 82) of the start command reception process will be described. 91 and 92 are flowcharts showing the procedure of the navigation game state transition process during the navigation game state 2 in the present embodiment.

  First, the sub CPU 71 determines whether or not the current unit game is a unit game won in “BB” (“BB1” to “BB4”) (whether or not it is a BB win game) (S301).

  When the sub CPU 71 determines in S301 that the game is a BB winning game (when S301 is Yes), the sub CPU 71 performs a process for shifting the navigation game state to the navigation game state 1 after the end of the BB ( S302). In this process, the sub CPU 71 turns on the navigation game state 1 flag, and shifts the navigation game state to the navigation game state 1 if the navigation game state 1 flag is on after BB ends. After the process of S302, the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when it is determined in S301 that the sub CPU 71 is not a BB winning game (S301 is No), the sub CPU 71 determines whether or not “BB” is being carried over (S303).

  In S303, when the sub CPU 71 determines that “BB” is being carried over (if S303 is Yes), the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 and starts the process. The process proceeds to S210 in the reception process (see FIGS. 81 and 82). On the other hand, when the sub CPU 71 determines that “BB” is not being carried over in S303 (when S303 is No), the sub CPU 71 determines whether or not the navigation game state 3 transition flag is on. (S304).

  In S304, when the sub CPU 71 determines that the navigation game state 3 transition flag is on (when S304 is Yes), the sub CPU 71 performs the process of S306 described later. On the other hand, when the sub CPU 71 determines in S304 that the navigation game state 3 transition flag is not on (when S304 is No), the sub CPU 71 determines that the value of the navigation game state transition standby counter is “1” or more. It is determined whether or not there is (S305).

  In S305, when the sub CPU 71 determines that the value of the navigation gaming state transition standby counter is “1” or more (when S305 is Yes), the sub CPU 71 performs processing of S306 described later.

  When S304 or S305 is Yes, the sub CPU 71 performs a navigation game state 3 transition process during the navigation game state 2 (S306). The details of the navigation game state 3 transition process in the navigation game state 2 will be described later with reference to FIG. 93 described later. After the process of S306, the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, in S305, when the sub CPU 71 determines that the value of the navigation game state transition standby counter is not “1” or more (when S305 is No), the sub CPU 71 sets the value of the navigation game number counter to “1”. Subtraction is performed (S307). Next, the sub CPU 71 determines whether or not the value of the navigation game number counter has become “0” (S308).

  In S308, when the sub CPU 71 determines that the value of the navigation game number counter is not “0” (when S308 is No), the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 Then, the process proceeds to S210 of the start command reception process (see FIGS. 81 and 82). On the other hand, when the sub CPU 71 determines that the value of the navigation game number counter has become “0” in S308 (when S308 is Yes), the sub CPU 71 has the value of the navigation set number counter “0”. Whether or not (S309).

  When the sub CPU 71 determines that the value of the navigation set number counter is not “0” in S309 (when S309 is No), the sub CPU 71 sets “50” as the value of the navigation game number counter (S310). ). Next, the sub CPU 71 subtracts “1” from the value of the navigation set number counter (S311). After the process of S311, the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, in S309, when the sub CPU 71 determines that the value of the navigation set number counter is “0” (when S309 is Yes), the sub CPU 71 reads the navigation mode transition lottery table C (see FIG. 51). Refer to the navigation mode transition lottery (S312). Next, the sub CPU 71 determines whether or not the destination navigation mode is determined to be “0” as a result of the navigation mode transition lottery in S312 (S313).

  In S313, when the sub CPU 71 determines that the shift destination navigation mode is determined to be “0” (in the case where S313 is Yes), the sub CPU 71 performs the process of S318 described later.

  On the other hand, when the sub CPU 71 determines in S313 that the navigation mode of the transfer destination has not been determined to be “0” (when S313 is No), the sub CPU 71 performs the ART initial hit processing described in FIG. (S314). Next, the sub CPU 71 refers to the navigation game state transition standby number lottery table (see FIG. 52) and lots the navigation game state transition standby number (S315). Next, the sub CPU 71 sets the navigation game state transition standby number determined in S315 in the navigation game state transition standby number counter (S316).

  After the process of S316, the sub CPU 71 determines whether or not the value of the navigation game state transition standby number counter is “0” (S317). In S317, when the sub CPU 71 determines that the value of the navigation game state transition standby number counter is not “0” (when S317 is No), the sub CPU 71 performs the process of S318 described later.

  If S313 is Yes or S317 is No, the sub CPU 71 performs processing for shifting the navigation game state from the next unit game to the navigation game state 0 (S318). In this process, the sub CPU 71 turns on the navigation game state 0 flag, and shifts the navigation game state to the navigation game state 0 if the navigation game state 0 flag is on at the start of the next unit game. After the process of S318, the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines that the value of the navigation game state transition standby number counter is “0” in S317 (when S317 is Yes), the sub CPU 71 changes the navigation game state from the next unit game. Processing for shifting to the navigation game state 2 is performed (S319). In this process, the sub CPU 71 turns on the navigation game state 2 flag, and shifts the navigation game state to the navigation game state 2 if the navigation game state 2 flag is on at the start of the next unit game. After the process of S319, the sub CPU 71 ends the navigation game state transition process during the navigation game state 2 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

[Navi gaming state 2 during navigation gaming state 3 transition processing]
Next, with reference to FIG. 93, the navigation game state 2 navigation game state 3 transition process performed in S306 in the navigation game state 2 navigation game state transition process (see FIGS. 91 and 92) will be described. FIG. 93 is a flowchart showing the procedure of the navigation game state 3 transition process during the navigation game state 2 in the present embodiment.

  First, the sub CPU 71 determines whether or not the value of the navigation game state 3 transition standby number counter is “0” (S321). The navigation game state 3 transition standby number counter is a counter indicating the number of games until the navigation game state transitions from the navigation game state 2 to the navigation game state 3.

  In S321, when the sub CPU 71 determines that the value of the navigation game state 3 transition standby number counter is not “0” (when S321 is No), the sub CPU 71 performs the process of S327 described later. On the other hand, when the sub CPU 71 determines that the value of the navigation game state 3 transition standby number counter is “0” in S321 (when S321 is Yes), the sub CPU 71 determines that the navigation game state is the navigation game state 2. It is determined whether or not the navigation game state 3 transition flag is on (S322).

  In S322, when the sub CPU 71 determines that the navigation game state 3 transition flag is not in the on state (when S322 is No), the sub CPU 71 determines the navigation game state 3 transition standby number lottery table (see FIG. 53). With reference to the value of the navigation game number counter or the like, the navigation game state 3 transition standby number is lottery (S323). Next, the sub CPU 71 sets the navigation game state 3 transition standby number determined in S323 to the navigation game state 3 transition standby number counter (S324). Then, after the process of S324, the sub CPU 71 performs a process of S327 described later.

  On the other hand, in S322, when the sub CPU 71 determines that the navigation game state 3 transition flag is on (when S322 is Yes), the sub CPU 71 determines that before the navigation game state transitions to the navigation game state 2. It is determined whether the navigation game state is 0 or the navigation game state is 1 (S325).

  When the sub CPU 71 determines in S325 that the navigation gaming state is the navigation gaming state 0 or the navigation gaming state 1 before the navigation gaming state shifts to the navigation gaming state 2 (when S325 is Yes), the sub CPU 71 is described later. The process of S329 is performed. On the other hand, when the sub CPU 71 determines that the navigation game state is not the navigation game state 0 or the navigation game state 1 before the navigation game state shifts to the navigation game state 2 in S325 (when S325 is No), the sub CPU 71 “2” is set to the value of the navigation game state 3 transition standby number counter (S326).

  Then, after the processing of S324 or S326, or when S321 is No, the sub CPU 71 decrements the value of the navigation gaming state 3 transition standby number counter by “1” (S327). Next, the sub CPU 71 determines whether or not the value of the navigation game state 3 transition standby number counter is “0” (S328).

  In S328, when the sub CPU 71 determines that the value of the navigation game state 3 transition standby number counter is not “0” (when S328 is No), the sub CPU 71 performs the navigation game state 2 navigation game state 3 transition process. And the navigation game state transition process during the navigation game state 2 is also ended. On the other hand, in S328, when the sub CPU 71 determines that the value of the navigation game state 3 transition standby number counter is “0” (when S328 is Yes), the sub CPU 71 performs the process of S329 described later.

  When S325 or S328 is Yes, the sub CPU 71 performs processing for shifting the navigation game state from the next unit game to the navigation game state 3 (S329). In this process, the sub CPU 71 turns on the navigation game state 3 flag, and shifts the navigation game state to the navigation game state 3 if the navigation game state 3 flag is on at the start of the next unit game. After the process of S329, the sub CPU 71 ends the navigation game state 3 transition process during the navigation game state 2 and also ends the navigation game state transition process during the navigation game state 2.

[Navigation gaming state transition processing during navigation gaming state 3]
Next, with reference to FIG. 94, the navigation game state transition process during the navigation game state 3 performed in S209 in the flowchart (see FIGS. 81 and 82) of the start command reception process will be described. FIG. 94 is a flowchart showing the procedure of the navigation game state transition process during the navigation game state 3 in the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state 3 interruption flag is on (S331).

  In S331, when the sub CPU 71 determines that the navigation game state 3 interruption flag is in the on state (when S331 is Yes), the sub CPU 71 performs the process of S337 described later. On the other hand, in S331, when the sub CPU 71 determines that the navigation game state 3 interruption flag is not on (when S331 is No), the sub CPU 71 determines that the current game is in the navigation game state 3 from another navigation game state. It is determined whether or not the game has shifted to (Navi gaming state 3 transition game) (S332).

  In S332, when the sub CPU 71 determines that the game is not the navigation game state 3 transition game (S332 is No), the sub CPU 71 performs the process of S339 described later. On the other hand, when the sub CPU 71 determines that the game is the navigation game state 3 transition game in S332 (when the determination of S332 is Yes), the sub CPU 71 acquires information from the navigation game state 3 information storage area, and the navigation game state. The number of 3-added games and the navigation game state 3-added lottery mode are set (S333).

  After the processing of S333, the sub CPU 71 sets “1” in the navigation gaming state 3 continuation counter (S334). The navigation game state 3 continuation counter is a counter that manages the number of continuous games in the navigation game state 3. Next, the sub CPU 71 determines whether or not there is no information stored in the navigation game state 3 information storage area by acquiring information from the navigation game state 3 information storage area in the process of S333 (navigation game state 3 information). It is determined whether or not the storage area has become empty (S335).

  In S335, when the sub CPU 71 determines that the navigation game state 3 information storage area is not empty (when S335 is No), the sub CPU 71 performs a process of S339 described later. On the other hand, when the sub CPU 71 determines that the navigation game state 3 information storage area is empty in S335 (when S335 is Yes), the sub CPU 71 turns off the navigation game state 3 transition flag (S336). Then, after the process of S336, the sub CPU 71 performs a process of S339 described later.

  Here, returning to the processing of S331 again, if S331 is Yes, the sub CPU 71 determines the number of navigation game state 3 addition games, navigation game state 3 addition lottery mode, and navigation game state saved in the processing of S341 described later. The continuation counter is returned (S337). Next, the sub CPU 71 turns off the navigation game state 3 transition flag (S338). Then, after the process of S338, the sub CPU 71 performs a process of S339 described later.

  After the process of S336 or S338, or when S332 or S335 is No, the sub CPU 71 performs a navigation game number addition process (S339). The details of the navigation game number addition process will be described later with reference to FIG. 95 described later.

  Next, the sub CPU 71 determines whether or not the current unit game is a unit game won in “BB” (“BB1” to “BB4”) (whether or not it is a BB win game) (S340).

  In S340, when the sub CPU 71 determines that the game is BB winning game (when S340 is Yes), the sub CPU 71 determines the number of navigation game state 3 addition games, the navigation game state 3 addition lottery mode, and the navigation game state continuation counter. Is saved (S341). Next, the sub CPU 71 turns on the navigation game state 3 interruption flag (S342).

  After the process of S342, the sub CPU 71 performs a process for shifting the navigation game state to the navigation game state 1 after the end of the BB (S343). In this process, the sub CPU 71 turns on the navigation game state 1 flag, and shifts the navigation game state to the navigation game state 1 if the navigation game state 1 flag is on after BB ends. After the process of S343, the sub CPU 71 ends the navigation game state transition process during the navigation game state 3 and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S340 that the game is not a BB winning game (when S340 is No), the sub CPU 71 determines whether or not the result of the navigation game state 3 navigation game number addition lottery is non-winning. A determination is made (S344).

  In S344, when the sub CPU 71 determines that the result of the navigation game state 3 navigation game number addition lottery is a win (when S344 is No), the sub CPU 71 performs the navigation game state 3 navigation game state transition process. The process is terminated, and the process proceeds to S210 of the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines that the result of the navigation game state 3 navigation game number addition lottery is non-winning in S344 (when S344 is Yes), the sub CPU 71 starts the navigation game state from the next unit game. Is performed to shift to the navigation game state 2 (S345). In this process, the sub CPU 71 turns on the navigation game state 2 flag, and shifts the navigation game state to the navigation game state 2 if the navigation game state 2 flag is on at the start of the next unit game. After the process of S345, the sub CPU 71 ends the navigation game state transition process during the navigation game state 3, and moves the process to S210 of the start command reception process (see FIGS. 81 and 82).

[Navigation game number addition processing]
Next, with reference to FIG. 95, the navigation game number addition process performed in S339 in the flowchart of the navigation game state transition process during the navigation game state 3 (see FIG. 94) will be described. FIG. 95 is a flowchart showing the procedure of the navigation game number addition process in this embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state is the navigation game state 3 (S351).

  In S351, when the sub CPU 71 determines that the navigation game state is not the navigation game state 3 (when S351 is No), the sub CPU 71 ends the navigation game number addition process, and the process proceeds to the navigation in the navigation game state 3. The process proceeds to S340 of the game state transition process (see FIG. 94). On the other hand, when the sub CPU 71 determines that the navigation game state is the navigation game state 3 in S351 (when S351 is Yes), the sub CPU 71 determines that the current unit game is “BB” (“BB1” to “BB1” to “BB1” to “BB1” to “BB1”). It is determined whether or not the unit game has won BB4 ") (whether or not it is a BB winning game) (S352).

  When the sub CPU 71 determines in S352 that the game is a BB winning game (when S352 is Yes), the sub CPU 71 refers to the navigation game number special addition lottery table (see FIG. 64) and wins “BB”. Based on the type of navigation game, a special addition lottery for the number of navigation games is performed (S353), and then the sub CPU 71 adds the number of navigation games determined in S353 to the value of the navigation game number counter (S354). After the process of S354, the sub CPU 71 ends the navigation game number addition process, and moves the process to S340 of the navigation game state transition process (see FIG. 94) during the navigation game state 3.

  On the other hand, in S352, when the sub CPU 71 determines that the game is not a BB winning game (when S352 is No), the sub CPU 71 returns to the first game from the BB winning game in which the current game is in the navigation gaming state 3. It is determined whether or not (S355).

  In S355, when the sub CPU 71 determines that the current game is the first game that has returned from the BB winning state in the navigation game state 3 (when S355 is Yes), the sub CPU 71 executes the process of S360 described later. Process. On the other hand, when the sub CPU 71 determines in S355 that the current game is not the first game that has returned from the BB winning state in the navigation game state 3 (when S355 is No), the sub CPU 71 determines that the game state is the navigation game state. It is determined whether or not the value of the 3 continuation counter is “1” or “2” (S356).

  In S356, when the sub CPU 71 determines that the value of the navigation game state 3 continuation counter is “1” or “2” (when S356 is Yes), the sub CPU 71 performs the process of S360 described later. On the other hand, when the sub CPU 71 determines that the value of the navigation game state 3 continuation counter is not “1” or “2” in S356 (when S356 is No), the sub CPU 71 determines the number of navigation game state 3 navigation games. With reference to the addition lottery table (see FIG. 63), the navigation game state 3 addition game lottery mode, the small role / replay pointer data pointer, the bonus data pointer, etc. are used to perform the navigation game state 3 navigation game number addition lottery ( S357).

  After the process of S357, the sub CPU 71 determines whether or not the result of the navigation game state 3 navigation game number addition lottery is winning (S358).

  In S358, when the sub CPU 71 determines that the result of the navigation game state 3 navigation game number addition lottery is a win (when S 358 is Yes), the sub CPU 71 performs a process of S360 described later. On the other hand, in S358, when the sub CPU 71 determines that the result of the navigation game state 3 navigation game number addition lottery is not winning (when S358 is No), the sub CPU 71 determines that the navigation game state 3 addition lottery mode, navigation game The number of state 3 addition games and the navigation game state 3 continuation counter are cleared (S359). Then, after the processing of S359, the sub CPU 71 ends the navigation game number addition processing, and moves the processing to S340 of the navigation gaming state transition processing during the navigation gaming state 3 (see FIG. 94).

  When S355, S356, or S358 is Yes, the sub CPU 71 adds the number of navigation game state 3 addition games to the value of the navigation game number counter (S360). Next, the sub CPU 71 determines whether or not the value of the navigation gaming state 3 continuation counter is a specific value (S361). Specifically, the sub CPU 71 determines that the value of the navigation game state 3 continuation counter is a value (5, 7, 10, 15, 20, 25, 30 specified in the navigation game number special addition lottery table (see FIG. 64)). , 35, 40,...

  In S361, when the sub CPU 71 determines that the value of the navigation game state 3 continuation counter is not a specific value (when S361 is No), the sub CPU 71 performs the process of S364 described later. On the other hand, in S361, when the sub CPU 71 determines that the value of the navigation game state 3 continuation counter is a specific value (when S361 is Yes), the sub CPU 71 determines that the navigation game number special addition lottery table (FIG. 64). Referring to), the navigation game number special addition lottery is performed based on the value of the navigation game state 3 continuation counter (S362). Next, the sub CPU 71 adds the number of navigation games determined by the navigation game number special addition lottery to the value of the navigation game number counter (S363).

  After the processing of S363 or when S361 is No, the sub CPU 71 adds “1” to the value of the navigation gaming state 3 continuation counter (S364). Then, after the process of S364, the sub CPU 71 ends the navigation game number addition process, and moves the process to S340 of the navigation game state 3 navigation game state transition process (see FIG. 94).

[Billy get challenge lottery process]
Next, with reference to FIG. 96, the billy get challenge lottery process performed in S210 in the flowchart (see FIGS. 81 and 82) of the start command reception process will be described. FIG. 96 is a flowchart showing the procedure of the billy get challenge lottery process in the present embodiment.

  First, the sub CPU 71 determines whether or not “BB” is in operation (S371).

  In S371, when the sub CPU 71 determines that “BB” is in operation (in the case where S371 is Yes), the sub CPU 71 ends the billy get challenge lottery process, and starts the process when the start command is received (FIG. 81 and FIG. 82). On the other hand, when the sub CPU 71 determines that “BB” is not in operation in S371 (when S371 is No), the sub CPU 71 determines whether “BB” is being carried over (S372). .

  In S372, when the sub CPU 71 determines that “BB” is being carried over (in the case where S372 is Yes), the sub CPU 71 ends the billy get challenge lottery process, and starts the process when the start command is received (FIG. 81 and FIG. 82). On the other hand, when the sub CPU 71 determines that “BB” is not being carried over in S372 (when S372 is No), the sub CPU 71 determines whether or not the navigation mode is “0” (S373). .

  In S373, when the sub CPU 71 determines that the navigation mode is not “0” (when S373 is No), the sub CPU 71 ends the billy get challenge lottery process, and starts the process when the start command is received (FIG. 81). And the process proceeds to S211 in FIG. On the other hand, when the sub CPU 71 determines that the navigation mode is “0” in S373 (when S373 is Yes), the sub CPU 71 refers to the billy get challenge control counter lottery table (see FIG. 66), Based on the small role / replay pointer, the bonus data pointer, and the presence / absence of the effect game stoppage, a billy get challenge control counter lottery is performed (S374).

  Next, the sub CPU 71 determines whether or not the result of the billy get challenge control counter lottery is winning (S375).

  In S375, when the sub CPU 71 determines that the result of the billy get challenge control counter lottery is not winning (when S375 is No), the sub CPU 71 performs a process of S377 described later. On the other hand, when the sub CPU 71 determines that the result of the billy get challenge control counter lottery is winning in S375 (when S375 is Yes), the sub CPU 71 sets “1” to the value of the billy get challenge control counter. Addition is performed (S376).

  Then, after the processing of S376 or when S375 is No, the sub CPU 71 determines whether or not the value of the billy get challenge control counter is “1” or more (S377). In S377, when the sub CPU 71 determines that the value of the billy get challenge control counter is not equal to or greater than “1” (when S377 is No), the sub CPU 71 ends the billy get challenge lottery process and starts the process. The process proceeds to S211 in the reception process (see FIGS. 81 and 82).

  On the other hand, in S377, when the sub CPU 71 determines that the value of the billy get challenge control counter is “1” or more (when S377 is Yes), the sub CPU 71 determines that the current unit game is the end of the specific liquid crystal effect. It is determined whether it is the next unit game (S378). Here, the “specific liquid crystal effect” is, for example, a continuous effect over a plurality of unit games by the liquid crystal display device 10 or an effect that expects a bonus or ART.

  In S378, when the sub CPU 71 determines that the current unit game is not the next unit game after the end of the specific liquid crystal effect (when S378 is No), the sub CPU 71 ends the billy get challenge lottery process and performs the process. The process proceeds to S211 in the start command reception process (see FIGS. 81 and 82).

  On the other hand, when the sub CPU 71 determines in S378 that the current unit game is the next unit game after the end of the specific liquid crystal effect (when S378 is Yes), the sub CPU 71 determines the billy get described in FIG. 86 above. Challenge processing is performed (S379). Next, the sub CPU 71 subtracts “1” from the value of the billy get challenge control counter (S380). Then, after the process of S380, the sub CPU 71 ends the billy get challenge lottery process, and moves the process to S211 of the start command reception process (see FIGS. 81 and 82).

[Billy Get Challenge Judgment Processing]
Next, with reference to FIG. 97, the billy get challenge determination process performed in S175 in the flowchart of the effect content determination process (see FIG. 80) will be described. FIG. 97 is a flowchart showing a procedure of billy get challenge determination processing in the present embodiment.

  First, the sub CPU 71 determines whether or not the billy get challenge effect is registered in S243 during the billy challenge process described with reference to FIG. 86 (S391).

  In S391, when the sub CPU 71 determines that the billy get challenge effect is not registered (when S391 is No), the sub CPU 71 ends the billy get challenge determination process, and the process is determined as an effect content determination process (FIG. 80). On the other hand, when the sub CPU 71 determines in S <b> 391 that the billy get challenge effect is registered (when S <b> 391 is Yes), the sub CPU 71 determines whether or not it is the third stop time (S <b> 392). .

  In S392, when the sub CPU 71 determines that it is not at the time of the third stop (when S392 is No), the sub CPU 71 ends the billy get challenge determination process, and the process is an effect content determination process (see FIG. 80). Move on to S176. On the other hand, when it is determined in S392 that the sub CPU 71 is at the time of the third stop (when S392 is YES), the sub CPU 71 determines whether or not the billy get challenge is successful (S393).

  In the process of S393, first, the sub CPU 71 determines whether or not a player's selection operation has been performed on the infrared sensors (120L and 120R) by the time of the third stop. If the selection operation is performed, the sub CPU 71 confirms whether the result of the selection operation matches the correct answer determined by the billy get challenge correct answer lottery (S241 during the billy challenge process described in FIG. 86). Determine whether or not. When the two match, the sub CPU 71 determines that the billy get challenge is successful, and when the two do not match, the sub CPU 71 determines that the billy get challenge has failed.

  If the selection operation is not performed before the third stop, the sub CPU 71 determines that if the result of the lottery when no billy get challenge is selected (S242 during the billy challenge process described with reference to FIG. 86) is a win, It is determined that the get challenge is successful, and if it is non-winning, it is determined that the billy get challenge has failed. Further, although not shown, if the billy get challenge is successful, the sub CPU 71 registers billy get challenge success effect data indicating that the billy get challenge is successful, and notifies the player of that fact.

  In S393, when the sub CPU 71 determines that the billy get challenge has failed (when S393 is No), the sub CPU 71 ends the billy get challenge determination process, and the process is an effect content determination process (see FIG. 80). To S176. On the other hand, when the sub CPU 71 determines in S393 that the billy get challenge is successful (S393 is Yes), the sub CPU 71 determines whether or not “BB4” is in operation (S394).

  In S394, when the sub CPU 71 determines that “BB4” is not in operation (NO in S394), the sub CPU 71 increases the navigation mode by one level (S395). Next, the sub CPU 71 performs a navigation game state transition process (S396). The details of the navigation game state transition process will be described later with reference to FIG. Next, the sub CPU 71 performs the ART initial hit processing described with reference to FIG. 88 (S397). And after the process of S397, sub CPU71 complete | finishes a billy get challenge determination process, and moves a process to S176 of an effect content determination process (refer FIG. 80).

  On the other hand, when the sub CPU 71 determines that “BB4” is in operation in S394 (in the case where S394 is Yes), the sub CPU 71 turns on the billy get challenge success flag (S398). Next, the sub CPU 71 increases the navigation mode by one level (S399).

  Next, the sub CPU 71 determines whether or not the navigation mode has shifted from “0” to “1” to “4” (S400).

  In S400, when the sub CPU 71 determines that the navigation mode has not shifted from “0” to “1” to “4” (when S400 is No), the sub CPU 71 performs the process of S402 described later. . On the other hand, in S400, when the sub CPU 71 determines that the navigation mode has shifted from “0” to “1” to “4” (when S400 is Yes), the sub CPU 71 determines that the ART described with reference to FIG. An initial hit process is performed (S401).

  After the processing of S401 or when S400 is No, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table D (see FIG. 57) and lots the navigation game state 3 addition game number (S402). . Next, the sub CPU 71 determines whether or not the lottery result of the number of navigation game state 3 addition games is winning (a value other than “0” is determined as the number of navigation game state 3 addition games) (S403).

  In S403, when the sub CPU 71 determines that the lottery result of the number of navigation game state 3 addition games is not winning (when S403 is No), the sub CPU 71 ends the billy get challenge determination process, and performs the process. The process proceeds to S176 in the determination process (see FIG. 80). On the other hand, in S403, when the sub CPU 71 determines that the lottery result of the number of navigation game state 3 addition games is winning (S403 is Yes determination), the sub CPU 71 determines that the navigation game state 3 addition lottery mode lottery table D is determined. With reference to (refer FIG. 61), a navigation game state 3 addition lottery mode lottery is performed based on the present navigation mode (S404).

  Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in the lottery process in S402 with the navigation game state 3 addition lottery mode determined in the lottery process in S404, and sets the combination data. The navigation game state 3 information is stored in the information storage area (S405). Next, the sub CPU 71 turns on the navigation game state 3 transition flag (S406). Then, after the process of S406, the sub CPU 71 ends the billy get challenge determination process, and moves the process to S176 of the effect content determination process (see FIG. 80).

[Navi game state transition processing]
Next, with reference to FIG. 98, the navigation game state transition process performed in S396 in the flowchart of the billy get challenge determination process (see FIG. 97) will be described. FIG. 98 is a flowchart showing the procedure of the navigation game state transition process in the present embodiment.

  First, the sub CPU 71 determines whether or not it is in the RT3 gaming state (S411).

  In S411, when the sub CPU 71 determines that it is in the RT3 gaming state (when S411 is Yes), the sub CPU 71 performs processing for shifting the navigation game state from the next unit game to the navigation game state 2. This is performed (S412). In this process, the sub CPU 71 turns on the navigation game state 2 flag, and shifts the navigation game state to the navigation game state 2 if the navigation game state 2 flag is on at the start of the next unit game. Then, after the process of S412, the sub CPU 71 ends the navigation game state transition process, and moves the process to S397 of the billy get challenge determination process (see FIG. 97).

  On the other hand, when it is determined in S411 that the sub CPU 71 is not in the RT3 gaming state (when S411 is No), the sub CPU 71 performs processing for shifting the navigation game state from the next unit game to the navigation game state 1. (S413). In this process, the sub CPU 71 turns on the navigation game state 1 flag, and shifts the navigation game state to the navigation game state 1 if the navigation game state 1 flag is on at the start of the next unit game. Then, after the processing of S413, the sub CPU 71 ends the navigation game state transition processing, and moves the processing to S397 of the billy get challenge determination processing (see FIG. 97).

[Process when receiving display command]
Next, with reference to FIG. 99, the display command reception process performed in S178 in the flowchart of the effect content determination process (see FIG. 80) will be described. FIG. 99 is a flowchart showing the procedure of the display command reception process in this embodiment.

  First, the sub CPU 71 determines whether or not the current unit game is a unit game won by “BB” (“BB1” to “BB4”) (whether or not it is a BB win game) (S421).

  When the sub CPU 71 determines in S421 that the game is a BB winning game (when S421 is Yes), the sub CPU 71 determines whether or not the display combination is “BB” (internally winning “BB”). (S422).

  In S422, when the sub CPU 71 determines that the display combination is “BB” (in the case where S422 is Yes), the sub CPU 71 ends the display command reception process and also ends the effect content determination process. On the other hand, when the sub CPU 71 determines that the display combination is not “BB” in S422 (when S422 is No), the sub CPU 71 turns on the BB carryover flag (S423). Then, after the processing of S423, the sub CPU 71 ends the display command reception processing and also ends the effect content determination processing.

  Here, returning to the processing of S421 again, when the sub CPU 71 determines that the game is not a BB winning game (when S421 is No), the sub CPU 71 determines whether or not the BB carryover flag is on. It discriminate | determines (S424).

  In S424, when the sub CPU 71 determines that the BB carryover flag is not on (when S424 is No), the sub CPU 71 ends the display command reception process and the effect content determination process. On the other hand, when the sub CPU 71 determines in S424 that the BB carryover flag is on (in the case where S424 is Yes), the sub CPU 71 has the display combination of “BB” (“BB” being carried over). It is determined whether or not there is (S425).

  When the sub CPU 71 determines that the display combination is not “BB” in S425 (when S425 is No), the sub CPU 71 ends the display command reception process and also ends the effect content determination process. On the other hand, when the sub CPU 71 determines that the display combination is “BB” in S425 (when S425 is Yes), the sub CPU 71 turns off the BB carryover flag (S426). Then, after the process of S426, the sub CPU 71 ends the display command reception process and ends the effect content determination process.

[Process when receiving bonus end command]
Next, with reference to FIG. 100, the bonus end command reception process performed in S184 in the flowchart of the effect content determination process (see FIG. 80) will be described. FIG. 100 is a flowchart showing a procedure of bonus end command reception processing in the present embodiment.

  First, the sub CPU 71 determines whether or not the BB4 gaming state is over (S431).

  In S431, when the sub CPU 71 determines that it is not the end of the BB4 gaming state (when S431 is No), the sub CPU 71 performs the process of S434 described later. On the other hand, when it is determined in S431 that the sub CPU 71 is at the end of the BB4 gaming state (when S431 is Yes), the sub CPU 71 determines whether or not the billy get challenge success flag is on. (S432).

  In S432, when the sub CPU 71 determines that the billy get challenge success flag is not on (when S432 is No), the sub CPU 71 performs the process of S434 described later. On the other hand, in S432, when the sub CPU 71 determines that the billy get challenge success flag is on (when S432 is Yes), the sub CPU 71 turns off the billy get challenge success flag (S433).

  After the processing of S433, or when S431 or S432 is No, the sub CPU 71 determines whether or not it is at the end of the BB gaming state (any of BB1 to BB4) (S434).

  In S434, when the sub CPU 71 determines that it is not at the end of the BB gaming state (when S434 is No), the sub CPU 71 ends the bonus end command reception process, and the process is an effect content determination process (FIG. 80). (See reference) S185. On the other hand, when it is determined in S434 that the sub CPU 71 is at the end of the BB gaming state (when S434 is Yes), the sub CPU 71 determines whether the navigation mode is any of “1” to “4”. It is determined whether or not (S435).

  In S435, when the sub CPU 71 determines that the navigation mode is not any of “1” to “4” (when S435 is No), the sub CPU 71 performs the process of S439 described later. On the other hand, when the sub CPU 71 determines that the navigation mode is any one of “1” to “4” in S435 (when S435 is Yes), the sub CPU 71 transitions by lottery in the BB winning game. It is determined whether or not there is (S436).

  In S436, when the sub CPU 71 determines that it is not a lottery transition in the BB winning game (when S436 is No), the sub CPU 71 performs a process of S440 described later. On the other hand, when it is determined in S436 that the sub CPU 71 has made a lottery transition in the BB winning game (when S436 is Yes), the sub CPU 71 has won a navigation mode transition lottery in the BB gaming state. Is discriminated (S437).

  In S437, when it is determined that the sub CPU 71 has won the navigation mode transition lottery during the BB gaming state (when S437 is Yes), the sub CPU 71 performs the process of S440 described later. On the other hand, when it is determined in S437 that the sub CPU 71 has not won the navigation mode transition lottery in the BB gaming state (when S437 is No), the sub CPU 71 determines the navigation gaming state transition standby number lottery table (FIG. 52), the navigation game state transition standby number is determined, and the winning navigation game state transition standby number is set in the navigation game state transition standby counter (S438).

  After the process of S438 or when S435 is No, the sub CPU 71 performs a process for shifting the navigation game state from the next unit game to the navigation game state 0 (S439). In this process, the sub CPU 71 turns on the navigation game state 0 flag, and shifts the navigation game state to the navigation game state 0 if the navigation game state 0 flag is on at the start of the next unit game. Then, after the process of S439, the sub CPU 71 ends the bonus end command reception process, and moves the process to S185 of the effect content determination process (see FIG. 80).

  When S436 is No, or when S437 is Yes, the sub CPU 71 performs processing for shifting the navigation game state from the next unit game to the navigation game state 1 (S440). In this process, the sub CPU 71 turns on the navigation game state 1 flag, and shifts the navigation game state to the navigation game state 1 if the navigation game state 1 flag is on at the start of the next unit game. Then, after the process of S440, the sub CPU 71 ends the process at the time of receiving the bonus end command, and moves the process to S185 of the effect content determination process (see FIG. 80).

  In the present embodiment, the navigation mode transition lottery may be performed at the end of the BB gaming state. In this case, lottery may be performed according to the game content in the BB game state to be ended. For example, if JAC 1-7 (pointer / replay pointers “25”-“31”) do not win once in BB gaming states 1-3, navigation mode will increase “1” with high probability. A lottery may be performed. Further, in the present embodiment, when the billy get challenge is failed a specific number of times during the BB gaming state, lottery may be performed so that the navigation mode is increased by “1” with high probability.

<Explanation of various processes related to error management by sub-control circuit>
Next, the contents of various processes (tasks) related to error management executed by the sub CPU 71 of the sub control circuit 70 using a program will be described with reference to FIGS. Various tables necessary for various processes of the sub CPU 71 described below are stored in the sub ROM 72, and various control flags, various control counters, various storage areas and the like are provided in the sub RAM 73 and the like.

[Main board communication reception interrupt processing]
First, the main board communication reception interrupt process by the sub control circuit 70 will be described with reference to FIG. FIG. 101 is a flowchart showing a procedure of main board communication reception interrupt processing in the present embodiment. The main board communication reception interrupt process program described below is executed by the sub CPU 71 as an interrupt process when transmission data is transmitted from the main control circuit 60 to the sub control circuit 70.

  First, the sub CPU 71 acquires received data from the received data register of the I / O port interposed between the main CPU 31 (S451). Further, the sub CPU 71 acquires reception status data from the reception status register of the I / O port (S452).

  Next, the sub CPU 71 registers the reception data and the reception status data related to the reception data in each queue buffer (S453). Then, after the processing of S453, the sub CPU 71 ends the main board communication reception interrupt processing.

  The sub CPU 71 processes the received data of 1 byte by executing the main board communication reception interrupt process described above once. In the present embodiment, one command is composed of 8-byte data. Therefore, the sub CPU 71 completes the processing of one command by executing the serial data communication by processing the above-described main board communication reception interrupt processing eight times in succession.

[Main board communication task]
Next, with reference to FIG. 102, the main board communication task (processing) by the sub CPU 71 will be described. FIG. 102 is a flowchart showing the procedure of the main board communication task in this embodiment.

  In response to the scheduling function of the OS, the sub CPU 71 sets a cycle so that the main board communication task program of the sub CPU 71 is executed at a cycle of 2 msec (S461). By this setting process, the main board communication task is repeated at a cycle of 2 msec including the processing time. Next, the sub CPU 71 waits for a cycle of 2 msec (S462). If this process is performed first, the sub CPU 71 waits for 2 msec in S462. On the other hand, when the processing after S463 described later is repeated, in S462, the sub CPU 71 waits for the remaining time within 2 msec.

  The cycle of the main board communication task is not limited to 2 msec, and can be arbitrarily set between 2 msec and 4 msec. The program of the main board communication task of the sub CPU 71 is not limited to one executed every predetermined time. For example, the predetermined condition is not performed without performing the period setting process and the period waiting process, that is, regardless of the time interval. It may be executed when it is satisfied.

  Next, the sub CPU 71 acquires the reception data from the queue in which the reception data is registered in the processing of S453 during the main board communication reception interruption processing described with reference to FIG. 101 (S463). Next, the sub CPU 71 determines whether there is reception data in the queue (S464).

  In S464, when the sub CPU 71 determines that there is no received data in the queue (when S464 is No), the sub CPU 71 returns the process to S462 and repeats the processes after S462. On the other hand, when the sub CPU 71 determines in S464 that there is received data in the queue (when S464 is Yes), the sub CPU 71 determines whether or not a physical layer error has occurred in the received data ( S465).

  In S465, when the sub CPU 71 determines that a physical layer error has occurred in the received data (when S465 is No), the sub CPU 71 performs the process of S479 described later. On the other hand, when the sub CPU 71 determines in S465 that no physical layer error has occurred in the received data (when S465 is Yes), the sub CPU 71 obtains the value of the received command, which is the received command. It is checked whether or not the value is within the numerical range (S466). In the present embodiment, the numerical value range of the received command is “01H” to “10H” as shown in FIG. Then, the sub CPU 71 determines whether or not the numerical value of the received command is within an appropriate range (S467).

  In S467, when the sub CPU 71 determines that the numerical value of the received command is not within the appropriate range (when S467 is No), the sub CPU 71 performs the process of S479 described later. On the other hand, when the sub CPU 71 determines in S467 that the numerical value of the received command is within the appropriate range (when S467 is Yes), the sub CPU 71 performs BCC check processing on the received data (S468). ).

  In the process of S468, since one command is composed of 8-byte data, the sub CPU 71 performs an XOR (exclusive OR) operation on the data of the first byte to the seventh byte of each command in this BCC check process. Then, the calculation result is compared with the eighth byte data set in advance corresponding to the correct result. Then, the sub CPU 71 determines whether or not the result of the BCC check process is normal (S469).

  In S469, when the sub CPU 71 determines that the result of the BCC check process is not normal (when S469 is No), the sub CPU 71 performs the process of S479 described later. On the other hand, when the sub CPU 71 determines that the result of the BCC check process is normal in S469 (when S469 is Yes), the sub CPU 71 extracts the command type (S470). Next, the sub CPU 71 determines whether or not the extracted command is a no-operation command (S471).

  In S471, when the sub CPU 71 determines that the extracted command is a no-operation command (when S471 is Yes), the sub CPU 71 returns the process to S462 and repeats the processes after S462. On the other hand, when the sub CPU 71 determines that the extracted command is not a no-operation command in S471 (when S471 is No), the sub CPU 71 performs main board communication reception data log saving processing (S472). The details of the main board communication reception data log saving process will be described later with reference to FIG.

  After the process of S472, the sub CPU 71 performs a main board communication reception command check process (S473). The details of the main board communication reception command check process will be described later with reference to FIG.

  Next, the sub CPU 71 determines whether or not the command received this time is different from the command received last time (immediately before) (S474).

  In S474, when the sub CPU 71 determines that the command received this time is not different (same) as the command received last time (when S474 is No), the sub CPU 71 returns the process to S462, and S462. The subsequent processing is repeated. On the other hand, when the sub CPU 71 determines in S474 that the command received this time is different from the command received last time (when S474 is Yes), the sub CPU 71 registers the command received this time in the message queue. (S475).

  Next, the sub CPU 71 performs a sum check on the game data stored in the sub control game data sum value area 73b (see FIG. 11) (S476). Then, the sub CPU 71 determines whether or not the game data is normal as a result of the sum check (S477).

  When the sub CPU 71 determines that the game data is normal in S477 (when S477 is Yes), the sub CPU 71 returns the process to S462, and repeats the processes after S462. On the other hand, when the sub CPU 71 determines that the game data is not normal in S477 (when S477 is No), the sub CPU 71 (error information registering means 71d) uses the data (RAM) destruction error occurrence information as error information. Registration is made in the history storage area 73e (see FIG. 11) (S478). Then, after the processing of S478, the sub CPU 71 returns the processing to S462 and repeats the processing after S462.

  If S465, S467, or S469 is No, the sub CPU 71 determines that a communication error has occurred, and performs a COM error check process (S479). The details of the COM error check process will be described later with reference to FIG. 107 described later. After the process of S479, the sub CPU 71 returns the process to S462 and repeats the processes after S462.

[Main board communication received data log saving process]
Next, with reference to FIG. 103, the main board communication reception data log storing process performed in S472 in the main board communication task flowchart (see FIG. 102) will be described. FIG. 103 is a flowchart showing a procedure of main board communication reception data log storage processing in the present embodiment. The main board communication reception data log storage process is mainly executed by the reception data log storage unit 71e (see FIG. 9) of the sub CPU 71.

  First, the sub CPU 71 performs a main board communication reception data log temporary area saving process (S481). In the main board communication reception data log temporary area saving process, the communication log collection ring buffer area 73f shown in FIG. 15 is used, and all communication logs are stored in the communication log collection ring buffer area 73f regardless of the occurrence of an error. Saved. Details of the main board communication reception data log temporary area storage processing will be described later with reference to FIG.

  Next, the sub CPU 71 performs main board communication error history data storage processing (S482). In the main board communication error history data saving process, a communication error saving buffer area 73g shown in FIG. 16 is used, and when a communication error occurs, a related communication log is saved in the communication error saving buffer area 73g. Details of the main board communication error history data storage process will be described later with reference to FIG. After the processing of S482, the sub CPU 71 ends the main board communication reception data log saving process, and moves the process to S473 of the main board communication task (see FIG. 102).

[Main board communication received data log temporary area saving process]
Next, with reference to FIG. 104, the main board communication received data log temporary area saving process performed in S481 in the main board communication received data log saving process flowchart (see FIG. 103) will be described. FIG. 104 is a flowchart showing a procedure of main board communication reception data log temporary area storage processing in the present embodiment.

  First, the sub CPU 71 acquires the communication log data buffer index of the communication log collection ring buffer area 73f (see FIG. 15) (S491). Note that the number of buffers here is set as appropriate.

  Next, the sub CPU 71 calculates the communication log data buffer storage position of the communication log collection ring buffer area 73f (S492). In this process, the sub CPU 71 calculates the storage position in the communication log collection ring buffer area 73f from the value of the buffer index.

  Next, the sub CPU 71 stores the received data in the communication log collection ring buffer area 73f (S493). As shown in FIG. 15, in the communication log collection ring buffer area 73f of this embodiment, a maximum of 256 sets of data in which a command and a parameter corresponding to the command are consecutive for one buffer command. Saved.

  Next, the sub CPU 71 updates the communication log data buffer index (S494). In this process, the sub CPU 71 adds “1” to the buffer index storing the received data. Then, the sub CPU 71 determines whether or not the value of the buffer index is an upper limit value (S495).

  In S495, when the sub CPU 71 determines that the value of the buffer index is not the upper limit value (when S477 is No), the sub CPU 71 ends the main board communication reception data log temporary area saving process and performs the process on the main board. The process proceeds to S482 in the communication reception data log storage process (see FIG. 103). On the other hand, when the sub CPU 71 determines that the buffer index value is the upper limit value in S495 (when S477 is Yes), the sub CPU 71 returns the communication log data buffer index to the first value (S496). With this processing, this buffer functions as a ring buffer.

  After the process of S496, the sub CPU 71 ends the main board communication reception data log temporary area saving process, and moves the process to S482 of the main board communication reception data log saving process (see FIG. 103).

[Main board communication error history data saving process]
Next, with reference to FIG. 105, the main board communication error history data storage process performed in S482 in the flowchart (see FIG. 103) of the main board communication reception data log storage process will be described. FIG. 105 is a flowchart showing a procedure of main board communication error history data storage processing in the present embodiment.

  First, the sub CPU 71 obtains a storage buffer selection index in the communication error storage buffer area 73g (see FIG. 16) (S501). Next, the sub CPU 71 selects a communication error storage buffer based on the storage buffer selection index (S502).

  Next, the sub CPU 71 determines whether or not a communication error (COM error) has occurred (S503).

  In S503, when the sub CPU 71 determines that a communication error (COM error) has occurred (when S503 is Yes), the sub CPU 71 (received data log storage unit 71e) selects the communication error storage buffer selected in S502. The communication log relating to the communication error is stored (S504). Next, the sub CPU 71 updates the selected buffer index (S505). Then, after the processing of S505, the sub CPU 71 ends the main board communication error history data storage process and also ends the main board communication reception data log storage process (see FIG. 103).

  On the other hand, in S503, when the sub CPU 71 determines that a communication error (COM error) has not occurred (S503: No), the sub CPU 71 acquires the selected buffer index (S506). Next, the sub CPU 71 determines whether or not reception data is being collected (S507).

  When the sub CPU 71 determines in S507 that the received data is not being collected (when S507 is No), the sub CPU 71 ends the main board communication error history data saving process and saves the main board communication received data log. The processing (see FIG. 103) is also terminated. On the other hand, when the sub CPU 71 determines that the received data is being collected in S507 (when S507 is Yes), the sub CPU 71 determines whether or not the buffer index value is the upper limit value (S508). ). In the present embodiment, the buffer index value is “0” to “255”, and the upper limit value is “255”.

  In S508, when the sub CPU 71 determines that the value of the buffer index is not the upper limit (when S508 is No), the sub CPU 71 stores the received data in the communication error storage buffer selected in S502 (S509). . Next, the sub CPU 71 updates the selected buffer index (S510). After the processing of S510, the sub CPU 71 ends the main board communication error history data storage process and also ends the main board communication reception data log storage process (see FIG. 103).

  On the other hand, when the sub CPU 71 determines that the value of the buffer index is the upper limit value in S508 (when S508 is Yes), the sub CPU 71 acquires the storage buffer selection index (S511). Next, the sub CPU 71 determines whether or not the value of the storage buffer selection index is an upper limit value (S512). In the present embodiment, the upper limit value of the storage buffer selection index is “1024”.

  In S512, when the sub CPU 71 determines that the value of the storage buffer selection index is the upper limit value (when S512 is Yes), the sub CPU 71 ends the main board communication error history data saving process and The communication reception data log saving process (see FIG. 103) is also terminated. On the other hand, when the sub CPU 71 determines in S512 that the value of the storage buffer selection index is not the upper limit value (when S512 is No), the sub CPU 71 updates the storage buffer selection index (S513). In this process, the sub CPU 71 adds “1” to the storage buffer selection index.

  Then, after the processing of S513, the sub CPU 71 ends the main board communication error history data storage process and also ends the main board communication reception data log storage process (see FIG. 103).

[Main board communication reception command check processing]
Next, with reference to FIG. 106, the main board communication reception command check process performed in S473 in the main board communication task flowchart (see FIG. 102) will be described. FIG. 106 is a flowchart showing a procedure of main board communication reception command check processing in the present embodiment.

  First, the sub CPU 71 acquires received data (S521). Next, the sub CPU 71 sets a received command check table (S522). Next, the sub CPU 71 obtains the previous (preceding time) reception data (S523).

  Then, the sub CPU 71 sets a command check counter (S524). Next, the sub CPU 71 acquires confirmation data from a reception protocol confirmation data table (not shown) (S525). That is, in this process, a table of received commands and previous received commands shown in FIG. 27 is acquired.

  Next, the sub CPU 71 checks the table of the received command and the previous received command acquired in S525, and determines whether or not the received command is a command when the operation procedure is a normal procedure performed in a normal game. A determination is made (S526). For example, when the received command is a command of the type “BET: game medal insertion” defined in “03H” of the “Data” column in the table shown in FIG. 27, the previous received command is the type “Demo Display”. ”,“ BET ”,“ payout end ”,“ bonus start ”, or“ error ”, the sub CPU 71 determines that the operation procedure is in the normal order.

  In S526, when the sub CPU 71 determines that the received command is a command in the normal order (when S526 is Yes), the sub CPU 71 ends the main board communication reception command check process, and the process is performed by the main board communication. The process moves to S474 of the task (see FIG. 102).

  On the other hand, when the sub CPU 71 determines in S526 that the received command is not a command in the normal order (when S526 is No), the sub CPU 71 updates the received command check table (S527). Specifically, for example, when the received data is a command of type “display” defined in “07H” of the “Data” column in the table shown in FIG. If it is not “stop” but “winning operation”, it is determined that the operation procedure is not performed in a normal game, and the received command check table is updated.

  After the processing of S527, the sub CPU 71 subtracts the command check counter (S528). Next, the sub CPU 71 determines whether or not the command check is finished (S529). In this process, the sub CPU 71 determines that the command check is completed when the command check counter becomes equal to or less than a threshold value such as “0”, for example.

  In S529, when the sub CPU 71 determines that the command check has not ended (when S529 is No), the sub CPU 71 returns the process to S525 and repeats the processes after S525. On the other hand, when the sub CPU 71 determines in S529 that the command check has been completed (in the case where S529 is Yes), the sub CPU 71 (error information registration means 71d) sets the error procedure error (sequence error) occurrence information as an error. Registration is made in the information history storage area 73e (see FIGS. 11 and 12) (S530). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to the sequence error.

  Then, after the process of S530, the sub CPU 71 ends the main board communication reception command check process, and moves the process to S474 of the main board communication task (see FIG. 102).

[COM error check processing]
Next, referring to FIG. 107, the COM error check process performed in S479 in the main board communication task flowchart (see FIG. 102) will be described. FIG. 107 is a flowchart showing the procedure of the COM error check process in this embodiment.

  First, the sub CPU 71 executes the main board communication reception data log saving process described with reference to FIG. 103 (S541). At this point, since it is determined that a COM error has occurred in S503 during the main board communication error history data storage process of FIG. 105, the sub CPU 71 (reception data log storage means 71e) stores the selected communication error. A communication log related to the communication error is stored in the buffer (S504 in FIG. 105).

  Next, the sub CPU 71 determines whether or not the COM error timer is counting (S542).

  When the sub CPU 71 determines that the COM error timer is not being counted in S542 (when S542 is No), the sub CPU 71 sets the count start of the COM error timer (S546). Then, after the process of S546, the sub CPU 71 ends the COM error check process, and moves the process to S462 of the main board communication task (see FIG. 102).

  On the other hand, when the sub CPU 71 determines that the COM error timer is counting in S542 (when S542 is Yes), the sub CPU 71 determines whether or not the COM error timer is within 30 minutes ( S543).

  In S543, when the sub CPU 71 determines that the COM error timer is not within 30 minutes (when S543 is No), the sub CPU 71 sets the count start of the COM error timer (S546). Then, after the process of S546, the sub CPU 71 ends the COM error check process, and moves the process to S462 of the main board communication task (see FIG. 102).

  On the other hand, in S543, when the sub CPU 71 determines that the COM error timer is within 30 minutes (when S543 is Yes), the sub CPU 71 (error information registration means 71d) displays the communication error alarm occurrence information (“ COM ERR ALM ") is registered in the error information history storage area 73e (see FIG. 12) (S544). At this time, the sub CPU 71 registers the error occurrence date and time and the release date and time in the error information history storage area 73e together with the error code corresponding to the occurrence of the communication error alarm.

  Next, the sub CPU 71 sets the count stop of the COM error timer (S545). Then, after the process of S545, the sub CPU 71 ends the COM error check process, and moves the process to S462 of the main board communication task (see FIG. 102).

[Sub CPU power-on processing]
Next, the power-on process of the sub CPU 71 will be described with reference to FIG. FIG. 108 is a flowchart of power-on processing of the sub CPU 71 in the present embodiment.

  The power-on process of the sub CPU 71 is an initialization process in the OS. When the power of the sub CPU 71 is turned on, first the sub CPU initialization is performed to initialize the CPU and internal devices and the peripheral ICs. Processing is executed (S551). Next, the sub CPU 71 executes a start request process of a mother task (see FIG. 110 described later) in order to make various task start requests (S552).

  Next, the sub CPU 71 executes a sub RAM management process (see FIG. 112 described later) (S553). Next, the sub CPU 71 registers the power recovery time (occurrence date and time of the error code “POWER UP”) in the error information history storage area 73e as error information (S554). More specifically, the sub CPU 71 (error information registration means 71d) registers the occurrence date and time of power recovery in the error information history storage area 73e together with an error code corresponding to power recovery. Then, after the process of S554, the sub CPU 71 ends the power-on process.

[Sub CPU power interruption processing]
In the present embodiment, as shown in FIG. 9, a power interruption detection circuit 90 is provided in the sub control circuit 70. When the power failure detection circuit 90 detects the occurrence of power failure (for example, the power supply voltage has dropped to 4.5V), as described above, the power failure detection circuit 90 generates a power failure detection signal as an interrupt signal. Is output. And sub CPU71 will perform a power interruption interruption process, if an interruption signal is inputted from an external interruption port (NMI).

  Here, the power interruption interrupt processing of the sub CPU 71 will be described with reference to FIG. FIG. 109 is a flowchart of the power interruption interrupt process of the sub CPU 71 in this embodiment.

  When a power outage (a drop in power supply voltage) occurs, first, the sub CPU 71 (error information registration means 71d) uses an error occurrence time (occurrence date and time of the error code “POWER DOWN”) as error information to store an error information history 73e is registered (S561). More specifically, the sub CPU 71 (error information registration unit 71d) stores the error code corresponding to the occurrence of power interruption and the date and time of occurrence of power interruption as one error information history (data set) in the error information history storage area 73e. sign up. Next, the sub CPU 71 performs a backup creation process (S562). Details of the backup creation process will be described later with reference to FIG. 113 described later.

  Note that, unlike the main control, in the power interruption interruption process of the sub CPU 71, the sub CPU 71 does not calculate the sum value. The calculation of the sum value by the sub CPU 71 is performed, for example, every time a valid command is received or when the effect mode is changed.

[Mother task]
Next, a mother task by the sub CPU 71 will be described with reference to FIG. FIG. 110 is a flowchart of the mother task performed by the sub CPU 71 in this embodiment. Note that the mother task request process shown in FIG. 110 is a process of making a task activation request necessary for the function of the pachislot 1 to the OS.

  First, the sub CPU 71 issues a main task activation request (S571). Next, the sub CPU 71 issues an accessory control task activation request as a subtask activation request (S572). Next, the sub CPU 71 issues a lamp control task activation request (S573). Next, the sub CPU 71 issues a sound control task activation request (S574).

  Next, the sub CPU 71 makes a start request for the main board communication task (S575). Next, the sub CPU 71 makes an animation task activation request (S576). Next, the sub CPU 71 makes an activation request for the inter-subdevice communication control task (S577).

  Next, the sub CPU 71 makes an activation request for the RTC control task (S578). Then, the sub CPU 71 makes a request for starting the fraud monitoring processing task (S579).

  In the processing of the mother task described above, for example, when a main board communication task request is generated from the OS in response to a request for starting the main board communication task by the sub CPU 71, the main board communication task is executed along the procedure described in FIG. Executed.

[RTC control task]
Next, an RTC control task by the sub CPU 71 will be described with reference to FIG. FIG. 111 is a flowchart of the RTC control task in the present embodiment.

  First, the sub CPU 71 sets a period of 100 msec as an OS management period (S581). Next, the sub CPU 71 reads date / time information from the external RTC 70b (S582). Next, the sub CPU 71 sets the read date and time information of the external RTC 70b as an initial value of the date and time information of the built-in RTC 70a (S583).

  Next, the sub CPU 71 reads status information from the external RTC 70b (S584). Next, the sub CPU 71 determines whether or not the status information has been successfully read (S585).

  In S585, when the sub CPU 71 determines that the status information cannot be read normally (when S585 is No), the sub CPU 71 performs processing of S591 described later. On the other hand, when the sub CPU 71 determines in S585 that the status information has been successfully read (in the case where S585 is Yes), the sub CPU 71 determines whether or not there is an abnormality in the power supply (S586).

  When the sub CPU 71 determines that there is an abnormality in the power supply in S586 (in the case where S586 is Yes), the sub CPU 71 performs a process of S591 described later. On the other hand, when the sub CPU 71 determines that there is no abnormality in the power source in S586 (when S586 is No), the sub CPU 71 determines whether there is an oscillation abnormality (S587).

  In S587, when the sub CPU 71 determines that there is an oscillation abnormality (when S 587 is Yes), the sub CPU 71 performs a process of S591 described later. On the other hand, when the sub CPU 71 determines that there is no oscillation abnormality in S587 (when S587 is No), the sub CPU 71 determines whether or not a reset signal has been detected (S588).

  In S588, when the sub CPU 71 determines that a reset signal has been detected (Yes in S 588), the sub CPU 71 performs processing of S591 described later. On the other hand, when it is determined in S588 that the sub CPU 71 has not detected the reset signal (when S 588 is No), the sub CPU 71 reads the date / time information from the external RTC 70b (S589).

  Next, the sub CPU 71 determines whether or not there is an abnormality in the range of the read date and time information (S590). In this process, for example, when the value of “year”, “month”, “day”, or “time” exceeds two digits, the sub CPU 71 determines that the date and time range is abnormal.

  In S590, when the sub CPU 71 determines that there is an abnormality in the range of the read date and time information (when S 590 is Yes), the sub CPU 71 performs the process of S591 described later. On the other hand, when the sub CPU 71 determines that there is no abnormality in the range of the read date / time information in S590 (when S590 is No), the sub CPU 71 performs the process of S593 described later.

  If S585 is No, or if S586, S587, S588, or S590 is Yes, the sub CPU 71 registers an error code corresponding to the type of the RTC error in the error information history storage area 73e of the sub RAM 73 as error information. (S591).

  Specifically, when S585 is No (when the status information cannot be normally read from the external RTC 70b), the sub CPU 71 determines that the error code “RTC DSC” corresponding to “RTC communication error” (see FIG. 13). ) Is registered in the error information history storage area 73e. When the determination of S586 is Yes (when there is an abnormality in the power supply regarding the external RTC 70b), the sub CPU 71 displays an error code “RTC POWER” (see FIG. 13) corresponding to “RTC voltage drop” in the error information history storage area 73e. sign up. When S587 is Yes (when there is an oscillation abnormality with respect to the external RTC 70b), the sub CPU 71 stores an error code “RTC CLK” (see FIG. 13) corresponding to “RTC oscillation stop detection” in the error information history storage area 73e. sign up. When S588 is Yes (when a reset signal is detected), the sub CPU 71 registers an error code “RTC RESET” (see FIG. 13) corresponding to “RTC reset detection” in the error information history storage area 73e. If S590 is Yes (when the date / time range is abnormal), the sub CPU 71 displays an error code “RTC TIM” (see FIG. 13) corresponding to “RTC time abnormality” in the error information history storage area 73e. sign up. In the process of S591, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to each error event.

  After the processing of S591, the sub CPU 71 initializes the external RTC 70b, and sets the current date / time information of the internal RTC 70a to the date / time information of the external RTC 70b (S592).

  After the processing of S592 or when S590 is No, the sub CPU 71 determines whether or not the date / time information setting of the external RTC 70b has been changed from the clerk operation screen (S593).

  In S593, when the sub CPU 71 determines that the date / time information setting of the external RTC 70b has not been changed from the clerk operation screen (when S593 is No), the sub CPU 71 performs the process of S595 described later. On the other hand, in S593, when the sub CPU 71 determines that the setting of the date and time information of the external RTC 70b has been changed from the clerk operation screen (when S593 is Yes), the sub CPU 71 uses the date and time data of the built-in RTC 70a. The external RTC 70b is set (S594).

  After the processing of S594 or when S593 is No, the sub CPU 71 waits for a cycle of 100 msec (S595). After the process of S595, the sub CPU 71 returns the process to S584 and repeats the processes after S584.

[Sub RAM management processing]
Next, the sub RAM management processing (management processing of the backup RAM (SRAM) 74) by the sub CPU 71 will be described with reference to FIG. FIG. 112 is a flowchart of sub-RAM management processing in the present embodiment.

  First, the sub CPU 71 calculates the sum value of the first backup data area 74a of the backup RAM 74 (see FIG. 17), and obtains the 4-byte first backup data sum value (S601). Next, the sub CPU 71 has the normal first backup data sum value acquired, and the magic code of the first backup data area 74a and the magic code of the program management data area 72f of the sub ROM 72 (see FIG. 10) are the same. It is determined whether or not (S602).

  In S602, when the sub CPU 71 determines that the determination condition of S602 is satisfied (when S602 is YES), the sub CPU 71 transfers the data in the first backup data area 74a of the backup RAM 74 to the sub RAM 73 (see FIG. 11). Copy to the control game data area 73a (S603). Then, after the processing of S603, the sub CPU 71 performs processing of S609 described later.

  On the other hand, when it is determined in S602 that the sub CPU 71 does not satisfy the determination condition of S602 (when S602 is No), the sub CPU 71 determines the sum of the second backup data area 74c that is mirroring of the first backup data area 74a. The value is calculated to obtain a 4-byte second backup data sum value (S604). Next, the sub CPU 71 determines whether or not the acquired second backup data sum value is normal and the magic code in the second backup data area 74c and the magic code in the program management data area 72f of the sub ROM 72 are the same. Is discriminated (S605).

  In S605, when the sub CPU 71 determines that the determination condition of S605 is satisfied (when S605 is Yes), the sub CPU 71 transfers the data in the second backup data area 74c of the backup RAM 74 to the sub control game data area 73a of the sub RAM 73. (S606). Then, after the processing of S606, the sub CPU 71 performs processing of S608 described later.

  On the other hand, when the sub CPU 71 determines that the determination condition of S 605 is not satisfied in S 605 (when S 605 is No), the sub CPU 71 stores the data in the game data initialization setting data area 72 c of the sub ROM 72 in the sub RAM 73. Copy to the control game data area 73a (S607).

  After the processing in S606 or S607, the sub CPU 71 registers the error code “MEM ERR1” (see FIG. 13) corresponding to “abnormal backup sum (game)” in the error information history storage area 73e (S608). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “abnormal backup sum (game)”. At this time, the screen as shown in FIG. 21 for notifying the RAM data abnormality is not displayed.

  Next, after the processing of S603 or S608, the sub CPU 71 calculates the sum value of the clerk backup data area 74e of the backup RAM 74 and obtains the 4-byte clerk backup data sum value (S609). The sub CPU 71 stores the clerk backup data sum value in the clerk backup data sum value area 74f.

  Next, the sub CPU 71 determines whether or not the sum value of the stored clerk backup data area 74e is normal (S610).

  In S610, when the sub CPU 71 determines that the sum value of the clerk backup data area 74e is normal (when S610 is Yes), the sub CPU 71 transfers the data in the clerk backup data area 74e to the sub RAM 73 (DRAM). Copy to the clerk operation setting data area 73d (S611). Then, after the process of S611, the sub CPU 71 performs a process of S614 described later.

  On the other hand, when the sub CPU 71 determines in S610 that the sum value of the clerk backup data area 74e is not normal (when S610 is No), the sub CPU 71 stores the data in the clerk operation initial setting data area 72d of the sub ROM 72. The data is copied to the staff operation setting data area 73d of the sub RAM 73 (S612). Next, the sub CPU 71 registers the error code “MEM ERR2” (see FIG. 13) corresponding to “abnormal backup sum (person)” in the error information history storage area 73e (S613). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “abnormal backup sum (personnel)”. Also at this time, the screen as shown in FIG. 21 for notifying the RAM data abnormality is not displayed.

  Then, after the process of S611 or S613, the sub CPU 71 performs a backup creation process (S614). Details of the backup creation process will be described later with reference to FIG. 113 described later.

  As described above, in the sub RAM management processing of this embodiment, the sub CPU 71 has a normal sum value, and the magic code in the second backup data area 74c and the magic in the program management data area 72f in the sub ROM 72 are stored. It is determined whether or not the code is the same. If at least one of the sum value and the magic code is not satisfied, the sub CPU 71 copies the data in the game data initialization setting data area 72 c in the sub ROM 72 to the sub control game data area 73 a in the sub RAM 73.

  In this embodiment, the sub CPU 71 determines whether or not the sum value in the clerk backup data area 74e is normal. If the sum value is abnormal, the sub CPU 71 sets the clerk operation initial setting data area 72d in the sub ROM 72. Is copied to the clerk operation setting data area 73 d of the sub RAM 73.

  With these processes, in the present embodiment, it is possible to confirm whether or not the data in the sub RAM 73 is damaged when the power is turned on, and without using the data in the damaged backup RAM (SRAM) 74, The initial value can be set automatically.

[Backup creation process]
Next, referring to FIG. 113, the process is performed in S156 during the effect registration process shown in FIG. 79, S562 during the power interruption interrupt process shown in FIG. 109, and S614 during the sub-RAM management process shown in FIG. The backup creation process will be described. FIG. 113 is a flowchart of backup creation processing in the present embodiment. With this processing, correct data can be stored as backup data even if the data is destroyed.

  First, the sub CPU 71 creates a sum value in the sub control game data area 73a (see FIG. 11) of the sub RAM 73 (DRAM), and stores the created sum value in the sub control game data sum value area 73b (S621). . Next, the sub CPU 71 copies the data in the sub control game data area 73a to the first backup data area 74a (see FIG. 17) of the backup RAM 74 (SRAM), and uses the sum value stored in S621 as the first backup data sum value. Save in the area 74b (S622).

  Next, the sub CPU 71 copies the data of the sub control game data area 73a to the second backup data area 74c which is the mirroring of the first backup data area 74a, and the sum value stored in S621 is the second backup data sum value area. 74d is stored (S623).

  Next, the sub CPU 71 creates a sum value in the clerk operation setting data area 73d of the sub RAM 73 (DRAM), and stores the created sum value in the clerk operation setting data sum value area in the clerk operation setting data area 73d. (S624).

  Next, the sub CPU 71 copies the data in the clerk operation setting data area 73d to the clerk backup data area 74e of the backup RAM 74 (SRAM), and saves the sum value stored in S624 in the clerk backup data sum value area 74f (S625). ). Then, after the process of S625, the sub CPU 71 ends the backup creation process.

[Sub-device communication control task]
Next, an inter-subdevice communication control task by the sub CPU 71 will be described with reference to FIG. FIG. 114 is a flowchart of the inter-subdevice communication control task in this embodiment.

  First, the sub CPU 71 sets a period of 4 msec (S631). Next, the sub CPU 71 collectively performs initial setting of the sub device serial port (S632). Then, the sub CPU 71 waits for a cycle of 4 msec (S633).

  Next, the sub CPU 71 performs a sub device command reception process (S634). Details of the sub-device command reception process will be described later with reference to FIG. 115 described later. Next, the sub CPU 71 determines whether or not a command has been received (S635).

  In S635, when it is determined that the sub CPU 71 has received the command (S635 is Yes), the sub CPU 71 performs a sub device communication return process (S636). Details of the sub-device communication return processing will be described later with reference to FIG. 116 described later. Next, the sub CPU 71 performs a sub device communication reception process (S637). Details of the sub-device communication reception process will be described later with reference to FIG. 117 described later.

  After the processing of S637, the sub CPU 71 determines whether there is a command to be transmitted (S638). When the sub CPU 71 determines that there is no command to be transmitted in S638 (when S638 is No), the sub CPU 71 returns the process to S633 and repeats the processes after S633. On the other hand, when the sub CPU 71 determines in S638 that there is a command to be transmitted (when S638 is Yes), the sub CPU 71 performs a sub device command transmission process (S639). Then, after the process of S639, the sub CPU 71 returns the process to S633, and repeats the processes after S633.

  Here, returning to the process of S635 again, when it is determined in S635 that the sub CPU 71 has not received the command (S635 is No), the sub CPU 71 performs a sub-device communication disconnection process (S640). . The details of the sub-device communication disconnection process will be described later with reference to FIG. 121 described later. Then, after the processing of S640, the sub CPU 71 returns the processing to S633, and repeats the processing after S633.

[Subdevice command reception processing]
Next, with reference to FIG. 115, the subdevice command reception process performed in S634 in the flowchart of the intersubdevice communication control task (see FIG. 114) will be described. FIG. 115 is a flowchart showing a procedure of sub-device command reception processing in the present embodiment.

  First, the sub CPU 71 sets a reception buffer address in the communication log collection ring buffer area 73f (see FIG. 15), and turns off the STX reception flag (S651). Next, the sub CPU 71 attempts to obtain 1 byte of received data from the communication log collection ring buffer area 73f (S652). Then, the sub CPU 71 determines whether there is received data (S653).

  In S653, when the sub CPU 71 determines that there is no received data (when S653 is No), the sub CPU 71 performs the process of S665 described later. On the other hand, when the sub CPU 71 determines that there is received data in S653 (when S653 is Yes), the sub CPU 71 determines whether the received data is STX and the STX reception flag is off. Is discriminated (S654).

  In S654, when the sub CPU 71 determines that the determination condition of S654 is satisfied (when S654 is Yes), the sub CPU 71 turns on the STX reception flag (S655). Next, the sub CPU 71 clears the command registration buffer (S656). Next, the sub CPU 71 updates the reception buffer address and adds 1 byte (S657). Then, after the processing of S657, the sub CPU 71 returns the processing to S652, and repeats the processing after S652. This iterative process is repeated for the number of data.

  On the other hand, when the sub CPU 71 determines in S654 that the determination condition in S654 is not satisfied (when S654 is No), the sub CPU 71 determines that the received data is ETX and the STX reception flag is on. It is determined whether or not there is (S658).

  In S658, when the sub CPU 71 determines that the determination condition of S658 is satisfied (in the case where S658 is Yes), the sub CPU 71 creates a sum value from the received data, and also stores the received data stored in the reception buffer. The thumb value is acquired (S659). Next, the sub CPU 71 compares the sum value created in S659 with the sum value stored in the reception buffer, and determines whether or not the sum value of the received data is normal (S660).

  In S660, when the sub CPU 71 (sub device error detecting means 71h) determines that the sum value of the received data is normal (when S660 is Yes), the sub CPU 71 ends the sub device command receiving process, The processing moves to S635 of the inter-subdevice communication control task (see FIG. 114). On the other hand, when the sub CPU 71 (sub device error detecting means 71h) determines in S660 that the sum value of the received data is not normal (when S660 is No), the sub CPU 71 responds to “sub device SUM error”. The error code “SD COM SUM” (see FIG. 14) to be registered is registered in the error information history storage area 73e (S661). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “sub device SUM abnormality”.

  Then, after the processing of S661, the sub CPU 71 ends the sub device command reception processing, and moves the processing to S635 of the inter-subdevice communication control task (see FIG. 114).

  Here, returning to the process of S658 again, in S658, when the sub CPU 71 determines that the determination condition of S658 is not satisfied (when S658 is No), the sub CPU 71 receives the received data as ETX, Further, it is determined whether or not the STX reception flag is OFF (S662).

  In S662, when the sub CPU 71 determines that the determination condition of S662 is satisfied (when S662 is Yes), the sub CPU 71 performs the process of S665 described later. On the other hand, when the sub CPU 71 determines in S662 that the determination condition in S662 is not satisfied (when S662 is No), the sub CPU 71 stores the received data in the command registration buffer (S663). Next, the sub CPU 71 updates the reception buffer address and adds 1 byte (S664). Then, after the processing of S664, the sub CPU 71 returns the processing to S652, and repeats the processing after S652. This iterative process is repeated for the number of data.

  If S653 is No, or if S662 is Yes, the sub CPU 71 registers the error code “SD COM STX” (see FIG. 14) corresponding to these cases in the error information history storage area 73e. (S665). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to each error event. After the process of S665, the sub CPU 71 ends the sub device command reception process, and moves the process to S635 of the inter-sub-device communication control task (see FIG. 114).

[Subdevice communication recovery processing]
Next, with reference to FIG. 116, the subdevice communication return process performed in S636 in the flowchart of the intersubdevice communication control task (see FIG. 114) will be described. FIG. 116 is a flowchart showing the procedure of the sub-device communication return process in this embodiment.

  First, the sub CPU 71 determines whether or not the transmission source ID of the received command is the scaler control board 80 (S671).

  In S671, when the sub CPU 71 determines that the transmission source ID of the received command is not the scaler control board 80 (when S671 is No), the sub CPU 71 ends the sub device communication return processing, and the processing is performed by the sub device. The process proceeds to S637 of the inter-communication control task (see FIG. 114). On the other hand, when the sub CPU 71 determines in S671 that the transmission source ID of the received command is the scaler control board 80 (when S671 is Yes), the sub CPU 71 determines whether the scaler communication disconnection flag is on. It is determined whether or not (S672).

  In S672, when the sub CPU 71 (sub device error detecting unit 71h) determines that the scaler communication disconnection flag is not on (when S672 is No), the sub CPU 71 performs the process of S674 described later. On the other hand, when the sub CPU 71 (sub device error detecting means 71h) determines in S672 that the scaler communication disconnection flag is on (when S672 is Yes), the sub CPU 71 corresponds to “communication restart”. The error code “SCL RSM” (see FIG. 14) is registered in the error information history storage area 73e (S673). At this time, the sub CPU 71 registers the occurrence date and time of the event in the error information history storage area 73e together with the error code corresponding to “communication restart”.

  After the process of S673 or when S672 is No, the sub CPU 71 turns off the scaler communication disconnection flag and clears the scaler communication disconnection counter to “0” (S674). Then, after the processing of S674, the sub CPU 71 ends the sub device communication return processing, and shifts the processing to S637 of the inter sub device communication control task (see FIG. 114).

[Sub-device communication reception processing]
Next, with reference to FIG. 117, the sub-device communication reception process performed in S637 in the inter-subdevice communication control task flowchart (see FIG. 114) will be described. FIG. 117 is a flowchart illustrating a procedure of sub-device communication reception processing in the present embodiment.

  First, the sub CPU 71 obtains a device ID from “ADR” of the command stored in the command registration buffer (S681). Next, the sub CPU 71 determines whether or not the transmission destination of the device ID is the sub CPU 71 (S682).

  In S682, when the sub CPU 71 (sub device error detecting means 71h) determines that the transmission destination of the device ID is not the sub CPU 71 (when S682 is No), the sub CPU 71 performs the process of S685 described later. On the other hand, when the sub CPU 71 (sub device error detecting unit 71h) determines in S682 that the transmission destination of the device ID is the sub CPU 71 (when S682 is Yes), the sub CPU 71 determines that the transmission source of the device ID is It is determined whether or not the scaler control board 80 is a scaler control LSI (S683).

  In S683, when the sub CPU 71 determines that the transmission source of the device ID is not the scaler control LSI of the scaler control board 80 (when S683 is No), the sub CPU 71 performs the process of S685 described later. On the other hand, when the sub CPU 71 determines in S683 that the transmission source of the device ID is the scaler control LSI of the scaler control board 80 (when S683 is Yes), the sub CPU 71 performs a process at the time of receiving the scaler control command. (S684). Details of the processing at the time of receiving the scaler control command will be described later with reference to FIG. 118 described later.

  Then, after the process of S684, the sub CPU 71 ends the process at the time of reception of the sub device communication, and moves the process to S638 of the inter sub device communication control task (see FIG. 114).

  If S682 or S683 is No, the sub CPU 71 registers an error code “SD COM DVC” (see FIG. 14) corresponding to “sub device ID error” in the error information history storage area 73e (S685). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “sub device ID abnormality”. Then, after the process of S685, the sub CPU 71 ends the process at the time of reception of the sub device communication, and moves the process to S638 of the inter sub device communication control task (see FIG. 114).

[Processing when receiving scaler control command]
Next, with reference to FIG. 118, the processing at the time of receiving the scaler control command performed at S684 in the flowchart (see FIG. 117) of the processing at the time of receiving the sub device communication will be described. FIG. 118 is a flowchart showing a procedure of processing at the time of receiving a scaler control command in the present embodiment.

  First, the sub CPU 71 reads the sub device communication check table (sub device communication data consistency check table) shown in FIG. 20 from the various program table areas 72e of the sub ROM 72, and sets it in the work area 73c of the sub RAM 73 (DRAM). (S691). Next, the sub CPU 71 passes the set table as an argument for the reception data determination process of the next processing step, thereby executing the sub device reception data determination process (S692). Details of the sub-device received data determination process will be described later with reference to FIG. 119 described later.

  Next, the sub CPU 71 determines whether or not the reception data after the sub device reception data determination process is normal (S693). When the sub CPU 71 (sub device error detecting means 71h) determines in S693 that the received data is not normal (the received data is inconsistent) (when S693 is No), the sub CPU 71 determines that the sub device (scalar) Based on the error information returned as a return value from the control board 80), the corresponding error code (see the error code in FIG. 14) is registered (S694). At this time, the sub CPU 71 registers the error occurrence date and time together with the error code in the error information history storage area 73e. Then, after the processing of S694, the sub CPU 71 ends the process at the time of receiving the scaler control command, and also ends the process at the time of receiving the sub device communication.

  On the other hand, when the sub CPU 71 (sub device error detecting means 71h) determines that the received data is normal (no error code) in S693 (when S693 is Yes), the sub CPU 71 determines that the CMD of the received data is It is determined whether or not the request is a “startup parameter request” (S695).

  In S695, when the sub CPU 71 determines that the CMD of the received data is “activation parameter request” (when S695 is Yes), the sub CPU 71 sets a scaler activation parameter request confirmation command in the sub device transmission buffer. (S696). Next, the sub CPU 71 sets the scaler setting phase to “1” (S697). Then, after the process of S697, the sub CPU 71 ends the process at the time of receiving the scaler control command, and also ends the process at the time of receiving the sub device communication.

  On the other hand, in S695, when the sub CPU 71 determines that the CMD of the received data is not “activation parameter request” (when S695 is No), the sub CPU 71 determines whether or not the CMD of the received data is “reception confirmation”. Is discriminated (S698).

  In S698, when the sub CPU 71 determines that the CMD of the received data is “reception confirmation” (in the case where S698 is Yes), the sub CPU 71 performs a scaler control setting process (S699). Details of the scaler control setting process will be described later with reference to FIG. 120 described later. Then, after the processing of S699, the sub CPU 71 ends the process at the time of receiving the scaler control command, and also ends the process at the time of receiving the sub device communication.

  On the other hand, in S698, when the sub CPU 71 determines that the CMD of the received data is not “reception confirmation” (when S698 is No), the sub CPU 71 determines whether or not the CMD of the received data is “reset notification”. Is discriminated (S700). In S700, when the sub CPU 71 (sub device error detecting means 71h) determines that the CMD of the received data is not “reset notification” (when S700 is No), the sub CPU 71 ends the process at the time of receiving the scaler control command. At the same time, the sub-device communication reception process is also terminated.

  On the other hand, in S700, when the sub CPU 71 (sub device error detecting unit 71h) determines that the CMD of the received data is “reset notification” (when S700 is Yes), the sub CPU 71 sets “reset generation”. The corresponding error code “SCL RST” (see FIG. 14) is registered in the error information history storage area 73e (S701). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “reset occurrence”. Then, after the processing of S701, the sub CPU 71 ends the processing at the time of receiving the scaler control command, and also ends the processing at the time of receiving the sub device communication.

[Sub-device received data judgment processing]
Next, with reference to FIG. 119, the sub-device received data determination process performed in S692 in the flowchart (see FIG. 118) of the scaler control command reception process will be described. FIG. 119 is a flowchart illustrating a procedure of sub-device reception data determination processing in the present embodiment.

  First, the sub CPU 71 acquires the size of the DATA part of the reception buffer (S711). At this time, the sub CPU 71 passes the target position address of the sub device communication check table shown in FIG. 20 as an argument address to various program table areas 72e of the sub ROM 72 (see FIG. 10). Regarding the scaler, No. in the sub-device communication check table. The position corresponds to 2. Then, the sub CPU 71 checks the presence / absence and size of the received data based on this.

  Next, the sub CPU 71 determines whether or not the DATA size is 256 bytes or less (S712).

  In S712, when the sub CPU 71 (sub device error detecting means 71h) determines that the DATA size is not 256 bytes or less (when S712 is No), the sub CPU 71 corresponds to “data size error (257 or more)”. The error code “SCL COM SIZ” (see FIG. 14) to be registered is registered in the error information history storage area 73e (S713). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “data size abnormality (257 or more)”. Then, after the processing of S713, the sub CPU 71 ends the sub device reception data determination processing, and shifts the processing to S693 of processing at the time of receiving the scaler control command (see FIG. 118).

  On the other hand, when the sub CPU 71 (sub device error detecting means 71h) determines in S712 that the DATA size is 256 bytes or less (when S712 is Yes), the sub CPU 71 checks the sub device communication check table (FIG. 20). In step S714, it is determined whether there is a type registration.

  In S714, when the sub CPU 71 determines that the type is not registered in the sub device communication check table (when S712 is No), the sub CPU 71 determines that the error code “SCL COM TYP” corresponding to “command type error” ( 14) is registered in the error information history storage area 73e (S722). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “command type abnormality”. After the process of S722, the sub CPU 71 ends the sub device reception data determination process, and moves the process to S693 of the scaler control command reception process (see FIG. 118).

  On the other hand, in S714, when the sub CPU 71 determines that there is a type registration in the sub device communication check table (in the case of Yes determination in S712), the sub CPU 71 determines the CMD type in the sub device communication check table (see FIG. 20). Determination conditions are acquired (S715). Next, the sub CPU 71 determines whether or not the CMD type of the received data matches the determination condition (S716).

  In S716, when the sub CPU 71 determines that the CMD type of the received data does not match the determination condition (when S716 is No), the sub CPU 71 updates the check table (S717). In this process, for example, the check table is updated from the CMD of “determination 1” to the CMD of “determination 2”. Then, after the processing of S717, the sub CPU 71 returns the processing to S714 and repeats the processing after S714.

  On the other hand, when the sub CPU 71 determines that the CMD type of the received data matches the determination condition in S716 (when S716 is Yes), the sub CPU 71 updates the check table to determine the DATA determination corresponding to the CMD. (S718). In this processing, for example, in the case of “determination 3” for the scaler, No. The check table is updated to the position of “determination 3” in 2. Next, the sub CPU 71 acquires a determination condition regarding the DATA size from the check table (S719).

  Next, the sub CPU 71 determines whether or not the DATA size of the received data matches the determination condition (S720).

  In S720, when the sub CPU 71 (sub device error detecting means 71h) determines that the DATA size of the received data matches the determination condition (when S720 is Yes), the sub CPU 71 ends the sub device received data determination processing. Then, the process shifts to S693 of the scaler control command reception process (see FIG. 118). On the other hand, when the sub CPU 71 (sub device error detecting means 71h) determines in S720 that the DATA size of the received data does not match the determination condition (when S720 is No), the sub CPU 71 determines that the packet size is abnormal. The error code “SCL COM PKT” (see FIG. 14) corresponding to is registered in the error information history storage area 73e (S721). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “abnormal packet size”.

  After the process of S721, the sub CPU 71 ends the sub device reception data determination process, and moves the process to S693 of the scaler control command reception process (see FIG. 118).

[Scaler control setting process]
Next, with reference to FIG. 120, the scaler control setting process performed in S699 in the flowchart (see FIG. 118) of the scaler control command reception process will be described. FIG. 120 is a flowchart showing the procedure of the scaler control setting process in the present embodiment.

  First, the sub CPU 71 determines whether or not the scaler setting phase is “1” (S731).

  When the sub CPU 71 determines that the scaler setting phase is “1” in S731 (when S731 is Yes), the sub CPU 71 sets the luminance setting command data in the sub device transmission buffer and sets the scaler. “2” is set in the phase (S732). Then, after the process of S732, the sub CPU 71 ends the scaler control setting process and also ends the scaler control command reception process (see FIG. 118).

  On the other hand, when the sub CPU 71 determines that the scaler setting phase is not “1” in S731 (when S731 is No), the sub CPU 71 determines whether or not the scaler setting phase is “2” ( S733).

  When the sub CPU 71 determines that the scaler setting phase is “2” in S733 (when S733 is Yes), the sub CPU 71 sets the contour setting command data in the sub device transmission buffer, and sets the scaler. “3” is set in the phase (S734). Next, the sub CPU 71 determines whether or not the luminance setting value setting result is normal (S735).

  In S735, when the sub CPU 71 (sub device error detecting means 71h) determines that the setting result of the brightness setting value is normal (when S735 is Yes), the sub CPU 71 ends the scaler control setting process. The scaler control command reception process (see FIG. 118) is also terminated. On the other hand, when the sub CPU 71 (sub device error detecting unit 71h) determines that the setting result of the brightness setting value is not normal in S735 (when S735 is No), the sub CPU 71 responds to “brightness setting abnormality”. The error code “SCL SET ERR1” (see FIG. 14) to be registered is registered in the error information history storage area 73e (S736). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “brightness setting abnormality”. Then, after the process of S736, the sub CPU 71 ends the scaler control setting process and also ends the scaler control command reception process (see FIG. 118).

  On the other hand, when the sub CPU 71 determines in S733 that the scaler setting phase is not “2” (when S733 is No), the sub CPU 71 determines whether or not the scaler setting phase is “3” ( S737).

  In S737, when the sub CPU 71 determines that the scaler setting phase is “3” (when S737 is Yes), the sub CPU 71 sets the interpolation setting command data in the sub device transmission buffer, and sets the scaler. “4” is set in the phase (S738). Next, the sub CPU 71 determines whether or not the setting result of the contour setting value is normal (S739).

  In S739, when the sub CPU 71 determines that the setting result of the contour setting value is normal (in the case where S739 is Yes), the sub CPU 71 ends the scaler control setting process and receives a scaler control command process ( (See FIG. 118). On the other hand, when the sub CPU 71 determines in S739 that the setting result of the contour setting value is not normal (when S739 is No), the sub CPU 71 determines that the error code “SCL SET ERR2” corresponding to “abnormal contour setting” is detected. (See FIG. 14) is registered in the error information history storage area 73e (S740). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “contour setting abnormality”. Then, after the processing of S740, the sub CPU 71 ends the scaler control setting process and also ends the scaler control command reception process (see FIG. 118).

  On the other hand, in S737, when the sub CPU 71 determines that the scaler setting phase is not “3” (when S737 is No), the sub CPU 71 sets a scaler setting completion command in the sub device transmission buffer, and the scaler. The setting phase is cleared to “0” (S741). Next, the sub CPU 71 determines whether or not the interpolation setting value setting result is normal (S742).

  In S742, when the sub CPU 71 determines that the setting result of the interpolation setting value is normal (in the case where S742 is Yes), the sub CPU 71 ends the scaler control setting process and receives the scaler control command ( (See FIG. 118). On the other hand, in S742, when the sub CPU 71 determines that the setting result of the interpolation setting value is not normal (when S742 is No), the sub CPU 71 determines that the error code “SCL SET ERR3” corresponding to “interpolation setting abnormality”. (See FIG. 14) is registered in the error information history storage area 73e (S743). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “interpolation setting abnormality”. Then, after the process of S743, the sub CPU 71 ends the scaler control setting process and also ends the scaler control command reception process (see FIG. 118).

[Subdevice communication disconnection processing]
Next, with reference to FIG. 121, the subdevice communication disconnection process performed in S640 in the flowchart of the intersubdevice communication control task (see FIG. 114) will be described. FIG. 121 is a flowchart showing a procedure of sub-device communication disconnection processing in the present embodiment.

  First, since the inter-subdevice communication control task shown in FIG. 114 is executed at a cycle of 4 msec, the sub CPU 71 updates the value of the scaler communication disconnection counter (adds “1”) at a cycle of 4 msec (S751).

  Next, the sub CPU 71 determines whether or not the value of the scaler communication disconnection counter is equal to or greater than the count value corresponding to the period during which communication disconnection is determined (S752). Specifically, in this embodiment, since the period for which communication is determined to be disconnected is 5 seconds, the count value corresponding to the period for which communication is determined to be disconnected is “1250” (= 5 sec / 4 msec). Therefore, in the process of S752, the sub CPU 71 determines whether or not the value of the scaler communication disconnection counter is “1250” or more.

  In S752, when the sub CPU 71 determines that the value of the scaler communication disconnection counter is less than the count value corresponding to the period during which communication disconnection is determined (when S752 is No), the sub CPU 71 The device communication disconnection process is terminated, and the process proceeds to S633 of the inter-subdevice communication control task (see FIG. 114). On the other hand, when the sub CPU 71 determines in S752 that the value of the scaler communication disconnection counter is equal to or greater than the count value corresponding to the period during which communication disconnection is determined (when S752 is Yes), the sub CPU 71 Then, it is determined whether or not the scaler communication disconnection flag is on (S753).

  In S753, when the sub CPU 71 determines that the scaler communication disconnection flag is on (when S753 is Yes), the sub CPU 71 ends the sub device communication disconnection process, and the process is controlled between the sub devices. The process moves to S633 (see FIG. 114).

  On the other hand, when the sub CPU 71 determines in S753 that the scaler communication disconnection flag is not on (when S753 is No), the sub CPU 71 turns on the scaler communication disconnection flag (S754). Next, the sub CPU 71 registers the error code “SCL DSC” (see FIG. 14) corresponding to “communication disconnection” in the error information history storage area 73e (S755). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “communication disconnection”. Then, after the processing of S755, the sub CPU 71 ends the sub device communication disconnection processing, and moves the processing to S633 of the inter sub device communication control task (see FIG. 114).

  In the inter-subdevice communication control task shown in FIG. 114, even if the subdevice communication disconnection process described above ends, the task does not end, and the flow of task processing returns to S633 as described above. Subsequently, the sub-device communication return process described with reference to FIG. 116 is executed, and when communication is resumed, “communication return” is registered as an error history. Therefore, in the present embodiment, communication can be resumed without ending the communication task even if communication interruption and error occur between the sub CPU 71 and the scaler control board 80. Since “communication restart” is registered in the error history, the date and time of “communication disconnection” and “communication restart” can be confirmed from the error history.

[Subdevice serial reception interrupt processing]
Next, the sub device serial reception interrupt processing by the sub CPU 71 will be described with reference to FIG. FIG. 122 is a flowchart of sub-device serial reception interrupt processing in the present embodiment.

  First, the sub CPU 71 reads the reception status (S761). Next, the sub CPU 71 determines whether or not there is an error in the physical layer (S762).

  When the sub CPU 71 determines that there is no error in the physical layer in S762 (when S762 is No), the sub CPU 71 stores the received data in the communication log collection ring buffer area 73f (S763). Note that the size of the buffer for storing the received data is 512 bytes. After the process of S763, the sub CPU 71 ends the sub device serial reception interrupt process.

  On the other hand, when the sub CPU 71 determines in S762 that there is an error in the physical layer (in the case where S762 is Yes), the sub CPU 71 determines that the error code “SD COM” corresponding to “subdevice physical layer error” (FIG. 14) is registered in the error information history storage area 73e (S764). At this time, the sub CPU 71 registers the error occurrence date and time in the error information history storage area 73e together with the error code corresponding to “sub device physical layer abnormality”. In addition, the subdevice physical layer error is not as serious as the COM error, and is registered separately from the COM error. Then, after the processing of S764, the sub CPU 71 ends the sub device serial reception interrupt processing.

[Unauthorized monitoring processing task]
Next, the fraud monitoring processing task by the sub CPU 71 will be described with reference to FIG. FIG. 123 is a flowchart of the fraud monitoring processing task in this embodiment. In this process, the occurrence of a short-term power outage abnormality, the occurrence of a medium-term power outage abnormality, and the occurrence of a long-term power outage abnormality that can occur due to the above-described goto action (clear goto) are monitored.

  First, the sub CPU 71 sets a cycle of 100 msec as a fraud monitoring cycle (S771). The fraud monitoring period is not limited to 100 msec, and can be arbitrarily set according to the processing capability of the sub CPU 71, the pattern type of the goto action to be monitored, and the like.

  Next, the sub CPU 71 sets the head address of the error information history storage area 73e of the sub RAM 73 as a search address (S772). By this process, the latest error information history stored in the error information history storage area 73e can be confirmed. Note that the error information history content confirmation processing (retrieval processing) in the fraud monitoring processing task of this embodiment is sequentially performed from the latest error information history.

  Next, the sub CPU 71 determines whether or not the error information history stored in the search address area is “POWER ERR1 (short-term power failure occurrence)” (S773).

  In S773, when the sub CPU 71 determines that the error information history is “POWER ERR1” (when S773 is YES), the sub CPU 71 performs processing of S783 described later. On the other hand, when the sub CPU 71 determines that the error information history is not “POWER ERR1” in S773 (when S773 is No), the sub CPU 71 determines that the error information history stored in the search address area is “ It is determined whether or not "POWER ERR2 (intermediate power failure abnormality occurrence)" (S774).

  In S774, when the sub CPU 71 determines that the error information history is “POWER ERR2” (when S774 is Yes), the sub CPU 71 performs the process of S783 described later. On the other hand, when the sub CPU 71 determines in S774 that the error information history is not “POWER ERR2” (when S774 is No), the sub CPU 71 determines that the error information history stored in the search address area is “ It is determined whether or not “POWER ERR3 (Long-term power failure occurrence)” (S775).

  In S775, when the sub CPU 71 determines that the error information history is “POWER ERR3” (when S775 is Yes), the sub CPU 71 performs processing of S783 described later. On the other hand, when the sub CPU 71 determines that the error information history is not “POWER ERR3” in S775 (when S775 is No), the sub CPU 71 updates the search address in the error information history storage area 73e (S776). ).

  Then, the sub CPU 71 determines whether or not there is an error information history in the updated address area (S777). In S777, when the sub CPU 71 determines that there is an error information history in the updated address area (in the case where S777 is Yes), the sub CPU 71 returns the process to S773 and repeats the processes after S773.

  On the other hand, in S777, when the sub CPU 71 determines that there is no error information history in the updated address area (S777 is No), the sub CPU 71 performs short-term power failure abnormality determination processing (S778). ). At this time, from the processing program for the fraud monitoring processing task to the processing program for the power failure abnormality determination processing described later, as a parameter, a determination period of 30 seconds and the number of times of abnormality determination, which is a determination parameter for a short-term power failure abnormality occurrence error Is passed.

  In the process of S778, the sub CPU 71 determines whether or not a power failure has occurred abnormally (occurred five times or more) in a short period (30 seconds) based on the error information history stored in the error information history storage area 73e. Determine. If it is determined that a short-term power failure has occurred, the sub CPU 71 performs power interruption for the number of power interruptions (five or more) stored in the error information history storage area 73e within this short period. Related error information histories (repetition of “POWER DOWN” and “POWER UP”) are aggregated into one error information history, and the aggregated (edited) error information history is stored in a predetermined area in the error information history storage area 73e. sign up. Note that details of the power failure abnormality determination process will be described later with reference to FIG. 124 described later.

  Then, after the processing of S778, the sub CPU 71 determines whether or not a short-term power failure error has occurred based on the result of the determination processing of S778 (S779). In this process, the sub CPU 71 generates a power failure abnormality occurrence error when an error registration editing process (S805 described later) is performed during a power failure abnormality illegal determination process (described later with reference to FIG. 124). It is determined that

  In S779, when the sub CPU 71 determines that a short-term power failure abnormality occurrence error has occurred (in the case where S779 is Yes), the sub CPU 71 performs processing of S783 described later.

  On the other hand, when the sub CPU 71 determines in S779 that a short-term power failure abnormality occurrence error has not occurred (when S779 is No), the sub CPU 71 performs medium-term power failure abnormality determination processing (S780). . At this time, from the processing program for the fraud monitoring processing task to the processing program for the power failure abnormality determination processing to be described later, as a parameter, a determination period of 10 minutes and a number of times of abnormality determination serving as a determination parameter for a medium-term power failure abnormality occurrence error are used. Is passed.

  In the process of S780, the sub CPU 71 determines whether or not a power interruption has occurred abnormally (occurred 10 times or more) during the middle period (10 minutes) based on the error information history stored in the error information history storage area 73e. Determine. If it is determined that there has been a power failure abnormality in the middle period, the sub CPU 71 performs power interruption for the number of power interruptions (10 or more) stored in the error information history storage area 73e within this medium period. Related error information histories (repetition of “POWER DOWN” and “POWER UP”) are aggregated into one error information history, and the aggregated (edited) error information history is stored in a predetermined area in the error information history storage area 73e. sign up. Note that details of the power failure abnormality determination process will be described later with reference to FIG. 124 described later.

  Then, after the processing of S780, the sub CPU 71 determines whether or not a medium-term power failure error has occurred based on the result of the determination processing of S780 (S781). When the sub CPU 71 determines in S781 that an intermediate power failure error occurrence error has occurred (when S781 is Yes), the sub CPU 71 performs processing of S783 described later.

  On the other hand, when the sub CPU 71 determines in S781 that a medium-term power failure error has not occurred (when S781 is No), the sub CPU 71 performs a long-term power failure abnormality determination process (S782). . At this time, from the processing program for the fraud monitoring processing task to the processing program for the power failure abnormality determination processing described later, as a parameter, a determination period of 4 hours and the number of times of abnormality determination is 30 times, which is a determination parameter for a long-term power failure abnormality occurrence error. Is passed.

  In the processing of S782, the sub CPU 71 determines whether or not a power outage has occurred abnormally (occurred 30 times or more) over a long period (4 hours) based on the error information history stored in the error information history storage area 73e. Determine. If it is determined that a long-term power failure has occurred, the sub CPU 71 performs power interruption for the number of power interruptions (30 or more) stored in the error information history storage area 73e within this long time period. Related error information histories (repetition of “POWER DOWN” and “POWER UP”) are aggregated into one error information history, and the aggregated (edited) error information history is stored in a predetermined area in the error information history storage area 73e. sign up. Note that details of the power failure abnormality determination process will be described later with reference to FIG. 124 described later.

  Then, after the processing of S782, or when S773, S774, S775, S779 or S781 is Yes, the sub CPU 71 waits for a cycle of 100 msec (S783). Next, the sub CPU 71 returns the process to the process of S772, and repeats the processes after S772.

  In the present embodiment, as described above, a short-term power failure abnormality error, a medium-term power failure abnormality error, and a long-term power failure abnormality error, which may occur due to a gotting action or the like, are monitored. Although not shown, if any of the short-term power failure abnormality error, the medium-term power failure abnormality error, and the long-term power failure abnormality error is detected by the monitoring process, for example, FIG. In the form as shown, the occurrence of abnormality is displayed on the display screen of the liquid crystal display device 10, and effects such as AT display are suppressed. Then, when such an abnormality occurrence screen is displayed, when the clerk performs a setting change operation (initialization operation) on the pachislot 1, the abnormality occurrence screen is canceled and the normal game is restored. Further, the error information history stored in the error information history storage area 73e is also cleared by the setting change operation of the staff.

  In the fraud monitoring processing task of the present embodiment, an example has been described in which the error information history search processing (content confirmation processing) stored in the error information history storage area 73e is sequentially performed from the latest error information history. However, the present invention is not limited to this. For example, the above-described error information history search processing (content confirmation processing) may be sequentially performed from the oldest error information history.

[Power failure abnormality judgment processing]
Next, the power failure abnormality fraud determination processing performed in S778, S780, or S782 in the fraud monitoring processing task flowchart (see FIG. 123) will be described with reference to FIG. FIG. 124 is a flowchart illustrating a procedure of power failure abnormality fraud determination processing in the present embodiment. In this embodiment, in S778, S780, or S782, only the determination period and the number of times of abnormality determination, which are determination parameters for the power failure abnormality occurrence error, are different from each other, and the processing contents (processing procedures) are all the same. It is.

  First, the sub CPU 71 clears the value of the check counter (S791). The check counter is a counter for managing the number of power interruptions (error events corresponding to “POWER DOWN”) that occurred within the determination period (30 sec (short term), 10 min (medium term), or 4 hours (long term)). is there.

  Next, the sub CPU 71 sets the head address of the error information history storage area 73e of the sub RAM 73 as a search address (S792). By this process, the latest error information history stored in the error information history storage area 73e can be confirmed. Note that the error information history content confirmation processing (retrieval processing) in the power failure abnormality determination processing of this embodiment is sequentially performed from the newest error information history.

  Next, the sub CPU 71 determines whether or not there is an error information history in the set (or updated) address area (S793).

  In S793, when the sub CPU 71 determines that there is no error information history in the set (or updated) address area (when S793 is No), the sub CPU 71 ends the power failure abnormality fraud determination process. Then, the process proceeds to S779, S781 or S783 of the fraud monitoring process task (see FIG. 123). On the other hand, in S793, when the sub CPU 71 determines that there is an error information history in the set (or updated) address area (when S793 is Yes), the sub CPU 71 indicates that the error information history is “POWER”. It is determined whether or not it is “DOWN” (error information regarding power interruption) (S794).

  In S794, when the sub CPU 71 determines that the error information history is not “POWER DOWN” (when S794 is No), the sub CPU 71 updates the address in the error information history storage area 73e to be searched (S795). . In this process, the sub CPU 71 updates the address to the address of the area where the next new error information history is stored. Then, after the process of S795, the sub CPU 71 returns the process to S793, and repeats the processes after S793.

  On the other hand, when the sub CPU 71 determines that the error information history is “POWER DOWN” in S794 (when S794 is Yes), the sub CPU 71 updates the value of the check counter (adds “1”) ( S796).

  After the processing of S796, the sub CPU 71 acquires information on the occurrence time (occurrence date / time) of the power interruption error corresponding to the error information history being searched from the error information history storage area 73e, and uses the occurrence time information as the error information. The information is stored in a predetermined end time storage area in the information history storage area 73e (S797). The end time storage area is a storage area provided for storing the end time of occurrence of power interruption abnormality in a predetermined period (short term, medium term or long term). Next, the sub CPU 71 subtracts the determination period (30 sec (short term), 10 min (medium term), or 4 hour (long term)) from the occurrence time of the error information history (power failure error) acquired in S797, and obtains the result by subtraction. The determined time is set as the determination time (S798).

  After the processing of S798, the sub CPU 71 updates the address in the error information history storage area 73e to be searched (S799). In this process, the sub CPU 71 updates the address to the address of the area where the next new error information history is stored. Next, the sub CPU 71 determines whether or not there is an error information history in the updated address area (S800).

  In S800, when the sub CPU 71 determines that there is no error information history in the area of the updated address (when S800 is No), the sub CPU 71 performs the process of S805 described later. On the other hand, in S800, when the sub CPU 71 determines that there is an error information history in the updated address area (when S800 is Yes), the sub CPU 71 determines that the error information history is “POWER DOWN” (related to power interruption). Error information) is determined (S801).

  In S801, when the sub CPU 71 determines that the error information history is not “POWER DOWN” (when S801 is No), the sub CPU 71 returns the process to S799 and repeats the processes after S799. On the other hand, when the sub CPU 71 determines that the error information history is “POWER DOWN” in S801 (when S801 is Yes), the sub CPU 71 determines the occurrence time of the error information history (power failure error) during the search. Is determined after the determination time (occurrence time ≧ determination time) (S802).

  In S802, when the sub CPU 71 determines that the occurrence time of the error information history (power interruption error) is not after the determination time (when S802 is No), the sub CPU 71 performs the process of S805 described later. On the other hand, when the sub CPU 71 determines in S802 that the occurrence time of the error information history (power failure error) is after the determination time (S802 is Yes), the sub CPU 71 updates the value of the check counter ( "1" is added) (S803).

  After the processing of S803, the sub CPU 71 stores the information (occurrence date and time) of the occurrence time of the error information history (power failure error) being searched in the predetermined start time storage area in the error information history storage area 73e (S804). ). The start time storage area is a storage area provided for storing the start time of occurrence of power interruption abnormality in a predetermined period (short term, medium term or long term). Next, the sub CPU 71 returns the process to S799 and repeats the processes after S799.

  When S800 or S802 is No, the sub CPU 71 determines whether or not the value of the check counter is equal to or greater than the number of times of abnormality determination (5 times (short term), 10 times (medium term), or 30 times (long term)). (S805).

  In S805, when the sub CPU 71 determines that the value of the check counter is not equal to or greater than the number of times of abnormality determination (when S805 is No), the sub CPU 71 ends the power failure abnormality fraud determination processing, and performs the fraud monitoring processing task. Move to S779, S781 or S783 (see FIG. 123). On the other hand, when the sub CPU 71 determines in S805 that the value of the check counter is equal to or greater than the number of times of abnormality determination (a power failure abnormality occurrence error has occurred) (when S805 is Yes), Registration editing processing is performed (S806). Then, after the process of S806, the power failure abnormality fraud determination process is terminated, and the process proceeds to S779, S781 or S783 of the fraud monitoring process task (see FIG. 123).

  In the process of S806, the sub CPU 71 (error information registration unit 71d) relates to power interruptions for the number of power interruptions stored in the error information history storage area 73e within a predetermined determination period (short term, medium term or long term). Error information history (repetition of “POWER DOWN” and “POWER UP”) is integrated into one error information history (any one of “POWER ERR1”, “POWER ERR2” and “POWER ERR3”). Register and edit information history. At this time, the sub CPU 71 stores the error code corresponding to the power failure abnormality error for a predetermined period, the end time information (release date / time) saved in the end time storage area in S797, and the start time storage area in S804. The stored start time information (occurrence date and time) is stored (registered) in a predetermined area in the error information history storage area 73e as one data set (error information history).

  In addition, in the error information history registration editing process of S806, when an error information history corresponding to the power failure abnormality occurrence error for a predetermined period is generated, a plurality of power interruptions within the determination period stored before aggregation are performed. The error information history related to may be deleted or may be left in another area. In any case, the error information history related to a plurality of power interruptions within the determination period is erased from the area stored before the aggregation, and is stored in the area of the latest address (first address) within the determination period. The error information history corresponding to the power failure abnormality occurrence error during the period is stored.

  And after the error information history corresponding to the power failure abnormality occurrence error in the predetermined period is stored in the area of the latest address in the determination period, before the determination period stored in the area of the address after the last address in the determination period These error information histories are sequentially stored with addresses prepended. Therefore, in the present embodiment, when the error information history corresponding to the power failure abnormality occurrence error for a predetermined period is generated in the error information history registration editing process of S806, the power failure abnormality occurrence error for the predetermined period is generated. The error information history before the determination period is stored in chronological order after the address next to the address where the corresponding error information history is stored.

  In addition, when a power failure error occurrence error for a predetermined period is detected, an error event other than power failure occurs in the middle of error information histories related to multiple power interruptions (repeat of “POWER DOWN” and “POWER UP”). When the corresponding error information history is registered, the error information history registration and editing process can be performed as follows.

  For example, when the error information history is arranged in chronological order based on the end time (cancellation date and time) of the power failure abnormality occurrence error for a predetermined period, the end time of the power failure abnormality occurrence error for the predetermined period is The time is later than the time of occurrence of an error other than power interruption that occurred in the middle. That is, the error information history of the occurrence of power failure during a predetermined period becomes a newer error information history than the error information history other than power failure. Therefore, in this case, in the error information history storage area 73e, the address of the error information history storage area corresponding to the occurrence of the power interruption abnormality for a predetermined period is greater than the address of the error information history storage area other than the power interruption. Each error information history is stored so as to be located at the head side. In this case, on the error information history confirmation screen as shown in FIG. 25, the error information history corresponding to the occurrence of the power interruption abnormality for a predetermined period is displayed in a column above the error information history other than the power interruption. The

  Further, for example, when the error information history is arranged in chronological order based on the start time (occurrence date / time) of the power failure abnormality occurrence error in a predetermined period, the start time of the power failure abnormality occurrence error in the predetermined period is the predetermined time. The time is before the time of occurrence of an error other than the power interruption that occurred in the middle of the period. That is, the error information history other than the power interruption becomes a newer error information history than the error information history corresponding to the occurrence of the power interruption abnormality during the predetermined period. Therefore, in this case, in the error information history storage area 73e, the address of the error information history storage area other than the power interruption is more than the address of the error information history storage area corresponding to the occurrence of power interruption abnormality for a predetermined period. Each error information history is stored so as to be located at the head side. In this case, on the error information history confirmation screen as shown in FIG. 25, the error information history other than power interruption is displayed in a column above the error information history of power failure abnormality corresponding to a predetermined period. The

  Note that the error information history registration and editing method (aggregation method and storage form) corresponding to the power failure abnormality occurrence error for the predetermined period described above is the power interruption for the predetermined period as shown in the error information history confirmation screen shown in FIG. Any method can be used as long as the error information history corresponding to the occurrence of abnormality can be displayed in time series by the error information history display means 71f, as with other various error information histories.

  In the present embodiment, the example in which the number of power interruptions is counted based on the number of occurrences of an error event (power interruption) corresponding to “POWER DOWN” has been described, but the present invention is not limited to this. For example, the number of power interruptions may be counted based on the number of occurrences of an error event (power recovery) corresponding to “POWER UP”. In this case, in the determination processing of S794 and S801 in FIG. 124, the sub CPU 71 determines whether or not the error information history is “POWER UP”.

  Furthermore, in the power failure abnormality fraud determination processing according to the present embodiment, an example in which search processing (content confirmation processing) of the error information history stored in the error information history storage area 73e is sequentially performed from the latest error information history will be described. However, the present invention is not limited to this. For example, the above-described error information history search processing (content confirmation processing) may be sequentially performed from the oldest error information history. In this case, for example, the determination time calculation process and the magnitude relationship (determination condition) between the determination time and the occurrence time are appropriately changed according to the search order.

<Description of various processes by the scaler control LSI>
Next, the contents of various processes (tasks) executed by the scaler control LSI of the scaler control board 80 using a program will be described with reference to FIGS. Note that various control flags, various control counters, various buffers, and the like necessary for various processing of the scaler control LSI described below are provided in a working RAM (not shown).

[Scalar control main task]
Next, the scaler control main task will be described with reference to FIG. FIG. 125 is a flowchart of the scaler control main task in the present embodiment.

  Note that “U1” described in the flowchart of the scaler control main task in FIG. 125 is a serial port U1 provided in the scaler control LSI of the scaler control board 80. This serial port U1 is a subdevice (scaler). This is a port used for transmission / reception between the scaler control LSI of the control board 80 and the sub CPU 71. “U2” is also a serial port provided in the scaler control LSI of the scaler control board 80. However, when the touch sensor or the camera is connected to the sub CPU 71 as another sub device via the scaler control board 80, the serial port U2 is connected to the other device from the scaler control LSI of the scaler control board 80, for example. This is a port used to allow received data to pass through. Both “U1” and “U2” acquire received data in units of 1 byte at the time of reception interrupt.

  The processing of the scaler control main task is substantially the same as the sub device serial reception interrupt processing of the sub CPU 71 shown in FIG. 122, but no error registration processing is performed in the processing of the scaler control main task.

  In the scaler control main task, first, the scaler control LSI of the scaler control board 80 performs an initial setting process (S811). In this process, for example, the scaler control LSI performs setting of the timer, serial port, and the like in the scaler control board 80, initialization of the work RAM, and initial setting of the resolution conversion LSI.

  Next, the scaler control LSI sets a period of 10 msec (S812). After this processing, the scaler control LSI stands by for the remaining time after subtracting the processing time from 10 msec to S812. For example, if the processing time up to S812 is 1.5 msec, the remaining 8.5 msec is the standby time. However, the reception interrupt process operates even during standby.

  Next, the scaler control LSI performs a sub control reception process (U1) (S813). Details of the sub-control reception process will be described later with reference to FIG. 126 described later. Next, when other subdevices such as a touch sensor and a camera are connected to the subcontrol circuit 70 in addition to the scaler control board 80 as a subdevice, the scaler control LSI receives signals from other subdevices. Processing (U2) is performed (S814).

  Next, the scaler control LSI determines whether there is transmission data to the sub CPU 71 (S815).

  In S815, when the scaler control LSI determines that there is no transmission data to the sub CPU 71 (when S815 is No), the scaler control LSI performs the process of S817 described later. On the other hand, when the scaler control LSI determines in S815 that there is transmission data to the sub CPU 71 (when S815 is Yes), the scaler control LSI performs a sub control transmission process (U1) (S816). The details of the sub control transmission process will be described later with reference to FIG. 128 described later.

  After the process of S816, or when S815 is No, the scaler control LSI determines whether there is transmission data to other subdevices (S817).

  In S817, when the scaler control LSI determines that there is no transmission data to other subdevices (when S817 is No), the scaler control LSI performs the process of S819 described later. On the other hand, when the scaler control LSI determines in S817 that there is transmission data to other subdevices (when S817 is Yes), the scaler control LSI performs transmission processing (U2) to other subdevices. Perform (S818). In S818, when the sub CPU 71 is the transmission destination, other sub devices perform through transmission. Further, when there is no connection of other subdevices, no transmission / reception data is generated.

  After the process of S818 or when S817 is No, the scaler control LSI performs an operation state determination process (S819). Details of the operation state determination process will be described later with reference to FIG.

  Next, the scaler control LSI waits for the remaining time in the 10 msec cycle period (S820). Then, after the process of S820, the scaler control LSI returns the process to S813 and repeats the processes after S813.

[Sub-control reception processing]
Next, with reference to FIG. 126, the sub-control reception process performed in S813 in the flowchart (see FIG. 125) of the scaler control main task will be described. FIG. 126 is a flowchart showing the procedure of sub-control reception processing in this embodiment.

  First, the scaler control LSI determines whether there is received data (S831).

  When the scaler control LSI determines in S831 that there is no received data (when S831 is No), the scaler control LSI ends the sub-control reception process and performs the process of the scaler control main task (see FIG. 125). Move to S814. On the other hand, when the scaler control LSI determines in S831 that there is received data (when S831 is Yes), the scaler control LSI determines whether or not the destination ID of the received data is the scaler control LSI. (S832).

  When the scaler control LSI determines in S832 that the destination ID of the received data is the scaler control LSI (when S832 is Yes), the scaler control LSI determines whether the command CMD is a setting item. It is determined (S833). Note that, as shown in the table of FIG. 19, there are three items of CMD of setting items related to the scaler control board 80: backlight luminance setting, contour enhancement setting, and interpolation table setting.

  In S833, when the scaler control LSI determines that the command CMD is a setting item (when S833 is Yes), the scaler control LSI performs resolution conversion LSI setting processing (S834). Details of the resolution conversion LSI setting process will be described later with reference to FIG. 127 described later. Then, after the process of S834, the scaler control LSI ends the sub-control reception process, and moves the process to S814 of the scaler control main task (see FIG. 125).

  On the other hand, when the scaler control LSI determines in step S833 that the command CMD is not a setting item (in the case where S833 is No), the scaler control LSI sets a reception confirmation command in the sub-control transmission buffer (S835). After the process of S835, the scaler control LSI ends the sub-control reception process, and moves the process to S814 of the scaler control main task (see FIG. 125).

  Here, returning to the processing of S832 again, when the scaler control LSI determines in S832 that the destination ID of the received data is not the scaler control LSI (when S832 is No), the scaler control LSI In order to transmit the received data through to the subdevice, the transmission data is copied to another subdevice transmission buffer (S836). Then, after the process of S836, the scaler control LSI ends the sub-control reception process, and moves the process to S814 of the scaler control main task (see FIG. 125).

[Resolution conversion LSI setting processing]
Next, the resolution conversion LSI setting process performed in S834 in the flowchart of the sub control reception process (see FIG. 126) will be described with reference to FIG. FIG. 127 is a flowchart showing a procedure of resolution conversion LSI setting processing in this embodiment.

  First, the scaler control LSI acquires setting items from the reception buffer and also acquires setting data from the reception buffer (S841). Note that the setting item acquired in this process is one of the three items of backlight luminance, contour enhancement, and scaler interpolation table setting.

  Next, the scaler control LSI sets the acquired setting data in the setting item of the resolution conversion LSI (S842). Next, the scaler control LSI reads the setting contents from the resolution conversion LSI (S843).

  Next, the scaler control LSI determines whether or not the value of the setting content (read value) read in S843 is the same as the value (set value) set in S842 (S844).

  When the scaler control LSI determines in S844 that the read value is not the same as the set value (when S844 is No), the scaler control LSI turns on the resolution conversion LSI setting abnormality flag (S845). Then, after the process of S845, the scaler control LSI ends the resolution conversion LSI setting process and also ends the sub-control reception process (see FIG. 126).

  On the other hand, when the scaler control LSI determines in S844 that the read value is the same as the set value (when S844 is Yes), the scaler control LSI sends a reception confirmation command with a setting item to the sub-control transmission buffer. Is set (S846). Then, after the process of S846, the scaler control LSI ends the resolution conversion LSI setting process and also ends the sub-control reception process (see FIG. 126).

  In the resolution conversion LSI setting process described above, when a parameter request is made from the scaler control LSI to the sub CPU 71 and a command of a predetermined setting item is transmitted from the sub CPU 71 to the scaler control LSI, the scaler control LSI sends a command to the sub CPU 71. Command receipt confirmation is sent. However, in the command transmission / reception process between the scaler control LSI and the sub CPU 71, the following problems may occur.

  For example, let us consider a case where a first parameter request is made from the scaler control LSI to the sub CPU 71 and a command for outline enhancement setting is transmitted from the sub CPU 71 to the scaler control LSI. In this case, the second parameter request is sent from the scaler control LSI to the sub CPU 71 after the contour emphasis setting command is transmitted and before the reception confirmation of the contour emphasis setting command is transmitted from the scaler control LSI to the sub CPU 71. On the other hand, for example, a backlight brightness setting command may be transmitted from the sub CPU 71 to the scaler control LSI. At this time, when the reception confirmation of the first command is transmitted from the scaler control LSI to the sub CPU 71, the sub CPU 71 erroneously recognizes that the reception confirmation of this command is the reception confirmation of the “backlight luminance setting command”. Subsequently, when the reception confirmation for the “backlight luminance setting command” is transmitted from the scaler control LSI to the sub CPU 71, the sub CPU 71 may ignore the reception confirmation due to the above-mentioned misidentification.

  On the other hand, in the resolution conversion LSI setting process of this embodiment, a reception confirmation command with a setting item is set in the sub-control transmission buffer in the process of S846. That is, instead of simply transmitting the reception confirmation from the scaler control LSI to the sub CPU 71, the setting items are added to the reception confirmation and transmitted. Therefore, in the processing method of the present embodiment, the sub CPU 71 can correctly determine which setting change command reception confirmation command is the reception confirmation command received from the scaler control LSI.

[Sub-control transmission processing]
Next, with reference to FIG. 128, the sub-control transmission process performed in S816 in the flowchart (see FIG. 125) of the scaler control main task will be described. FIG. 128 is a flowchart showing the procedure of sub-control transmission processing in the present embodiment.

  First, the scaler control LSI updates (adds “1”) the sub-control transmission interval counter of the transmission data to the sub CPU 71 (S851). Next, the scaler control LSI determines whether or not the data transmission interval from the sub CPU 71 is 100 msec or more (S852).

  In S852, when the scaler control LSI determines that the data transmission interval from the sub CPU 71 is not 100 msec or more (when S852 is No), the scaler control LSI ends the sub control transmission process and performs the scaler control. The process moves to S817 of the main task (see FIG. 125). On the other hand, when the scaler control LSI determines in S852 that the data transmission interval from the sub CPU 71 is 100 msec or more (when S852 is Yes), the scaler control LSI determines whether there is transmission data in the transmission buffer. Is discriminated (S853).

  In S853, when the scaler control LSI determines that there is transmission data in the transmission buffer (when S853 is Yes), the scaler control LSI performs the process of S859 described later. On the other hand, when the scaler control LSI determines in S853 that there is no transmission data in the transmission buffer (when S853 is No), the scaler control LSI transmits a parameter request command to the sub CPU 71 at a cycle of 200 msec. It is determined whether the transmission interval is 200 msec or more (S854).

  In S854, when the scaler control LSI determines that the transmission interval is not 200 msec or more (in the case where S854 is No), the scaler control LSI ends the sub-control transmission process, and the process is the scaler control main task (see FIG. 125). ) To S817. On the other hand, when the scaler control LSI determines in S854 that the transmission interval is 200 msec or more (when S854 is Yes), the scaler control LSI determines whether or not the activated flag is on ( S855). Note that the activated flag is turned off by clearing the RAM in an initial setting process performed at a reset interrupt (power-on or counter reset).

  In S855, when the scaler control LSI determines that the activated flag is not on (when S855 is No), the scaler control LSI sets an activation parameter request command in the sub-control transmission buffer (S856). Next, the scaler control LSI turns on the activated flag (S857). Then, after the processing of S857, the scaler control LSI performs processing of S859 described later.

  On the other hand, when the scaler control LSI determines in S855 that the activated flag is on (when S855 is Yes), the scaler control LSI sets a parameter request command in the sub-control transmission buffer (S858). ).

  After the processing of S857 or S858, or when S853 is Yes, the scaler control LSI transmits transmission data to the sub CPU 71 (S859). Next, the scaler control LSI clears the sub-control transmission interval counter to “0” (S860). Then, after the processing of S860, the scaler control LSI ends the sub-control transmission processing, and moves the processing to S817 of the scaler control main task (see FIG. 125).

[Operating state judgment processing]
Next, with reference to FIG. 129, the operation state determination process performed in S819 in the flowchart (see FIG. 125) of the scaler control main task will be described. In addition, FIG. 129 is a flowchart which shows the procedure of the operation state determination process in this embodiment.

  First, the scaler control LSI updates the determination interval counter (adds “1”) (S871). Next, the scaler control LSI determines whether the determination interval is 500 msec or more (S872).

  When the scaler control LSI determines in S872 that the determination interval is not 500 msec or more (when S872 is No), the scaler control LSI performs the process of S879 described later.

  On the other hand, when the scaler control LSI determines in S872 that the determination interval is 500 msec or more (when S872 is Yes), the scaler control LSI clears the determination interval counter to “0” (S873). Next, the scaler control LSI reads the data of the ROM self-diagnosis area into the register (S874). Next, the scaler control LSI writes the data read into the register to the self-diagnosis area of the RAM (S875).

  After the process of S875, the scaler control LSI determines whether or not the value of the data (read value) read into the register in S874 is the same as the value of the self-diagnosis area of the ROM (S876).

  In S876, when the scaler control LSI determines that the value of the data read into the register in S874 (read value) is not the same as the value of the ROM self-diagnosis area (when S876 is No), the scaler control LSI. Performs the process of S878 described later. On the other hand, when the scaler control LSI determines in S876 that the value of the data read into the register in S874 (read value) is the same as the value of the self-diagnosis area of the ROM (when S876 is Yes). The scaler control LSI determines whether or not the value of the data (read value) read into the register in S874 is the same as the value of the RAM self-diagnosis area (S877).

  In S877, when the scaler control LSI determines that the value of the data read into the register in S874 (read value) is the same as the value of the RAM self-diagnosis area (when S877 is Yes), the scaler control is performed. The LSI performs a process of S879 described later. On the other hand, when the scaler control LSI determines in S877 that the value of the data (read value) read into the register in S874 is not the same as the value of the RAM self-diagnosis area (when S877 is No), the scaler. The control LSI performs a process of S878 described later.

  When S876 or S877 is NO, the scaler control LSI sets a reset notification (1) command in the sub-control transmission buffer (S878). Then, after the processing of S878, the scaler control LSI performs processing of S881 described later.

  Here, returning to the processing of S872 and S877 again, if S872 is No, or if S877 is Yes, the scaler control LSI determines whether or not the resolution conversion LSI setting abnormality flag is on. A determination is made (S879).

  In S879, when the scaler control LSI determines that the resolution conversion LSI setting abnormality flag is on (when S879 is Yes), the scaler control LSI sends a reset notification (2) command to the sub-control transmission buffer. Set (S880). Then, after the processing of S880 or S878, the scaler control LSI transmits transmission data to the sub CPU 71 (S881). A few seconds after this processing, the scaler control LSI and resolution conversion LSI are reset.

  On the other hand, when the scaler control LSI determines in step S879 that the resolution conversion LSI setting abnormality flag is not on (in the case where S879 is No), the scaler control LSI clears the WDT counter register (S882). After the WDT is cleared, it automatically starts counting. Then, after the process of S882, the scaler control LSI ends the operation state determination process, and moves the process to S820 of the scaler control main task (see FIG. 125).

  As described above, in the operation state determination process of this embodiment, the scaler control LSI compares the ROM value and the register value at a constant interval of 500 msec, and if the two values are different, the scaler control LSI and the resolution The conversion LSI is reset. Thereby, when an error occurs, the scaler control board 80 can be self-recovered by reset.

  This reset is detected by the sub-device error detection means 71h, and an error code “SCL RST” (see FIG. 14) corresponding to “reset occurrence” is registered in the error information history storage area 73e. You can check the date and time later.

<Various effects>
Here, effects obtained in the various error monitoring techniques of the pachislot machine 1 of the present embodiment described above will be described.

  As described above, in the pachislot machine 1 of the present embodiment, when power interruption (instantaneous interruption) occurs more than a predetermined number of times (abnormal occurrence) in a predetermined period (short period, middle period, and long period), the predetermined period The error information history relating to the number of power interruptions registered in the error information history storage area 73e is stored as one error information history (error information history corresponding to the occurrence of power failure abnormalities in the short term, medium term, and long term). Collect (edit) and register to. Then, the error information history corresponding to the generated short-term, medium-term, and long-term power interruption abnormalities is displayed on the error information history confirmation screen (see FIG. 25).

  Therefore, in this embodiment, the error information history confirmation screen may be filled with the corresponding error information history (repetition of “POWER DOWN” and “POWER UP”) due to frequent occurrences of instantaneous interruptions due to, for example, a got action. It is possible to confirm at a glance the presence / absence and number of times of the goto action and the period during which the goto action was performed. Furthermore, in this embodiment, since the goto action is monitored in different periods of a short period (second unit), a medium period (minute unit), and a long period (hour unit), various goto actions with different patterns can be detected. A deterrent effect to goto acts is obtained.

  Further, in the pachislot machine 1 of the present embodiment, a specific operation (simple operation: rotating the door key 2 in the counterclockwise direction to reset the error of the pachislot machine 1 for a certain period of time) is performed on the door key 2. As a result, the error information history confirmation screen can be displayed on the display screen of the liquid crystal display device 10. In other words, in the present embodiment, an attendant at the amusement shop can check the history of error information without operating the setting key of the pachislot 1. Therefore, in this embodiment, the staff can display the error information history confirmation screen even during business hours, and can more efficiently promote the cause identification of the error occurrence.

  Furthermore, in the pachi-slot 1 of the present embodiment, the clerk can display the error information history on the display screen of the liquid crystal display device 10 by a simple operation on the door key 2. Therefore, an error information history can be easily displayed by a staff member who has the door key 2. Furthermore, since there are usually more clerks who hold the door key 2 than clerks who hold the setting key, in this embodiment, the convenience of the error information history confirmation operation can be improved.

  Further, in the pachislot machine 1 of the present embodiment, as described above, when the occurrence of a communication error is detected, the sub CPU 71 indicates that a communication error has occurred, its occurrence time, and its release time as error information. Are sequentially stored in the sub-RAM 73. Further, the sub CPU 71 creates an error information history from the stored communication error information, and displays an error information history on the display screen of the liquid crystal display device 10 when there is an information disclosure request by operating the door key 2 ( (See FIG. 23). Therefore, in this embodiment, it is possible to confirm the unauthorized release of the communication error notification, and it is possible to confirm the generation time and the release time of the communication error notification later.

  In the present embodiment, the sub-CPU 71 detects such an abnormality when the procedure detecting means 71b detects an operation procedure that cannot occur in a normal game, that is, an abnormal operation procedure. That the operation procedure has occurred and the procedure that was missed in the normal operation procedure are sequentially stored in the sub-RAM 73 as error information. Further, the sub CPU 71 creates an error information history from the stored error information of the abnormal operation procedure, and when there is an information disclosure request by operating the door key 2, the error information history is displayed on the display screen of the liquid crystal display device 10. Is displayed (see error number “10” in FIG. 23).

  Therefore, compared to the case where an abnormal operation procedure occurs just like the conventional case where the screen simply returns to the demo screen, in the present embodiment, an abnormal operation procedure has occurred, the number of steps lost, the number of occurrences, Since the presence / absence and the like can be confirmed, the error information can be used as a material for determining the occurrence of the goto action.

  In the pachislot machine 1 of this embodiment, when the data destruction of the sub RAM 73 is detected by the data destruction detection unit 71c, the sub CPU 71 sequentially stores the occurrence of the data destruction in the sub RAM 73 as error information ( (See S478 in FIG. 102). Further, when there is an information disclosure request by operating the door key 2, the sub CPU 71 reads out an error information history regarding data destruction from the error information history storage area 73 e and displays it on the display screen of the liquid crystal display device 10.

  Therefore, in this embodiment, the data destruction of the sub RAM 73 during the game can be detected, so that an error notification can be immediately given to the data destruction, and the occurrence of goto can be suppressed. As an error notification at this time, for example, as shown in FIG. 21, a fatal error indicates that the game cannot be continued because an abnormality has occurred in the RAM data over almost the entire display screen of the liquid crystal display device 10. Show. Thereby, the RAM destruction action by a goto action can be suppressed.

  Further, as described above, in the present embodiment, when a communication error occurs between the sub control circuit 70 and the scaler control board 80, the date and content of the occurrence of the error is confirmed on the error information history confirmation screen. Therefore, the error monitoring technique of this embodiment is useful as a management method for the pachislot 1.

  Furthermore, in the present embodiment, only when the occurrence of a communication error is detected by the sub CPU 71, the communication error information related to the communication error is converted into the two-dimensional code 300. Therefore, since the two-dimensional code is not generated more than necessary, the control can be simplified. In the present embodiment, the two-dimensional code 300 displayed on the error information history confirmation screen is transmitted to an information processing apparatus for analysis provided outside the pachislot 1. Therefore, in the present embodiment, the cause of the error can be analyzed and specified by an external information processing apparatus, and the analysis result can be used for the subsequent improvement of the pachislot 1 or the like.

<Modification>
In the above embodiment, a pachislot machine has been described as an example of a gaming machine, but the present invention is not limited to this, and the present invention can also be applied to a gaming machine or a slot machine called “pachinko”. Here, a configuration example of a pachinko is described.

[Configuration of pachinko machines]
First, the configuration of the pachinko will be described with reference to FIGS. 130 to 133. FIG. 130 is a perspective view showing an external configuration of a pachinko in a modified example. FIG. 131 is an external front view of a pachinko according to a modification. FIG. 132 is an exploded perspective view showing a configuration of a pachinko in a modified example. FIG. 133 is a front view of a pachinko game board according to a modification.

  As shown in FIGS. 130 to 132, the pachinko 210 includes a glass door 211, a wooden frame 212, a base door 213, a game board 214, a dish unit 220, a liquid crystal display device 232 that displays an image, and a launching device that launches a game ball 330, a payout unit 700, a substrate unit 750, and the like.

  The glass door 211 is attached so that it can be opened and closed with respect to the base door 213. In addition, an opening 211a is formed at the center of the glass door 211, and a protective glass 219 having light permeability is attached to the opening 211a. The protective glass 219 is disposed so that the back surface thereof faces the front surface of the game board 214 in a state where the glass door 211 is closed.

  The dish unit 220 is a unit body in which the upper dish 221 and the lower dish 222 are integrated, and is attached to the lower part of the glass door 211 at the base door 213. Further, the lower plate 222 is disposed below the upper plate 221. The upper plate 221 and the lower plate 222 are formed with payout ports 221a and 222a for renting out game balls and paying out game balls (prize balls), respectively. When a predetermined payout condition is satisfied, the game balls are discharged to the upper plate 221 and the lower plate 222 through the payout ports 221a and 222a, respectively. In particular, the upper plate 221 has a game area 215 to be described later. A game ball for firing is stored.

  The launching device 330 is attached to the lower right position of the base door 213 when viewed from the front side (player side) of the pachinko 210. The launching device 330 includes a launching handle 226 that can be operated by a player, and a panel body 227 that fits in the space on the lower right side of the dish unit 220. The firing handle 226 is provided on the front side of the panel body 227. A driving device for launching a game ball is provided on the back side of the panel body 227.

  The dish unit 220 and the launching device 330 are attached to the base door 213, and the panel body 227 is provided integrally with the lower right portion of the dish unit 220. Then, the pachinko game is advanced by operating the launch handle 226 by the player.

  The game board 214 is disposed so as to be located on the back surface of the protective glass 219 and on the front surface side of the base door 213. Further, a spacer 231, a liquid crystal display device 232, and the like are disposed on the back side of the game board 214. Further, a payout unit 700 and a substrate unit 750 are disposed on the back side of the base door 213. In addition, a speaker 246 is disposed below the lower plate 222.

  The game board 214 is entirely formed of a substantially plate-like resin material having light permeability. Examples of the resin material having optical transparency include various resin materials such as acrylic resin, polycarbonate resin, and methacrylic resin. In addition, the game board 214 has a game area 215 in which a game ball launched by the launching device 330 can roll down, and the game area 215 is provided on the front side of the game board. The game area 215 is an area surrounded by the guide rail 230 (specifically, an outer rail 230a shown in FIG. 133 to be described later), and is an area where the game ball can roll. In addition, a plurality of game nails 218 are provided in the game area 214 of the game board 214 by being driven into the game board 214. Note that the configuration of the game board 214 shown in FIG. 133 is one configuration example of a game board including a game area in which a game ball can roll, and is not limited thereto.

  The liquid crystal display device 232 is disposed on the back side (back side) of the game board 214. In other words, the liquid crystal display device 232 is disposed behind the game board 214 formed of a material having optical transparency. The liquid crystal display device 232 has a display area 232a that enables display of an image relating to a game. The display area 232a is arranged so as to overlap all or part of the back surface of the game board 214.

  In other words, the display area 232a of the liquid crystal display device 232 is arranged on the back side of the game board 214 so as to overlap at least the whole or part of the game area 215 of the game board 214. Specifically, the liquid crystal display device 232 is disposed on the back side of the game board 214 so that the display area 232a overlaps with all or part of the game area 215 and all or part of the game area outer area 216. . In the display area 232a of the liquid crystal display device 232, various images such as an effect identification symbol, an effect image, and an ornamental decoration image are displayed.

  The spacer 231 is disposed between the back (rear side) of the game board 214 and the front (front side) of the liquid crystal display device 232, and defines a space serving as a flow path for the game ball rolling on the game board 214. To do. In addition, an LED unit 253 (see FIG. 133) is provided below the spacer 231. The spacer 231 is made of a light transmissive material. In this example, the spacer 231 is formed of a light-transmitting material. However, the present invention is not limited to this, and for example, a part of the spacer 231 is formed of a light-transmitting material. May be. Further, the spacer 231 may be formed of a material that does not have optical transparency.

  The firing handle 226 is rotatable, and a firing solenoid (not shown) as a driving device is provided on the back side of the firing handle 226. Further, a touch sensor (not shown) is provided on the peripheral edge of the firing handle 226. Furthermore, a firing volume (not shown) is provided inside the firing handle 226 to change the electric power supplied to the firing solenoid (not shown) by changing the resistance value according to the rotation amount of the firing handle 226.

  When the player touches a touch sensor (not shown) provided on the peripheral edge of the firing handle 226, it is detected that the firing handle 226 is gripped by the player. When the firing handle 226 is gripped by the player and is rotated clockwise when viewed from the front side (player side), the resistance value of the firing volume (not shown) changes according to the rotation angle. Then, electric power corresponding to the resistance value at this time is supplied to the firing solenoid (not shown). As a result, the game balls stored in the upper plate 221 are sequentially launched into the game area 215 of the game board 214 to advance the game. When a firing stop button (not shown) is pressed, the game ball is stopped firing even when the firing handle 226 is held and rotated.

  A decorative member in which three general winning holes 256a, 256b, and 256c are formed is disposed in the lower left area in the game board 214, and a portion of the decorative member that faces the LED unit 253 is transparent. Yes. Therefore, as shown in FIG. 133, the LED unit 253 is visible from the lower left area of the game board 214. The LED unit 253 includes a special symbol display device, a normal symbol display device 233, a first special symbol hold display LED 234a, 234b, a second special symbol hold display LED 234c, 234d, a normal symbol hold display LED 250a, 250b, etc. Reference) is provided.

  In this example, the special symbol display device is constituted by 16 LEDs. These 16 LEDs are divided into two groups of 8 LEDs, and details will be described later, but one group performs a variable display in response to a start winning at the first start port 225. Yes, the other group performs variable display triggered by a start winning at the second start port 244. For convenience of explanation, in the following description, one LED group is a first special symbol display device 235a (see FIG. 134 described later), and the other LED group is a second special symbol display device 235b (see FIG. 134 described later). Called.

  The LEDs of the first special symbol display device 235a and the second special symbol display device 235b perform variable display that repeatedly turns on and off in units of groups when a predetermined special symbol variable display start condition is satisfied. Then, the display pattern formed by turning on / off the eight LEDs is stopped and displayed as a special symbol (also referred to as an identification symbol). When the special symbol displayed in a stopped state is in a specific stop display mode, the gaming state shifts from a normal gaming state to a winning gaming state (special gaming state) that is advantageous to the player. In this win game state, as will be described later, the shutter 240 (see FIG. 133) is controlled to be in an open state, and the special winning opening 239 (see FIG. 133) is capable of receiving a game ball. It becomes.

  In other words, the game in which the big winning opening 239 is opened is a winning game. In this example, two types of winning games, a big hit game and a small hit game, are prepared. In addition, it is a big hit that the special symbol becomes a stop display mode in which it shifts to the big hit gaming state, and a special symbol becomes a stop display mode in which the special symbol goes to the small hit gaming state.

  The difference between the big hit and the small hit will be described later. In the case of the big hit, there is a high possibility that a lot of balls can be obtained. On the other hand, when the lost symbol is stopped and displayed as a special symbol, the gaming state is maintained. As described above, a game in which a special symbol is variably displayed and then stopped and the game state is shifted or maintained according to the result is referred to as a “special symbol game”.

  A normal symbol display device 233 is provided below the special symbol display device. The normal symbol display device 233 is composed of two display lamps, and the normal symbols are variably displayed by alternately turning on and off these display lamps. A game in which the normal symbol is variably displayed and then stopped is displayed, and the open / closed state of the normal electric accessory 248 (see FIG. 133) differs depending on the result, which is referred to as a “normal symbol game”.

  Below the normal symbol display device 233, normal symbol hold display LEDs 250a and 250b are provided. The normal symbol hold display LEDs 250a and 250b display the number of executions of the fluctuation display of the normal symbols that are held by turning on, turning off, or blinking (so-called “hold number”, “hold number related to normal symbols”).

  Specifically, when the execution of the normal symbol variation display is held once, the normal symbol hold display LED 250a is turned on, and the normal symbol hold display LED 250b is turned off. When the execution of the normal symbol variation display is held twice, the normal symbol hold display LED 250a is turned on, and the normal symbol hold display LED 250b is turned on. When the execution of the normal symbol variation display is held three times, the normal symbol hold display LED 250a blinks and the normal symbol hold display LED 250b lights. When the execution of the normal symbol variation display is held four times, the normal symbol hold display LED 250a blinks and the normal symbol hold display LED 250b blinks.

  Below the normal symbol hold display LEDs 250a and 250b, first special symbol hold display LEDs 234a and 234b and second special symbol hold display LEDs 234c and 234d are provided. The first special symbol hold display LEDs 234a and 234b and the second special symbol hold display LEDs 234c and 234d indicate the number of executions of the variable symbol display that is held by turning on, turning off, or blinking (so-called “hold number”, “special symbols”). Display the number of pending items "). The display mode of the number of reserved symbols related to special symbols by the first special symbol hold display LEDs 234a and 234b and the second special symbol hold display LEDs 234c and 234d is the same as the display mode of the number of held normal symbols by the normal symbol hold display LEDs 250a and 250b. is there.

  On the side of the normal symbol display device 233, a hit notification LED (not shown) that lights up regardless of whether a big hit or a small hit is provided. In this example, since the number of rounds is constant, an LED for displaying the number of rounds is not provided. Therefore, on the display of the hit notification LED controlled by the main control circuit 260 (see FIG. 134 described later), there is no difference in notification of the big hit and the small hit. In addition, as described later, the opening / closing pattern of the shutter 240 is also selected from the same between the big hit and the small hit, and the sub control circuit 400 (see FIG. 134 described later). The effects produced by the liquid crystal display device 232 and the like controlled by the above are the same. For this reason, the player cannot discriminate them visually even between the sudden big hit and the small hit.

  In addition, in the display area 232a of the liquid crystal display device 232 arranged on the back side (back side) of the game board 214, display is performed by the first special symbol display device 235a and the second special symbol display device 235b (see FIG. 134 described later). The effect image related to the special symbol to be displayed is displayed.

  For example, during the variable display of the special symbols displayed on the first special symbol display device 235a and the second special symbol display device 235b, the display area 232a of the liquid crystal display device 232 is composed of numbers except for specific cases. Identification symbols (which are also identification information for effects), for example, numbers such as “1-8” are variably displayed. In addition, for example, the special symbols that have been variably displayed on the first special symbol display device 235a and the second special symbol display device 235b are stopped and displayed, and the identification symbols for presentation are also displayed on the display area 232a of the liquid crystal display device 232. Is stopped.

  Further, in the first special symbol display device 235a and the second special symbol display device 235b, when the special symbol that has been changed or stopped is in a specific stop display mode, the player can grasp that it is a win. The effect image is displayed in the display area 232 a of the liquid crystal display device 232. Specifically, in either one of the first special symbol display device 235a and the second special symbol display device 235b, the special symbol is stopped and displayed in a specific display mode corresponding to, for example, a big hit that can be obtained by many balls. In such a case, the combination of effect identification symbols displayed in the display area 232a of the liquid crystal display device 232 is stopped in a state where all the same symbols are arranged in a specific display mode (for example, a plurality of symbol rows). In addition, the effect image for the big hit is displayed in the display area 232a of the liquid crystal display device 232. In the case of hits where it is difficult to obtain a lot of balls (small hits, 15 hits, big hits, 16 hits, big hits), an effect image that allows the player to grasp that is a win is displayed on the liquid crystal display device 232. It is not necessary to display in the area 232a.

  As shown in FIG. 133, on the game board 214 of the pachinko 210, the guide rails 230 (230a and 230b), the stage 255, the first starting port 225, the second starting port 244, the passing gate 254, the shutter 240, the big prize The game members such as the mouth 239, the general winning mouths 256a, 256b, 256c, 256d, and the ordinary electric accessory 248 are provided.

  A substantially inverted L-shaped stage 255 is provided on the top of the game board 214. A guide rail 230 is provided so as to surround the game area 215.

  The guide rail 230 includes an outer rail 230a that partitions (defines) the game area 215, and an inner rail 230b disposed inside the outer rail 230a. The game balls launched by the launching device 330 are guided by guide rails 230 provided on the game board 214 and moved to the upper part of the game board 214, and then provided on the plurality of game nails 218 and the game board 214. Due to the collision with the stage 255 or the like, it flows down toward the lower side of the game board 214 while changing its traveling direction. Specifically, the game ball flow down system is a system that flows down the left side of the stage 255 (so-called left-handed), and the launch handle 226 is rotated to the right to the maximum, and the game ball is driven into the right side of the stage 255 There is a system that flows down the right side of the stage 255 (so-called right-handed).

  A first start port 225 is provided below the stage 255 and below the center of the game board 214. A passage gate 254 is provided on the upper right side of the stage 255, and a second start port 244 is provided below the passage gate 254. An ordinary electric accessory 248 is provided at the second start port 244. The ordinary electric accessory 248 includes a tongue-like member 248 a that projects and retracts in the front-rear direction with respect to the plate surface of the game board 214. In this example, when the tongue-like member 248a protrudes, the game ball riding on the tongue-like member 248a wins the second starting port 244, and when the tongue-like member 248a is retracted, the game ball is second. The start opening 244 is configured not to win a prize.

  Then, when the normal symbol is stopped and displayed at the predetermined symbol on the normal symbol display device 233 (see FIG. 134 described later), the tongue-like member 248a of the ordinary electric accessory 248 is in the protruding state from the retracted state for a predetermined time. This makes it easier for a game ball to enter the second start port 244. The ordinary electric accessory 248 is not limited to the one that projects and retracts the tongue-like member 248a, and may be one that opens and closes a pair of blade members (so-called electric tulip), for example.

  In addition, when a game ball is driven to the right side of the stage 255, the game nail 218 is driven into a path along which the game ball rolls from the right side of the stage 255 to the first start port 225. It is impossible for the game ball to win the first starting port 225 from the right side of the stage 255.

  When a game ball passes through the passing gate 254 during the normal symbol variation display, the display mode by the normal symbol hold display LEDs 250a and 250b is switched, and the passing gate is displayed until the normal symbol in the variation display is stopped and displayed. The execution (start) of the normal symbol variation display based on the passing of the game ball to 254 is suspended. After that, when the normal symbol that has been variably displayed is stopped and displayed, the variably displayed normal symbol that has been suspended is started.

  When a specific symbol is stopped and displayed as a normal symbol on the normal symbol display device 233, an effect image that allows the player to grasp that the normal symbol lottery is winning is displayed in the display area 232a of the liquid crystal display device 232. You may be made to do.

  In addition, a shutter 240 that opens and closes the grand prize winning port 239 is disposed immediately below the first start port 225. An out port 257 is formed at the lowermost part of the game area 215 immediately below the shutter 240. Three general winning holes 256a, 256b, and 256c are provided in the lower left portion of the game area 215. In addition, a general winning opening 256d is provided at the lower right side of the game area 215.

  In addition, a winning area is provided in the first starting opening 225 described above, and a first starting winning opening switch 316 (see FIG. 134 described later) is provided in the winning area. A winning area is provided in the second starting opening 244, and a second starting winning opening switch 317 (see FIG. 134 described later) is provided in the winning area. When a game medium such as a game ball is detected by the first start winning a prize opening switch 316, the special symbol variation display by the first special symbol display device 235a is started.

  In addition, when a game ball enters the first start port 225 during the special symbol variation display, the game ball enters the first start port 225 until the special symbol during the variation display is stopped and displayed. Execution (start) of the special symbol variation display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started. In the following description, the special symbol variably displayed on the first special symbol display device 235a based on the entry of the game ball into the first start port 225 is referred to as a first special symbol.

  Further, when a game medium such as a game ball is detected by the second start winning a prize opening switch 317, the special symbol variation display by the second special symbol display device 235b is started. In addition, when a game ball enters the second start port 244 during the variation display of the special symbol, the game ball enters the second start port 244 until the special symbol during the variation display is stopped. Execution (start) of the special symbol variation display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started.

  In the following description, the special symbol variably displayed on the second special symbol display device 235b based on the game ball entering the second start port 244 is referred to as a second special symbol.

  In this example, the first special symbol display device 235a and the second special symbol display device 235b do not change the special symbols at the same time. Further, in this example, the special symbol variation display is performed with priority given to the start winning at the second start port 244. Note that the first start port 225 and the second start port 244 in this example are examples of start regions provided in the game region of the game board 214 through which game balls can pass.

  In this example, an upper limit is set for the number of times the execution of the special symbol variation display is suspended, and the special symbol variation display is suspended due to entering the first start port 225 and the second start port 244. The upper limit of the number is set to 4 times. Specifically, when the special symbol game of the first special symbol is held four times, information on the special symbol game corresponding to the changing first special symbol is the main RAM 270 (see FIG. 134 described later). The information of the four special symbol games stored as the start memory information in the first special symbol start memory area (0) of the first special symbol start memory area (1) to the first special symbol start memory It is stored in the area (4) as starting storage information.

  Similarly, for the special symbol game of the second special symbol, when the special symbol game of the second special symbol is held four times, the information of the special symbol game corresponding to the changing second special symbol is the main information. The information of the four special symbol games stored and stored in the second special symbol start storage area (0) of the RAM 270 (see FIG. 134 described later) is stored in the second special symbol start storage area (1 ) To the second special symbol start storage area (4). Therefore, in this example, the special symbol game can be held up to 8 times.

  In addition, as another variable display start condition for the predetermined special symbol in this example, the special symbol is stopped and displayed. In other words, every time a predetermined special symbol variable display start condition is satisfied, the special symbol variable display is started.

  In the first special symbol display device 235a and the second special symbol display device 235b, when the special symbol is in a specific stop display mode and the gaming state is shifted to the big hit gaming state, the shutter 240 is in an open state in which it is easy to accept the game ball. It is driven to become. As a result, the special winning opening 239 is in an open state (first state) in which a game ball can be easily received.

  On the other hand, the special winning opening 239 provided on the back side (rear side) of the shutter 240 has an area (not shown) having a count switch 304 (see FIG. 134 described later), and a predetermined number of game balls (not shown) The shutter 240 is driven to open until a predetermined time (for example, about 0.1 second or about 30 seconds) elapses. When either a predetermined number of game balls are awarded to the grand prize winning opening 239 or a predetermined time elapses in the open state, the shutter 240 is driven so as to be in a closed state where it is difficult to accept the game balls. . As a result, the special winning opening 239 is in a closed state in which it is difficult to accept a game ball (second state).

  Note that a game in which the special winning opening 239 easily accepts a game ball for a certain period of time is called a round game. Therefore, the shutter 240 is opened during the round game and closed between the round games. The number of round games is counted as the number of rounds such as “1” round and “2” round. For example, the first round game may be referred to as the first round and the second round as the second round. In this example, in one round, the shutter 240 may be opened and closed a plurality of times, and the time for the open state may be set to a certain time.

  Next, the shutter 240 driven from the open state (first state) to the closed state (second state) is again driven to the open state. That is, when the round game is finished, it is possible to continue to the next round game. A game from the first round game until the end of the round game (final round game) that cannot continue to the next round game is referred to as a special game or a jackpot game. In this example, the number of round games in all jackpots is 15 rounds.

  Further, in this example, when the special symbol is in a specific stop display mode in the first special symbol display device 235a and the second special symbol display device 235b and the gaming state shifts to the small hit gaming state, the big prize opening 239 is displayed. The shutter 240 is driven so as to be in an open state where it is easy to accept the game ball 15 times or 16 times. The small hit game is a game in which the big winning opening 239 is opened 15 times or 16 times, and there is no concept of a round game like the big win. However, the configuration of the above-described winning prize opening 239 and the shutter 240 is provided on the game board 214 and can be changed between an open state in which a game ball is easy to enter and a closed state in which the game ball is difficult to enter. It is an example of 1 structure of a variable member.

  In addition, when game balls win the first start port 225, the second start port 244, the general winning ports 256a to 256d, and the big winning port 239, the number of game balls set in advance according to the type of each winning port. Is dispensed to the upper plate 221 or the lower plate 222.

  Further, in this example, after the big hit game is over, the gaming state shifts to a short time state in which the winning probability of the normal symbol lottery becomes a high probability state and the holding ball of the special symbol game is easily stored by the support by the ordinary electric accessory 248. There is a case. In this example, in the short-time state, passing the game ball to the passing gate 254 is a condition for executing the normal symbol lottery, so that the game proceeds while making a right strike.

  Further, when a big hit occurs in the right-handed state, it is possible to win the big winning opening 239 by continuing the right-handed as it is. Further, when the support by the ordinary electric accessory 248 is not received, the game is advanced while making a left strike.

  In addition, as shown in FIG. 131, three effect buttons 280a, 280b, and 280c are provided on the front side of the upper plate 221, and during these mini-games such as a push game, a card turn, a sugoro, etc. By pressing the effect button, the effect display content on the liquid crystal display device 232 can be changed.

  In this example, as described above, the example in which the liquid crystal display device 232 is used as the production means has been described, but the present invention is not limited to this. As the production means, for example, production means such as a plasma display, a rear projection display, a CRT display, a lamp, a speaker, and a movable accessory may be used.

[Pachinko circuit configuration]
Next, the circuit configuration of the pachinko 210 in this example will be described with reference to FIG. FIG. 134 is a block diagram showing a circuit configuration of the pachinko 210 of this example.

  The pachinko 210 is mainly composed of a main control circuit 260 that controls a game and a sub-control circuit 400 that controls an effect according to the progress of the game.

  The main control circuit 260 includes a main CPU 266, a main ROM 268 (read only memory), and a main RAM 270 (read / write memory).

  The main CPU 266 is connected to the main ROM 268, the main RAM 270, and the like, and has a function of executing various processes in accordance with programs stored in the main ROM 268.

  The main ROM 268 stores various programs for controlling the operation of the pachinko 210 by the main CPU 266, various programs for causing the main CPU 266 to execute main processing, and various tables necessary for the various processes.

  The main RAM 270 is a temporary storage area of the main CPU 266 and has a function of storing various flags and variable values necessary for various processes. In this example, an example in which the main RAM 270 is used as the temporary storage area of the main CPU 266 will be described. However, the present invention is not limited to this, and the temporary storage area of the main CPU 266 may be any readable / writable storage medium. Things can be used.

  The main control circuit 260 includes an initial reset circuit 264, an I / O port 271, and a command output port 272. The initial reset circuit 264 is a circuit that generates a reset signal when the power is turned on, and is connected to the main CPU 266. The I / O port 271 is a port that transmits input signals from various devices to the main CPU 266, and a port that transmits output signals from the main CPU 266 to various devices. The command output port 272 is a port for transmitting a command output from the main CPU 266 to the sub control circuit 400.

  The main control circuit 260 includes a backup capacitor 274. The backup capacitor 274 is provided to quickly supply power to the main RAM 270, for example, when power is interrupted. As a result, various data stored in the main RAM 270 can be held even when power is interrupted.

  Various devices are connected to the main control circuit 260.

  In this example, the first special symbol display device 235a and the second special symbol display device 235b that perform variable display of the special symbol in the special symbol game as various devices according to the signal output from the main control circuit 260, in the special symbol game First special symbol hold display LEDs 234a and 234b and second special symbol hold display LEDs 234c and 234d for displaying the number of reserved special symbols for variable display, and a normal symbol display device for performing variable display of normal symbols as identification symbols in a normal symbol game 233, normal symbol hold display LEDs 250a and 250b for displaying the number of hold of variable display of the normal symbol in the normal symbol game, the start-port solenoid 318 for bringing the tongue-like member 248a of the normal electric accessory 248 into the protruding state or the retracted state, and the shutter 240 , And the grand prize winning opening 239 is opened or closed Winning opening solenoid 320 such that the state is connected to the main control circuit 260.

  The main control circuit 260 is used to transmit data to a call device (not shown) having a function of calling a hall attendant, a function of displaying the number of hits, and a hall computer that manages pachinko gaming machines throughout the hall. An external terminal board 510 is connected.

  Further, the main control circuit 260 includes, for example, a count switch 304 that supplies a predetermined detection signal to the main control circuit 260 when the game ball passes through an area in the big winning opening 239, and general winning holes 256a to 256d. When a game ball passes, the main detection circuit switches 306, 308, 310, 312 and a pass gate 254 that supply a predetermined detection signal to the main control circuit 260. When the game ball wins the passing gate switch 314 and the first starting port 225 supplied to the control circuit 260, the first starting winning port switch 316 and the second starting port 244 that supply a predetermined detection signal to the main control circuit 260. When a game ball wins, a second start winning port switch 317 that supplies a predetermined detection signal to the main control circuit 260, a back-up at power failure, etc. Such as backup clear switch 324 to be cleared in accordance with the Pudeta operation of the gaming field of administrators is connected.

  The main control circuit 260 is connected to a payout / launch control circuit 326. The payout / firing control circuit 326 is connected to a payout device 328 for paying out game balls, a launch device 330 for launching game balls, and a card unit 500. Note that the card unit 500 can be transmitted / received to / from a ball lending operation panel 355 that outputs a signal for requesting the card unit 500 to lend a game ball by a player's operation.

  The payout / launch control circuit 326 receives a prize ball control command supplied from the main control circuit 260 and a lending ball control signal supplied from the card unit 500, and transmits a predetermined signal to the payout device 328. The game ball payout operation by the payout device 328 is controlled. Further, the payout / firing control circuit 326 supplies electric power to the firing solenoid according to the turning angle when the launching handle 226 is gripped by the player and is turned clockwise. Controls the launch operation of the sphere.

  Further, the sub control circuit 400 is connected to the command output port 272. The sub control circuit 400 performs display control in the liquid crystal display device 232, control related to sound generated from the speaker 246, control of lamps including a decoration lamp, and the like in accordance with various commands supplied from the main control circuit 260. Further, the sub control circuit 400 has the same configuration as the configuration of the sub control circuit 70 described in the pachislot 1 of the above embodiment, and can execute the same various processes. Furthermore, a sub device such as a scaler control board 80 may be connected to the sub control circuit 400 as in the sub control circuit 70 of the pachislot 1 of the above embodiment.

  In this example, a command can be supplied from the main control circuit 260 to the sub control circuit 400, but a signal cannot be supplied from the sub control circuit 400 to the main control circuit 260. However, the present invention is not limited to this, and a configuration may be adopted in which a signal can be transmitted from the sub control circuit 400 to the main control circuit 260.

  Even in the pachinko machine 210 of the above-described modified example, the sub-control circuit 400 can execute the error detection process and the monitoring process of illegal operations such as the goto action described in the pachislot 1 of the above embodiment. The same effect as the above embodiment can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Pachi slot, 1a ... Cabinet, 1b ... Front door, 2 ... Door key, 3L, 3C, 3R ... Reel, 4L, 4C, 4R ... Symbol display area, 10 ... Liquid crystal display device, 20S ... Stop switch, 21S ... Start switch 31 ... main CPU, 32 ... main ROM, 33 ... main RAM, 39 ... motor drive circuit, 49L, 49C, 49R ... stepping motor, 50 ... reel position detection circuit, 60 ... main control circuit, 70 ... sub-control circuit, 71 ... sub CPU, 71a ... communication error detection means, 71b ... procedure detection means, 71c ... data destruction detection means, 71d ... error information registration means, 71e ... received data log storage means, 71f ... error information history display means, 71g ... Two-dimensional code conversion means 71h Sub-device error detection means 72 Sub-ROM 73 RAM (DRAM), 73a ... error information history storage area, 74 ... Backup RAM (SRAM), 80 ... scaler control board, 90 ... power interruption detecting circuit, 100 ... sub-device group

Claims (2)

Control means for executing control relating to the game;
Power supply monitoring means for monitoring a power supply voltage supplied to the control means;
Storage means for maintaining and rewriting stored information;
Display means for displaying predetermined information,
The power supply monitoring means monitors the lowering of the power supply voltage supplied to the control means and outputs an interrupt signal to the control means when the power supply voltage falls below a predetermined power supply voltage. Have
The control means includes an interrupt processing means for performing predetermined processing based on the interrupt signal from the interrupt signal generating means, and a monitoring means for monitoring the content processed by the interrupt processing means at a predetermined cycle And having
The first generation information indicating that the interrupt signal is generated is different from the first generation information and is associated with a plurality of types of generation modes of the plurality of first generation information. A plurality of types of second generation information that is information,
It said interrupt processing means stores the previous SL first occurrence information and the date and time information in the storage means,
It said monitoring means, on the basis of the above stored in the storage means the first occurrence information and the date and time information, a plurality of the first second occurrence information one predetermined corresponding to the occurrence mode of occurrence information A gaming machine characterized in that it can be displayed on the display means instead of a plurality of the first occurrence information . The game according to claim 1 , wherein the generation modes of the plurality of first generation information include the number of times of generation of the first generation information and the generation period of the plurality of first generation information. Machine.

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