JP6362448B2 - Power supply selection circuit, signal processing circuit using the same, and electronic equipment - Google Patents

Description

  The present invention relates to a power supply selection circuit used in a multi-power supply system.

  An electronic device having a built-in battery is configured to be operable using power from an external power adapter or bus in addition to power from the built-in battery. ICs (Integrated Circuits) installed in electronic devices that support multiple power supplies have a plurality of power supply terminals that receive battery voltage and voltage from an external power supply, respectively, and the power supply voltage is selected by a power supply selection circuit built into the IC. , Is operational.

FIG. 1 is a circuit diagram of a signal processing circuit 200r including a power supply selection circuit 100r examined by the present inventors.
The signal processing circuit 200r includes a plurality of power supply terminals VDD1 to VDD3, a capacitor connection terminal REG, a power supply selection circuit 100r, internal circuits 202 and 206, and a power supply circuit 204. An external capacitor C1 is connected to the capacitor connection terminal REG. The power supply voltages V _{DD1 to} V _DD3 from different power supplies are supplied to the plurality of power supply terminals VDD1 to _VDD3 . For example, when the signal processing circuit 200r is mounted on a notebook PC, the bus voltage V _BUS from the USB host, the battery voltage V _BAT from the battery, and the voltage V _AC from the AC adapter are supplied to the power supply terminals VDD1 to VDD3, respectively. Is done.

Power selection circuit 100r, a plurality of power supply voltages _{V BUS,} V _BAT, among _{V AC,} select the power supply voltage currently input, and outputs to the internal bus 20 steps down to a predetermined level. The internal bus 20 is connected to the REG terminal.

  The power supply selection circuit 100r includes a plurality of clamp circuits 10_1 to 10_3. The clamp circuit 10 is a diode clamp circuit and has the same configuration. Specifically, the clamp circuit 10 includes a Zener diode 12, a first transistor 14, a second transistor 16, and a resistor R1. The first transistor 14 and the second transistor 16 are N-channel MOSFETs, and are arranged to face each other so that the body diodes are reversed. The gates of the first transistor 14 and the second transistor 16 are connected in common and connected to the corresponding power supply terminal VDD via the resistor R1. A Zener diode 12 is provided between the gates of the first transistor 14 and the second transistor 16 and the ground.

When a voltage is supplied to the power supply terminal V _DD , the gate voltages of the first transistor 14 and the second transistor 16 are clamped to the Zener voltage Vz by the Zener diode 12. And the internal bus 20, the gate voltage Vz, the gate-source voltage _{V F} drop the voltage _{V REG} of the first transistor 14 is generated. If Vz = 5.5V and V _F = 0.5V, the internal voltage V _REG becomes Vz−V _F ≈5V.

  The clamp circuits 10_1 to 10_3 constitute a so-called diode OR circuit. Therefore, when a plurality of power supply voltages are supplied, they are stepped down to the same voltage level and generated in the internal bus 20.

Internal circuits 202 and 206 and a power supply circuit 204 are connected to the internal bus 20. The internal circuit 202 is a 5V system circuit. The power supply circuit 204 is, for example, an LDO (Low Drop Output), and steps down the internal power supply _VREG to 1.5V. The internal circuit 206 is a 1.5V system circuit.

JP 2011-239482 A JP 2008-078723 A

As a result of studying the power supply selection circuit 100r of FIG. 1, the present inventor has recognized the following problems. In the power supply selection circuit 100r of FIG. 1, the plurality of power supply terminals VDD1 to VDD3 are equal and have no priority. Thus, for example, to the power supply terminal VDD2 is 19V voltage _{V AC,} when the battery voltage _{V BAT} of 8.4V to the power supply terminal VDD3 is supplied simultaneously, the internal circuit 202, the power supply circuit 204, from both the power adapter and the battery Electric power will be supplied.

  Here, a designer who has an electronic device equipped with the signal processing circuit 200r will not want the internal battery to be consumed when he wants to extend the duration of the internal battery. Alternatively, another electronic device designer may desire to preferentially consume the built-in battery from the viewpoint of power loss. The power supply selection circuit 100 in FIG. 1 has a problem that it cannot meet the demands of such designers.

  The present invention has been made in such a situation, and one exemplary object of an embodiment thereof is to provide a power supply selection circuit capable of selecting a power supply voltage of an appropriate channel.

  One embodiment of the present invention relates to a power supply selection circuit that receives a plurality of different power supply voltages from power supplies of a plurality of channels. The power supply selection circuit corresponds to a plurality of channels, each of which corresponds to a plurality of power supply terminals that receive a corresponding power supply voltage, an internal bus, and a plurality of channels, and each of the corresponding power supply voltages is clamped to a predetermined clamp voltage or less. Corresponding to a plurality of clamp circuits, a plurality of channels, each of a plurality of first switches provided in parallel with the corresponding clamp circuit, and corresponding to a plurality of channels, each of the output terminal of the corresponding clamp circuit and the internal bus A plurality of second switches provided therebetween, a plurality of voltage determiners corresponding to a plurality of channels, each of which determines a voltage level of a corresponding power supply voltage, and a priority order of the plurality of channels are determined. And a controller for controlling the plurality of first switches and the plurality of second switches based on the outputs of the plurality of voltage determiners. And, equipped with a.

  According to this aspect, the designer of the device equipped with the power supply selection circuit selects and uses the power supply of the optimum channel by connecting the power supply to be used with priority to the power supply terminal of the channel with higher priority. can do.

The voltage determiner may be configured to determine whether or not the corresponding power supply voltage is included in a predetermined normal voltage range. When there are a plurality of power supply voltages included in the normal voltage range, the controller turns on the first switch and the second switch of the channel with the highest priority among them, and turns off the second switches of the other channels. It is good.
By turning on the first switch, the diode clamp circuit is bypassed, and the voltage drop can be reduced to reduce the power loss. In addition, by turning off the second switches of channels with low priority, it is possible to reliably prevent power from being consumed from the power sources of those channels.

  For each channel, the controller may turn on the first switch when the power supply voltage is included in the normal voltage range. In this case, it is only necessary to control the first switch of each channel based only on the power supply voltage of that channel, and it is not necessary to refer to other channels, so that the control of the controller can be simplified.

Each of the plurality of first switches may be configured to be turned off at the time of startup.
Thus, when an overvoltage is input to a certain channel, it is possible to prevent the clamp circuit from being bypassed and an overvoltage to be supplied to the power supply bus.

  The controller may operate by receiving the voltage of the internal bus. Each of the plurality of second switches may be configured to be turned on at startup. Thus, it is ensured that at least one power supply voltage is supplied to the internal bus via the clamp circuit, and the controller can be operated reliably.

  The first switch may include two P-channel MOSFETs arranged to face each other in series so that the body diodes are reversed. Thereby, the backflow of an electric current can be prevented.

  The second switch may be a P-channel MOSFET whose source is connected to the output terminal of the corresponding clamp circuit and whose drain is connected to the internal bus.

  The voltage determiner includes an overvoltage lockout circuit that compares the power supply voltage with an upper threshold value in a predetermined normal voltage range, and an undervoltage lockout circuit that compares the power supply voltage with a lower threshold value in a predetermined normal voltage range. , May be included.

  In the first channel with the highest priority, the controller turns on the first switch of the first channel when (1A) the power supply voltage of the first channel is included in the normal voltage range, and (1B) the first channel when not included. (2A) when the power supply voltage of the first channel is higher than the upper threshold and the power supply voltage of at least one other channel is included in the normal voltage range, 2 switch may be turned off, and (2B) otherwise, the second switch of the first channel may be turned on.

  In the second channel having the second priority, the controller turns on the first switch of the second channel when (1A) the power supply voltage of the second channel is included in the normal voltage range, and (1B) when the power supply voltage of the second channel is not included. The two-channel first switch may be turned off.

The voltage selection circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  The voltage selection circuit may include a capacitor connection terminal connected to the internal bus, and a capacitor may be externally attached to the capacitor connection terminal. Thereby, the voltage of the internal bus can be stabilized.

  One of the power sources of the plurality of channels may be a USB (Universal Serial Bus) host. One of the multi-channel power supplies may be an AC adapter. One of the power sources of the plurality of channels may be a built-in battery of a battery-driven electronic device on which a power source selection circuit is mounted.

  Another aspect of the present invention relates to a signal processing circuit. The signal processing circuit may include any of the power supply selection circuits described above and an internal circuit that operates in response to the voltage of the internal bus of the power supply selection circuit, and may be integrated on a single semiconductor substrate.

  The signal processing circuit may conform to USB (Universal Serial Bus) -PD (Power Delivery) standards. One power supply terminal of the power supply selection circuit may be connected to the USB bus, and the internal circuit may communicate with the power supply of the USB host via the USB bus and negotiate the bus voltage to be supplied.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes the above-described signal processing circuit.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, an appropriate channel power supply voltage can be selected.

It is a circuit diagram of a signal processing circuit provided with a power supply selection circuit examined by the present inventors. It is a circuit diagram of a signal processing circuit including a power supply selection circuit according to an embodiment. FIGS. 3A and 3B are circuit diagrams illustrating configuration examples of the first switch and the second switch. It is a flowchart regarding control of a some 1st switch. 5A to 5C are truth tables of a plurality of second switches. 1 is a block diagram of an electronic device including a signal processing circuit according to an embodiment. It is an external view of an electronic device.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state. In addition, “the state in which the member C is provided between the member A and the member B” means that the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 2 is a circuit diagram of a signal processing circuit 200 including the power supply selection circuit 100 according to the embodiment. The signal processing circuit 200 includes a power supply selection circuit 100, internal circuits 202a to 202c, and power supply circuits 204a and 204b, and is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate.

The power supply selection circuit 100 receives a plurality of different power supply voltages V _{DD1 to} V _DD3 from the power supplies PS1 to PS3 of the plurality of channels CH1 to CH3 and supplies them to the internal circuit 202 and the power supply circuit 204 connected to the internal bus 20. Although the number of channels may be arbitrary, in this embodiment, the case of three channels will be described for easy understanding.

  The power supply selection circuit 100 includes a plurality of power supply terminals VDD1 to VDD3, a capacitor connection terminal REG, an internal bus 20, a plurality of clamp circuits 10_1 to 10_3, a plurality of voltage determiners 30_1 to 30_3, a controller 40, and a plurality of first switches SW1_1 to SW1_1. SW1_3 and a plurality of second switches SW2_1 to SW2_3 are provided.

The plurality of power supply terminals VDD correspond to a plurality of channels CH, and each receives a corresponding power supply voltage V _DD .

The plurality of clamp circuits 10 correspond to the plurality of channels CH, and clamp the corresponding power supply voltage V _DD to a predetermined clamp voltage V _CL or less. For example, the clamp circuit 10 may be a diode clamp circuit including a Zener diode 12, a first transistor 14, a second transistor 16, and a resistor R1. However, the configuration of the clamp circuit 10 is not limited thereto. For example, the clamp voltage _VCL is set around 5V.

The plurality of first switches SW1 correspond to the plurality of channels CH and are provided in parallel with the corresponding clamp circuits 10 respectively. The plurality of second switches SW2 correspond to the plurality of channels CH, and are provided between the output terminal of the clamp circuit 10 and the internal bus 20 corresponding to each of the plurality of channels CH. FIGS. 3A and 3B are circuit diagrams illustrating configuration examples of the first switch SW1 and the second switch SW2.
As shown in FIG. 3A, the first switch SW1 includes two P-channel MOSFETs arranged in series so as to face each other in the opposite direction.
As shown in FIG. 3B, the second switch SW2 is a P-channel MOSFET having a source connected to the output terminal of the corresponding clamp circuit 10 and a drain connected to the internal bus 20.

Returning to FIG. The plurality of voltage determiners 30 correspond to the plurality of channels CH, and determine the voltage level of the power supply voltage V _DD corresponding to each channel CH. More specifically, the voltage determiner 30 is configured to determine whether or not the corresponding power supply voltage V _DD is included in a predetermined normal voltage range. The voltage determiner 30 includes an overvoltage lockout circuit 32 that compares the power supply voltage V _DD with an upper threshold value of a predetermined normal voltage range to V _OVLO, and _sets the power supply voltage V _DD as a lower voltage threshold value of the normal voltage range to V _UVLO. An undervoltage lockout circuit 34 may be included.

The upper threshold value V _OVLO is set higher than the clamp voltage V _CL , and the lower threshold value V _UVLO is set lower than the clamp voltage V _CL . For example, when the clamp voltage V _CL is 5V, the upper threshold value V _OVLO is determined to be around 5.5V and the lower threshold value V _UVLO is set to around 4.5V.

  In the controller 40, the priority order of the plurality of channels CH1 to CH3 is determined. In the present embodiment, it is assumed that CH1 has the highest priority and becomes lower in the order of CH2 and CH3.

  The controller 40 is configured to control the plurality of first switches SW1_1 to SW1_3 and the plurality of second switches SW2_1 to SW2_3 based on the priority order and the outputs of the plurality of voltage determiners 30.

The internal bus 20 is supplied with power from an arbitrary power source PS according to the on / off states of the plurality of first switches SW1_1 to SW1_3 and the plurality of second switches SW2_1 to SW2_3. The internal bus 20 is connected to the capacitor connection terminal REG, and a large-capacity capacitor C1 is externally attached to the capacitor connection terminal REG. The capacitor C1 can suppress the fluctuation of the internal power supply voltage V _REG generated in the internal bus 20 when the load is changed or the switch is switched.

Internal circuit 202 and power supply circuit 204 operate upon receiving internal power supply voltage V _REG .
The internal circuit 202c is a 5V system circuit, and can operate by directly receiving the internal power supply voltage V _REG in the vicinity of V _CL = 5V. The internal circuit 202a is a 2.8V system, and the power supply circuit 204a steps down the internal power supply voltage _VREG to 2.8V and supplies it to the internal circuit 202a. The internal circuit 202b is a 1.5V system, and the power supply circuit 204b steps down the internal power supply voltage _VREG to 1.5V and supplies it to the internal circuit 202b. Note that the operating voltage of the internal circuit 202 is not particularly limited.

The controller 40 and the voltage determiners 30_1 to 30_3 operate upon receiving the voltage V _REG of the internal bus 20, and therefore belong to any of the internal circuits 202a to 202c. Subsequently, specific control by the controller 40 will be described.

When there are a plurality of power supply voltages V _DD included in the normal voltage range, the controller 40 turns on the first switch SW1_i and the second switch SW2_i of the channel CHi having the highest priority among them, and sets the other channels. The second switch SW_j (j ≠ i) is turned off. This is the basic operation of the controller 40.

  More specifically, the controller 40 may perform the following control. When the signal processing circuit 200 is activated, the controller 40 turns off the plurality of first switches SW1_1 to SW1_3 and turns on the plurality of second switches SW2_1 to SW2_3, and then performs a determination process.

For each channel k, the controller 40 turns on the first switch SW1_k when the power supply voltage V _DDk is included in the normal voltage range.

The control of the controller 40 is summarized as follows.
Highest priority first channel CH1:
SW1_1: (1A) When the power supply voltage V _DD1 of the first channel CH1 is included in the normal voltage range, the first switch SW1_1 of the first channel CH1 is turned on. (1B) When not included, the first channel CH1 first The switch SW1_1 is turned off.
SW2_1: (2A) When the power supply voltage V _DD1 of the first channel CH1 is higher than the upper threshold value V _OVLO and at least one of the power supply voltages V _DD2 and V _DD3 of the other channels is included in the normal voltage range The second switch SW2_1 of the first channel CH1 is turned off, and (2B) otherwise, the second switch SW2_1 of the first channel CH1 is turned on.

Second priority channel 2 CH2:
SW1_2: (1A) when the power supply voltage _{V DD2} of the second channel CH2 are included in the normal voltage range, the first switch SW1_2 of the second channel CH2 on, the first switch of the second channel when not included (1B) SW1_2 is turned off.
SW2_2: (2A) (i) When the power supply voltage V _DD1 of the first channel CH1 is higher than the upper threshold value V _OVLO , or (ii) Power supply voltages V _DD1 and V _{DD2 of} the first channel CH1 and the second channel CH2 Is higher than the upper threshold value V _OVLO and the power supply voltage V _DD3 of the other channel CH3 is included in the normal voltage range, or (iii) the power supply voltages V _{DD1 to} V _{DD3 of} all the channels CH1 to _CH3 are on the upper side When higher than the threshold value V _OVLO , the second switch SW2 of the second channel CH2 is turned off. (2B) In other cases, the second switch SW2 of the second channel CH2 is turned on.

Third-preferred third channel CH3:
SW1_3: (1A) When the power supply voltage V _DD3 of the third channel CH3 is included in the normal voltage range, the first switch SW1_3 of the third channel CH3 is turned on. The switch SW1_3 is turned off.
SW2_3: (2A) (i) when at least one of the power supply voltage _{V DD1, V DD2} other channels CH1, CH2 are included in the normal voltage range, or (ii) all channels CH1~CH3 supply voltage _V DD1 ~V _{When DD3} is higher than the upper threshold value _VOVLO , the third switch SW3 of the third channel CH3 is turned off. (2B) In other cases, the third switch SW3 of the third channel CH3 is turned on.

  After the activation of the signal processing circuit 200 is completed, the controller 40 continues to monitor the outputs of the voltage determiners 30_1 to 30_3, and when the outputs change, the state of the first switches SW1_1 to SW1_3 and the second switches SW2_1 to SW2_3 is updated. .

The above is the configuration of the power supply selection circuit 100. Next, the operation will be described.
FIG. 4 is a flowchart regarding control of the plurality of first switches SW1.
When the signal processing circuit 200 is activated, the first switches SW1_1 to SW1_3 of all the channels CH1 to CH3 are turned off (S100). Thereby, when an overvoltage power supply voltage is input, it can be prevented from being applied to the internal bus 20 without going through the clamp circuit 10.

When the controller 40 and the plurality of voltage determiners 30_1 to 30_3 are operable, the control of the first switch SW1 is started. For each of the plurality of channels CH1 to CH3 (S102), the controller 40 determines whether or not the power supply voltage V _DDi is included in the normal voltage range (S104). When included in the i-th channel CHi (Y in S104), the first switch SW1_i of the channel CHi is turned on (S106). When not included (N in S104), the first switch SW1_i is turned off (S108).

  The controller 40 repeats the process S102 at a predetermined cycle. The controller 40 may simultaneously control the first switch SW1 of a plurality of channels.

  FIGS. 5A to 5C are truth tables of the plurality of second switches SW2_1 to SW2_3. A blank in the truth table indicates ON.

Reference is made to FIG. The second switch SW2_1 of the first channel CH1 is kept on as long as V _DD1 <V _OVLO . In the case of V _OVLO <V _DD1 , it is turned off when the power supply voltages V _DD2 and V _{DD3 of} the second channel CH2 or the third channel CH3 are included in the normal voltage range, and is kept on otherwise.

Reference is made to FIG. The second switch SW2_2 of the second channel CH2 is off when the channel CH1 having a higher priority than itself is included in the normal voltage range (V _UVLO <V _DD1 <V _OVLO ).
Further, when the channel CH1 having a higher priority than itself is in a low voltage state (V _DD1 <V _UVLO ), the channel CH3 having a lower priority than itself is in the overvoltage state (V _DD2 <V _OVLO ). It is off when included in the range (V _UVLO <V _DD3 <V _OVLO ), and is on otherwise.
When the channel CH1 higher priority than they are over-voltage condition _(V OVLO _{<V DD1)} is itself an overvoltage condition _{(V DD2 <V OVLO),} and the channel CH3 lower priority than you are not a low voltage state It is off when (V _UVLO <V _DD3 ) and is on otherwise.

Reference is made to FIG. The second switch SW2_3 of the third channel CH3 is off when the uppermost channel CH1 is included in the normal voltage range (V _UVLO <V _DD1 <V _OVLO ).
Further, the second switch SW2_3 is configured such that (i) the second channel CH2 is in a normal voltage range (V _UVLO <V _DD2 <V _OVLO ) when the uppermost channel CH1 is in a low voltage state (V _DD1 <V _UVLO ). ), Or (ii) when both the second channel CH2 and the third channel CH3 are in an overvoltage state (V _OVLO <V _DD2 && V _OVLO <V _DD3 ). Otherwise it is on.
Further, the second switch SW2_3 is configured such that when the highest channel CH1 is in an overvoltage state (V _OVLO < _VDD1 ), (i) when the second channel CH2 is in a normal voltage range (V _UVLO <V _DD2 <V _OVLO ). Or (ii) when the third channel CH3 is in an overvoltage state (V _OVLO <V _DD3 ), it is off. Otherwise it is on.

  The above is the operation of the power supply selection circuit 100. Next, the advantages will be described.

  According to the power source selection circuit 100, the plurality of channels CH1 to CH3 are prioritized and the power of the channel with the higher priority is used with priority. Therefore, the designer of the device on which the signal processing circuit 200 is mounted should select and use the power supply of the optimum channel by connecting the power supply to be used with priority to the power supply terminal of the channel having a higher priority. Can do.

  In the power source selection circuit 100, the first switch SW1 is provided in parallel with the clamp circuit 10, and the clamp circuit 10 is bypassed by turning on the first switch SW1 of the used channel, thereby reducing the voltage drop and reducing the power loss. it can. In addition, by turning off the second switch SW2 of the unused channel with low priority, it is possible to reliably prevent power from being consumed from the power source of the channel CH2.

  The controller 40 turns on the first switch when the power supply voltage is included in the normal voltage range for each channel. That is, since the first switch of each channel is controlled based only on the power supply voltage of that channel, there is no need to refer to other channels. Thereby, control of the controller 40 can be simplified.

  Further, the plurality of first switches SW1 are configured to be turned off at the time of startup. Thereby, when an overvoltage is input to a certain channel, the clamp circuit 10 is bypassed and an overvoltage can be prevented from being supplied to the internal bus 20.

  The plurality of second switches SW2 are configured to be turned on at the time of startup. Thereby, it is ensured that at least one power supply voltage is supplied to the internal bus 20 via the clamp circuit, and the controller 40 can be operated reliably.

(Use)
Next, the application of the signal processing circuit 200 will be described. FIG. 6 is a block diagram of an electronic device 500 including the signal processing circuit 200 according to the embodiment. FIG. 7 is an external view of the electronic device 500.
The electronic device 500 is a notebook PC, a smart phone, a tablet terminal, a digital camera, a portable audio player, or the like.
In addition to the signal processing circuit 200, the electronic device 500 includes a USB port 502, an AC adapter port 504, a built-in battery 506, a USB transceiver 508, a charging circuit 510, a power supply circuit 512, a USB-PD controller 514, and a load 520.

The built-in battery 506 is a secondary battery such as lithium ion or nickel metal hydride, and outputs a battery voltage V _{BAT of 4} to 8.4 V corresponding to the remaining battery level. A host device 600 is detachably connected to the USB port 502 via a USB cable 604. The host device 600 supplies the bus voltage _VBUS via the bus line 606 of the USB cable 604. The host device 600 and the electronic device 500 can perform data communication via data lines (608) D + and D-. Communication via the data lines D + and D− is performed by the USB transceiver 508.

An AC adapter 602 is detachably connected to the AC adapter port 504. The AC adapter 602 converts the _AC voltage V _AC into a DC voltage V _DC and supplies it to the AC adapter port 504.

The electronic device 500 is compliant with the USB-PD standard. When the host device 600 compliant with the USB-PD standard is connected to the USB port 502, the electronic device 500 and the host device 600 negotiate the voltage level and the charging current of the bus voltage _VBUS by communication via the bus line 606. To do. The voltage level of the bus voltage V _BUS before the negotiation is 5V. The USB-PD controller 514 is an IC for performing communication for negotiating the bus voltage _VBUS and the charging current via the bus line 606. The host device 600 supplies the bus voltage _VBUS at the voltage level determined by negotiation to the electronic device 500. The bus voltage and charging current determined by the negotiation are notified to the charging circuit 510.

The charging circuit 510 receives the bus voltage V _BUS from the host device 600 or the DC voltage _VDC from the AC adapter 602 and charges the built-in battery 506. For example, the direct voltage _VDC is 12V. When the built-in battery 506 is charged with power from the host device 600, the charging circuit 510 charges the built-in battery 506 with the amount of charging current determined by negotiation.

Charging circuit 510 outputs battery voltage V _BAT to power supply circuit 512 when host device 600 and AC adapter 602 are not connected. When the host device 600 or the AC adapter 602 is connected, the power from them is preferentially output to the power supply circuit 512.

The power supply circuit 512 receives the battery voltage V _BAT , the bus voltage V _BUS , and the DC voltage V _DC via the charging circuit 510. The power supply circuit 512 is a multi-channel power supply and includes a DC / DC converter or a linear regulator (LDO). The power supply for each channel boosts or steps down the voltage from the charging circuit 510 and supplies it to the load 520. For example, the load 520 includes a CPU 520a, a memory 520b, a display 520c, and the like.

  The power supply selection circuit 100 according to the embodiment can be suitably used for the USB-PD controller 514. That is, the USB-PD controller 514 corresponds to the signal processing circuit 200 in FIG. The USB-PD controller 514 (200) includes a power supply selection circuit 100, a USB-PD communication unit 202d, and a power supply circuit 204.

The VDD1 terminal of the USB-PD controller 514 is connected to the host device 600 (PS1) via the bus line 606. The VDD2 terminal is connected to the AC adapter 602 (PS2). The VDD3 terminal is connected to the built-in battery 506 (PS3). The power supply selection circuit 100 selects one from the bus voltage V _BUS , the battery voltage V _BAT , and the direct current voltage V _DC and outputs it to the internal bus 20. The power supply circuit 204 steps down the voltage of the internal bus 20. The USB-PD communication unit 202 d corresponds to the internal circuit 202 in FIG. 2 and performs negotiation via the bus line 606.

The above is the configuration of the electronic device 500. According to the electronic device 500, since the host device 600 is connected to the highest priority VDD1 terminal, the power of the host device 600 is used with the highest priority. As described above, the initial value of the bus voltage V _BUS before the negotiation is 5 V, whereas the DC voltage V _DC from the AC adapter 602 is 12 V. Therefore, by preferentially using the bus voltage V _BUS , Power loss in the power supply selection circuit 100 can be greatly reduced.

  Subsequently, the AC adapter 602 connected to the VDD2 terminal has priority, and the built-in battery 506 connected to the VDD3 terminal is not used as much as possible. Thereby, the duration of the internal battery 506 can be lengthened.

  In electronic device 500, when priority is given to reducing the heat generation of USB-PD controller 514 over the duration of internal battery 506, internal battery 506 is connected to the VDD2 terminal and AC adapter 602 is connected to the VDD3 terminal. Also good.

Alternatively, when the rated voltage of the DC voltage _VDC from the AC adapter 602 is 5 V and is included in the normal voltage range of the power supply selection circuit 100, the AC adapter 602 may be connected to the VDD1 terminal to give the highest priority.

  As described above, by using the power supply selection circuit 100 according to the embodiment, the designer of the electronic device 500 can determine and use a power supply to be preferentially used according to the required specifications of the electronic device 500. it can.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
In the embodiment, the case where the power supply selection circuit 100 receives three power supply voltages has been described. However, the power supply voltage may be two, or may be four or more.

(Second modification)
In FIG. 2, since the voltage determiners 30_1 to 30_3 have the same configuration, one voltage determiner 30 may be used in a time division manner.

(Third Modification)
The control of the first switch SW1 to the second switch SW2 in the embodiment is an example, and there are various modifications. For example, in the embodiment, in the unused channel CHi, the first switch SW1_i is turned on as long as the power supply voltage V _DDi is included in the normal voltage range, but the first switch SW1_i of the unused channel CHi is turned off. Also good.

  Regarding the second switch SW2, the on / off conditions are not limited to the truth table of FIG.

(Fourth modification)
In the embodiment, the case where the power supply voltage V _DD is compared with the upper threshold value V _OVLO and the lower threshold value V _UVLO by the voltage determiner 30 has been described, but the present invention is not limited to this. The voltage determiner 30 may compare the power supply voltage V _DD with a single threshold (V _UVLO only, V _OVLO only, or another voltage level), or with more than two voltage levels. May be.

(5th modification)
The USB-PD controller 514 in FIG. 6 may be configured integrally with the IC of the charging circuit 510.

  Although the present invention has been described using specific words and phrases based on the embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Power supply selection circuit, 10 ... Clamp circuit, R1 ... Resistance, 12 ... Zener diode, 14 ... 1st transistor, 16 ... 2nd transistor, 20 ... Power supply bus, VDD ... Power supply terminal, C1 ... Capacitor, 30 ... Voltage determination 32 ... Overvoltage lockout circuit, 34 ... Undervoltage lockout circuit, 40 ... Controller, 200 ... Signal processing circuit, 202 ... Internal circuit, 204 ... Power supply circuit, SW1 ... First switch, SW2 ... Second switch, PS ... Power supply, VDD ... Power supply terminal, 500 ... Electronic device, 502 ... USB port, 504 ... AC adapter port, 506 ... Built-in battery, 508 ... USB transceiver, 510 ... Charging circuit, 512 ... Power supply circuit, 514 ... USB-PD controller 520 ... Load 520a ... CPU 520b ... Memory 520c ... LCD 60 ... the host device, 602 ... AC adapter.

Claims (15)

A power supply selection circuit that receives a plurality of different power supply voltages from a plurality of channel power supplies,
A plurality of power supply terminals corresponding to the plurality of channels, each receiving a corresponding power supply voltage;
An internal bus,
A plurality of clamp circuits corresponding to the plurality of channels, each of which clamps a corresponding power supply voltage below a predetermined clamp voltage;
A plurality of first switches corresponding to the plurality of channels, each provided in parallel with the corresponding clamp circuit;
A plurality of second switches provided between the output terminal of the clamp circuit and the internal bus, each corresponding to the plurality of channels;
A plurality of voltage determiners corresponding to the plurality of channels, each of which determines a voltage level of a corresponding power supply voltage;
A controller that controls the plurality of first switches and the plurality of second switches based on the priority and outputs of the plurality of voltage determiners;
Bei to give a,
The voltage determiner is configured to determine whether a corresponding power supply voltage is included in a predetermined normal voltage range;
In the first channel with the highest priority, the controller
(1A) When the power supply voltage of the first channel is included in the normal voltage range, the first switch of the first channel is turned on. (1B) When not included, the first switch of the first channel Turn off
(2A) When the power supply voltage of the first channel is higher than the normal voltage range and the power supply voltages of other channels are included in the normal voltage range, the second switch of the first channel is turned off, (2B) A power supply selection circuit characterized by turning on the second switch of the first channel at other times .   The controller in the second channel with the second highest priority,
  (1A) When the power supply voltage of the second channel is included in the normal voltage range, the first switch of the second channel is turned on. (1B) When not included, the first switch of the second channel The power supply selection circuit according to claim 1, wherein the power supply selection circuit is turned off.   The power supply selection circuit according to claim 1, wherein each of the plurality of first switches is configured to be turned off at the time of startup. The controller is operated by receiving the voltage of the internal bus,
Power supply selection circuit according to any one of claims 1 to 3, characterized in that it is configured to turn on at the respective plurality of second switches, during startup. Wherein the first switch, the power supply selection circuit according to any one of claims 1, characterized in that it comprises two P-channel MOSFET disposed opposite in series so that the body diode in the opposite direction 4. The second switch has a source connected to the output terminal of the corresponding clamp circuit, a drain according to claim 1, wherein the 5 to be the internal bus and connected P-channel MOSFET Power supply selection circuit. The voltage determiner is
And an overvoltage lockout circuit for comparing the upper threshold of the normal voltage range the power supply voltage,
And undervoltage lockout circuit for comparing the power supply voltage and the lower threshold of the normal voltage range,
Power supply selection circuit according to any one of claims 1 to 6, which comprises a. The power supply selection circuit according to any one of claims 1 to 7 , wherein the power supply selection circuit is integrated on a single semiconductor substrate. 9. The power supply selection circuit according to claim 8 , further comprising a capacitor connection terminal connected to the internal bus, wherein a capacitor can be externally attached to the capacitor connection terminal. Wherein the plurality of channels of source one, USB (Universal Serial Bus) power supply selection circuit according to any one of claims 1-9, characterized in that a host. Wherein one of the plurality of channels of power, the power supply selection circuit according to any one of claims 1 to 10, characterized in that the AC adapter. Wherein one of the plurality of channels of power, the power supply selection circuit according to any one of claims 1 to 11, characterized in that said power supply selection circuit is a built-in battery of the battery-driven electronic equipment mounted. A power supply selection circuit according to any one of claims 1 to 7 ,
An internal circuit that operates in response to the voltage of the internal bus of the power supply selection circuit;
And a signal processing circuit integrated on a single semiconductor substrate. The signal processing circuit conforms to the USB (Universal Serial Bus) -PD (Power Delivery) standard,
One power supply terminal of the power supply selection circuit is connected to a USB bus,
The signal processing circuit according to claim 13 , wherein the internal circuit communicates with a power source of a USB host via the USB bus and negotiates a bus voltage to be fed. An electronic apparatus comprising the signal processing circuit according to claim 13 .

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