JP6356647B2 - Current mirror circuit and memory cell - Google Patents

Description

  Embodiments described herein relate generally to a current mirror circuit and a memory cell.

  The current mirror circuit is a circuit used when distributing a current having the same magnitude as the reference current, or when distributing the current by multiplying the reference current by a magnification. For example, this is used when two or more current sources are required, but only one current source can be secured. This current mirror circuit is often composed of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a bipolar transistor.

  A current mirror circuit composed of a MOSFET normally drives an input-side transistor in a saturation current region. The saturation current of the transistor is proportional to the reciprocal of the channel length. For this reason, when the input current is reduced by a factor of 1/10 or 1/100 in a current mirror circuit composed only of a conventional MOSFET, that is, when an output current obtained by amplifying the input current at a high magnification is to be obtained. It is necessary to increase the channel length of the MOSFET on the input side.

  However, if the channel length is increased, the load capacity of the input side transistor increases. Furthermore, the layout area of the entire current mirror circuit is also increased.

JP 2014-73028 A JP2014-187296 JP 2004-319932 A JP-A-7-326729

  Therefore, the embodiment of the present invention realizes a current mirror circuit capable of lowering the input current region without increasing the channel length by using a TFET (Tunnel FET) and a MOSFET together in the current mirror circuit. That is, it is possible to realize a current mirror circuit capable of suppressing an increase in layout area and further suppressing an increase in parasitic capacitance on the input side while lowering an input current region.

A current mirror circuit according to an embodiment of the present invention includes:
A first transistor comprising a TFET through which an input current flows;
A second transistor composed of a MOSFET through which an output current flows, wherein the first transistor and the gate of each other are connected;
Is provided.

The current mirror circuit according to the embodiment of the present invention is
The drain of the first transistor composed of TFET and the gate of the first transistor are connected,
The gate of the second transistor constituted by the MOSFET and the gate of the first transistor are connected.

FIG. 1 is a diagram illustrating a current mirror circuit according to the first embodiment. FIG. 2 is a graph showing the relationship between the input current and the gate area of the current mirror circuit according to the first embodiment. FIG. 3 is a diagram schematically illustrating an example of the layout of the current mirror circuit according to the first embodiment. FIG. 4 is a diagram schematically illustrating an example of the layout of the current mirror circuit according to the first embodiment. FIG. 5 is a diagram illustrating a circuit simulation state of the current mirror circuit according to the first embodiment. FIG. 6 is a graph showing a circuit simulation result of the current mirror circuit according to the first embodiment. FIG. 7 is a diagram illustrating another example of the current mirror circuit according to the first embodiment. FIG. 8 is a diagram illustrating a memory cell and a memory array according to the second embodiment. FIG. 9 is a diagram illustrating another example of the memory array according to the second embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
The current mirror circuit according to the first embodiment reduces the input current region without increasing the channel length by using a transistor on the side where the input current flows as a TFET and a transistor on the side where the output current flows as a MOSFET. Is possible. More details will be described below.

  FIG. 1 is a diagram showing a current mirror circuit 10 according to the present embodiment. As shown in FIG. 1, the current mirror circuit 10 according to the present embodiment includes an n-type TFET 12 on the input side and an n-type MOSFET 14 on the output side. In general, the current mirror circuit uses a current having the same magnitude as the input current as an output current, or increases or decreases the input current by a predetermined magnification to obtain an output current. In this embodiment, the input current is 1 or more. Amplified at a predetermined magnification and output. That is, in this embodiment, it is assumed that the saturation current amount of the n-type TFET 12 during operation is smaller than the saturation current amount of the n-type MOSFET 14.

  In the n-type TFET 12, a drain D and a gate G are connected to an input terminal to which an input current IREF is input, and a source S is grounded. In the n-type MOSFET 14, the drain D is connected to the output terminal from which the output current IOUT is output, the gate G is connected to the gate G of the n-type TFET 12, and the source S is grounded. That is, the n-type TFET 12 and the n-type MOSFET 14 constitute a current mirror circuit to which the gates G of each other are connected. In the example of FIG. 1, the input current IREF is represented by the current source 16 as an example, but may be a current generated on the circuit.

FIG. 1 is a circuit diagram. Next, the configuration of the current mirror circuit 10 will be described from the viewpoint of layout. FIG. 2 is a diagram illustrating the relationship between the on-state current of the transistor and the gate area of the input-side transistor. Both the horizontal and vertical axes are represented by logarithmic axes. Here, the reference value “1” on the vertical axis is the gate area of the input-side transistor in the shortest channel length and the shortest channel width that can form both the TFET and the MOSFET. Also, placing the on-current of the TFET in the gate area of the input side transistor _{I On_TFET} Distant, the MOSFET on the current in the gate area of the input side transistor and _{I on_MOSFET.} Here, the on-current refers to the value of the drain current that flows when the transistor is on. As described above, since the input current region is considered to be lowered, the transistor on the input current side will be mainly described.

  The straight line rising to the right represents the gate area of the input side transistor of the TFET / MOSFET hybrid type current mirror circuit 10 having the TFET 12 on the input side and the MOSFET 14 on the output side. In TFET, there is no significant change in on-current due to increase / decrease in channel length, and the on-current increases when the channel width is widened. Therefore, it is necessary to increase the gate area of the input side transistor in order to increase the input current. Is shown. It can be seen that both the input current and the gate area of the input side transistor increase from the lower left point P3 to the upper right point P2.

  On the other hand, the straight line descending to the right represents the gate area of the input side transistor of the current mirror circuit including the MOSFET 14 on both the input side and the output side. The on-current of the MOSFET increases or decreases depending on the ratio of channel width / channel length. Since the value of the channel width cannot be further reduced, it can be seen that the area of the input current can be reduced by fixing the channel width to the minimum value and increasing the channel length. That is, when the input current of the current mirror circuit is reduced, it is necessary to increase the channel length, so that the gate area of the input side transistor increases. This is represented by a straight line from the lower right point P4 to the upper left point P1.

FIGS. 3A to 3D are diagrams showing the layout of the current mirror circuit at points P1 to P4 in FIG. Each current mirror circuit includes an input-side transistor and an output-side transistor each including a gate region G, a source region S, and a drain region D. In the input-side transistor, the gate region G and the drain region D are short-circuited. Here, let L ₀ be the shortest channel length capable of creating both TFETs and MOSFETs, and W ₀ be the minimum channel width. In each figure, the left side transistor of the current mirror is the input side, and the right side transistor is the output side transistor.

As shown in FIGS. 3A to 3D, the layout area of the current mirror circuit varies depending on the area of the gate region G. That is, in the layout of the current mirror circuit, the length of the channel length and the size of the channel width are realized by changing the size of the gate region G. Specifically, in a channel length of the input side is longer than L ₀ (a), the layout area becomes large based on the channel length is made longer. Similarly, in the channel width of the input side is greater than W ₀ (b), the layout area becomes large based on the larger the channel widths.

The current mirror circuit at a point P1 in FIG. 3 (a), the transistor on the input side and the output side are both composed of MOSFET, as described above, the channel length of the input side is longer than the L _0. The current mirror circuit at a point P2 in FIG. 3 (b), the transistor on the input side is composed of TFET, transistors on the output side is constituted by MOSFET, the channel width of the input side TFET is larger than the _{W 0} It has become. The layouts at the points P3 and P4 are configured with the minimum layout size as shown in FIGS. 3C and 3D, respectively.

2 and 3, the gate area increases toward the upper part of the graph of FIG. 2, and the layout area of the circuit increases accordingly. From the viewpoint of the layout area, the current mirror is displayed at the lower part of the graph. It is desirable to construct a circuit. Assuming that the channel length and the channel width are approximately the same size, the value on the horizontal axis at the intersection of the two graphs is a logarithmic scale, so it can be calculated that √ (I _{on_MOSFET} · I _{on_TFET} ). That is, in the range where the input current is I _{on_TFET} <(input current) <√ (I _{on_MOSFET} · I _{on_TFET} ), the current on the input side is composed of _TFETs and the output side transistor is composed of MOSFETs. The mirror circuit can reduce the layout area.

On the other hand, in the input current range where √ (I _{on_MOSFET} · I _{on_TFET} ) <(input current) <I _{on_MOSFET} , the current mirror circuit in which both the input side and output side transistors are constituted by MOSFETs is more _suitable. It can be seen that the layout area can be reduced. Note that when √ (I _{on_MOSFET} · I _{on_TFET} ) = (input current), there is no superiority or inferiority of the current input and layout area in either configuration of the current mirror circuit. The side transistor can be selected.

Next, an actual layout will be described. FIG. 4A is a diagram showing a circuit size including a margin and an offset determined from a design rule between active areas, ion implantation conditions, and the like. It is assumed that L ₀ is 120 nm, W ₀ is 90 nm, the MOSFET on-current is 50 uA, and the TFET on-current is 5 nA. The overall layout area is 580 nm × 500 nm in consideration of the above margin and offset. FIG. 4B shows the relationship between the input current and the circuit layout area in this case.

From this graph, as described above, in the range where 5 nA <(input current) <500 nA (= √ (50 uA · 500 nA)), it is possible to reduce the layout area by making the transistor on the input side TFET. I understand that. Note that the numerical values in this figure are given as examples and do not specify the present embodiment, and the range of the input current is I _{on_TFET} <(input current) <√ (I _{on_MOSFET} · I _{on_TFET} ) described above. That's fine.

  Next, the operation of the current mirror circuit 10 according to the present embodiment will be described with reference to FIG. FIG. 5A shows a circuit for operating the current mirror circuit 10 according to the present embodiment. Specifically, the drain voltage VDD is applied to the current mirror circuit 10 shown in FIG. 1, and the drain terminal of the output n-type MOSFET 14 is connected to the resistor R1 in order to monitor the current.

  When the voltage VDD is applied to the drain side of the n-type TFET 12 and the applied voltage VDD exceeds the gate threshold voltage of the n-type TFET 12, the n-type TFET 12 is turned on and a current flows between the drain and source of the n-type TFET 12. IREF flows. At this time, if the voltage Vx applied to the gates of both the n-type TFET 12 and the n-type MOSFET 14 exceeds the gate threshold voltage of the n-type MOSFET 14, the gate-source voltage and the drain current of the n-type MOSFET The current IOUT flows based on the electrical characteristics between the two. That is, since the output current IOUT changes according to the characteristics of the MOSFET on the output side, the desired output current IOUT can be obtained by changing the MOSFET as necessary.

  On the other hand, FIG. 5B shows a case where the input side transistor is changed from the n-type TFET 12 to the n-type MOSFET 14 having the same layout. In this case, if the characteristics of the transistors are exactly the same, current flows with the same gate threshold voltage, so that a current that satisfies IOUT = IREF flows to the output side. However, a large amount of current on the output side may flow under the influence of Early voltage.

  5A and 5B, for both the n-type TFET 12 and the n-type MOSFET 14, the channel length is 0.12 um, the channel width is 1 um, and the driving force of the n-type TFET 12 is n-type MOSFET 14. The driving force is about 1/1000. The resistance value of the resistor R1 is 1 MΩ. FIG. 6 shows a graph obtained by simulating these current mirror circuits by SPICE (Simulation Program with Integrated Circuit Emphasis) with a drain voltage VDD of 1.2V.

  FIG. 6 is a graph showing the simulation result, with the horizontal axis representing the input current IREF [A], the vertical half of the vertical axis representing the output current IOUT [A], and the vertical half of the vertical axis representing the output voltage VOUT [V]. It is. Note that the axes of the current IREF and the current IOUT are logarithmic axes. As shown in FIG. 6, the TFET / MOSFET hybrid type current mirror circuit 10 operates while the saturation current amount of the output current IOUT is the same as that of a current mirror circuit composed of only MOSFETs. It can be seen from the graph that the current region can be reduced by about 2.5 orders of magnitude. That is, when the output current IOUT and the output voltage VOUT are saturated, the input current of the current mirror circuit 10 of the TFET / MOSFET hybrid type is 2.5 digits as compared with the current mirror circuit configured by MOSFET drinking. It can be seen that it can be made as small as possible.

As described above, according to the current mirror circuit 10 according to the present embodiment, since the input side transistor is configured by the TFET 12 and the output side transistor is configured by the MOSFET 14, the input current is I _{on_TFET} <(input current). In the range of <√ (I _{on_MOSFET} · I _{on_TFET} ), an increase in layout area can be suppressed as compared with the case where both the input side and output side transistors are formed of MOSFETs. Further, since it is not necessary to increase the channel length in order to reduce the input current, the gate area can be reduced, and as a result, an increase in load capacity as a whole current mirror circuit can be suppressed. Further, since a MOSFET is used on the output side, the value of the output current IOUT is determined by the characteristics of the MOSFET.

  In the above example, the TFET and MOSFET are n-type transistors, but the same effect can be obtained even if these transistors are p-type. In this case, a current mirror circuit 20 may be configured as shown in FIG. The p-type TFET 22 on the input side has a drain D and a gate G connected to a terminal 26 to which an input current is input, and a source S connected to a power source. In the p-type MOSFET 24 on the output side, the drain D is connected to the output terminal, the gate G is connected to the drain D and gate G of the p-type TFET 22, and the source S is connected to the power source.

(Second Embodiment)
In the above-described first embodiment, the current mirror circuit in which the input side transistor is configured by a TFET and the output side transistor is configured by a MOSFET has been described. However, in the present embodiment, the first embodiment has been described. A memory cell using a current mirror circuit will be described. Hereinafter, parts different from the above-described embodiment will be described in detail.

  FIG. 8 is a diagram showing a memory cell and a memory array in the present embodiment. As shown in FIG. 8A, the memory cell 30 according to the present embodiment includes a current mirror circuit 20 and a storage element 32. The current mirror circuit 20 is, for example, equivalent to the current mirror circuit 20 according to the first embodiment shown in FIG. 7, and includes an input-side transistor p-type TFET 22 and an output-side transistor p-type MOSFET 24. The The sources S of the TFET 22 and the MOSFET 24 are connected to the power supply VDD. The drain D of the TFET 22 is connected to the storage element 32, and the drain D of the MOSFET 24 is connected to the bit line BL and the output side of the storage terminal 32.

  The storage element 32 is composed of, for example, a FeMOSFET (ferroelectric MOSFET), is connected to the drain terminal D of the TFET 22 that is a transistor on the input side of the current mirror circuit 20, and is connected to the bit line BL. . More specifically, the memory device is configured by a memory element that makes a judgment based on a current, in which a binary judgment is made based on a current between a source and a drain by two states of 0/1 stored in a gate insulating film. In this case, the resistance value at the time of low resistance of the memory element 32 and the resistance value in the saturation state of the TFET 22 are set close to each other. The selection of the word line WL shown in FIG. 8B is performed by applying a voltage to the gate of the storage element 32.

  FIG. 8B is a diagram for explaining reading of data from the memory array 40 using the memory cell 30 of FIG. The memory array 40 has memory cells 30 arranged in an array. Information stored in the memory array 40 can be read out by a circuit including a capacitor CBL, a current mirror circuit 42, a resistor R2, and a sense amplifier 48.

  The capacitor CBL is a capacitor for reading out two states of 0/1 stored in the memory cell 30, and one terminal is connected to the memory cell 30 and the other terminal is grounded. The charge is retained by being precharged, and the state held by the memory cell 30 is either 0/1 depending on the voltage of the held charge and the voltage output from the memory cell. Can be read out.

  The current mirror circuit 42 includes an n-type MOSFET 44 that is an input-side transistor and an n-type MOSFET 46 that is an output-side transistor. As shown in the figure, the drain D and the gate G of the MOSFET 44 are connected to each other and then connected to the output terminal of the memory cell 30, and the source S is grounded. The gate G of the MOSFET 46 is connected to the drain D and the gate G of the MOSFET 44, the source S is grounded, and the drain D is connected to the resistor R2 and the sense amplifier 48.

  The resistor R2 is a resistor for causing a voltage drop by IREAD from the voltage VDD, and is connected in parallel with the sense amplifier 48 on the output side of the current mirror circuit 42. The sense amplifier 48 is a circuit that amplifies the voltage output from the memory cell 30 and can handle it as a digital level.

Hereinafter, an operation of reading information stored in the memory array 40 will be described. The memory element 32 is an element that can read stored data by reading the state of the gate insulating film with a current. The current mirror circuit 20 and the circuit shown in FIG. 8B make the minute read current of the storage element 32 a current that can be handled as a digital level. For example, when a current mirror circuit equivalent to the current mirror circuit used in the simulation of FIG. 6 is used as the current mirror circuit 20, the read current I ₀ of the storage element 32 is used as the input current of the current mirror circuit 20, so that the output A current αI ₀ having a magnitude of 100 times or more is output as the current. That is, α> 100 in FIG. 8A, and the current IREAD = αI ₀ is output from the memory cell 30.

  Next, the current IREAD output from the memory cell 30 is input to the current mirror circuit 42 by comparing the potential of the charge stored in the capacitor CBL with the potential output from the memory cell 30. Specifically, when the potential due to the charge stored in the capacitor CBL is higher than the potential output from the memory cell 30, no current is output from the memory cell 30, and the output result is zero. On the other hand, when the potential due to the charge stored in the capacitor CBL is equal to or lower than the potential output from the memory cell 30, the current IREAD is output from the memory cell 30.

  When the output current IREAD from the memory cell 30 is input to the drain D of the input side transistor 44 of the current mirror circuit 42, the current IREAD is mirrored to the output side by the current mirror circuit 42. In the resistor R <b> 2, a voltage drop occurs due to IREAD output from the current mirror circuit 42, and a voltage dropped from the drain voltage VDD is input to the sense amplifier 48. The voltage input to the sense amplifier 48 is amplified to a voltage required for reading information by the difference from the reference voltage VREF. By reading the result output from the sense amplifier 48, the state stored in the memory cell 30, that is, the state stored in the storage element 32 can be read out.

  As described above, according to the present embodiment, it is possible to read out a signal having a necessary voltage level from a storage element that allows a weak current to flow by using the current mirror circuit 20 according to the first embodiment described above. Become. A current mirror circuit using a TFET as a transistor on the input side can amplify an output current while keeping its layout area small as described above. Furthermore, in this case, the memory element 32 only needs to be able to output a weak current, so that the circuit layout area of the memory element 32 itself can be reduced. That is, by reducing both the layout area of the memory element 32 and the layout area of the current mirror circuit 20 for reading a weak current, the layout area of the memory cell can be further reduced.

  If the output current IREAD from the memory cell 30 is not a sufficient value for reading data, it is conceivable to use a current mirror circuit 10 using a TFET for the read circuit as shown in FIG. On the other hand, the capacitor CBL can be omitted as long as the state of the memory element 32 can be acquired by the current IREAD output from the memory cell 30.

In each of the above-described embodiments, a part of the transistor is described as p-type or n-type. However, these are not intended to limit the scope of the gist of the invention, and depending on the usage mode, n-type or p-type. You may change suitably to a type.
Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof. Of course, it is possible to appropriately combine these embodiments partially within the scope of the present invention.

10: current mirror circuit, 12: n-type TFET, 14: n-type MOSFET, 20: current mirror circuit, 22: p-type TFET, 24: p-type MOSFET

Claims (7)

A first transistor comprising a TFET through which an input current flows;
A second transistor composed of a MOSFET through which an output current flows, wherein the first transistor and the gate of each other are connected;
A current mirror circuit comprising:   2. The current mirror circuit according to claim 1, wherein a saturation current amount of the first transistor during operation is smaller than a saturation current amount of the second transistor. The input current range is:
A drain current value flowing when the first transistor is in an on state;
A drain current value flowing when the second transistor is in an on state;
The current mirror circuit according to claim 1, wherein the current mirror circuit is set based on   The value of the drain current that flows when the first transistor is on and the value of the drain current that flows when the second transistor is on are the values of the first transistor and the second transistor, respectively. The first transistor having the shortest channel length capable of creating both, the first transistor having the smallest channel width capable of creating both the first transistor and the second transistor, and the first transistor 4. The current mirror circuit according to claim 3, wherein the current mirror circuit is set based on two transistors. The value of the drain current that flows when the first transistor is on in the shortest channel length and the minimum channel width is I _{on_TFET} ,
When the drain current value that flows when the second transistor is on in the shortest channel length and the shortest channel width is I _{on_MOSFET} ,
The input current _is greater than _{I On_TFET, and, √ (I on_TFET · I on_MOSFET} ) be set to a smaller extent than,
The current mirror circuit according to claim 4. A first transistor comprising a TFET, the first transistor having its drain and gate connected;
A second transistor comprising a MOSFET, the gate of which is connected to the gate of the first transistor;
A current mirror circuit comprising: A storage element capable of reading by current; and
The current mirror circuit according to any one of claims 1 to 6, wherein the storage element is connected to a drain side of the first transistor;
A memory cell comprising:

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