JP6351442B2 - Semiconductor test equipment - Google Patents

Description

  The present disclosure relates to a semiconductor test apparatus that performs a test for detecting a defect of a semiconductor device, a test method thereof, and a method of manufacturing a semiconductor device. Regarding technology.

  Conventionally, a semiconductor test apparatus has been used to detect defects in a semiconductor device. The semiconductor test apparatus includes, for example, a plurality of probe needles, these probe needles are brought into contact with the semiconductor device, and an energization test for the semiconductor device is performed according to a test program. Such an energization test usually includes a plurality of test items. For example, in each test item shown in the test program, a clamp voltage or current supplied to the semiconductor device is specified. The semiconductor test apparatus supplies the designated clamp voltage to the semiconductor device via the probe needle, and receives a signal output from the semiconductor device as a measurement signal. The semiconductor test apparatus inspects the semiconductor device based on the measurement signal.

  The test by the semiconductor test apparatus is performed in the process until the semiconductor device is manufactured and shipped. The manufacturing process of a semiconductor device can be divided into, for example, a process of forming an integrated circuit on a silicon wafer and a process of cutting out the semiconductor device from the semiconductor wafer and mounting it on a package substrate. Test with semiconductor test equipment. For example, electrical characteristics, functions, structures, etc. are tested on a semiconductor wafer that has completed the process of forming an integrated circuit on a silicon wafer. As a result, it is possible to avoid a situation in which a broken semiconductor device is shipped.

  In order to improve the productivity of a semiconductor device as a technology of a semiconductor test apparatus, for example, Japanese Patent Laying-Open No. 2013-140117 (Patent Document 1) detects a failure caused by a defect occurring on the semiconductor test apparatus side, It is described that the recognition accuracy of erroneous determination of the test apparatus is improved.

JP 2013-140117 A

  The test of the semiconductor device is performed over a plurality of items. For example, according to a test program for performing a test, the semiconductor test apparatus performs a plurality of tests such as a direct current characteristic test and a function test for testing the function of the semiconductor device. For each of these test items, conditions such as the current and voltage of a test signal applied to the semiconductor device and the timing for supplying the signal are specified in the test program. The test program is created by a user using an information processing apparatus such as a PC (Personal Computer) using a test programming language. The test program is compiled in the information processing apparatus or the semiconductor test apparatus, and the semiconductor test apparatus executes the test program.

  However, the test of the semiconductor device may include several hundred items, and it is necessary to set test conditions such as current and voltage applied to the semiconductor device for each test item. For this reason, test conditions are not set correctly or are not set properly. For example, a large voltage is applied to the semiconductor device exceeding the limit value of the voltage applied to the semiconductor device to be tested, and the semiconductor device is accidentally destroyed. There is a fear. In addition, a large voltage is applied to the jig exceeding the limit value of the voltage applied to the jig for giving a signal to the semiconductor device, causing the destruction of the jig, thereby forcing the production line of the semiconductor device to stop, There is a risk of requiring recovery costs.

  Therefore, there is a need for a technique for efficiently testing a semiconductor device and suppressing the occurrence of defects in the semiconductor device in a process of manufacturing a semiconductor test device or a semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor test apparatus according to an embodiment includes a storage unit, a jig that contacts the semiconductor device, and supplies a signal for current test to the semiconductor device via the contact part, and one or more test items of the semiconductor device, respectively. And a control unit for controlling signal output to the jig so as to supply a signal for an energization test to the semiconductor device via the jig. The storage unit is for storing a limit setting value indicating a limit setting of a signal output value for one or more test items. The controller controls to supply a signal that does not exceed the limit set value from the jig to the semiconductor device.

  According to one embodiment, a method is provided for a semiconductor test apparatus to conduct a current test of a semiconductor device. A semiconductor test apparatus is a jig for contacting a semiconductor device and supplying a signal for an electric current test to the semiconductor device via the contact portion, and a limit indicating setting of a limit of a signal output value for one or more test items. A storage unit for storing the set value. In this method, the semiconductor test apparatus outputs a signal to the jig so as to supply a signal for energization test to the semiconductor apparatus via the jig in accordance with each of one or more test items of the semiconductor device; Controlling to supply a signal not exceeding the limit set value from the jig to the semiconductor device.

  According to one embodiment, a method for manufacturing a semiconductor device is provided. In this manufacturing method, a semiconductor test apparatus compares a signal output value of a signal for an energization test with a limit set value indicating a limit setting of the signal output value for each of one or more test items of the semiconductor device. Thus, the method includes a step of supplying a signal that does not exceed the limit set value to the semiconductor device via a jig of the semiconductor test device, and a step of detecting a defect of the semiconductor device using the signal output from the semiconductor device as a measurement signal.

  According to the semiconductor test apparatus, the semiconductor device test method, and the semiconductor device manufacturing method according to the embodiment, the semiconductor test apparatus uses a jig to output a signal that does not exceed the signal output value limit setting according to each test item. Therefore, the jig can be prevented from being damaged and the semiconductor device can be prevented from being damaged.

1 is a block diagram showing a configuration of a semiconductor test apparatus according to a first embodiment. It is a figure which shows the data structure of the limit setting value. 4 is a diagram illustrating an example of a test program 41. FIG. FIG. 3 is a diagram illustrating an operation of the semiconductor test apparatus 1 according to the first embodiment. FIG. 10 is a diagram illustrating an operation of the semiconductor test apparatus according to the second embodiment. FIG. 10 is a diagram illustrating an operation of the semiconductor test apparatus according to the third embodiment. It is a flowchart which shows the process which controls execution of compilation according to the presence or absence of the setting of a fixed limit value. It is a flowchart which shows the process which stops execution of the test program 41 according to the presence or absence of the setting of a fixed limit value. FIG. 6 is a flowchart showing a process for assigning a category to a test item in an identifiable manner when a measurement result acquired from the jig 6 by the test reaches a limit set value 42 when a test of the wafer 4 is performed by the semiconductor test apparatus. is there.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

<Embodiment 1>
The semiconductor test apparatus according to the first embodiment will be described with reference to the drawings.

<Configuration>
FIG. 1 is a block diagram showing a configuration of the semiconductor test apparatus according to the first embodiment. The semiconductor test apparatus 1 includes a tester 50, jigs 6A and 6B (hereinafter, the jig 6A and the jig 6B may be collectively referred to as “jig 6”), and a test semiconductor device. A stage 5 for mounting a wafer 4 and a computer 20 for generating a program for a tester to create a test program for testing the wafer 4 are provided. The tester 50 includes an input / output IF (Interface) 51, an operation unit 52, a display unit 53, a storage unit 54, a selector 55, a selector 56, a control unit (CPU (Central Processing Unit)) 57, a power source Unit 58, signal generation unit 71, and DC (Direct Current) measurement unit 79. The signal generating unit 71 includes a signal generating unit 77 and a pseudo load unit 78.

  The tester 50 supplies a test signal such as a current test to the jig 6, receives a measurement signal output from the wafer 4 via the jig 6, and displays the test result of the wafer 4.

  The input / output IF 51 is an interface for connecting the tester 50 to an information processing apparatus (for example, a PC (Personal Computer) such as the computer 20 for generating programs), and is based on a general-purpose standard such as USB (Universal Serial Bus). Corresponding input / output interface. Accordingly, the tester 50 can be controlled from an external information processing apparatus such as the program generation computer 20. Although not shown, the semiconductor test apparatus 1 may include a communication interface such as a LAN (Local Area Network) and may be connected to an external information processing apparatus through a communication line.

  A test program as a source program created by the program generation computer 20 is held in the program storage unit 22. The program generation computer 20 functions as a compiler 21. The compiler 21 is for compiling a source program created by a tester into a machine language program that can be executed by the tester 50.

  A test program for testing a semiconductor device is created, for example, as follows. A tester creates a test program (source program) described in a program language dedicated to the tester using the program generation computer 20. The created test program (source program) is held in the program storage unit 22. The program generation computer 20 functions as a compiler 21. The compiler 21 converts the source program into a machine language test program. The program storage unit 22 is a storage device (for example, a magnetic disk) having a storage area for storing information used for processing of the information processing device such as data and programs. The test program converted into the machine language is stored in the program storage unit 22. The program generation computer 20 is connected to the tester 50 via, for example, the input / output IF 51 of the tester 50 and transmits the test program to the tester 50. The tester 50 stores the test program received from the program generation computer 20 in the storage unit 54 as the test program 41. The program generation computer 20 accepts the tester's operation, and causes the tester 50 to start testing the semiconductor device based on the test program.

  The operation unit 52 is an operation member for accepting a user's input operation to the tester 50. For example, the display unit 53 including a switch or the like is a display such as an LCD (Liquid Crystal Display), and information is controlled according to control of the control unit 57. Is displayed.

  The storage unit 54 is a memory configured by a RAM (Random Access Memory) or the like, and stores a test program 41 and a limit set value 42. The test program 41 is a program for the tester 50 to test the wafer 4 by controlling the jig 6, and is created by the program generator 20 by the tester. The limit setting value 42 indicates a limit setting of a signal supplied from the tester 50 to the wafer 4 via the jig 6. The limit set value is also included in the test program that was originally set in the source program and converted into machine language. The limit setting value in the test program transferred from the program generation computer 20 is stored in the storage unit 54 as the limit setting value 42 together with the test program 41.

  The controller 57 operates according to the test program 41 and controls signal output for testing the wafer 4 by the tester 50. The control unit 57 includes a CPU, a ROM (Read Only Memory), a RAM, and the like, and functions as the test program execution unit 73 by reading and operating a program. The test program execution unit 73 executes the test program 41 in order to test the semiconductor device.

  For each of a plurality of test items for testing the wafer 4, the test program 41 outputs a signal output value (for example, voltage output value, current output) for each test item of a signal supplied to the wafer 4 via the jig 6. Value). The test program execution unit 73 sequentially executes each test item shown in the test program 41, and for each test item, the voltage value and the current value determined by the test program 41 are transmitted to the signal of the semiconductor device via the jig 6. Terminal and power supply terminal.

  When the tester 50 tests the semiconductor device, the signal generation unit 71 is controlled by the control unit 57 to generate a signal input to the signal terminal of the semiconductor device. The signal generating unit 71 includes a signal generating unit 77 and a pseudo load unit 78. The signal generator 77 generates a clock signal and a data signal to be supplied to the input terminal of the semiconductor device when testing the semiconductor device. At this time, the signal generator 77 generates a clock signal having a voltage value and a current value determined by the test program 41 and a data signal having a voltage value and a current value determined by the test program 41.

  The pseudo load unit 78 applies a pseudo load to the output terminal of the semiconductor device when testing the semiconductor device. At that time, the pseudo load unit 78 generates a load determined by the test program 41. The DC measurement unit 79 measures a DC voltage and a DC current, and outputs the measurement result to the control unit 57 and the like. When testing the semiconductor device, the power supply unit 58 is controlled by the control unit 57 based on the execution of the test program, and supplies a voltage determined by the test program 41 to the power supply terminal of the semiconductor device via the jig 6B. The test program 41 defines a voltage value and a current value given to the power supply terminal for each test item.

  The control unit 57 further executes the test program 41 to load the limit setting value 42 in the storage unit 54 and hold it as a limit setting value 75 in a storage device (register or the like) provided in the control unit 57. The limit setting value 75 supplies the held value to the selector 55 and the selector 56.

  The selector 55 receives a clock signal and a data signal generated by the signal generation unit 71. The selector 55 controls the voltage or current of the clock signal supplied to the wafer 4 with reference to the value specified by the limit setting value 75 and supplies the wafer 4 with reference to the value specified by the limit setting value 75. Control the voltage or current of the data signal to be generated. Specifically, the selector 55 determines the magnitude relationship between the voltage or current value of each of the clock signal and the data signal (hereinafter also simply referred to as “signal”) and the value indicated by the limit setting value 75. When the voltage or current of the signal supplied to the wafer does not exceed the limit set value 75, the selector 55 supplies the signal received from the signal generator 77 to the wafer 4 as it is, and when it exceeds, the limit is reached. It is converted into a signal fixed (clamped) to a voltage or current of a set value 75 or a value within the limit range and supplied to the wafer 4.

  The selector 55 also determines the magnitude relationship between the load generated by the pseudo load unit 78 and the value indicated by the limit set value 75. When the load generated by the pseudo load unit 78 does not exceed the limit set value 75, the selector 55 supplies the load generated by the pseudo load unit 78 to the wafer 4 as it is. A load having a limit set value 75 or a value within the limit range is supplied to the wafer 4.

  The selector 56 receives power generated by the power supply unit 58. The selector 56 refers to the value specified by the limit setting value 75 and controls the voltage or current of the power supplied to the power terminal of the wafer 4. Specifically, the selector 56 determines the magnitude relationship between the value of the power supply voltage or current and the value indicated by the limit set value 75. When the power does not exceed the limit set value 75, the selector 56 supplies the power supplied from the power supply unit 58 to the wafer 4 as it is, and when it exceeds, the limit set value 75 or within the limit range. A power supply fixed (clamped) to the voltage or current of the value of is supplied to the wafer 4.

<Data>
FIG. 2 is a diagram illustrating a data structure of the limit setting value 42. As shown in FIG. 2, the limit setting value 42 holds the limit of the signal output value and the range that the signal output value can take for the power supply, signal input, and pseudo load that the tester 50 supplies to the wafer 4. Yes. The limit set value 42 includes the voltage clamp range 24 of the power supply, the current clamp range 25 of the power supply, the voltage clamp range 26 of the signal input to the jig 6, and the current clamp of the signal input to the jig 6. A range 27 and a setting value 28 of a pseudo load applied to the wafer 4 are included. In the example of FIG. 2, as the setting values of the voltage clamp, the setting value 23 and the setting value 29 are referred to the range 24 and the range 26, and the voltage limit setting values “maximum 5.0 V, minimum −1.0 V are used. The range of “to” is specified. As setting values of the current clamp, the setting value 23 and the setting value 29 refer to the range 25 and the range 27, and the range of the current limit setting value “maximum 100 mA, minimum 0 mA” is designated. Further, as shown in the setting value 28, the range of the pseudo load limit setting values "maximum 5.0V, minimum -1.0V, minimum -2mA, maximum 2mA" is specified.

<Example of test program 41>
FIG. 3 is a diagram illustrating an example of the test program 41. FIG. 3 shows an example of a source program. The test program 41 includes, for each test item for the tester 50 to test the wafer 4, designation of a voltage clamp value in the test program 41 in association with information for identifying the test item. The test program 41 includes a setting unit 19 for designating a limit setting value at the head of the test program 41. One part of the setting unit 19 includes designation of set values for the power source, signal input, and pseudo load.

  For example, in the setting unit 19, the set value “VCC_LIMIT” indicates a limit value for supplying the power supply voltage from the tester 50 to the wafer 4 via the jig 6. For example, in the setting unit 19, the setting value “VI_LIMIT” indicates the setting of the current limit value. For example, in the setting unit 19, the setting value “D_LIMIT” indicates setting of the limit value of the pseudo load. Each limit value is set as a value common to a plurality of test items executed by the tester 50.

  For other test items, for each item, the test program 41 includes a specified voltage value, a specified voltage clamp value, a specified current value, and a specified current clamp value in order. For example, test item A is included in test item 2p, test item B is included in test item 3p, and test item C is included in test item 4p.

<Operation of Embodiment 1>
FIG. 4 is a diagram illustrating the operation of the semiconductor test apparatus 1 according to the first embodiment. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the voltage supplied from the tester 50 to the jig 6.

  In FIG. 4, a period 101 is a period in which the test of the test item A is being performed, a period 102 is a period in which the test of the test item B is being performed, and a period 103 is a test of the test item C. This is the period of implementation. The ground 110 indicates a ground voltage. The limit set value 111 indicates a limit set value 42 (voltage limit set value in the example of FIG. 4) specified by the test program 41 or the like. The limit value 112 indicates the limit value of the voltage applied to the wafer 4. The limit value 113 indicates the limit value of the voltage applied to the jig 6. The limit value 114 indicates a limit value of a voltage that can be generated by the tester 50.

  In FIG. 4, the voltage clamp value specified by the test program 41 is indicated by a solid line, and the voltage clamp value that the tester 50 desirably supplies to the wafer 4 via the jig 6 is indicated by a dotted line.

  The designated voltage clamp value 115 indicates a voltage clamp value designated by the test program 41 in the test item A. The voltage clamp value 116 indicates a preferable voltage clamp value in the test item B. The voltage clamp value 117 indicates a preferable voltage clamp value in the test item C. The designated voltage clamp value 118 indicates a voltage clamp value designated by the test program 41 in the test item C.

  In the example shown in FIG. 4, in the test item A, the voltage clamp value (designated voltage clamp value 115) specified in the test program 41 does not exceed the limit value 112, so that the wafer 4 and the jig 6 are damaged. There is little risk of being connected.

  In the test item B, the voltage clamp value 116 is originally set, but the test program 41 does not specify the voltage clamp value because of the omission of setting by the tester. During this period, the tester 50 of the first embodiment sets the voltage clamp value to the limit setting value 111, for example, within a range not exceeding the voltage value indicated by the limit setting value 111, and the voltage of the limit setting value 111 is set to the tester 50. To the wafer 4 through the jig 6. Since the voltage value indicated by the limit set value 111 is smaller than the limit value 112 and the limit value 113, there is little possibility that the wafer 4 and the jig 6 will be damaged.

  In the test item C, a voltage value exceeding the limit value 112 and the limit value 113 is specified in the test program 41 where the voltage clamp value 117 should be originally set due to an erroneous input by the tester. In this case, if the tester 50 supplies a voltage to the wafer 4 via the jig 6 with the voltage clamp value indicated in the test program 41, the jig 6 and the wafer 4 may be damaged. However, the tester 50 of the first embodiment supplies the voltage of the limit setting value 111 from the tester 50 to the wafer 4 via the jig 6 within a range not exceeding the voltage indicated by the limit setting value 111. 6 and the risk of damage to the wafer 4 are reduced.

<Summary of Embodiment 1>
According to the semiconductor test apparatus 1 of the first embodiment, by specifying a certain limit set value 42 for each test item, the tester 50 through the jig 6 within a range not exceeding the voltage indicated by the limit set value 42. A signal is supplied to the wafer 4. Since the output value of the signal indicated by the limit setting value 42 is smaller than the limit value of the voltage applied to the jig 6 and the wafer 4, the risk of damaging or breaking the jig 6 and the wafer 4 is reduced. Further, since the limit setting value 42 is set to be constant for each test item, the creator of the test program can easily set the limit setting value 42.

  Here, when the test program is created, the limit setting value 42 is set by the test program creator exceeding the limit value of the current and voltage of the semiconductor device, or the limit value of the current and voltage of the jig 6. If the tester 50 is set to exceed the limit value of the current and voltage that can be generated by the tester 50, an error is displayed in the software for creating the test program and the creator is notified of the test program. It is good also as urging correction. Further, a plurality of limit setting values may be set within a range not exceeding the limit values of the tester 50, the semiconductor device, and the jig 6.

<Embodiment 2>
A semiconductor test apparatus according to another embodiment will be described.

  FIG. 5 is a diagram illustrating the operation of the semiconductor test apparatus according to the second embodiment. In FIG. 5, the horizontal axis represents time, and the vertical axis represents current supplied from the tester 50 to the jig 6. Compared with the semiconductor test apparatus of the first embodiment, the semiconductor test apparatus controls the signal output applied to the wafer 4 via the jig 6 based on the limit set value for the current.

  In FIG. 5, a period 201 is a period in which a test of the test item A is being performed, a period 202 is a period in which a test of the test item B is being performed, and a period 203 is a test of the test item C. This is the period of implementation. The ground 210 indicates a ground current. The limit set value 211 indicates the limit set value 42 (current limit set value in the example of FIG. 5) specified by the test program 41 or the like. The limit value 212 indicates the limit value of the current applied to the wafer 4. The limit value 213 indicates the limit value of the current applied to the jig 6. The limit value 214 indicates the limit value of the current that can be generated by the tester 50.

  In FIG. 5, the current clamp value designated by the test program 41 is indicated by a solid line, and the current clamp value that the tester 50 desirably supplies to the wafer 4 via the jig 6 is indicated by a dotted line.

  The designated current clamp value 215 indicates a current clamp value designated by the test program 41 in the test item A. The current clamp value 216 indicates a preferable current clamp value in the test item B. The current clamp value 217 indicates a preferable current clamp value in the test item C. The designated current clamp value 218 indicates a current clamp value designated by the test program 41 in the test item C.

  In the example shown in FIG. 5, in the test item A, the current clamp value (specified current clamp value 215) specified in the test program 41 does not exceed the limit value 212, so that the wafer 4 and the jig 6 are damaged. There is little risk of being connected.

  In the test item B, the current clamp value is not specified in the test program 41 because of a setting omission of the tester. During this period, the tester 50 of the second embodiment sets the current clamp value to the limit setting value 211, for example, within a range not exceeding the current value indicated by the limit setting value 211, and the current of the limit setting value 211 is set to the tester 50. To the wafer 4 through the jig 6. Since the current value indicated by the limit set value 211 is smaller than the limit value 212 and the limit value 213, there is little possibility that the wafer 4 and the jig 6 will be damaged.

  In the test item C, in the test program 41, a current value exceeding the limit value 212 and the limit value 213 is designated by the tester by mistake. In this case, if the tester 50 supplies current to the wafer 4 via the jig 6 with the current clamp value indicated in the test program 41, the jig 6 and the wafer 4 may be damaged. However, the tester 50 according to the second embodiment supplies the current of the limit setting value 211 from the tester 50 to the wafer 4 via the jig 6 within a range not exceeding the current indicated by the limit setting value 211. 6 and the risk of damage to the wafer 4 are reduced.

<Summary of Embodiment 2>
According to the semiconductor test apparatus 1 of the second embodiment, by specifying the limit set value 42, a signal is supplied from the tester 50 to the wafer 4 via the jig 6 within a range not exceeding the current indicated by the limit set value 42. Is done. Since the output value of the signal indicated by the limit setting value 42 is smaller than the limit value of the current applied to the jig 6 and the wafer 4, the risk of damaging or breaking the jig 6 and the wafer 4 is reduced.

<Embodiment 3>
A semiconductor test apparatus according to another embodiment will be described.

  FIG. 6 is a diagram illustrating the operation of the semiconductor test apparatus according to the third embodiment. In the test of the semiconductor device, a negative voltage or current may be applied, so the limit set value is also set in the negative direction.

  In FIG. 6, a period 301 is a period in which the test of the test item A is being performed, a period 302 is a period in which the test of the test item B is being performed, and a period 303 is a test of the test item C. This is the period of implementation. The ground 310 indicates a ground voltage. The limit set value 311 indicates a limit set value 42 (voltage limit set value in the example of FIG. 6) specified by the test program 41 or the like. In the third embodiment, the limit set value of the voltage is set in the negative direction. The limit value 312 indicates a limit value in the negative direction of the voltage applied to the wafer 4. The limit value 313 indicates a limit value in the negative direction of the voltage applied to the jig 6. The limit value 314 indicates a limit value in the negative direction of the voltage that can be generated by the tester 50.

  In FIG. 6, the voltage clamp value specified by the test program 41 is indicated by a solid line, and the voltage clamp value that the tester 50 desirably supplies to the wafer 4 via the jig 6 is indicated by a dotted line.

  The designated voltage clamp value 315 indicates a voltage clamp value designated by the test program 41 in the test item A. The voltage clamp value 316 indicates a preferable voltage clamp value in the test item B. The voltage clamp value 317 indicates a preferable voltage clamp value in the test item C. The designated voltage clamp value 318 indicates a voltage clamp value designated by the test program 41 in the test item C.

  In the example illustrated in FIG. 6, in the test item A, the voltage clamp value (designated voltage clamp value 315) specified in the test program 41 does not exceed the limit value 312 in the minus direction. There is little risk of damage.

  In the test item B, a voltage clamp value is not specified in the test program 41 because of a setting omission by the tester. During this period, the tester 50 according to the third embodiment sets the voltage clamp value to, for example, the limit set value 311 within a range that does not exceed the voltage value indicated by the limit set value 311 in the negative direction. Is supplied from the tester 50 to the wafer 4 via the jig 6. Since the voltage value indicated by the limit set value 311 is smaller than the limit value 312 and the limit value 313, there is little possibility that the wafer 4 and the jig 6 will be damaged.

  In the test item C, the test program 41 specifies a voltage value by which the tester mistakenly exceeds the limit value 312 and the limit value 313 in the negative direction. In this case, if the tester 50 supplies a voltage to the wafer 4 via the jig 6 with the voltage clamp value indicated in the test program 41, the jig 6 and the wafer 4 may be damaged. However, the tester 50 according to the third embodiment supplies the voltage of the limit setting value 311 from the tester 50 to the wafer 4 via the jig 6 within a range not exceeding the voltage indicated by the limit setting value 311. 6 and the risk of damage to the wafer 4 are reduced.

<Modification of Embodiment 3>
In the third embodiment, the example in which the limit set value is set for the minus-direction voltage has been described. However, by similarly setting the limit set value for the minus-direction current, the jig 6 and the wafer 4 can be damaged. It is possible to provide a semiconductor test apparatus that can reduce the possibility of connection.

<Modifications of Embodiments 1 to 3>
In the first to third embodiments, when the voltage or current value of the signal output from the signal generating unit 71 exceeds the limit set value 75, the selector 55 limits the voltage and / or current of the signal. Although it has the structure clamped to the value within the range of the setting value 75, it is good also as a structure which stops supply of a signal instead. At that time, the selector 55 may further supply a signal notifying an error to the control unit 57. When the value of the power supply voltage or current output from the power supply unit 58 exceeds the limit set value 75, the selector 56 sets the voltage and / or current of the power supply to a value within the range of the limit set value 75. However, instead of this, the supply of power may be stopped. At that time, the selector 56 may further supply a signal notifying an error to the control unit 57. The control unit 57 receives an error notification signal from the selector 55 and the selector 56 and outputs an error signal to the outside of the tester 50. The error signal may be output together with a signal that can specify a test item related to the error.

  As described above, instead of controlling the control mechanism including the selectors 55 and 56 and the control unit 57 to supply a signal that does not exceed the limit set value from the jig to the wafer, a signal exceeding the limit set value is supplied to the wafer. If it is determined that the error has occurred, the signal supply may be stopped, and if necessary, an error may be notified to the outside of the tester.

<Embodiment 4>
Another embodiment will be described. The semiconductor test apparatus of the fourth embodiment stops the supply of test signals from the tester 50 to the wafer 4 when no limit set value is set in the test program 41. Specifically, in order to stop the supply of the test signal from the tester 50 to the wafer 4, (1) the limit setting value is included in the source program when the test generation program 20 compiles the test program. If not, stop compilation. (2) When the tester 50 executes the test program 41, if the test program 41 does not include a limit setting value, execution of the test program 41 is stopped.

  FIG. 7 is a flowchart showing a process for controlling the execution of compilation according to whether or not a certain limit value is set. The source program to be compiled is generated by the program generation computer 20. In the following description, a case where the program generation computer 20 generates the test program 41 by compilation will be described.

  The computer 20 for program generation starts the compiler 21 and starts compiling the source program.

  In step S <b> 71, the compiler 21 determines whether or not a limit setting value indicating a limit setting of an output value of a signal supplied from the tester 50 to the wafer 4 is included in a certain area that is a head portion of the source program. To do. If the limit set value is included in the source program (YES in step S71), the compiler 21 performs the process of step S73. If not (NO in step S71), the compiler 21 performs the process of step S75. .

  In step S <b> 73, the compiler 21 compiles the source program, generates a test program 41, and stores the generated test program 41 in the program storage unit 22.

  In step S75, the compiler 21 stops the compilation of the source program and outputs a compilation error.

  In this way, by setting a certain limit set value for voltage, current, etc. at one location at the beginning of the source program, the test program creator can easily set the limit set value. become. Further, damage to the wafer 4 or the jig 6 due to a program creation error or the like can be prevented before the test program 41 is completed. Note that the fixed limit value is not limited to one place at the beginning of the source program, but may be set at an arbitrary position.

  FIG. 8 is a flowchart showing a process for stopping the execution of the test program 41 in accordance with the presence or absence of a fixed limit value. It is assumed that the limit set value is included in the head portion of the test program 41.

  In step S <b> 81, the control unit 57 of the tester 50 starts execution of the test program 41 and determines whether or not a limit set value is included in the head portion of the test program 41. If the limit set value is included (YES in step S81), control unit 57 performs the process of step S83. If not (NO in step S81), control unit 57 performs the process of step S85.

  In step S83, the control unit 57 sequentially executes at least one test item included in the test program 41 according to the number of test items.

  In step S85, the control unit 57 outputs an execution error of the test program 41 and stops the execution of the test program 41.

  In this way, by setting a certain limit set value for voltage, current, etc. at one location at the top of the test program 41, voltage is applied to the wafer 4 or jig 6 or current is applied. In addition, it is possible to find a mistake in creating the test program 41 and to reduce the possibility of damaging the wafer 4 and the jig 6.

<Embodiment 5>
Another embodiment will be described.

  FIG. 9 shows a process of assigning a category to a test item in an identifiable manner when the measurement result acquired from the jig 6 by the test reaches the limit set value 42 when the test of the wafer 4 is performed by the semiconductor test apparatus. It is a flowchart which shows.

  In step S <b> 91, the control unit 57 executes a test of an arbitrary test item (for example, test item A) and acquires a measurement result from the jig 6.

  In step S93, it is determined whether the result of the test in step S91 is defective or normal. When the result of the test is defective (defective in step S93), the control unit 57 performs the process of step S95, and when it is normal (normal in step S93), the test of the subsequent test item is executed (step S96). ).

  In step S95, the control unit 57 refers to the measurement result acquired from the jig 6, and determines whether or not the measurement result (for example, the voltage measurement result) has reached a certain limit set value 42. If the measurement result does not reach the certain limit set value 42 (NO in step S95), the control unit 57 performs the process of step S97. If the measurement result has reached the certain limit set value 42 (step In S95, YES), control unit 57 performs step S99.

  In step S97, the control unit 57 adds a category indicating that the test is defective to the test item A, and executes the test of the subsequent test items.

  In step S99, the control unit 57 attaches a special category indicating that the output value indicated in the measurement result is abnormal to the test item A, and ends without continuing the subsequent test items.

  As a result, when the measurement result of the test exceeds a certain limit set value 42, a special category is attached so that the test can be identified, and the subsequent test is terminated without continuing, so that The load can be reduced.

<Embodiment 6>
Another embodiment will be described.

  In the description of each of the above embodiments, the limit setting value is set for the output value of the signal supplied from the semiconductor test apparatus to the wafer 4 via the jig 6, but the signal supplied from the semiconductor test apparatus to the semiconductor device. As examples, there are a power supply of a semiconductor device, a signal input, and a pseudo load. About these, based on each limit setting value, the output value of the signal supplied to the wafer 4 from the semiconductor test apparatus via the jig 6 is controlled. Thus, the wafer 4 can prevent the jig 6 from being broken during the test.

  As described above, the semiconductor device test method using the semiconductor test apparatus has been described. This test method is performed in the process of manufacturing the semiconductor device. The test by the semiconductor test apparatus is performed in the process until the semiconductor device is manufactured and shipped. The manufacturing process of a semiconductor device can be divided into, for example, a process of forming an integrated circuit on a silicon wafer and a process of cutting out the semiconductor device from the semiconductor wafer and mounting it on a package substrate. Test with semiconductor test equipment. For each test item of the semiconductor device, the semiconductor test device compares the output value of the current test signal with the limit setting value, and puts a jig from the semiconductor test device to the semiconductor device so that the limit setting value is not exceeded. The signal is supplied via The semiconductor test apparatus receives a signal output from the semiconductor device as a measurement signal, and detects a malfunction of the semiconductor device based on the measurement signal.

  Each embodiment has been described above, but it goes without saying that these embodiments may be combined.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus, 4 wafers, 5 stages, 6 jig | tool, 41 test program, 42 limit set value, 51 input / output IF, 52 operation part, 53 display part, 54 memory | storage part, 55,56 selector, 57 control part, 58 power supply control unit, 59 power supply.

Claims (4)

A semiconductor test apparatus for conducting a current test of a semiconductor device,
A storage unit;
A jig for contacting the semiconductor device and supplying a signal for an electrical test to the semiconductor device via the contact portion;
A control unit that controls a signal output to the jig so as to supply a signal for an energization test to the semiconductor device via the jig according to each of one or more test items of the semiconductor device;
The storage unit is for storing a limit setting value indicating a limit setting of a signal output value for the one or more test items,
The control unit controls to supply a signal that does not exceed the limit set value from the jig to the semiconductor device,
The storage unit is for storing a test program for controlling the energization test,
Wherein, in the program for the test, if the there is no setting of limit setting, and stops the supply of the semiconductor device of the signal for the electrical test, semi-conductor test device. The storage unit is for storing a source program for controlling the energization test as the test program,
Wherein the control unit may stop the supply to the semiconductor device of the signal for the power-on test, when compiling the source program by the compiler, the case where the source program the does not contain setting of the limit setting in, it includes withdrawing said compilation, semiconductor test apparatus according to claim 1. The control unit stops the supply of the current test signal to the semiconductor device when the test program does not include the setting of the limit set value. the includes suspending, semiconductor test apparatus according to claim 1. The test program can include the setting of the limit setting value in one place at the top of the program body,
The control unit stops the supply of the signal for the energization test to the semiconductor device when the setting of the limit set value is not included in one part of the head of the test program main body. The semiconductor test apparatus according to claim 1 .

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