JP6345842B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including an oxide semiconductor and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electric appliance are all semiconductor devices.

A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor.

JP 2006-165528 A

It is known that oxygen vacancies in an oxide semiconductor serve as donors. When an oxide semiconductor is used for a channel formation region of a transistor, an oxide semiconductor layer with as few oxygen vacancies as possible is preferably used.

However, even when there are few oxygen vacancies in the initial oxide semiconductor layer, oxygen vacancies can increase due to various factors. An increase in oxygen vacancies in the oxide semiconductor layer may cause defective electrical characteristics, such as a transistor being normally on, an increase in leakage current, and a shift in threshold voltage due to stress application.

Therefore, an object of one embodiment of the present invention is to provide a semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device.

According to one embodiment of the present invention, in a semiconductor device including an oxide semiconductor layer in a channel formation region, the oxide insulating film provided in contact with the lower side of the oxide semiconductor layer and the upper side of the oxide semiconductor layer are provided. The oxide insulating film or oxygen in the gate insulating film is supplied into the oxide semiconductor layer using the gate insulating film thus formed. Further, by using conductive nitride for the metal film used for the source electrode layer and the drain electrode layer, diffusion or movement of oxygen to the metal film is suppressed. More details are as follows.

One embodiment of the present invention includes an oxide insulating film, an oxide semiconductor layer formed over the oxide insulating film,
A first source electrode layer and a first drain electrode layer in contact with the oxide semiconductor layer; a second source electrode layer covering the first source electrode layer and the first drain electrode layer and in contact with the oxide semiconductor layer;
Source electrode layer and second drain electrode layer, oxide insulating film, oxide semiconductor layer, second source electrode layer, gate insulating film formed on second drain electrode layer, and gate insulating film A gate electrode layer formed at a position overlapping with the oxide semiconductor layer, and a protective insulating film formed on the gate insulating film and the gate electrode layer, the gate insulating film being an oxide In this semiconductor device, the insulating film is in partial contact with the outer periphery of the second source electrode layer and the second drain electrode layer.

Another embodiment of the present invention is an oxide insulating film, an oxide semiconductor layer formed over the oxide insulating film, a first source electrode layer in contact with the oxide semiconductor layer, and a first drain electrode Layers,
A second source electrode layer and a second drain electrode layer in contact with each of the first source electrode layer and the first drain electrode layer and in contact with the oxide semiconductor layer; an oxide insulating film; an oxide semiconductor layer; A gate insulating film formed on the first source electrode layer, the first drain electrode layer, the second source electrode layer, and the second drain electrode layer; and an oxide semiconductor layer formed on the gate insulating film And a protective insulating film formed on the gate insulating film and the gate electrode layer, and the gate insulating film includes the oxide insulating film and the first source electrode layer. In addition, the semiconductor device is partially in contact with the outer periphery of the first drain electrode layer.

In each of the above structures, the first source electrode layer and the first drain electrode layer are made of Al, Cr
At least one material selected from Cu, Ta, Ti, Mo, and W, or an alloy material containing these as a main component is preferable.

In each of the above structures, it is preferable that end portions of the first source electrode layer and the first drain electrode layer have a stepped shape.

In each of the above structures, the second source electrode layer and the second drain electrode layer are at least one material selected from tantalum nitride, titanium nitride, and ruthenium, or an alloy material containing these as a main component. And preferred.

  In each of the above structures, the protective insulating film is preferably a silicon nitride film.

In each of the above structures, the oxide semiconductor layer preferably contains a crystalline material, and the crystalline c-axis is preferably parallel to the normal vector of the surface of the oxide semiconductor layer.

According to one embodiment of the present invention, a semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer is suppressed can be provided. In addition, a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

8A and 8B are a cross-sectional view and a top view illustrating a semiconductor device. 8A and 8B illustrate a method for manufacturing a semiconductor device. 8A and 8B illustrate a method for manufacturing a semiconductor device. 8A and 8B illustrate a method for manufacturing a semiconductor device. 8A and 8B are a cross-sectional view and a top view illustrating a semiconductor device. 8A and 8B illustrate a method for manufacturing a semiconductor device. 8A and 8B are a cross-sectional view and a top view illustrating a semiconductor device. 8A and 8B illustrate a method for manufacturing a semiconductor device. 8A and 8B are a cross-sectional view and a top view illustrating a semiconductor device. 8A and 8B are a cross-sectional view and a top view illustrating a semiconductor device. 2A and 2B are a cross-sectional view and a circuit diagram of a semiconductor device. FIG. 6 is a circuit diagram and a perspective view of a semiconductor device. 1 is a block diagram of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. 1 is a block diagram of a semiconductor device. 6A and 6B illustrate an electronic device to which a semiconductor device can be applied. The figure which shows the result of having performed the SIMS analysis of the lamination | stacking of an IGZO film | membrane and a tungsten film. The figure which shows the result of having conducted the SIMS analysis of the lamination | stacking of an IGZO film | membrane and a tantalum nitride film | membrane. The figure which shows the result of having conducted the SIMS analysis of the lamination | stacking of an IGZO film and a titanium nitride film. The figure which shows the result of having conducted the SIMS analysis of the lamination | stacking of an IGZO film and a tantalum nitride film, and the lamination | stacking of an IGZO film and a titanium nitride film. The figure which shows the result of having conducted the SIMS analysis of the lamination | stacking of an IGZO film and a tantalum nitride film, and the lamination | stacking of an IGZO film and a titanium nitride film. The figure which shows the result of having measured the sheet resistance value with respect to the depth which etched the IGZO film | membrane. The figure which shows the result of having measured the sheet resistance value with respect to the depth which etched the IGZO film | membrane.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In this embodiment, the functions of “source” and “drain” of a transistor may be switched when a transistor with a different polarity is used or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention is described with reference to drawings.

1A, 1B, 1C, 1D, and 1E are a top view and cross-sectional views of a transistor of one embodiment of the present invention. FIG. 1A illustrates a top view of a transistor, and FIG. 1B corresponds to a cross section taken along dashed-dotted line X1-Y1 in FIG. Further, FIG. 1 (C) is shown in FIG.
It corresponds to the cross section of the dashed-dotted line V1-W1 shown in FIG. FIG. 1D illustrates the width of each structure of the transistor illustrated in FIG. FIG. 1E illustrates a region 1 illustrated in FIG.
FIG. Note that in the top view of FIG. 1A, some elements are illustrated as transparent or omitted for the sake of clarity.

The transistor 150 shown in FIGS. 1A, 1B, 1C, 1D, and 1E includes a substrate 10
2, an oxide semiconductor layer 106 formed on the oxide insulating film 104, a first source electrode layer 108 a and a first source electrode layer 108 a formed on the oxide semiconductor layer 106. Drain electrode layer 108b, and second source electrode layer 110a and second drain electrode layer 110b formed on each of first source electrode layer 108a and first drain electrode layer 108b, and oxide insulation A gate insulating film 112 formed over the film 104, the oxide semiconductor layer 106, the second source electrode layer 110a, and the second drain electrode layer 110b; and an oxide semiconductor layer 106 formed over the gate insulating film 112. A gate electrode layer 114 formed at a position overlapping with the gate insulating film 112, and a protective insulating film 116 formed on the gate electrode layer 114. . Note that another insulating layer, a wiring, or the like may be formed above the protective insulating film 116.

The substrate 102 is not limited to a simple support material, and may be a substrate on which other devices such as transistors are formed. In this case, at least one of the gate electrode layer 114, the first source electrode layer 108a, the first drain electrode layer 108b, the second source electrode layer 110a, and the second drain electrode layer 110b of the transistor 150 has the above structure. It may be electrically connected to other devices.

The oxide insulating film 104 has a role of preventing diffusion of impurities from the substrate 102,
Since the oxide semiconductor layer 106 can function to supply oxygen, the insulating film containing oxygen is used. In particular, the oxide insulating film 104 is more preferably an insulating film containing excess oxygen. An oxide insulating film containing excess oxygen refers to an oxide insulating film that can release oxygen by heat treatment or the like. Preferably, the film has an oxygen release amount of 1.0 × 10 ¹⁹ atoms / cm ³ or more in terms of oxygen atoms in temperature-programmed desorption gas spectroscopy analysis. Excess oxygen exists in excess of oxygen that can move in an oxide semiconductor layer, silicon oxide, or silicon oxynitride by heat treatment, or oxygen in an original stoichiometric composition. oxygen,
Alternatively, oxygen having a function of filling or filling Vo (oxygen vacancy) due to lack of oxygen is shown. Oxygen released from the oxide insulating film 104 is emitted from the oxide semiconductor layer 1.
Since oxygen can be diffused into the channel formation region 06, oxygen can be compensated for oxygen vacancies that can be formed in the oxide semiconductor layer. Therefore, stable electrical characteristics of the transistor can be obtained.

In addition, since the oxide insulating film 104 is provided in contact with the oxide semiconductor layer 106, oxygen can be directly diffused into the oxide semiconductor layer 106 from below and provided in contact with the gate insulating film 112. Therefore, the oxide semiconductor layer 10 is interposed through the gate insulating film 112.
6 can diffuse oxygen from above. More specifically, oxygen released from the oxide insulating film 104 is outside the second source electrode layer 110a (left side in FIG. 1) and outside the second drain electrode layer 110b (in FIG. 1). , Right side) to gate insulating film 112
The oxide semiconductor layer 106 can enter the upper side of the oxide semiconductor layer 106. In other words, the gate insulating film 112 has a structure in which part of the oxide insulating film 104 is in contact with the outer periphery of the second source electrode layer 110a and the second drain electrode layer 110b.

Therefore, the gate insulating film 112 includes the second source electrode layer 110a and the second source electrode layer 110a so that oxygen released from the oxide insulating film 104 can diffuse into the channel of the oxide semiconductor layer 106.
The drain electrode layer 110b and the protective insulating film 116 are sandwiched. Therefore, the second
Source electrode layer 110a and second drain electrode layer 110b, and protective insulating film 11
For 6, a material with little diffusion or movement of oxygen is used. Therefore, when oxygen is diffused into the oxide semiconductor layer through the gate insulating film, oxygen can be prevented from diffusing or moving to the source electrode layer and the drain electrode layer.

By using the transistor having such a structure, excess oxygen can be supplied from the oxide insulating film 104 and the gate insulating film 112 to the channel formation region of the oxide semiconductor layer 106. Therefore, the oxide semiconductor layer 106 was used. The threshold voltage of the transistor can be normally off. Therefore, a semiconductor device in which an increase in oxygen vacancies in the oxide semiconductor layer 106 is suppressed can be provided. In addition, a highly reliable semiconductor device can be provided.

Note that in the case where the substrate 102 is a substrate over which another device is formed, the oxide insulating film 104 also has a function as an interlayer insulating film. In that case, planarization treatment is preferably performed by a CMP (Chemical Mechanical Polishing) method or the like so that the surface of the oxide insulating film 104 is planarized.

An oxide semiconductor that can be used as the oxide semiconductor layer 106 preferably contains at least indium (In) or zinc (Zn). Or it is preferable that both In and Zn are included. For a material that can be used for the oxide semiconductor layer 106 and a formation method thereof, a method for manufacturing a transistor will be described in detail.

Note that in order to impart stable electric characteristics to the transistor including the oxide semiconductor layer as a channel, the impurity concentration in the oxide semiconductor layer is reduced so that the oxide semiconductor layer is intrinsic or substantially intrinsic. It is valid. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × It indicates less than 10 ¹³ / cm ³ .

In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than the main component are impurities. For example, hydrogen and nitrogen form donor levels and increase the carrier density. Silicon forms impurity levels in the oxide semiconductor layer. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor.

In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ a in SIMS analysis.
It is less than toms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .
The hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ at.
oms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. The nitrogen concentration is 5 × 10 ¹⁹ a
less than toms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³
m ³ or less.

In addition, in the case where the oxide semiconductor layer includes a crystal, the crystallinity of the oxide semiconductor layer may be reduced if silicon or carbon is included at a high concentration. In order not to reduce the crystallinity of the oxide semiconductor layer, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ^18.
It may be less than atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . The carbon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ^1.
It may be less than ⁸ atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

In addition, the off-state current of the transistor using the oxide semiconductor film purified as described above for the channel formation region is extremely small, and the off-state current normalized by the channel width of the transistor is
It can be reduced to several yA / μm to several zA / μm.

An oxide semiconductor that can be used as the oxide semiconductor layer 106 can provide stable electric characteristics to the transistor including the oxide semiconductor layer 106 by reducing the localized states in the film. . Note that in order to impart stable electrical characteristics to the transistor, CPM measurement (CPM: Constant Photocurre) in the oxide semiconductor layer 106 is performed.
nt Method), the absorption coefficient due to the localized level is less than 1 × 10 ⁻³ / cm,
Preferably, it may be less than 3 × 10 ⁻⁴ / cm.

For the first source electrode layer 108a and the first drain electrode layer 108b, a conductive material that is easily bonded to oxygen can be used. For example, Al, Cr, Cu, Ta, Ti, Mo, W
Etc. can be used. It is particularly preferable to use W having a high melting point because the subsequent process temperature can be made relatively high. Note that the conductive material that easily binds to oxygen includes a material in which oxygen easily diffuses or moves.

When the conductive material that is easily bonded to oxygen is brought into contact with the oxide semiconductor layer, a phenomenon occurs in which oxygen in the oxide semiconductor layer diffuses or moves toward the conductive material that is easily bonded to oxygen. Since there are several heating steps in the manufacturing process of the transistor, oxygen vacancies are generated in the vicinity of the oxide semiconductor layer in contact with the source electrode and the drain electrode due to the above phenomenon, and the region becomes n-type. To do. Therefore, the n-type region can serve as the source or drain of the transistor.

However, in the case of forming a transistor with an extremely short channel length, the n-type region due to the generation of oxygen vacancies may extend in the channel length direction of the transistor.
In this case, a state (conduction state) in which on / off cannot be controlled by a threshold voltage shift or a gate voltage appears in the electrical characteristics of the transistor. Therefore, in the case of forming a transistor with an extremely short channel length, it is not preferable to use a conductive material that easily binds to oxygen for the source electrode and the drain electrode.

Therefore, in one embodiment of the present invention, the source electrode and the drain electrode are stacked, and the second source electrode layer 110a and the second drain electrode layer 110b that define the channel length are each formed using a conductive material that does not easily bond to oxygen. As the conductive material, for example, conductive nitride such as tantalum nitride or titanium nitride, or ruthenium is preferably used. Note that the conductive material which is difficult to bond with oxygen includes a material which does not easily diffuse or move oxygen.

Note that in the transistor having the structure in FIG. 1, the channel length refers to the second source electrode layer 11.
This is the distance between 0a and the second drain electrode layer 110b.

By using the conductive material which is not easily bonded to oxygen for the second source electrode layer 110a and the second drain electrode layer 110b, oxygen vacancies are formed in the channel formation region formed in the oxide semiconductor layer 106. It is possible to suppress the n-type channel. Therefore, good electrical characteristics can be obtained even with a transistor having a very short channel length.

Note that when the source electrode and the drain electrode are formed using only a conductive material that is not easily bonded to oxygen, the contact resistance with the oxide semiconductor layer 106 becomes too high, so that the first source electrode layer is formed as shown in FIG. 108a and the first drain electrode layer 108b are formed over the oxide semiconductor layer 106, and the first source electrode layer 108a and the first drain electrode layer 108 are formed.
The second source electrode layer 110a and the second drain electrode layer 110b are preferably formed so as to cover b.

At this time, the contact area between the first source electrode layer 108a and the first drain electrode layer 108b and the oxide semiconductor layer 106 is increased, and the contact resistance is reduced by the region that is made n-type by generation of oxygen vacancies. The contact area between the electrode layer 110a and the second drain electrode layer 110b and the oxide semiconductor layer 106 is preferably small. Second source electrode layer 11
When the contact resistance between 0a and the second drain electrode layer 110b and the oxide semiconductor layer 106 is large, the electrical characteristics of the transistor may be deteriorated.

Here, the n-type region described above will be described with reference to FIG. FIG.
FIG. 1B is an enlarged view of the region 105 illustrated in FIG. 1B. In the region where the oxide semiconductor layer 106 and the first source electrode layer 108a are in contact with each other, oxygen in the oxide semiconductor layer 106 is An n-type region 106a is formed by being extracted toward the source electrode layer 108a. In addition,
The n-type region 106a is a region having a large amount of oxygen vacancies in the oxide semiconductor layer 106, and when a tungsten film is used as a component of the first source electrode layer 108a, for example, the first source electrode layer 108a, n Tungsten elements are mixed in the mold region 106a. Although not illustrated, oxygen in the oxide semiconductor layer 106 enters a region in contact with the oxide semiconductor layer 106 on the first source electrode layer 108a side, so that a mixed layer can be formed.

Note that although the region 105 is mainly described with respect to an enlarged view of the oxide semiconductor layer 106 and the first source electrode layer 108a, the above-described n-type is also provided on the oxide semiconductor layer 106 and the first drain electrode layer 108b side. The formation region is formed.

Note that the n-type region 106 a may be used as a source region or a drain region in the oxide semiconductor layer 106.

In addition, by using a conductive material that does not easily bond to oxygen for the second source electrode layer 110a and the second drain electrode layer 110b, the oxide semiconductor layer 106 can be formed from the oxide insulating film 104 through the gate insulating film 112. When supplying oxygen from the upper side, the second source electrode layer 11
Since oxygen hardly diffuses or moves to 0a and the second drain electrode layer 110b, oxygen can be preferably supplied to the oxide semiconductor layer 106.

The gate insulating film 112 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film containing one or more of them can be used. In addition, the gate insulating film 112
May be a laminate of the above materials.

The gate electrode layer 114 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru
, Ag, Ta, and W can be used. The gate electrode layer 114 may be a stacked layer of the above materials.

For the protective insulating film 116, a material with little diffusion or movement of oxygen is preferably used. The protective insulating film 116 is preferably formed using a material with a low hydrogen content. Protective insulating film 116
The hydrogen content is preferably less than 5 × 10 ¹⁹ / cm ³ , more preferably 5
It is set to less than × 10 ¹⁸ / cm ³ . By setting the hydrogen content in the protective insulating film 116 to the above value, the off-state current of the transistor can be reduced. For example, the protective insulating film 11
6 may be a silicon nitride film or a silicon nitride oxide film.

  Here, intervals between the components are described with reference to a cross-sectional view illustrated in FIG.

The distance (L1) between the first source electrode layer 108a and the first drain electrode layer 108b is 0
. The thickness is 8 μm or more, preferably 1.0 μm or more. If L1 is smaller than 0.8 μm, the influence of oxygen vacancies generated in the channel formation region cannot be eliminated, and the electrical characteristics of the transistor may be deteriorated.

On the other hand, the distance (L2) between the second source electrode layer 110a and the second drain electrode layer 110b
Can be a value smaller than L1, for example, good electrical characteristics of a transistor can be obtained even when the thickness is 30 nm or less.

Further, when the width of the gate electrode layer 114 is L0, L0 ≧ L1 as shown in FIG.
By setting ≧ L2 (L1 is not less than L2 and not more than L0), the gate electrode layer 114 is connected to the source electrode layer (the first source electrode layer 108a and the second source electrode layer 1 through the gate insulating film 112)
10a) and a region overlapping with the drain electrode layer (the first drain electrode layer 108b and the second drain electrode layer 110b) can be provided. With this configuration,
The on characteristics (eg, on-state current and field-effect mobility) of a miniaturized transistor can be improved.

When the width of the oxide semiconductor layer 106 is L3 and the width of the transistor 150 is L4, L3 is preferably less than 1 μm and L4 is preferably 1 μm to 2.5 μm. By setting L3 and L4 to the above numerical values, the transistor can be miniaturized.

The above is the transistor of one embodiment of the present invention, and the structure of the transistor can suppress an increase in oxygen vacancies in the oxide semiconductor layer. In particular, the transistor
Oxygen can be supplied from the oxide insulating film in contact with the oxide semiconductor layer and the gate insulating film into the oxide semiconductor layer. Therefore, a semiconductor device that exhibits favorable electrical characteristics and high long-term reliability can be provided.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 2)
In this embodiment, a method for manufacturing the transistor 150 illustrated in FIG. 1 described in Embodiment 1 will be described with reference to FIGS.

As the substrate 102, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On
It is also possible to use an insulator) substrate, or a substrate in which a semiconductor element is provided on these substrates.

The oxide insulating film 104 is formed by a plasma CVD (Chemical Vapor Depos).
It is possible to use aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. These oxide insulating films or a mixed material thereof can be used. Alternatively, a stack of the above materials may be used, and at least an upper layer in contact with the oxide semiconductor layer 106 is formed using a material containing oxygen that can serve as a supply source of oxygen to the oxide semiconductor layer 106.

Further, oxygen may be added to the oxide insulating film 104 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. By adding oxygen, the oxide insulating film 104 can further contain excess oxygen.

Next, an oxide semiconductor layer is formed over the oxide insulating film 104 by sputtering, CVD, or MBE.
(Molecular Beam Epitaxy) method, ALD (Atomic Ray)
er Deposition) or PLD (Pulse Laser Deposi)
The oxide semiconductor layer 106 is formed by selective etching and film formation using a (ion) method (see FIG. 2A). Note that a heating step may be performed before etching.

An oxide semiconductor that can be used as the oxide semiconductor layer 106 preferably contains at least indium (In) or zinc (Zn). Or it is preferable that both In and Zn are included. In addition, in order to reduce variation in electrical characteristics of the transistor including the oxide semiconductor, a stabilizer is preferably included together with the transistor.

Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (
Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium ( Yb) and lutetium (Lu).

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg oxide, In—
Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I
n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al
-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn Oxide, I
n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy
-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga -Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al
-Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide can be used.

Note that here, for example, an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. In and G
Metal elements other than a and Zn may be contained. In this specification, In—Ga—
A film made of Zn oxide is also called an IGZO film.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 and m is not an integer) may be used. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 and n is an integer) may be used.

Note that a sputtering method is preferably used for forming the oxide semiconductor film. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In particular, the DC sputtering method is preferably used because dust generated during film formation can be reduced and the film thickness distribution can be made uniform.

As the oxide semiconductor film, a film having a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like can be used. Preferably, the oxide semiconductor film is CA.
AC-OS (C Axis Aligned Crystalline Oxide S
an emitter) film.

An oxide semiconductor film including a CAAC-OS film can be formed by a sputtering method. In order to obtain a CAAC-OS film by a sputtering method, it is important to form hexagonal crystals in the initial stage of deposition of the oxide semiconductor film and to grow crystals using the crystals as seeds. It is. For this purpose, the distance between the target and the substrate is increased (for example, about 150 mm to 200 mm) and the substrate heating temperature is set to 100 ° C. to 50
The temperature is preferably 0 ° C, preferably 200 ° C to 400 ° C, and more preferably 250 ° C to 300 ° C. In addition to this, the deposited oxide semiconductor film is heat-treated at a temperature higher than the substrate heating temperature at the time of film formation to repair micro defects contained in the film and defects at the lamination interface. Can do.

The CAAC-OS film is not completely single crystal nor completely amorphous. CAAC-OS
The film is an oxide semiconductor film having a crystal-amorphous mixed phase structure in which an amorphous phase includes a crystal part and an amorphous part. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. In addition, a transmission electron microscope (TEM) is used.
(on Microscope), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

In the crystal part included in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and triangular when viewed from the direction perpendicular to the ab plane. It has a shape or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, when simply described as vertical,
The range of 85 ° to 95 ° is also included. In addition, when simply describing as parallel,
A range of 5 ° to 5 ° is also included.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, CA
In the formation process of the AC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film may be higher in the vicinity of the surface. C
When an impurity is added to the AAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface).
Note that the c-axis direction of the crystal part is parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

The CAAC-OS film can be formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target, for example. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the ab plane, and may be separated as flat or pellet-like sputtered particles having a plane parallel to the ab plane. is there. In this case, the flat sputtered particles reach the substrate while maintaining the crystalline state, so that C
An AAC-OS film can be formed.

  In order to form the CAAC-OS film, the following conditions are preferably applied.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, impurities (hydrogen, water, carbon dioxide, nitrogen, and the like) existing in the deposition chamber may be reduced. In addition, impurities in the deposition gas may be reduced. Specifically, dew point is -80
A film forming gas having a temperature not higher than ° C., preferably not higher than −100 ° C. is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the substrate heating temperature is 100 ° C. or higher and 740 ° C. or lower, preferably 2
The film is formed at a temperature between 00 ° C. and 500 ° C. By increasing the substrate heating temperature during film formation, when flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100%.
Volume%.

As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.

In-Ga which is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder in a predetermined number of moles, and after heat treatment at a temperature of 1000 ° C. or higher and 1500 ° C. or lower.
—Zn—O compound target. X, Y and Z are arbitrary positive numbers. Here, the kind of powder and the mole number ratio to be mixed may be appropriately changed depending on the sputtering target to be produced.

Next, it is preferable to perform the first heat treatment. The first heat treatment is performed at 250 ° C. or higher and 650 ° C.
It may be performed at a temperature of not higher than ° C., preferably not lower than 300 ° C. and not higher than 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or higher, or in a reduced pressure state. The atmosphere of the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the oxide semiconductor layer 1
The crystallinity of 06 can be increased and impurities such as hydrogen and water can be removed from the oxide insulating film 104 and the oxide semiconductor layer 106. Note that the first heating step may be performed before the etching for forming the oxide semiconductor layer 106.

Next, the first conductive film 108 to be the first source electrode layer 108a and the first drain electrode layer 108b is formed over the oxide semiconductor layer 106 (see FIG. 2B). First conductive film 1
As 08, Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material containing these as a main component can be used. For example, a 100 nm tungsten film is formed by sputtering or the like.

Next, resist masks 190a and 190b are formed over the first conductive film 108 (see FIG. 2).
C)).

Next, using the resist masks 190a and 190b as masks, the first conductive film 108 is etched so as to be divided over the oxide semiconductor layer 106, so that the first source electrode layer 108a and the first drain electrode layer 108b are formed. After that, the resist masks 190a and 190b are removed (see FIG. 2D).

At this time, a part of the oxide semiconductor layer 106 is etched by over-etching of the first conductive film 108 as illustrated in FIG. However, the first conductive film 1
When the etching selectivity between 08 and the oxide semiconductor layer 106 is large, the oxide semiconductor layer 10
6 has a shape that is hardly etched.

Further, by over-etching the first conductive film 108, part of the oxide insulating film 104, more specifically, the first source electrode layer 108a and the first drain electrode layer as illustrated in FIG. 2D. The outer periphery of 108b is etched.

Next, the second conductive film 110 serving as the second source electrode layer 110a and the second drain electrode layer 110b is formed over the oxide semiconductor layer 106, the first source electrode layer 108a, and the first drain electrode layer 108b. (See FIG. 3A). As the second conductive film, a conductive nitride such as tantalum nitride or titanium nitride, ruthenium, or an alloy material containing these as a main component can be used. For example, a 20 nm tantalum nitride film is formed by sputtering or the like.

Next, the second conductive film 110 is etched so as to be divided over the oxide semiconductor layer 106, and
A second source electrode layer 110a and a second drain electrode layer 110b are formed (FIG. 3B
)reference). At this time, a shape in which part of the oxide semiconductor layer 106 is etched may be used as in the shape illustrated in FIG. Although not illustrated, when the second source electrode layer 110a and the second drain electrode layer 110b are etched, part of the oxide insulating film 104, more specifically, the second source electrode layer 110a and the second source electrode layer 110a are etched. The outer periphery of the second drain electrode layer 110b may be etched.

Note that in the case of forming a transistor with an extremely short channel length (between the second source electrode layer 110a and the second drain electrode layer 110b), first, the first source electrode layer 108a and the first drain electrode layer Etching the second conductive film 110 into a shape that covers 108b,
Thereafter, resist mask processing is performed using a method suitable for thin line processing such as electron beam exposure, and etching is performed, whereby the second source electrode layer 110a and the second drain electrode layer 110b can be formed. Note that when a positive resist is used as the resist mask, an exposure region can be minimized and throughput can be improved. By using such a method, a transistor with a channel length of 30 nm or less can be formed.

Next, it is preferable to perform the second heat treatment. The second heat treatment can be performed under conditions similar to those of the first heat treatment. By the second heat treatment, impurities such as hydrogen and water can be further removed from the oxide semiconductor layer 106.

Next, the gate insulating film 112 is formed over the oxide insulating film 104, the oxide semiconductor layer 106, the second source electrode layer 110a, and the second drain electrode layer 110b (see FIG. 3C).
. The gate insulating film 112 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Etc. can be used. Note that the gate insulating film 112 may be a stacked layer of any of the above materials. The gate insulating film 112 is formed by sputtering, CVD, MBE, A
An LD method, a PLD method, or the like can be used.

The gate insulating film 112 is preferably subjected to heat treatment continuously after formation. For example,
The gate insulating film 112 is formed with a PE-CVD apparatus, and heat treatment is continuously performed in a vacuum. The heat treatment can remove hydrogen, moisture, and the like from the gate insulating film 112. By performing the heat treatment, a dense gate insulating film 112 that has been dehydrated or dehydrogenated can be formed.

Next, a third conductive film 113 to be the gate electrode layer 114 is formed over the gate insulating film 112, and then a resist mask 192 is formed in a desired region (see FIG. 3D). As the third conductive film 113, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag
, Ta, W, or an alloy material containing these as a main component can be used. The third conductive film 113 can be formed by a sputtering method or the like.

Next, after the third conductive film 113 is etched to form the gate electrode layer 114, the resist mask 192 is removed (see FIG. 4A).

Next, the protective insulating film 116 is formed over the gate insulating film 112 and the gate electrode layer 114 (see FIG. 4B). As the protective insulating film 116, a material with little diffusion or movement of oxygen is preferably used. The protective insulating film 116 is preferably formed using a material with a low hydrogen content. The hydrogen content in the protective insulating film 116 is preferably 5 × 10 ¹⁹ / cm ^3.
Or less, more preferably less than 5 × 10 ¹⁸ / cm ³ . By setting the hydrogen content in the protective insulating film 116 to the above value, the off-state current of the transistor can be reduced.

For example, as the protective insulating film 116, a silicon nitride film or a silicon nitride oxide film is preferably used. The protective insulating film 116 can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. In particular, when the silicon nitride film is formed by a sputtering method, the protective insulating film 116 has a small content of water and hydrogen in the film.
preferable.

Next, it is preferable to perform a third heat treatment. The third heat treatment can be performed under conditions similar to those of the first heat treatment. By the third heat treatment, oxygen is easily released from the oxide insulating film 104 and the gate insulating film 112, so that oxygen vacancies in the oxide semiconductor layer 106 can be reduced.

  Through the above steps, the transistor 150 illustrated in FIG. 1 can be manufactured.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 3)
In this embodiment, a transistor having a structure different from that of the transistor described in Embodiment 1 will be described with reference to FIGS.

FIGS. 5A, 5B, and 5C are a top view and cross-sectional views of a transistor of one embodiment of the present invention. FIG. 5A illustrates a top view of the transistor, and FIG. 5B corresponds to a cross section taken along dashed-dotted line X2-Y2 in FIG. FIG. 5C shows a one-dot chain line V shown in FIG.
It corresponds to a cross section of 2-W2. Note that in the top view of FIG. 5A, some elements are illustrated as transparent or omitted for clarity. Further, the same portions as those of the transistor described in Embodiment 1 or portions having similar functions are denoted by the same reference numerals, and description thereof is not repeated.

5A, 5B, and 5C includes an oxide insulating film 104 formed over the substrate 102, an oxide semiconductor layer 106 formed over the oxide insulating film 104, The first source electrode layer 168a and the first drain electrode layer 168b formed over the oxide semiconductor layer 106, and the first source electrode layer 168a and the first drain electrode layer 168b, respectively. Second source electrode layer 110a and second drain electrode layer 110
b, the gate insulating film 112 formed on the oxide insulating film 104, the oxide semiconductor layer 106, the second source electrode layer 110a, and the second drain electrode layer 110b, and the gate insulating film 1
12 and the gate electrode layer 11 formed at a position overlapping with the oxide semiconductor layer 106.
4, the protective insulating film 116 formed on the gate insulating film 112 and the gate electrode layer 114.
And having. Note that another insulating layer, a wiring, or the like may be formed above the protective insulating film 116.

The transistor 152 described in this embodiment is different from the transistor 150 described in Embodiment 1 in that the shapes of the first source electrode layer 168a and the first drain electrode layer 168b are different. Note that the first source electrode layer 168a and the first drain electrode layer 168b
The second source electrode layer 110a, the second drain electrode layer 110b, the gate insulating film 112, the gate electrode layer 114, and the protective insulating film 116 formed above the first source electrode layer 168a are also formed.
, And the shape of the first drain electrode layer 168b.

By forming the first source electrode layer 168a and the first drain electrode layer 168b in a stepped shape as shown in FIG. 5, the second source electrode layer 110a and the second drain electrode layer 11 are formed.
The coverage of 0b and the gate insulating film 112 can be improved. In addition, since the coverage with the gate insulating film 112 is favorable, oxygen released from the oxide insulating film 104 is likely to diffuse upward to serve as a channel of the oxide semiconductor layer 106 through the gate insulating film 112. It becomes.

  Here, a method for manufacturing the transistor 152 is described with reference to FIGS.

The transistor is formed up to the process illustrated in FIG. 6A by a manufacturing method similar to that of the transistor 150 illustrated in FIG. 2C (see FIG. 6A). Note that the cross-sectional structures shown in FIGS. 6A and 2C are the same.

Next, the first conductive film 108 is etched using the resist masks 190a and 190b to form the first source electrode layer 108a and the first drain electrode layer 108b (FIG. 6).
(See (B)).

Next, the resist masks 194a and 194b are formed by retracting or reducing the resist mask by ashing the resist masks 190a and 190b (FIG. 6).
(See (C)).

Next, the first source electrode layer 108a and the first drain electrode layer 108b are etched using the resist masks 194a and 194b, and then the resist mask 194a and
By removing 194b, a first source electrode layer 168a and a first drain electrode layer 168b are formed (see FIG. 6D).

In this manner, the shape of the end portions of the first source electrode layer 168a and the first drain electrode layer 168b is stepped by alternately performing the step of retracting or reducing the resist mask by ashing and the step of etching a plurality of times. Can be formed.

Note that in the subsequent steps, the transistor 152 described in this embodiment can be manufactured by performing the same manufacturing steps as the transistor 150 described in the above embodiment.

The above is the transistor of one embodiment of the present invention, and the structure of the transistor can suppress an increase in oxygen vacancies in the oxide semiconductor layer. In particular, the transistor
Oxygen can be supplied from the oxide insulating film in contact with the oxide semiconductor layer and the gate insulating film into the oxide semiconductor layer. Therefore, a semiconductor device that exhibits favorable electrical characteristics and high long-term reliability can be provided.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 4)
In this embodiment, a transistor having a structure different from that of the transistor described in Embodiment 1 will be described with reference to FIGS.

7A, 7B, 7C, and 7D are a top view and cross-sectional views of a transistor of one embodiment of the present invention. 7A shows a top view of the transistor, and FIG. 7B shows a top view of the transistor in FIG.
Corresponds to the cross section of the alternate long and short dash line X3-Y3. FIG. 7C corresponds to a cross section taken along dashed-dotted line V3-W3 in FIG. FIG. 7D illustrates the width of each structure of the transistor illustrated in FIG. 7B. Note that in the top view of FIG. 7A, some elements are illustrated as transparent or omitted for the sake of clarity. Further, the same portions as those of the transistor described in Embodiment 1 or portions having similar functions are denoted by the same reference numerals, and description thereof is not repeated.

A transistor 154 illustrated in FIGS. 7A to 7D includes an oxide insulating film 104 formed over the substrate 102 and an oxide semiconductor formed over the oxide insulating film 104. Layer 10
6, the first source electrode layer 108 a and the first drain electrode layer 108 b formed over the oxide semiconductor layer 106, and the first source electrode layer 108 a and the first drain electrode layer 10.
8b, the second source electrode layer 110a and the second drain electrode layer 110b, the oxide insulating film 104, the oxide semiconductor layer 106, and the second source electrode layer 110.
a, a gate insulating film 112 formed over the second drain electrode layer 110b, a gate electrode layer 174 formed over the gate insulating film 112 and in a position overlapping with the oxide semiconductor layer 106, and a gate An insulating film 112; and a protective insulating film 116 formed over the gate electrode layer 174. Note that another insulating layer, a wiring, or the like may be formed above the protective insulating film 116.

The transistor 154 described in this embodiment is different from the transistor 150 described in Embodiment 1 in that the shape of the gate electrode layer 174 is different. In transistor 150,
The gate electrode layer 114 includes a first source electrode layer 108a, a first drain electrode layer 108b,
The transistor 154 is provided so as to overlap with the second source electrode layer 110a and the second drain electrode layer 110b. In the transistor 154 described in this embodiment, the second source electrode layer 110a and the second source electrode layer 110a This is a structure provided at a position overlapping with the drain electrode layer 110b. In other words, the gate electrode layer 174 is not provided in a position overlapping with the first source electrode layer 108a and the first drain electrode layer 108b.

  Here, intervals between the components are described with reference to a cross-sectional view illustrated in FIG.

The distance (L1) between the first source electrode layer 108a and the first drain electrode layer 108b is 0
. The thickness is 8 μm or more, preferably 1.0 μm or more. If L1 is smaller than 0.8 μm, the influence of oxygen vacancies generated in the channel formation region cannot be eliminated, and the electrical characteristics of the transistor may be deteriorated.

On the other hand, the distance (L2) between the second source electrode layer 110a and the second drain electrode layer 110b
Can be a value smaller than L1, for example, good electrical characteristics of a transistor can be obtained even when the thickness is 30 nm or less.

When the width of the gate electrode layer 114 is L0, by setting L1 ≧ L0 ≧ L2 (L0 is L2 or more and L1 or less), the parasitic capacitance between the gate and the drain and between the gate and the source can be minimized. The frequency characteristics of the transistor can be improved. For example, L0 is 4
It can be 0 nm. In order to obtain good transistor electrical characteristics, L0-L
2 is preferably 2 nm or more and 20 nm or less, and L1-L2 is preferably 20 nm or more and 1 μm or less.

However, in a transistor that does not require high frequency characteristics, L0 ≧ L1 ≧ L2 (L1 is L2 or more and L0 or less) may be used, as shown in FIG. In such a structure, the difficulty of the process at the time of forming the gate electrode can be reduced.

When the width of the oxide semiconductor layer 106 is L3 and the width of the transistor 154 is L4, L3 is preferably less than 1 μm and L4 is preferably 1 μm to 2.5 μm. By setting L3 and L4 to the above numerical values, the transistor can be miniaturized.

  Here, a method for manufacturing the transistor 154 is described with reference to FIGS.

The transistor is formed up to the process illustrated in FIG. 8A by a manufacturing method similar to that of the transistor 150 illustrated in FIG. 3D (see FIG. 8A). Note that the cross section shown in FIG. 3D and FIG.
The shape of the resist mask 196 is different in the cross section shown in FIG.

Note that the resist mask 196 is preferably a mask having a finer pattern by performing slimming treatment on a mask formed by a photolithography method or the like. As the slimming treatment, for example, an ashing treatment using radical oxygen (oxygen radical) or the like can be applied. As a result of the slimming treatment, a mask formed by a photolithography method or the like can be miniaturized to a line width of less than the resolution limit of the exposure apparatus, preferably ½ or less, more preferably １ ／ or less. . For example, the line width is 20
The thickness can be set in the range from nm to 2000 nm, preferably from 50 nm to 350 nm.

Next, the third conductive film 113 is etched using the resist mask 196 to form the gate electrode layer 174, and then the resist mask 196 is removed (see FIG. 8B).

Note that for the subsequent steps, the transistor 154 described in this embodiment can be manufactured by performing the same manufacturing steps as the transistor 150 described in the above embodiment.

The above is the transistor of one embodiment of the present invention, and the structure of the transistor can suppress an increase in oxygen vacancies in the oxide semiconductor layer. In particular, the transistor
Oxygen can be supplied from the oxide insulating film in contact with the oxide semiconductor layer and the gate insulating film into the oxide semiconductor layer. Therefore, a semiconductor device that exhibits favorable electrical characteristics and high long-term reliability can be provided.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 5)
In this embodiment, a transistor having a structure different from that of the transistor described in Embodiment 1 will be described with reference to FIGS.

  First, the transistor 156 illustrated in FIG. 9 is described.

9A, 9B, and 9C are a top view and cross-sectional views of a transistor of one embodiment of the present invention. 9A illustrates a top view of the transistor, and FIG. 9B corresponds to a cross section taken along dashed-dotted line X4-Y4 in FIG. 9A. Further, FIG. 9C shows a one-dot chain line V shown in FIG.
It corresponds to a cross section of 4-W4. Note that in the top view of FIG. 9A, some elements are illustrated as transparent or omitted for the sake of clarity. Further, the same portions as those of the transistor described in Embodiment 1 or portions having similar functions are denoted by the same reference numerals, and description thereof is not repeated.

A transistor 156 illustrated in FIGS. 9A, 9B, and 9C includes an oxide insulating film 104 formed over the substrate 102, an oxide semiconductor layer 106 formed over the oxide insulating film 104, The first source electrode layer 168a and the first drain electrode layer 168b formed over the oxide semiconductor layer 106, and the first source electrode layer 168a and the first drain electrode layer 168b, respectively. Second source electrode layer 110a and second drain electrode layer 110
b, the gate insulating film 112 formed on the oxide insulating film 104, the oxide semiconductor layer 106, the second source electrode layer 110a, and the second drain electrode layer 110b, and the gate insulating film 1
12 and a gate electrode layer 17 formed at a position overlapping with the oxide semiconductor layer 106.
4, the gate insulating film 112, and the protective insulating film 116 formed on the gate electrode layer 174
And having. Note that another insulating layer, a wiring, or the like may be formed above the protective insulating film 116.

The transistor 156 described in this embodiment is different from the transistor 150 in Embodiment 1 in that the shapes of the first source electrode layer 168a and the first drain electrode layer 168b and the gate electrode layer 174 are different. Different. Note that the first source electrode layer 168a,
And a second source electrode layer 110a formed above the first drain electrode layer 168b,
The second drain electrode layer 110b, the gate insulating film 112, the gate electrode layer 174, and the protective insulating film 116 also have shapes that match the shapes of the first source electrode layer 168a and the first drain electrode layer 168b.

In the transistor 150, the gate electrode layer 114 includes the first source electrode layer 1
08a, the first drain electrode layer 108b, the second source electrode layer 110a, and the second drain electrode layer 110b are provided so as to overlap with each other. In the transistor 156 described in this embodiment, Source electrode layer 110a and second drain electrode layer 11
In this structure, the gate electrode layer 174 is provided at a position overlapping 0b. In other words, the gate electrode layer 174 is not provided in a position overlapping with the first source electrode layer 108a and the first drain electrode layer 108b.

For other structures, the transistor 156 described in this embodiment can be formed with reference to the method for manufacturing the transistor 152 and the transistor 154 described in the above embodiment.

  Next, the transistor 158 illustrated in FIG. 10 is described.

10A, 10B, and 10C includes an oxide insulating film 104 formed over the substrate 102, an oxide semiconductor layer 106 formed over the oxide insulating film 104,
Formed on each of the first source electrode layer 178a and the first drain electrode layer 178b, and the first source electrode layer 178a and the first drain electrode layer 178b formed over the oxide semiconductor layer 106. Second source electrode layer 180a and second drain electrode layer 18
0b, the gate insulating film 112 formed on the oxide insulating film 104, the oxide semiconductor layer 106, the second source electrode layer 180a, and the second drain electrode layer 180b, and the gate insulating film 112. The gate electrode layer 1 formed at a position overlapping with the oxide semiconductor layer 106
74, the protective insulating film 11 formed on the gate insulating film 112 and the gate electrode layer 174
6. Note that another insulating layer, a wiring, or the like may be formed above the protective insulating film 116.

The transistor 158 described in this embodiment is different from the transistor 150 described in Embodiment 1 in that the first source electrode layer 178a, the first drain electrode layer 178b, the second source electrode layer 180a, and the second The shape of the drain electrode layer 180b and the shape of the gate electrode layer 174 are different. Note that the second source electrode layer 180a and the second drain electrode layer 1 formed above the first source electrode layer 178a and the first drain electrode layer 178b.
The shape of 80b, the gate insulating film 112, the gate electrode layer 174, and the protective insulating film 116 also matches the shapes of the first source electrode layer 178a and the first drain electrode layer 178b.

The first source electrode layer 178a and the first drain electrode layer 178b are shaped as shown in FIG. 10, so that the second source electrode layer 180a, the second drain electrode layer 180b, and the gate insulating film 112 are covered. Property can be improved.

The second source electrode layer 180a and the second drain electrode layer 180b are formed of the first source electrode layer 178a and the first drain electrode layer 178b in the cross section in the channel length direction (FIG. 10B). It is provided inside. Thus, the second source electrode layer 18
0a and the second drain electrode layer 180b may be provided at least in a region having a channel length of the oxide semiconductor layer 106 and do not cover the first source electrode layer 178a and the first drain electrode layer 178b. It is good also as a structure. However, as in the transistor described in the above embodiment, the first source electrode layer and the first drain electrode layer are covered with the second source electrode layer and the second drain electrode layer, so that the first source Since the possibility of oxygen diffusing or moving to the side surfaces of the electrode layer and the second drain electrode layer is reduced, oxygen can be preferably supplied from the oxide insulating film to the oxide semiconductor layer through the gate insulating film. it can.

The above is the transistor of one embodiment of the present invention, and the structure of the transistor can suppress an increase in oxygen vacancies in the oxide semiconductor layer. In particular, the transistor
Oxygen can be supplied from the oxide insulating film in contact with the oxide semiconductor layer and the gate insulating film into the oxide semiconductor layer. Therefore, a semiconductor device that exhibits favorable electrical characteristics and high long-term reliability can be provided.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 6)
In this embodiment, an example of a semiconductor device (memory device) that uses a transistor which is one embodiment of the present invention, can hold stored data even when power is not supplied, and has no limit on the number of writing times. This will be described with reference to the drawings.

FIG. 11A is a cross-sectional view of the semiconductor device, and FIG. 11B is a circuit diagram of the semiconductor device.

A semiconductor device illustrated in FIGS. 11A and 11B includes a transistor 3200 using a first semiconductor material in a lower portion and a transistor 3202 using a second semiconductor material in an upper portion.
And a capacitor 3204. Note that the transistor described in Embodiments 1 to 5 can be used as the transistor 3202, and this embodiment shows an example in which the transistor 150 illustrated in FIG. 1 of Embodiment 1 is applied. In addition, the capacitor 3204
Has one electrode as the gate electrode of the transistor 3202, and the other electrode as the transistor 320.
2 source electrode or drain electrode, and a dielectric as the gate insulating film 11 of the transistor 3202
2 can be formed at the same time as the transistor 3202.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be the oxide semiconductor described in Embodiment 1.
For example, a transistor using crystalline silicon as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time because of electrical characteristics with low off-state current.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. Further, in addition to using the transistor described in Embodiment 1 using an oxide semiconductor to hold information, a specific structure of the semiconductor device such as a material used for the semiconductor device and a structure of the semiconductor device is described here. It is not necessary to limit to what is shown by.

A transistor 3200 in FIG. 11A includes a channel formation region provided in a substrate 3000 containing a semiconductor material (e.g., crystalline silicon), an impurity region provided so as to sandwich the channel formation region, and an impurity region It has an intermetallic compound region in contact, a gate insulating film provided on the channel formation region, and a gate electrode layer provided on the gate insulating film. Note that in the drawing, the source electrode layer and the drain electrode layer may not be explicitly provided, but for convenience, the transistor may be referred to as a transistor including such a state. In this case,
In order to describe the connection relationship of the transistors, the source electrode layer and the drain electrode layer may be expressed including the source region and the drain region. That is, in this specification, the term “source electrode layer” can include a source region.

An element isolation insulating layer 3106 is provided over the substrate 3000 so as to surround the transistor 3200, and an oxide insulating film 3220 is provided so as to cover the transistor 3200. Note that the element isolation insulating layer 3106 is formed of LOCOS (Local Oxidation o
f Silicon) and STI (Shallow Trench Isolation)
) Or the like.

For example, the transistor 3200 using a crystalline silicon substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. As a treatment before the formation of the transistor 3202 and the capacitor 3204, CMP treatment is performed on the oxide insulating film 3220 covering the transistor 3200 so that the oxide insulating film 3220 is planarized and at the same time the top surface of the gate electrode layer of the transistor 3200 is exposed. .

A transistor 3202 is provided over the oxide insulating film 3220, and one of a source electrode and a drain electrode thereof extends and functions as one electrode of the capacitor 3204.

A transistor 3202 illustrated in FIG. 11A is a top-gate transistor in which a channel is formed in an oxide semiconductor layer. Since the off-state current of the transistor 3202 is small,
By using this, the stored contents can be retained for a long time. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

Further, the electrode 31 is interposed through the oxide insulating film 3220 so as to overlap with the transistor 3202.
50 is provided. By supplying an appropriate potential to the electrode, the transistor 3202 is supplied.
Can be controlled. In addition, long-term reliability of the transistor 3202 can be improved.

As illustrated in FIG. 11A, the transistor 3200 and the transistor 3202 can be formed so as to overlap with each other, so that the occupied area can be reduced. Therefore,
The degree of integration of the semiconductor device can be increased.

  Next, an example of a circuit configuration corresponding to FIG. 11A is illustrated in FIG.

In FIG. 11B, the first wiring (1st Line) and the source electrode layer of the transistor 3200 are electrically connected, and the second wiring (2nd Line) and the transistor 3 are electrically connected.
The drain electrode layer 200 is electrically connected. Also, the third wiring (3rd L
ine) and one of the source electrode layer and the drain electrode layer of the transistor 3202 are electrically connected, and the fourth wiring (4th Line) and the gate electrode layer of the transistor 3202 are electrically connected. . One of a gate electrode layer of the transistor 3200 and a source electrode layer or a drain electrode layer of the transistor 3202 is electrically connected to the other electrode of the capacitor 3204, and a fifth wiring (5th Line) and a capacitor 3204
The other electrode is electrically connected.

In the semiconductor device illustrated in FIG. 11B, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode layer of the transistor 3200 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 3202 is turned on, so that the transistor 3202 is turned on. Accordingly, the potential of the third wiring is changed between the gate electrode layer of the transistor 3200 and the capacitor 3.
204. That is, predetermined charge is supplied to the gate electrode layer of the transistor 3200 (writing). Here, a charge giving two different potential levels (hereinafter referred to as Lo)
Any one of w-level charge and high-level charge) is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 3202 is turned off and the transistor 3202 is turned off, whereby the charge given to the gate electrode layer of the transistor 3200 is held (held).

Since the off-state current of the transistor 3202 is extremely small, the charge of the gate electrode layer of the transistor 3200 is held for a long time.

Next, reading of information will be described. When an appropriate potential (readout potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, according to the amount of charge held in the gate electrode layer of the transistor 3200, The second wiring takes different potentials. In general, when the transistor 3200 is an n-channel transistor, a Hi electrode is formed on the gate electrode layer of the transistor 3200.
The apparent threshold V _{th_H} when the gh level charge is _applied is the same as that of the transistor 3
Apparent threshold V _t when low level charge is applied to the 200 gate electrode layers
_This is because it becomes lower than _{h_L} . Here, the apparent threshold voltage is the transistor 32.
A potential of the fifth wiring necessary to turn 00 into an “on state” is assumed. Therefore, by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} , the charge given to the gate electrode layer of the transistor 3200 can be determined. For example, in writing, when a high level charge is given, the potential of the fifth wiring is V ₀ (> V _{t
h_H} ), the transistor 3200 is turned on. In the case where the low-level charge is _supplied , the transistor 3200 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the retained information can be read by determining the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 3200 is turned “off” regardless of the state of the gate electrode layer, that is, V _th
A potential smaller than _{_H} may be supplied to the fifth wiring. _{Alternatively} , a potential that turns on the transistor 3200 regardless of the state of the gate electrode layer, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not required for writing data,
There is no problem of deterioration of the element. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times that is a problem in the conventional nonvolatile memory,
Reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

As described above, a semiconductor device that achieves miniaturization and high integration and is provided with high electrical characteristics, and the semiconductor device can be provided.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 7)
In this embodiment, a semiconductor device which uses a transistor which is one embodiment of the present invention, can hold stored data even when power is not supplied, and has no limit on the number of writing times is described in Embodiment 6. A description will be given of a semiconductor device different from the structure shown.

FIG. 12A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 12B is a conceptual diagram illustrating an example of a semiconductor device. Note that as the transistor 4162 included in the semiconductor device, the transistor described in any of Embodiments 1 to 5 can be used. Capacitance element 4
The transistor 254 can be manufactured at the same time in the manufacturing process of the transistor 4162 as in the capacitor 3204 described in Embodiment 6.

In the semiconductor device illustrated in FIG. 12A, the bit line BL and the source electrode of the transistor 4162 are electrically connected, the word line WL and the gate electrode of the transistor 4162 are electrically connected, and the drain electrode of the transistor 4162 And one terminal of the capacitor 4254 are electrically connected.

Next, the case where data is written and held in the semiconductor device (memory cell 4250) illustrated in FIG.

First, the potential of the word line WL is set to a potential at which the transistor 4162 is turned on, so that the transistor 4162 is turned on. As a result, the potential of the bit line BL is changed to the capacitive element 4.
It is given to one terminal of 254 (writing). After that, the potential of one terminal of the capacitor 4254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 4162 is turned off and the transistor 4162 being turned off.

The transistor 4162 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, the capacitor 4425 is turned off by turning off the transistor 4162.
The potential of the fourth first terminal (or the charge accumulated in the capacitor 4254) can be held for an extremely long time.

Next, reading of information will be described. When the transistor 4162 is turned on,
The bit line BL in a floating state and the capacitor 4254 are brought into conduction, and the bit line BL and the capacitor 4
The charge is redistributed between 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL depends on the potential of the first terminal of the capacitor 4254 (or the capacitor 425).
The value varies depending on the charge accumulated in 4.

For example, the potential of the first terminal of the capacitor 4254 is V, the capacitor of the capacitor 4254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Thus, memory cell 425
As a state of 0, the potential of the first terminal of the capacitor 4254 is 2 between V1 and V0 (V1> V0).
If the state is taken, the potential of the bit line BL when the potential V1 is held (= (CB × V
It can be seen that (B0 + C × V1) / (CB + C)) is higher than the potential of the bit line BL when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)).

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 12A can hold charge that is accumulated in the capacitor 4254 for a long time because the off-state current of the transistor 4162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

  Next, the semiconductor device illustrated in FIG. 12B is described.

The semiconductor device illustrated in FIG. 12B includes a memory cell array 4251 (memory cell arrays 4251a and 4251b including a plurality of memory cells 4250 illustrated in FIG. 12A as a memory circuit in an upper portion and a memory cell array 4251 in a lower portion. A peripheral circuit 4253 necessary for operation is included, and the peripheral circuit 4253 is electrically connected to the memory cell array 4251.

With the structure shown in FIG. 12B, the peripheral circuit 4253 is provided in the memory cell array 4.
Since the semiconductor device can be provided directly below 251a and 4251b, the semiconductor device can be downsized.

A transistor provided in the peripheral circuit 4253 is preferably formed using a semiconductor material different from that of the transistor 4162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is more preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized by the transistors.

Note that in the semiconductor device illustrated in FIG. 12B, the structure in which the memory cell array 4251 is a stack of the memory cell array 4251a and the memory cell array 4251b is illustrated; however, the number of stacked memory cells is not limited thereto. Three or more memory cells may be stacked, or a single layer may be used.

The transistor 4162 is formed using an oxide semiconductor and is described in Embodiments 1 to 5.
The transistor described in the above can be used. Transistors using oxide semiconductors
Since the off-state current is small, stored data can be held for a long time. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

In addition, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficient off-state current is provided). By integrally including a memory circuit using a small transistor, a semiconductor device having unprecedented characteristics can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

As described above, a semiconductor device that achieves miniaturization and high integration and has high electrical characteristics can be provided.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

(Embodiment 8)
In this embodiment, examples of electronic devices that can use the transistors described in Embodiments 1 to 5 are described.

The transistor described in any of Embodiments 1 to 5 includes a variety of electronic devices (including game machines).
Can be applied to. Electronic devices include televisions, monitors and other display devices, lighting devices,
Desktop or laptop personal computer, word processor, DVD (
Digital Versatile Disc), an image playback device for playing back still images or moving images stored in a recording medium, portable CD player, radio, tape recorder,
Headphone stereo, stereo, cordless telephone cordless handset, transceiver, portable radio, mobile phone, car phone, portable game machine, calculator, personal digital assistant, electronic notebook, electronic book, electronic translator, voice input device, video camera, High-frequency heating devices such as digital still cameras, electric shavers, IC chips, microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioners, etc., dishwashers, dish dryers, clothes dryers, and futon dryers And medical equipment such as a refrigerator, an electric refrigerator, an electric freezer, an electric refrigerator-freezer, a DNA storage freezer, a radiation measuring instrument, and a dialysis machine. Moreover, alarm devices, such as a smoke detector, a gas alarm device, and a security alarm device, are also mentioned. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. In addition, an engine using petroleum and a moving body driven by an electric motor using electric power from a non-aqueous secondary battery are also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, and a plug-in hybrid vehicle (P
HEV), tracked vehicles with tire wheels changed to endless tracks, motorbikes including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial Examples include satellites, space probes, planetary probes, and spacecraft. Specific examples of these electronic devices are illustrated in FIGS. 13, 14, 15, and 16.

First, the structure of a fire alarm will be described with reference to FIG. 13 as an example of an alarm device. In addition,
In this specification, a fire alarm indicates a general device that promptly reports the occurrence of a fire. For example, a fire alarm used in a house, an automatic fire alarm facility, or a fire used in the automatic fire alarm facility. Sensors are also included in the fire alarm.

The alarm device illustrated in FIG. 13 includes at least a microcomputer 500. here,
The microcomputer 500 is provided inside the alarm device. The microcomputer 500 includes a power gate controller 503 electrically connected to the high potential power line VDD.
A power gate 504 electrically connected to the high potential power line VDD and the power gate controller 503, and a CPU (Central) electrically connected to the power gate 504
Processing Unit) 505, power gate 504 and CPU 505
And a detection unit 509 electrically connected to each other. The CPU 505 includes a volatile storage unit 506 and a nonvolatile storage unit 507.

The CPU 505 is electrically connected to the bus line 502 via the interface 508. The interface 508 is also electrically connected to the power gate 504 in the same manner as the CPU 505. As a bus standard of the interface 508, for example, I ² C
A bus or the like can be used. In addition, the alarm device described in this embodiment is provided with a light-emitting element 530 that is electrically connected to the power gate 504 through the interface 508.

The light emitting element 530 preferably emits light having a strong directivity, such as an organic EL element,
An inorganic EL element, an LED (Light Emitting Diode), or the like can be used.

The power gate controller 503 has a timer and controls the power gate 504 according to the timer. The power gate 504 is connected to the CPU 505, the detection unit 509, and the interface 508 according to the control of the power gate controller 503.
Supply or cut off the power supplied from D. Here, as the power gate 504, for example, a switching element such as a transistor can be used.

By using the power gate controller 503 and the power gate 504 as described above, the detection unit 509, the CPU 505, and the interface 508 are used during the period in which the amount of light is measured.
The power supply to the detection unit 509, the CPU 505, and the interface 508 can be interrupted between measurement periods. By operating the alarm device in this way, it is possible to reduce power consumption compared to the case where power is constantly supplied to each of the above components.

In the case where a transistor is used as the power gate 504, a transistor with extremely low off-state current used for the nonvolatile memory portion 507, for example, a transistor including an oxide semiconductor is preferably used. By using such a transistor, leakage current can be reduced and power consumption can be reduced when the power gate 504 shuts off the power supply.

A DC power supply 501 may be provided in the alarm device described in this embodiment so that power is supplied from the DC power supply 501 to the high potential power supply line VDD. The electrode on the high potential side of the DC power source 501 is the high potential power line V.
The electrode on the low potential side of the DC power supply 501 is electrically connected to the low potential power supply line VSS. The low potential power line VSS is electrically connected to the microcomputer 500. Here, a high potential H is applied to the high potential power supply line VDD. The low potential power supply line VSS is supplied with a low potential L such as a ground potential (GND).

In the case where a battery is used as the DC power supply 501, for example, an electrode electrically connected to the high potential power supply line VDD, an electrode electrically connected to the low potential power supply line VSS, and the battery can be held. A battery case having a housing may be provided in the housing. Note that the alarm device described in this embodiment is not necessarily provided with the DC power source 501, and may be configured to supply power from an AC power source provided outside the alarm device via a wiring, for example.

In addition, a secondary battery such as a lithium ion secondary battery (also referred to as a lithium ion storage battery, a lithium ion battery, or a lithium ion battery) can be used as the battery. In addition, a solar battery is preferably provided so that the secondary battery can be charged.

The detection unit 509 measures a physical quantity related to the abnormality and transmits the measurement value to the CPU 505. The physical quantity relating to the abnormality varies depending on the use of the alarm device, and the alarm device functioning as a fire alarm measures the physical quantity relating to the fire. Therefore, the detection unit 509 measures the amount of light as a physical quantity related to a fire and senses the presence of smoke.

The detection unit 509 includes an optical sensor 511 electrically connected to the power gate 504, an amplifier 512 electrically connected to the power gate 504, the power gate 504, and the CPU 5.
And an AD converter 513 electrically connected to 05. The light sensor 511, the amplifier 512, and the AD converter 513 provided in the light emitting element 530 and the detection unit 509 operate when the power gate 504 supplies power to the detection unit 509.

Here, FIG. 14 shows a part of a cross section of the alarm device shown in FIG. The alarm device includes an element isolation region 603 formed in a p-type semiconductor substrate 601, a gate insulating film 607, a gate electrode layer 609, an n-type impurity region 611a, an n-type impurity region 611b, an insulating film 615, and an insulating film. An n-type transistor 719 having a film 617 is formed. The n-type transistor 719 is formed using a semiconductor that is different from an oxide semiconductor, such as single crystal silicon, and thus can operate at a sufficiently high speed. Thereby, it is possible to form a volatile storage unit of the CPU that can be accessed at high speed.

A contact plug 619a and a contact plug 619b are formed in an opening obtained by selectively etching a part of the insulating film 615 and the insulating film 617, and an insulating film having a groove over the insulating film 617, the contact plug 619a, and the contact plug 619b 621 is provided.

A wiring 623 a and a wiring 623 b are formed in the groove of the insulating film 621, and the insulating film 62
1. An insulating film 620 formed by a sputtering method, a CVD method, or the like is provided over the wiring 623a and the wiring 623b. In addition, an insulating film 622 having a groove is formed over the insulating film.

An electrode 624 that functions as a back gate electrode of the second transistor 717 is formed in the groove portion of the insulating film 622. By providing such an electrode 624, the threshold voltage of the second transistor 717 can be controlled.

An oxide insulating film 625 formed by a sputtering method, a CVD method, or the like is provided over the insulating film 622 and the electrode 624. The second transistor 717, the photoelectric conversion element, and the like are formed over the oxide insulating film 625. 714 is provided.

The second transistor 717 includes an oxide semiconductor layer 606, a first source electrode layer 616a and a first drain electrode layer 616b in contact with the oxide semiconductor layer 606, a first source electrode layer 616a, and a first drain. Second source electrode layer 6 in contact with the upper part of electrode layer 616b
26a and the second drain electrode layer 626b, the gate insulating film 612, and the gate electrode layer 6
04 and a protective insulating film 618. In addition, the photoelectric conversion element 714 and the second transistor 71
7 and an insulating film 646 are provided, and a wiring 649 is provided on the insulating film 646 in contact with the first drain electrode layer 616b. The wiring 649 is connected to the second transistor 71.
7 serves as a node for electrically connecting the drain electrode 7 and the gate electrode layer 609 of the n-type transistor 719.

In this embodiment, the connection portion between the second transistor 717 and the wiring 649 is illustrated as being in contact with the first drain electrode layer 616b; however, the present invention is not limited to this.
For example, the structure may be in contact with the second drain electrode layer 626b.

Here, the transistor described in Embodiments 1 to 5 can be used as the second transistor 717, and the oxide semiconductor layer 606 corresponds to the oxide semiconductor layer 106 described in Embodiment 1. In addition, the first source electrode layer 616a and the first drain electrode layer 61
Each of 6b corresponds to the first source electrode layer 108a and the first drain electrode layer 108b described in Embodiment 1. Each of the second source electrode layer 626a and the second drain electrode layer 626b includes the second source electrode layer 110a described in Embodiment 1.
And correspond to the second drain electrode layer 110b.

The optical sensor 511 includes a photoelectric conversion element 714, a capacitor element, a first transistor, and a second transistor.
Transistor 717, a third transistor, and an n-type transistor 719. Here, as the photoelectric conversion element 714, for example, a photodiode or the like can be used.

One terminal of the photoelectric conversion element 714 is electrically connected to the low-potential power supply line VSS, and the other terminal is one of the first source electrode layer 616a and the first drain electrode layer 616b of the second transistor 717. And / or one of the second source electrode layer 626a and the second drain electrode layer 626b.

The gate electrode layer 604 of the second transistor 717 is supplied with the charge accumulation control signal Tx, and the other of the first source electrode layer 616a and the first drain electrode layer 616b and / or the second source electrode layer 626a. Alternatively, the other of the second drain electrode layers 626b is
One of the pair of electrodes of the capacitor, one of the source electrode and the drain electrode of the first transistor, and the gate electrode of the n-type transistor 719 are electrically connected to each other (hereinafter, this node may be referred to as a node FD). is there).

The other of the pair of electrodes of the capacitor is electrically connected to the low potential power supply line VSS. A reset signal Res is supplied to the gate electrode of the first transistor, and the other of the source electrode and the drain electrode is electrically connected to the high potential power supply line VDD.

One of a source electrode and a drain electrode of the n-type transistor 719 is electrically connected to one of the source electrode and the drain electrode of the third transistor and the amplifier 512. The other of the source electrode and the drain electrode of the n-type transistor 719 is electrically connected to the high potential power supply line VDD. The gate electrode of the third transistor is the bias signal Bia
s is provided, and the other of the source electrode and the drain electrode is electrically connected to the low potential power supply line VSS.

Note that the capacitor is not necessarily provided. For example, when the parasitic capacitance of the n-type transistor 719 or the like is sufficiently large, the capacitor may not be provided.

For the first transistor and the second transistor 717, it is preferable to use a transistor with extremely low off-state current. In addition, as the transistor with extremely low off-state current, a transistor including an oxide semiconductor is preferably used. With such a structure, the potential of the node FD can be held for a long time.

In the structure illustrated in FIG. 14, the photoelectric conversion element 714 is provided over the oxide insulating film 625 so as to be electrically connected to the second transistor 717.

The photoelectric conversion element 714 includes a semiconductor film 660 provided over the oxide insulating film 625, and a first source electrode layer 616a and an electrode 616c provided in contact with the semiconductor film 660. The first source electrode layer 616a is an electrode functioning as a source electrode or a drain electrode of the second transistor 717, and electrically connects the photoelectric conversion element 714 and the second transistor 717. In the photoelectric conversion element 714, the first source electrode layer 616 is used.
a and the electrode 616c over the second source electrode layer 626a and the electrode 626c, respectively.
Is provided.

A gate insulating film 612, a protective insulating film 618, an insulating film 645, and an insulating film 646 are provided over the semiconductor film 660, the second source electrode layer 626a, and the electrode 626c. A wiring 656 is provided over the insulating film 646, and includes a gate insulating film 612 and a protective insulating film 6.
18, the insulating film 645, and the electrode 616c are in contact with each other through an opening provided in the insulating film 646.

The electrode 616c can be formed in the same process as the wiring 649 and the first source electrode layer 616a and the first drain electrode layer 616b and the wiring 656 can be formed.

As the semiconductor film 660, a semiconductor film that can perform photoelectric conversion may be provided. For example, silicon, germanium, or the like can be used. In the case where silicon is used for the semiconductor film 660, the semiconductor film 660 functions as an optical sensor that detects visible light. Further, since the wavelength of electromagnetic waves that can be absorbed is different between silicon and germanium, a structure in which germanium is used for the semiconductor film 660 can be used as a sensor that detects infrared light at the center.

As described above, since the microcomputer 500 can be provided with the detection portion 509 including the optical sensor 511, the number of components can be reduced and the housing of the alarm device can be reduced. Note that in the case where a degree of freedom is required for the position of the optical sensor or the photoelectric conversion element, the optical sensor or the photoelectric conversion element may be externally connected and electrically connected to the microcomputer 500.

The alarm device including the IC chip described above uses a CPU 505 in which a plurality of circuits using the transistors described in the above embodiments are combined and mounted on one IC chip.

FIG. 15 illustrates a CP in which the transistor described in any of Embodiments 1 to 5 is used at least in part.
It is a block diagram which shows the specific structure of U.

The CPU illustrated in FIG. 15A is provided over the substrate 1190 with an ALU 1191 (ALU: Arit
hlogic logic unit (arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (ROM I / F). The substrate 1190 is a semiconductor substrate,
An SOI substrate, a glass substrate, or the like is used. ROM 1199 and ROM interface 1
189 may be provided in another chip. Needless to say, the CPU illustrated in FIG. 15A is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

The timing controller 1195 includes an ALU 1191 and an ALU controller 11.
92, a signal for controlling the operation timing of the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197 is generated. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

In the CPU illustrated in FIG. 15A, a memory cell is provided in the register 1196.
As the memory cell of the register 1196, the transistor described in the above embodiment can be used.

In the CPU shown in FIG. 15A, the register controller 1197 has an ALU 119.
1, the holding operation in the register 1196 is selected. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

The power supply is stopped by providing a switching element between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied as shown in FIG. Can do. The circuits in FIGS. 15B and 15C will be described below.

FIG. 15B and FIG. 15C illustrate an example of a structure of a memory circuit including the transistor described in the above embodiment as a switching element that controls supply of a power supply potential to a memory cell.

A memory device illustrated in FIG. 15B includes a switching element 1141 and a memory cell group 1143 including a plurality of memory cells 1142. Specifically, for each memory cell 1142, the transistor described in the above embodiment can be used. Memory cell group 1
A high-level power supply potential VDD is supplied to each memory cell 1142 included in 143 through the switching element 1141. Further, each memory cell 1142 included in the memory cell group 1143 is supplied with the potential of the signal IN and the low-level power supply potential VSS.

In FIG. 15B, the transistor described in the above embodiment is used as the switching element 1141, and the transistor includes the signal SigA supplied to the gate electrode layer.
The switching is controlled by.

Note that FIG. 15B illustrates a structure in which the switching element 1141 includes only one transistor; however, there is no particular limitation, and a plurality of transistors may be included. In the case where the switching element 1141 includes a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be combined in series and parallel. May be connected.

In FIG. 15B, the switching element 1141 controls the supply of the high-level power supply potential VDD to each memory cell 1142 included in the memory cell group 1143, but the switching element 1141 controls the low-level power supply potential VDD. The supply of the power supply potential VSS may be controlled.

FIG. 15C illustrates an example of a memory device in which a low-level power supply potential VSS is supplied to each memory cell 1142 included in the memory cell group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential VSS to each memory cell 1142 included in the memory cell group 1143.

Between the memory cell group and the node to which the power supply potential VDD or the power supply potential VSS is applied,
Even when a switching element is provided to temporarily stop the operation of the CPU and stop the supply of power supply voltage, data can be retained and power consumption can be reduced.
Specifically, for example, the operation of the CPU can be stopped while the user of the personal computer stops inputting information to an input device such as a keyboard, thereby reducing power consumption. it can.

Here, the CPU has been described as an example, but a DSP (Digital Signal)
Processor), custom LSI, FPGA (Field Program)
le Gate Array).

In FIG. 16A, an alarm device 8100 is a residential fire alarm and includes a detection unit and a microcomputer 8101. A microcomputer 8101 is an example of an electrical device including a CPU including the transistor described in the above embodiment.

In FIG. 16A, an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electrical device including a CPU including the transistor described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. FIG. 16A illustrates the case where the CPU 8203 is provided in the indoor unit 8200, but the CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. Power saving can be achieved by using the transistor described in the above embodiment for the CPU of the air conditioner.

In FIG. 16A, an electric refrigerator-freezer 8300 is an example of an electric device including a CPU including the transistor described in the above embodiment. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, and the like. In FIG. 12A, the CPU 8304 is provided inside the housing 8301. By using the transistor described in the above embodiment for the CPU 8304 of the electric refrigerator-freezer 8300, power saving can be achieved.

FIG. 16B illustrates an example of an electric vehicle which is an example of an electric device. Electric car 97
00 includes a secondary battery 9701. The power of the secondary battery 9701 is supplied to the control circuit 9
The output is adjusted by 702 and supplied to the driving device 9703. The control circuit 9702
It is controlled by a processing device 9704 having a ROM, RAM, CPU, etc. (not shown). By using the transistor described in the above embodiment for the CPU of the electric vehicle 9700, power saving can be achieved.

Drive device 9703 is configured by a DC motor or an AC motor alone, or a combination of an electric motor and an internal combustion engine. The processing device 9704 is based on input information such as operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and information at the time of travel (information such as uphill and downhill, load information on the drive wheels, etc.). The control signal is output to the control circuit 9702. The control circuit 9702 controls the output of the driving device 9703 by adjusting the electric energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter that converts direct current to alternating current is also built in, although not shown.

Note that this embodiment can be combined with any of the other embodiments or examples in this specification as appropriate.

In this embodiment, a conductive film is formed over an oxide semiconductor film, and SIMS (Secondary
A result obtained by examining the diffusion or movement of elements between stacked films by Ion Mass Spectrometry analysis will be described.

FIGS. 17A and 17B show results of SIMS analysis of the oxygen isotope ( ¹⁸ O) in the depth direction before and after the heat treatment by fabricating a stacked sample of an IGZO film and a tungsten film by using a sputtering method. is there. Note that the IGZO film uses In: Ga: Zn = 1: 1: 1 or 1: 3: 2 (atomic ratio) as a sputtering target, and Ar: O ₂ ( ¹⁸ O) =
It is formed by DC sputtering using 2: 1 (flow rate ratio) as a film forming gas. Also,
The tungsten film was formed by DC sputtering using tungsten as a sputtering target and Ar 100% as a deposition gas. The heat treatment is performed at 300 ° C. and 350
℃, 400 ℃, 450 ℃ each one hour, including the samples not subjected to heat treatment each 5
Comparisons were made with samples.

Here, the IGZO film formed using In: Ga: Zn = 1: 1: 1 (atomic ratio) as a sputtering target is an IGZO film having crystallinity, and In: Ga: Zn = 1: 3.
: 2 (atomic ratio) is an IGZO film formed using a sputtering target.
It is a GZO film.

As shown in FIGS. 17A and 17B, it is understood that oxygen in the oxide semiconductor film is taken into the tungsten film side when the heat treatment temperature is increased regardless of the composition and crystallinity of the oxide semiconductor film. .

Since there are several heating steps in the manufacturing process of the transistor, oxygen vacancies are generated in the vicinity of the oxide semiconductor layer in contact with the source electrode and the drain electrode due to the above phenomenon.
The region becomes n-type. Therefore, the n-type region can function as a source or a drain of the transistor.

18A and 18B show the results of SIMS analysis of a sample manufactured using a tantalum nitride film instead of the tungsten film. The tantalum nitride film was formed by a reactive sputtering method (DC sputtering method) using tantalum as a sputtering target and Ar: N ₂ = 5: 1 (flow rate ratio) as a film forming gas. In addition, as heat processing, it carried out on each of 4 conditions similar to the above, and compared with each of 5 samples including the sample which has not performed heat processing.

FIG. 18A shows SIMS analysis results of a stacked sample of an IGZO film and a tantalum nitride film of In: Ga: Zn = 1: 1: 1. None of the samples showed any movement of oxygen into the tantalum nitride film, and showed a behavior different from that of the tungsten film shown in FIG. FIG. 18B shows SIMS analysis results of a stacked sample of an IGZO film and a tantalum nitride film with In: Ga: Zn = 1: 3: 2. None of the samples showed any movement of oxygen into the tantalum nitride film, and showed a behavior different from that of the tungsten film shown in FIG. Therefore, it can be said that the tantalum nitride film is a film that hardly binds to oxygen or a film that hardly moves oxygen.

FIGS. 19A and 19B show the results of SIMS analysis of a sample manufactured using a titanium nitride film instead of the tungsten film. The titanium nitride film was formed by a reactive sputtering method (DC sputtering method) using titanium as a sputtering target and N ₂ 100% as a film forming gas. The heat treatment was performed under the same four conditions as described above, and a comparison was made with each of the five samples including the sample not subjected to the heat treatment.

FIG. 19A shows SIMS analysis results of a stacked sample of an IGZO film and a titanium nitride film with In: Ga: Zn = 1: 1: 1. None of the samples showed any movement of oxygen into the titanium nitride film, and showed a behavior different from that of the tungsten film shown in FIG. FIG. 19B shows SIMS analysis results of a stacked sample of an IGZO film and a titanium nitride film with In: Ga: Zn = 1: 3: 2. None of the samples showed any movement of oxygen into the titanium nitride film, and exhibited a behavior different from that of the tungsten film shown in FIG.
Therefore, the titanium nitride film can be said to be a film that hardly binds to oxygen or a film that hardly moves oxygen.

Next, the results of investigation by SIMS analysis on the migration of impurities into the IGZO film will be described.

20A and 20B show the results of SIMS analysis of the depth profile of nitrogen before and after the heat treatment by forming a tantalum nitride or titanium nitride film on the IGZO film by a sputtering method. Note that the IGZO film is formed by DC sputtering using In: Ga: Zn = 1: 1: 1 (atomic ratio) as a sputtering target and Ar: O ₂ = 2: 1 (flow ratio) as a deposition gas. Formed. Further, the tantalum nitride film and the titanium nitride film were formed by the above-described manufacturing method. In addition, heat processing was performed on 400 degreeC and the conditions for 1 hour, and each 2 samples including the sample which has not performed heat processing were compared.

As shown in FIGS. 20A and 20B, it was found that no migration of nitrogen into the IGZO film was confirmed in any sample. Therefore, it was found that nitrogen serving as a donor in the IGZO film does not move widely from the tantalum nitride and titanium nitride films into the IGZO film, and thus does not make the channel formation region of the transistor n-type.

FIGS. 21A and 21B are the results of SIMS analysis of the profile in the depth direction of Ta or Ti for the same sample illustrated in FIG. 21A and 21B
As shown in FIG. 3, it was found that Ta or Ti did not move into the IGZO film.
Therefore, it has been found that Ti and Ta, which can be impurities affecting the electric characteristics of the transistor, do not move widely from the tantalum nitride film or the titanium nitride film into the IGZO film.

As described above, a conductive nitride such as tantalum nitride or titanium nitride is a film that does not easily bond to oxygen or a film that does not easily transfer oxygen, and nitrogen and a metal element in the conductive nitride film can be contained in the oxide semiconductor film. It was difficult to move to.

This example can be implemented in combination with any of the other embodiments described in this specification as appropriate.

In this example, a result obtained by forming a conductive film over an oxide semiconductor film, removing the conductive film, and measuring the sheet resistance value of the oxide semiconductor film will be described.

FIG. 22 shows a sample formed by forming an IGZO film using a sputtering method, stacking the IGZO film on the IGZO film, forming a tungsten film or a titanium nitride film by a sputtering method, and then removing the tungsten film or the titanium nitride film. It is the result of having measured the sheet resistance value with respect to the depth which etched the IGZO film | membrane. For comparison, a sample in which a conductive film was not formed over the IGZO film was also produced. Note that the IGZO film has In: Ga: Zn = 1.
: 1: 1 (atomic ratio) as a sputtering target, Ar: O ₂ ( ¹⁸ O) = 2: 1
(Flow rate ratio) was used as a film forming gas and formed by DC sputtering. The tungsten film was formed by DC sputtering using tungsten as a sputtering target and Ar 100% as a film forming gas. The titanium nitride film was formed by a reactive sputtering method (DC sputtering method) using titanium as a sputtering target and N ₂ 100% as a film forming gas. Hydrogen peroxide water was used for etching the tungsten film and the titanium nitride film. For the etching of the IGZO film, a mixed aqueous solution of hydrogen peroxide and ammonia was used. The etching depth of the IGZO film was determined from the thickness of the remaining film measured using spectroscopic ellipsometry before and after etching.

As shown in FIG. 22, in the sample in which the tungsten film is formed on the IGZO film, the IGZ
It was confirmed that the resistance was reduced from the surface of the O film to a depth of about 5 nm. This is IGZ
A low-resistance mixed layer of IGZO and tungsten is formed in the vicinity of the surface of the O film, or oxygen in the IGZO film moves into the tungsten film so that it becomes n-type due to oxygen vacancies in the vicinity of the surface of the IGZO film. This suggests that a region has been formed.

On the other hand, in the sample in which titanium nitride was formed on the IGZO film and the sample in which the conductive film was not formed, the resistance reduction of the IGZO film could not be confirmed. This suggests that elements constituting titanium nitride are difficult to move into the IGZO film, or that oxygen in the IGZO film is difficult to move to the titanium nitride film.

FIG. 23A illustrates a case where an IGZO film is formed by a sputtering method, stacked over the IGZO film to form a tungsten film or a titanium nitride film, and then subjected to heat treatment, and then the tungsten film or the titanium nitride film is subjected to heat treatment. It is the result of having measured the sheet resistance value with respect to the depth which etched the IGZO film | membrane about the sample produced by removing a film | membrane. Also,
For comparison, a sample in which a conductive film was not formed over the IGZO film was also produced. IGZ
Formation and removal of the O film, tungsten film, and titanium nitride film were performed in the same manner as described above. The heat treatment was performed under the condition of 400 ° C. for 1 hour in an N ₂ atmosphere.

As shown in FIG. 23A, it was confirmed that the resistance of the IGZO film was lowered in any of the samples. Here, it was confirmed that the sample in which the tungsten film was formed on the IGZO film had the lowest resistance near the surface and the lowest resistance. This indicates that the tungsten film is most likely to take up oxygen in the IGZO film. Also IG
The sample in which titanium nitride is formed on the ZO film shows the same behavior as the sample in which the conductive film is not formed on the IGZO film. That is, in the sample in which the tungsten film is formed on the IGZO film, the resistance of the IGZO film is lowered by the movement of oxygen in the IGZO film to the tungsten film, whereas the titanium nitride film is formed on the IGZO film. In the sample, IG
This suggests that oxygen released from the ZO film is released upward through the titanium nitride film. This result is in good agreement with the SIMS analysis result shown in Example 1.

In FIG. 23B, a silicon oxide film is formed by a sputtering method, an IGZO film is formed on the silicon oxide film by a sputtering method, and a tungsten film or a titanium nitride film is formed by stacking the IGZO film by a sputtering method. Then, the sheet resistance value with respect to the depth obtained by etching the IGZO film is measured for a sample manufactured by removing the tungsten film or the titanium nitride film after the heat treatment. For comparison, IG
A sample in which a conductive film was not formed over the ZO film was also produced. The silicon oxide film was formed by a reactive sputtering method (DC sputtering method) using silicon as a sputtering target and O ₂ 100% as a film forming gas. Note that formation and removal of the IGZO film, the tungsten film, and the titanium nitride film were performed in the same manner as described above. The heat treatment is performed at 400 ° C. under a N ₂ atmosphere.
Performed under time conditions.

In FIG. 23B, it was confirmed that the region where the resistance of the IGZO film is reduced is shallower in the thickness direction than the result shown in FIG. This indicates that oxygen is supplied from the silicon oxide film to the IGZO film by the heat treatment, and oxygen vacancies in the IGZO film are reduced, so that the resistance of the IGZO film is increased. Thus, it was found that the thickness of the region of the IGZO film where the resistance is reduced can be controlled by using a film capable of releasing oxygen below the IGZO film.

As described above, it has been confirmed that by forming a conductive film that easily takes in oxygen, such as a tungsten film, in contact with the IGZO film, a region in the vicinity of the IGZO film in contact with the conductive film can be reduced in resistance. Furthermore, it has been confirmed that by performing the heat treatment, the region of the IGZO film where the resistance is reduced can be expanded in the depth direction. It was also found that the thickness of the region where the resistance is reduced can be controlled by forming a film capable of releasing oxygen in the vicinity of the IGZO film.

This example can be implemented in combination with any of the other embodiments described in this specification as appropriate.

102 substrate 104 oxide insulating film 105 region 106 oxide semiconductor layer 106a n-type region 108 first conductive film 108a first source electrode layer 108b first drain electrode layer 110 second conductive film 110a second source Electrode layer 110b Second drain electrode layer 112 Gate insulating film 113 Third conductive film 114 Gate electrode layer 116 Protective insulating film 150 Transistor 152 Transistor 154 Transistor 156 Transistor 158 Transistor 168a First source electrode layer 168b First drain electrode Layer 174 gate electrode layer 178a first source electrode layer 178b first drain electrode layer 180a second source electrode layer 180b second drain electrode layer 190a resist mask 190b resist mask 192 resist mask 194a resist mask 194b Resist mask 196 Resist mask 500 Microcomputer 501 DC power supply 502 Bus line 503 Power gate controller 504 Power gate 505 CPU
506 Volatile storage unit 507 Nonvolatile storage unit 508 Interface 509 Detection unit 511 Optical sensor 512 Amplifier 513 AD converter 530 Light emitting element 601 Semiconductor substrate 603 Element isolation region 604 Gate electrode layer 606 Oxide semiconductor layer 607 Gate insulating film 609 Gate electrode layer 611a Impurity region 611b Impurity region 612 Gate insulating film 615 Insulating film 616a First source electrode layer 616b First drain electrode layer 616c Electrode 617 Insulating film 618 Protective insulating film 619a Contact plug 619b Contact plug 620 Insulating film 621 Insulating film 622 Insulating Film 623a Wiring 623b Wiring 624 Electrode 625 Oxide insulating film 626a Second source electrode layer 626b Second drain electrode layer 626c Electrode 645 Insulating film 646 Insulating film 649 Wiring 65 Wiring 660 semiconductor film 714 photoelectric conversion element 717 transistor 719 transistor 1141 switching element 1142 memory cells 1143 memory cell group 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
3000 Substrate 3106 Element isolation insulating layer 3150 Electrode 3200 Transistor 3202 Transistor 3204 Capacitor element 3220 Oxide insulating film 4162 Transistor 4250 Memory cell 4251 Memory cell array 4251a Memory cell array 4251b Memory cell array 4253 Peripheral circuit 4254 Capacitor element 8100 Alarm device 8101 Microcomputer 8200 Indoor unit 8201 Housing 8202 Air outlet 8203 CPU
8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigeration room door 8303 Freezing room door 8304 CPU
9700 Electric vehicle 9701 Secondary battery 9702 Control circuit 9703 Driving device 9704 Processing device

Claims (2)

An oxide insulating film;
An oxide semiconductor layer on the oxide insulating film;
A first source electrode layer in contact with the oxide semiconductor layer;
A first drain electrode layer in contact with the oxide semiconductor layer;
A second source electrode layer on the first source electrode layer;
A second drain electrode layer on the first drain electrode layer;
A gate insulating film on the second source electrode layer and on the second drain electrode layer;
A gate electrode layer on the gate insulating film,
Wherein the oxide semiconductor layer, a first region in contact with the first source electrode layer, and a second region in contact with the second source electrode layer, and a third region in contact with the gate insulating film, wherein A fourth region in contact with the first drain electrode layer; and a fifth region in contact with the second drain electrode layer ;
The film thickness of the first region is larger than the film thickness of the second region,
The film thickness of the second region is larger than the film thickness of the third region,
The oxide insulating film may have a region in contact with the gate insulating film,
The gate electrode layer overlaps the second source electrode and does not overlap the first source electrode;
The semiconductor device , wherein the gate electrode layer overlaps with the second drain electrode and does not overlap with the first drain electrode . An oxide insulating film;
An oxide semiconductor layer on the oxide insulating film;
A first source electrode layer in contact with the oxide semiconductor layer;
A first drain electrode layer in contact with the oxide semiconductor layer;
A second source electrode layer on the first source electrode layer;
A second drain electrode layer on the first drain electrode layer;
A gate insulating film on the second source electrode layer and on the second drain electrode layer;
A gate electrode layer on the gate insulating film,
The oxide semiconductor layer includes: a first region in contact with the first source electrode layer; a second region in contact with the second source electrode layer; a third region in contact with the gate insulating film; A fourth region in contact with the first drain electrode layer; and a fifth region in contact with the second drain electrode layer;
The film thickness of the first region is larger than the film thickness of the second region,
The film thickness of the second region is larger than the film thickness of the third region,
The oxide insulating film has a region in contact with the gate insulating film,
The gate electrode layer overlaps the second source electrode and does not overlap the first source electrode;
The gate electrode layer overlaps the second drain electrode and does not overlap the first drain electrode;
The second source electrode layer and the second drain electrode layer each include a conductive nitride.