JP6340993B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  In a semiconductor device that can generate surge current due to ESD (Electro-Static Discharge) etc., there is a concern about deterioration or destruction of elements due to instantaneous large current flowing in the device or malfunction of the semiconductor device. Is done. Therefore, this type of semiconductor device is required to have a configuration resistant to surge current.

JP-A-2005-332891

  For example, a technique as disclosed in Patent Document 1 has been proposed as a technique relating to surge countermeasures. In the semiconductor device disclosed in Patent Document 1, the source layer 24 and the drain layer 22 are alternately formed in the element region EA in the semiconductor substrate 11, and between the alternately formed source layer 24 and drain layer 22. Each of the channels 23 is formed, and the outer periphery of the element region EA is terminated by the drain layer 22. With such a configuration, concentration of current near the outer periphery of the element region is relaxed, and resistance to surges caused by ESD or the like is increased.

  By the way, in the configuration of such a semiconductor device, as a method for improving the resistance against surge current, for example, the concentration of the buffer layer (n-type conductive layer) injected into the drift layer 21 is increased or the drift layer 21 is increased. For example, a method of increasing the concentration of the buffer layer (n-type conductive layer) injected into the substrate can be considered. However, simply increasing the concentration of the buffer layer causes a decrease in static withstand voltage, and merely increasing the drift length causes an increase in on-resistance.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a configuration that can effectively increase the withstand capability against a surge current while suppressing a decrease in electrical characteristics.

In order to achieve the above object, the invention of claim 1
A semiconductor substrate (10) having an upper surface formed on one side in the plate thickness direction and a first semiconductor region (11b) of the first conductivity type formed on at least the upper surface side;
A second semiconductor region (23) of a second conductivity type disposed on the upper surface side of the semiconductor substrate and configured as a channel region;
A third third layer of the first conductivity type formed at a position away from the first semiconductor region on the upper surface side of the semiconductor substrate and disposed with the second semiconductor region interposed between the first semiconductor region and the second semiconductor region; A semiconductor region (24);
A fourth semiconductor region (22) of the first conductivity type formed at a position away from the second semiconductor region and the third semiconductor region on the upper surface side of the semiconductor substrate;
A first insulator layer (32) disposed at a position covering at least the second semiconductor region above the semiconductor substrate;
A gate electrode layer (40) disposed at least above the second semiconductor region in a configuration covering the upper side of the first insulator layer; and
A second insulator layer (34, 95) formed between the second semiconductor region and the fourth semiconductor region on the upper surface side of the semiconductor substrate;
A dielectric layer (50) made of a dielectric material formed inside the semiconductor substrate at a position below the second insulator layer and away from the second insulator layer ;
In a predetermined lateral direction in which the third semiconductor region and the fourth semiconductor region face each other, an end portion of the dielectric layer on the third semiconductor region side is closer to the fourth semiconductor region side than the second semiconductor region. are arranged, characterized in Rukoto.

According to the first aspect of the present invention, the second conductivity type second semiconductor region configured as the channel region is disposed on the upper surface side of the semiconductor substrate, and the first conductivity type is disposed on one side of the second semiconductor region (channel region). A first semiconductor region and a fourth semiconductor region are provided, and a third semiconductor region of the first conductivity type is provided on the other side. A gate electrode layer is disposed above the second semiconductor region (channel region) via a first insulator layer. With such a configuration, it is possible to realize a MOS structure that can switch between the third semiconductor region and the fourth semiconductor region between an energized state and a non-energized state.
A second insulator layer is formed between the second semiconductor region and the fourth semiconductor region on the upper surface side of the semiconductor substrate, and is located below the second insulator layer and away from the second insulator layer. At the position, a dielectric layer made of a dielectric material is disposed. When the dielectric layer is present in this manner, potential concentration can be caused in the vicinity of the second insulator layer when a surge current is generated, and the potential from the second insulating layer to the second semiconductor region (channel region). The distribution can be steeper. In addition, since the current density is increased by locally generating a steep potential in this way and the parasitic bipolar operation is easily generated in the vicinity of the second semiconductor region, the surge current that flows can be efficiently extracted. In addition, the resistance to surge current can be increased more effectively.

FIG. 1 is a schematic cross-sectional view schematically illustrating the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view schematically showing a part of the semiconductor device of FIG. FIG. 3 is an enlarged schematic cross-sectional view showing a part of the semiconductor device of FIG. FIG. 4 is an explanatory diagram schematically illustrating a configuration for allowing surge current to flow into the semiconductor device of FIG. FIG. 5 is a diagram showing a potential distribution and a current density distribution when a surge current flows, and FIG. 5A is a diagram relating to a conventional semiconductor device having an LDMOS structure without a dielectric layer. FIG. 2B is a diagram related to the semiconductor device of FIG. 1. FIG. 6 is an explanatory diagram schematically illustrating a parasitic bipolar transistor formed in the semiconductor device of FIG. 7 is a diagram showing a state when a surge current flows into the semiconductor device of FIG. 1 and the parasitic bipolar transistor operates, and FIG. 7A is a diagram showing an electron current density distribution. (B) is a diagram showing a hole current density distribution. FIG. 8 is a diagram showing the dependency of the ESD resistance on the length of the dielectric layer when the depth of the dielectric layer is 0.8 μm in the semiconductor device of FIG. ) Is a diagram relating to a configuration in which the lateral distances from the end of the STI oxide film of the dielectric layer are −0.8 μm, −0.4 μm, and 0 μm, respectively. FIG. 9 is a diagram showing the same contents as FIG. 8, and FIGS. 9A and 9B are diagrams in which the lateral distance from the end of the STI oxide film of the dielectric layer is 0.4 μm, respectively. FIG. FIG. 10 is a diagram showing the dependency of ESD tolerance on the length of the dielectric layer when the depth of the dielectric layer is 1.3 μm in the semiconductor device of FIG. ) Is a diagram relating to a configuration in which the lateral distances from the end of the STI oxide film of the dielectric layer are −0.8 μm, −0.4 μm, and 0 μm, respectively. FIG. 11 is a diagram showing the same contents as FIG. 10, and FIGS. 11A and 11B show that the lateral distance from the end of the STI oxide film of the dielectric layer is 0.4 μm, respectively. FIG. FIG. 12 is a diagram showing the dependency of the ESD resistance on the length of the dielectric layer when the depth of the dielectric layer is 1.8 μm in the semiconductor device of FIG. ) Is a diagram relating to a configuration in which the lateral distances from the end of the STI oxide film of the dielectric layer are −0.8 μm, −0.4 μm, and 0 μm, respectively. FIG. 13 is a diagram showing the same contents as FIG. 12, and FIGS. 13A and 13B show that the lateral distance from the end of the STI oxide film of the dielectric layer is 0.4 μm, respectively. FIG. FIG. 14 is a diagram illustrating the thickness dependence of the ESD resistance of the dielectric layer when the depth of the dielectric layer is 0.8 μm in the semiconductor device of FIG. ) Is a diagram relating to a configuration in which the lateral distances from the end of the STI oxide film of the dielectric layer are −0.8 μm, −0.4 μm, and 0 μm, respectively. FIG. 15 is a diagram showing the same contents as FIG. 14, and FIGS. 15A and 15B are diagrams in which the lateral distance from the end of the STI oxide film of the dielectric layer is 0.4 μm, respectively. FIG. FIG. 16 is a diagram showing the dependence of the ESD tolerance on the thickness of the dielectric layer when the depth of the dielectric layer is 1.3 μm in the semiconductor device of FIG. ) Is a diagram relating to a configuration in which the lateral distances from the end of the STI oxide film of the dielectric layer are −0.8 μm, −0.4 μm, and 0 μm, respectively. FIG. 17 is a diagram showing the same contents as FIG. 16, and FIGS. 17A and 17B are diagrams in which the lateral distance from the end of the STI oxide film of the dielectric layer is 0.4 μm, respectively. FIG. FIG. 18 is a diagram showing the dependence of ESD resistance on the thickness of the dielectric layer when the depth of the dielectric layer is 1.8 μm in the semiconductor device of FIG. ) Is a diagram relating to a configuration in which the lateral distances from the end of the STI oxide film of the dielectric layer are −0.8 μm, −0.4 μm, and 0 μm, respectively. FIG. 19 is a diagram showing the same contents as FIG. 18. FIGS. 19A and 19B are diagrams in which the lateral distance from the end of the STI oxide film of the dielectric layer is 0.4 μm, respectively. FIG. 20 is a diagram showing the lateral distance dependency of the ESD tolerance from the end portion of the STI oxide film in the semiconductor device of FIG. 1, and FIGS. 20A to 20C are diagrams showing the arrangement of the dielectric layers, respectively. It is a figure regarding the structure whose depth is 0.8 micrometer, 0.9 micrometer, and 1.3 micrometer. FIG. 21 is a diagram showing the same contents as FIG. 20, and FIGS. 21A and 21B are diagrams regarding a configuration in which the arrangement depth of the dielectric layers is 1.5 μm and 1.8 μm, respectively. . FIG. 22 is an explanatory diagram for explaining each step sequentially performed in a part of the steps of manufacturing the semiconductor device according to the present invention. FIG. 23 is an explanatory diagram for explaining each step sequentially performed in a step subsequent to the step of FIG. FIG. 24 is an explanatory diagram for explaining each step sequentially performed in a step subsequent to the step of FIG. FIG. 25 is an explanatory diagram for explaining each step sequentially performed in a step subsequent to the step of FIG. FIG. 26 is a schematic cross-sectional view schematically illustrating a semiconductor device according to a first modification of the first embodiment. 27 is an enlarged schematic cross-sectional view showing a part of the semiconductor device of FIG. FIG. 28 is a schematic cross-sectional view schematically illustrating the semiconductor device according to the second embodiment. 29 is an enlarged schematic cross-sectional view showing a part of the semiconductor device of FIG. FIG. 30A is a diagram showing equipotential lines and current density in the first embodiment in which the dielectric constant of the dielectric layer 50 is 3.9, and FIG. It is a figure which shows the equipotential line and current density in 3rd Embodiment whose rate is 5000. FIG. 31 is a diagram showing the dependence of ESD tolerance on the distance between the STI oxide film end-dielectric layer when the dielectric constant is 3.9, 1000, and 5000 in the semiconductor device of FIG.

[First embodiment]
Hereinafter, a first embodiment embodying the present invention will be described with reference to the drawings.
(Configuration of semiconductor device)
First, the configuration of a semiconductor device 1 according to a representative example of the first embodiment will be described with reference to FIG. As shown in FIGS. 1 to 3, the semiconductor device 1 according to the present embodiment includes an LDMOS (Laterally Diffused Metal Oxide Semiconductor) 5 and is formed using an SOI (Silicon On Insulator) substrate 10. . FIG. 1 schematically shows a cross section of the semiconductor device 1 including a wiring structure provided in the semiconductor device 1, and FIG. 2 schematically shows an enlarged part of the cross section of FIG. . FIG. 3 schematically shows an enlarged cross section (portion surrounded by an alternate long and short dash line) in the vicinity of the surface layer portion of the SOI substrate 10 in the semiconductor device 1 shown in FIGS. 1 and 2. 2 and 3, the region above the gate electrode layer 40 is omitted. 1 to 3 schematically show only a part of the semiconductor device 1, the semiconductor device 1 is formed with one or a plurality of LDMOSs 5 as shown in FIGS. 1 to 3. Other elements may be formed or may not be formed.

  In this configuration, as shown in FIGS. 1 to 3, the thickness direction (thickness direction) of the SOI substrate 10 is the vertical direction. Of the plate surfaces formed on both sides of the SOI substrate 10 in the plate thickness direction, the plate surface on the side where the LDMOS 5 is formed is the upper surface 10a (front surface), and the plate surface opposite to the upper surface 10a is the lower surface (back surface). ). Therefore, in the plate thickness direction (thickness direction) of the SOI substrate 10, the side on which the LDMOS 5 is formed is the upper side, and the opposite side is the lower side. Further, the predetermined direction orthogonal to the vertical direction is the horizontal direction (left-right direction). In the example shown in FIG. 1 and the like, the direction in which the N + source region 24 and the N + drain region 22 are arranged is the horizontal direction (left-right direction). In the following description, the N + source region 24 side is the left side, and the N + drain region 22 side is the right side. In this configuration, the N conductivity type is the first conductivity type, and the P conductivity type is the second conductivity type.

Here, the semiconductor device 1 will be described in more detail.
As shown in FIGS. 1 to 3, the semiconductor device 1 has an upper surface 10 a on one side in the thickness direction, and at least an N conductivity type (first conductivity type) first semiconductor region (specifically, at least on the upper surface 10 a side). Includes an SOI substrate 10 in which an N − type semiconductor layer 11 b corresponds to a first semiconductor region). An LDMOS 5 is formed on the SOI substrate 10.

As shown in FIGS. 1 and 2, the SOI substrate 10 has a configuration in which an SOI layer 11 made of N-type silicon and a P-type support substrate 12 are bonded via a buried oxide film 13. . In this configuration, the SOI substrate 10 corresponds to an example of a “semiconductor substrate”. The SOI layer 11 is arranged as an N-type silicon layer on the upper surface side (upper side in FIGS. 1 to 3) of the SOI substrate 10, and the silicon substrate bonded to the support substrate 12 is polished to a predetermined thickness. Or by depositing silicon on the support substrate 12. The SOI layer 11 has a thickness of 5.0 μm, for example, and the buried oxide film 13 has a thickness of 2.5 μm, for example. In addition, a plurality of trench isolation portions 14 as shown in FIG. 1 are formed in the SOI layer 11, and the SOI layer 11 is partitioned into a plurality of regions by the trench isolation portions 14 so that elements can be separated. It has been. Each trench isolation portion 14 includes, for example, a trench 14a (see FIG. 22A) that reaches the buried oxide film 13 from the surface of the SOI layer 11, and a buried film 14b that is buried so as to fill the trench (for example, A multiple trench is formed by an oxide film such as SiO ₂ (see FIG. 22A).

The SOI layer 11 is configured as an N-conductivity type semiconductor layer, and an N-type semiconductor layer (buried layer) 11a and an N− type semiconductor layer (epitaxial layer) 11b having a lower concentration than the N-type semiconductor layer 11a are sequentially stacked. It has a structured. For example, the N − type semiconductor layer 11 b is configured by using, for example, arsenic as a dopant and having a carrier peak concentration of about 1.0 × 10 ¹⁵ cm ⁻³ . The N − type semiconductor layer 11b corresponds to an example of “first semiconductor region”.

  The SOI substrate 10 has an upper surface 10a on one side in the plate thickness direction and a lower surface (back surface) on the other side (illustration of the lower surface is omitted in FIG. 1 and the like). In the present configuration, the upper interface (boundary surface between the SOI substrate 10 and other regions other than the SOI substrate 10) is the upper surface 10a, and the lower interface (SOI substrate) in the SOI substrate 10 is used. 10 and a boundary surface between the region other than the SOI substrate 10) is a lower surface.

  A P-type channel region 23 of the P conductivity type (second conductivity type) configured as a channel region is formed at a position adjacent to the N − type semiconductor layer 11b on the upper surface side of the SOI substrate 10 configured as described above. . Further, the P-type channel region 23 is interposed between the SOI substrate 10 and the N-type semiconductor layer 11b at a position separated from the N-type semiconductor layer 11b and adjacent to the P-type channel region 23 on the upper surface 10a side. An N + source region 24 of N conductivity type (first conductivity type) is arranged in this manner. Further, an N conductivity type (first conductivity type) N + drain region 22 is formed at a position away from the P type channel region 23 and the N + source region 24 on the upper surface side of the SOI substrate 10. An N well region 21 having a higher carrier concentration than that of the N − type semiconductor layer 11 b is provided at a position laterally separated from the P type channel region 23 on the upper surface 10 a side of the SOI substrate 10. The N + drain region 22 and the STI oxide film 34 are disposed on the upper end side of the N well region 21, and the N + drain region 22 is surrounded by the N well region 21.

The N + source region 24 and the N + drain region 22 use, for example, arsenic as a dopant, have a carrier concentration peak concentration of, for example, 3.0 × 10 ²⁰ cm ⁻³ , and an upper and lower thickness of, for example, 0.25 μm. Yes. The P-type channel region 23 uses, for example, boron as a dopant, has a carrier peak concentration of, for example, 5.0 × 10 ¹⁷ cm ⁻³ , and an upper and lower thickness of, for example, 1.15 μm. The N well region 21 uses, for example, phosphorus as a dopant, has a carrier peak concentration of, for example, 5.0 × 10 ¹⁷ cm ⁻³ , and an upper and lower thickness of 1.7 μm.

  In this configuration, the N− type semiconductor layer 11b corresponds to an example of “first semiconductor region”, the P type channel region 23 corresponds to an example of “second semiconductor region”, and the N + source region 24 corresponds to “first semiconductor region”. The N + drain region 22 corresponds to an example of “fourth semiconductor region”.

  Further, in this configuration, the width indicated by W1 in FIG. 3 (that is, the width in the lateral direction (left-right direction) of the P-type channel region 23 at the position of the upper surface 10a of the SOI substrate 10) is the channel length. In the example shown in FIG. 3 and the like, the channel length W1 is, for example, 0.54 μm. In this configuration, the width of W2 in FIG. 3 (that is, the region of the SOI layer 11 (accumulation region) sandwiched between the P-type channel region 23 and the STI oxide film 34 at the position of the upper surface 10a of the SOI substrate 10). The width in the horizontal direction (left-right direction) is the accumulation length. In the example shown in FIG. 3 and the like, the accumulation length W2 is, for example, 1.0 μm. In FIG. 3, the position of the one-dot chain line indicated by reference numeral G conceptually indicates the position of the left end portion (end portion on the P-type channel region 23 side in the lateral direction) of the STI oxide film 34.

As shown in FIGS. 1 to 3, a gate insulating film 32 is disposed at a position covering at least the P-type channel region 23 above the SOI substrate 10. The gate insulating film 32 is made of an insulating material such as SiO _2, and is formed in a region between the N + source region 24 and the N + drain region 22 in the SOI substrate 10 as shown in FIGS. Yes. More specifically, the gate insulating film 32 is arranged so as to straddle the lateral direction so as to cover the entire region between the N + source region 24 and the STI oxide film 34. The gate insulating film 32 is configured, for example, as a PSG (Phosphorous Silicate Glass) film, uses phosphorus as a dopant, and has a carrier peak concentration of, for example, 5.0 × 10 ¹⁹ cm ⁻³ . The gate insulating film 32 corresponds to an example of a “first insulator layer”.

As shown in FIGS. 1 to 3, an STI (Shallow Trench Isolation) oxide film 34 is continuous with the gate insulating film 32 between the P-type channel region 23 and the N + drain region 22 on the upper surface 10 a side of the SOI substrate 10. It is formed to do. The STI oxide film 34 is disposed on the right side (that is, on the N + drain region 22 side) of the P-type channel region 23 and the accumulation region in the lateral direction, and on the left side of the N + drain region 22 (on the P-type channel region 23 side). ). The STI oxide film 34 is made of, for example, an insulating material such as SiO _2, and the length W3 (see FIG. 3) in the left-right direction on the upper end surface is 1.53 μm, for example. As shown in FIG. 1, on the upper surface side of the SOI substrate 10, on the right side of the N + drain region 22 (on the side opposite to the STI oxide film 34 in the lateral direction), the STI oxide having the same configuration as the STI oxide film 34 is provided. A film 35 is formed, and the above-described N well region 21 is disposed so as to straddle both the STI oxide films 34 and 35 and the N + drain region 22. The STI oxide film 34 corresponds to an example of a “second insulator layer”.

  The gate electrode layer 40 is disposed in the upper region of the P-type channel region 23 so as to cover the upper side of the gate insulating film 32 thus configured. The gate electrode layer 40 is formed on the top surfaces of the gate insulating film 32 and the STI oxide film 34. In the example shown in FIGS. 1 to 3 and the like, the gate electrode layer 40 is arranged so as to cover the entire region of the gate insulating film 32 in the lateral direction. ing. The gate electrode layer 40 is made of a conductive material such as aluminum or polysilicon.

  Further, the semiconductor device 1 is provided with a multilayer structure as shown in FIG. In the example of FIG. 1, an insulating film 37 configured as, for example, a PSG film is disposed above the SOI substrate 10 so as to cover the gate electrode layer 40, the STI oxide films 34 and 35, and the like. An insulating film 38 configured as, for example, a PSG film is stacked on the insulating film 37, and an insulating film 39 configured as, for example, a silicon nitride (SiN) film is stacked on the insulating film 38. Has been. In the region where the insulating films 37, 38 and 39 are laminated, a conductive layer (wiring layer) described later is formed in a multilayer wiring structure.

  As shown in FIG. 1, a first wiring layer 61a is formed on the N + source region 24 so as to penetrate the insulating film 37, and functions as a source electrode. A first wiring layer 61 b is formed on the gate electrode layer 40 so as to penetrate the insulating film 37. A first wiring layer 61c is formed on the N + drain region 22 so as to penetrate the insulating film 37, and functions as a drain electrode. Further, first vias 71a to 71c are formed on the first wiring layers 61a to 61c, respectively, and second wiring layers 62a to 62c are formed on the first vias 71a to 71c, respectively. Yes. Further, second vias 72a and 72c are respectively formed on the second wiring layers 62a and 62c, and third wiring layers 63a and 63c are respectively formed on the second vias 72a and 72c. . In addition, third vias 73a and 73c are formed on the third wiring layers 63a and 63c, respectively, and fourth wiring layers 64a and 64c are formed on the third vias 73a and 73c and on the insulating film 39, respectively. Is formed. The first wiring layers 61a to 61c, the second wiring layers 62a to 62c, the third wiring layers 63a and 63c, and the fourth wiring layers 64a and 64c are made of a known conductive material such as aluminum. The first vias 71a to 71c, the second vias 72a and 72c, and the third vias 73a and 73c are made of a known conductive material such as copper.

  The LDMOS 5 configured as described above is provided with a dielectric layer 50 made of a dielectric material on the lower side of the STI oxide film 34 inside the SOI substrate 10 and at a position away from the STI oxide film 34. Improvement of the tolerance is achieved. In this configuration, on the upper surface side of the SOI substrate 10, the P-type channel region 23, the N + drain region 22, the STI oxide film 34 and the like are in a predetermined front-rear direction (specifically, the plate thickness direction (vertical direction) and It extends in the longitudinal direction in a direction orthogonal to the lateral direction (left-right direction). The dielectric layer 50 is, for example, disposed in the longitudinal direction along the longitudinal direction of the STI oxide film 34 on the lower side of the STI oxide film 34 thus configured in the longitudinal direction. In the region where the P-type channel region 23, the N + drain region 22, the STI oxide film 34, etc. are arranged in the longitudinal direction in the front-rear direction, the P-type channel region 23 at a cut surface cut in parallel with the vertical direction and the horizontal direction. The structures of the N + drain region 22, the STI oxide film 34, the dielectric layer 50, etc. are the same as those shown in FIGS.

The dielectric layer 50 is made of a known dielectric material such as SiO ₂ . In the following, the dielectric layer 50 configured as SiO ₂ will be described as a representative example, but the dielectric layer 50 may be configured by other known insulating materials. It is desirable that at least a part of the dielectric layer 50 is disposed in a region immediately below the STI oxide film 34 inside the SOI substrate 10. Further, the dielectric layer 50 has an end portion 50a on the N + source region 24 side in the lateral direction (a direction perpendicular to the vertical direction and a predetermined direction in which the N + source region 24 and the N + drain region 22 face each other) (FIG. 1). It is desirable that the left end portion indicated by the symbol etc. is disposed closer to the N + drain region 22 side than the P-type channel region 23 (that is, the right side indicated in FIG. Further, in this lateral direction, the dielectric layer 50 has an end portion 50b (right end portion shown in FIG. 1 etc.) on the N + drain region 22 side that is N + more than an end portion 34b on the N + drain region 22 side in the STI oxide film 34. It is desirable to arrange on the source region 24 side (that is, the left side shown in FIG. 1 and the like). In addition, the upper end portion 50 c of the dielectric layer 50 is desirably disposed above the lower end portion 23 a of the P-type channel region 23 in the thickness direction (vertical direction) of the SOI substrate 10. 1 to 3 show an example satisfying all of these desirable conditions. In this example, a structure in which the entire dielectric layer 50 is arranged in a region immediately below the STI oxide film 34 in the lateral direction (left-right direction) is shown. It has become. That is, the left end 50 a of the dielectric layer 50 is disposed on the right side of the left end 34 a of the STI oxide film 34, and the right end 50 b of the dielectric layer 50 is the right end of the STI oxide film 34. It is arranged on the left side of 34b.

  The dielectric layer 50 shown in FIGS. 1 to 3 is merely an example. If the dielectric layer 50 is located below the STI oxide film 34 and away from the STI oxide film 34 inside the SOI substrate 10, The shape and arrangement can be changed variously. In the following description, as shown in FIG. 3, the distance in the horizontal direction (left-right direction) from the left end portion 34a of the STI oxide film 34 to the left end portion 50a of the dielectric layer 50 (that is, in the horizontal direction) The distance from the position of the line G shown in FIG. 1 to the position of the left end portion 50a of the dielectric layer 50 is defined as B1. This distance B1 is negative to the absolute value of the distance in the lateral direction (left and right direction) when the left end 50a of the dielectric layer 50 is located on the left side of the left end 34a of the STI oxide film 34. (That is, in this case, the distance B1 is a negative value). The depth of the dielectric layer 50 (specifically, the vertical distance from the lower end 34c of the STI oxide film 34 to the upper end 50c of the dielectric layer 50) is D1. Further, the length in the horizontal direction (left-right direction) of the dielectric layer 50 (specifically, the length in the horizontal direction from the left end 50a to the right end 50b of the dielectric layer 50) is L1. Furthermore, the thickness in the plate thickness direction (vertical direction) of the dielectric layer 50 (specifically, the vertical length from the upper end 50c to the lower end 50d of the dielectric layer 50) is defined as T1. .

  As a desirable example when the dielectric layer 50 is provided, a lateral distance B1 from the end portion 34a of the STI oxide film 34 to the end portion 50a of the dielectric layer 50 is, for example, 0.4 μm. The arrangement depth D1 is, for example, 0.8 μm, the length L1 of the dielectric layer 50 is, for example, 0.1 μm, the thickness T1 of the dielectric layer 50 is, for example, 0.2 μm, and the dielectric of the dielectric layer 50 An example in which the rate ε is 3.9, for example. Further, the present invention is not limited to this example, and any of the values of distance B1, depth D1, length L1, thickness T1, and dielectric constant ε can be changed variously.

(Operation of semiconductor device)
The LDMOS 5 configured in this way normally operates in the same manner as a known MOSFET. Specifically, when a predetermined voltage is applied to the gate electrode layer 40, a channel is generated in the P-type channel region 23, and the source and drain are energized. Further, the application of the gate voltage to the gate electrode layer 40 is canceled, so that the source and drain are switched to a non-energized state. Normally, it functions as a switching element in this way.

  On the other hand, when a surge current flows in due to ESD (Electro-Static Discharge) or the like, the operation is performed so that the surge current can be efficiently removed. As described above, in the LDMOS 5, the STI oxide film 34 is formed between the P-type channel region 23 and the N + drain region 22 on the upper surface 10 a side of the SOI substrate 10. A dielectric layer 50 made of a dielectric material is disposed at a position away from the film 34. When the dielectric layer 50 is thus present, when a surge current flows, the vicinity of the end of the STI oxide film 34 (specifically, the end on the accumulation region side (the lower left end) of the lower end 34c In the vicinity of the portion 34e), the electric field can be locally increased and potential concentration can be caused (see FIG. 5B: described later). As a result, the potential distribution from the vicinity of the lower left end 34e of the STI oxide film 34 to the P-type channel region 23 can be made steeper. In addition, the avalanche phenomenon can be actively generated by generating a steep potential gradient locally and increasing the current density in this way, thereby performing a parasitic bipolar operation in the vicinity of the P-type channel region 23. Can be induced. As described above, since the surge current flowing in by reducing the resistance in the element when the surge current is generated can be efficiently removed, the tolerance to the surge current can be more effectively increased. Also, with this configuration, ESD resistance can be increased without taking measures such as increasing the concentration of the buffer layer or increasing the drift length, so that the decrease in static withstand voltage and the increase in on-resistance are suppressed. The ESD tolerance can be improved.

  Here, simulation results when a surge current flows in the semiconductor device 1 having the structure shown in FIGS. 1 to 3 will be described with reference to FIGS. 4 shows a circuit configuration for performing a test on the LDMOS 5 shown in FIG. 3 and the like. One end of the resistor R1 is connected to the N + drain region 22 of the LDMOS 5, and one end of the switch SW2 is connected to the other end of the resistor R1. Is connected. Further, one end of the capacitor C1 and one end of the switch SW1 are connected to the other end of the switch SW2. In addition, the positive electrode of the power source V1 is connected to the other end of the switch SW1, and the negative electrode of the power source V1 and the ground are connected to the other end of the capacitor C1 and grounded. The capacity of the capacitor C1 is 330 pF, and the power supply voltage of the power supply V1 is, for example, 15 kV. The gate electrode layer 40 is in an open (open) state, and the N + source region 24 is connected to the ground and grounded.

  In the test circuit shown in FIG. 4, the capacitor C1 is charged by the power source V1 by turning on the switch SW1 and turning off the switch SW2. After the charging is completed, the switch SW1 is turned off and the switch SW2 is turned on, so that the charge accumulated in the capacitor C1 is released, and the capacitor C1 enters the semiconductor device 1 through the N + drain region 22. A large current flows in. FIG. 5B shows the potential distribution and current density distribution in the LDMOS 5 when such a current flows. On the other hand, FIG. 5A shows, as a comparative example, the potential when the same current supply is performed using the test circuit of FIG. 4 with respect to the configuration in which the dielectric layer 50 is omitted from the configuration of FIGS. Distribution and current density distribution are shown. That is, in the configuration in which the dielectric layer 50 is omitted from the configuration of FIG. 4, the switch SW1 is turned on and the switch SW2 is turned off to charge the capacitor C1, and after the charging is completed, the switch SW1 is turned off. FIG. 5A shows a potential distribution and a current density distribution when a large current flows from the capacitor C1 into the semiconductor device 1 through the N + drain region 22 by switching the switch SW2 to the ON state. Show. In FIG. 5, the potential distribution in the SOI substrate 10 is indicated by equipotential lines. In FIG. 5, the current density distribution in the SOI substrate 10 is indicated by the shading of the color, and the lighter the color, the higher the current density.

The LDMOS 105 of the semiconductor device 101 shown in FIG. 5A is the same as the LDMOS 105 of FIG. 4 except that the dielectric layer 50 is omitted. A P-type channel region 123, an N + source region 124, An N + drain region 122 is formed, and a gate insulating film 132 and a gate electrode 140 are formed on the SOI substrate 110. An STI oxide film 134 is formed between the N + source region 124 and the N + drain region 122, and an N well region 121 is formed below the STI oxide film 134. The structure of the SOI substrate 110, the P-type channel region 123, the N + source region 124, the N + drain region 122, the gate insulating film 132, the gate electrode 140, the STI oxide film 134, and the N well region 121 is an LDMOS5 SOI substrate. 10, the P-type channel region 23, the N + source region 24, the N + drain region 22, the gate insulating film 32, the gate electrode layer 40, the STI oxide film 34, and the N well region 21. In the LDMOS 105, the potential distribution and the current density distribution as shown in FIG. 5A are obtained when the current is supplied using the test circuit of FIG. 4, and the avalanche breakdown occurs in the vicinity of the lower left side end portion 134e of the STI oxide film 134. Is generated at 3.5 × 10 ²⁴ cm ⁻³ s ⁻¹ . On the other hand, when the dielectric layer 50 is present in the SOI substrate 10 as shown in FIG. 4, the potential distribution and current density distribution are as shown in FIG. 5B, and the dielectric layer 50 does not exist (FIG. 4). 5 (A)), the electric field strength in the vicinity of the lower left side end 34e of the STI oxide film 34 is increased, and the potential gradient in the vicinity thereof is increased. The rate of occurrence of avalanche breakdown occurring near the lower left end 34e of the STI oxide film 34 is 1.0 × 10 ²⁷ cm ⁻³ s ⁻¹ .

  As shown in FIG. 6, in the semiconductor device 1, an NPN type parasitic bipolar transistor is formed by the N− type semiconductor layer 11 b of the SOI layer 11, the P type channel region 23, and the N + source region 24. In this configuration, since the dielectric layer 50 exists in the SOI substrate 10, the electric field strength near the lower left side end 34 e of the STI oxide film 34 increases when a surge current flows as described above. Avalanche breakdown tends to occur. FIG. 7 is a diagram showing a state when a surge current flows into the semiconductor device 1 and the parasitic bipolar transistor is operated. FIG. 7A is a diagram showing an electron current density distribution, and FIG. ) Is a diagram showing a hole current density distribution. In FIG. 7, the potential distribution in the SOI substrate 10 is indicated by equipotential lines. Also in FIG. 7, the current density distribution in the SOI substrate 10 is indicated by shades of color, and the current density increases as the color is lighter.

  As shown in FIGS. 7A and 7B, when an avalanche breakdown occurs in the vicinity of the lower left side end portion 34e of the STI oxide film 34 and an electron-hole pair is generated, as shown in FIG. Holes (holes) easily move to the base (P-type channel region 23). As described above, the holes generated by the avalanche breakdown move to the base (P-type channel region 23), thereby inducing the operation of the parasitic bipolar transistor. Thereby, collector current flows and surge current can be extracted from the N + source region 24 side.

(Relationship between dielectric layer configuration and ESD tolerance)
Next, the relationship between the configuration of the dielectric layer 50 and the ESD tolerance when the above-described simulation is performed under various conditions will be described using the simulation result data shown in FIGS. 8 to 13 of these drawings are graphs showing the length dependence indicating how much the ESD tolerance of the semiconductor device 1 depends on the length L1 of the dielectric layer 50. The simulation results are shown in a configuration in which the thickness T1 of the film is 0.2 μm and the dielectric constant is 3.9. In each of FIGS. 8 to 13, the ESD tolerance under the condition that the length L1 is 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, and 0.7 μm is shown in each point. Is shown. In each graph, the specific value of the ESD tolerance (magnification) under each condition where the length L1 is 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm is 0. It is shown in the vicinity of each point of .05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, and 0.7 μm.

  8 to 13 showing the length dependence, FIGS. 8 and 9 are simulation results in a configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, and FIGS. 9C and 9B, the horizontal distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm, −0.4 μm, 0 μm, 0.4 μm, respectively. The simulation result in the structure which is 1.2 micrometers is shown.

  As shown in FIGS. 8 and 9, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm to 1 .2 μm and the length L1 of the dielectric layer 50 is in the range of 0.05 μm to 0.7 μm, the ESD tolerance (with respect to the ESD tolerance in the configuration in which the dielectric layer 50 is not provided in the semiconductor device 1) (Expressed by magnification, the same applies hereinafter) is 1.02-1.50, and the effect of improving ESD resistance is obtained. Therefore, under the conditions of FIGS. 8 and 9, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with a configuration included in these ranges. In particular, in the simulation conditions of FIGS. 8 and 9, the ESD tolerance is 1.07 to 1.50 in any case if the length L1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm. If the length L1 of the dielectric layer 50 is in the range of 0.2 μm to 0.7 μm, the effect is enhanced in any case.

  8 and 9, the distance B1 is −0.8 μm, the length L1 of the dielectric layer 50 is 0.7 μm, and the lateral direction from the end 34a of the STI oxide film 34. In the configuration in which the distance B1 is −0.4 μm and the length L1 of the dielectric layer 50 is in the range of 0.2 μm to 0.7 μm, the ESD resistance is in the range of 1.32 to 1.50. A remarkable effect is obtained. Further, the distance B1 is 0 μm and the length L1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm, and the distance B1 is 0.4 μm and the length of the dielectric layer 50 In the configuration in which L1 is in the range of 0.1 μm to 0.7 μm, the ESD tolerance is in the range of 1.47 to 1.50. In this case as well, a remarkable effect is obtained. For this reason, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, it is more desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  8 to 13 showing the length dependence, FIGS. 10 and 11 are simulation results of the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, and FIGS. 11C and 11B, the lateral distances B1 from the end 34a of the STI oxide film 34 are −0.8 μm, −0.4 μm, 0 μm, 0.4 μm, and 1.2 μm, respectively. It is a simulation result of a certain configuration.

  As shown in FIGS. 10 and 11, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm to 1 In the structure in which the thickness L1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm, the ESD resistance can be sufficiently improved. Therefore, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges under these conditions. In particular, under the simulation conditions of FIGS. 10 and 11, the effect is enhanced in any case as long as the length L1 of the dielectric layer 50 is in the range of 0.2 μm to 0.7 μm.

  10 and 11, in the configuration in which the depth D1 is 1.3 μm, in the configuration in which the distance B1 is −0.8 μm and the length L1 is in the range of 0.1 μm to 0.7 μm, The ESD tolerance is in the range of 1.02 to 1.21, and the effect is high. Further, the configuration in which the distance B1 is in the range of −0.4 μm to 0.4 μm and the length L1 is in the range of 0.05 μm to 0.7 μm, and the distance B1 is 1.2 μm and the length L1 is 0. In the configuration in the range of 0.1 μm to 0.7 μm, the ESD tolerance is in the range of 1.02 to 1.27, and the effect is high. Therefore, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges under these conditions.

  Further, as shown in FIGS. 10 and 11, the configuration in which the distance B1 is −0.8 μm and the length L1 is 0.7 μm, and the distance B1 is −0.4 μm and the length L1 is 0.00. In the configuration in the range of 3 μm to 0.7 μm, the ESD tolerance becomes 1.21 to 1.27, and a higher effect is obtained. The distance B1 is 0 μm and the length L1 is in the range of 0.1 μm to 0.7 μm, and the distance B1 is 0.4 μm and the length L1 is in the range of 0.1 μm to 0.7 μm. In a certain configuration, the ESD tolerance is 1.24 to 1.27, and a higher effect is obtained. Therefore, under these conditions, it is more desirable to provide the dielectric layer 50 in the semiconductor device 1 with a configuration included in these ranges.

  8 to 13 showing the length dependency, FIGS. 12 and 13 are simulation results of a configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, and FIGS. C), FIGS. 13A and 13B, the lateral distances B1 from the end 34a of the STI oxide film 34 are −0.8 μm, −0.4 μm, 0 μm, 0.4 μm, and 1.2 μm, respectively. It is a simulation result of a certain configuration.

  As shown in FIGS. 12 and 13, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, the lateral distance B1 from the end portion 34a of the STI oxide film 34 is −0.4 μm to 0. The effect is obtained more in the range of 0.4 μm and the length L1 of the dielectric layer 50 in the range of 0.2 μm to 0.7 μm. Therefore, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges under these conditions.

  12 and FIG. 13, a configuration in which the distance B1 is −0.8 μm and the length L1 is 0.7 μm, and the distance B1 is −0.4 μm and the length L1 is 0.2 μm to In the configuration in the range of 0.7 μm, the ESD tolerance is in the range of 1.02 to 1.06. The distance B1 is 0 μm and the length L1 is in the range of 0.2 μm to 0.7 μm, and the distance B1 is 0.4 μm and the length L1 is in the range of 0.1 μm to 0.7 μm. In some configurations, the ESD tolerance is in the range of 1.03 to 1.06. Therefore, under this condition, it is more desirable to provide the dielectric layer 50 in the semiconductor device 1 with a configuration included in these ranges.

  14 to 19 are graphs showing the thickness dependency indicating how much the ESD tolerance of the semiconductor device 1 depends on the thickness T1 of the dielectric layer 50. FIG. 14 to 19 are simulation results regarding a configuration in which the length L1 of the dielectric layer 50 is 0.2 μm and the dielectric constant is 3.9. Moreover, in each figure of FIGS. 14-19, ESD tolerance on the conditions which made thickness T1 0.05 micrometer, 0.1 micrometer, 0.2 micrometer, 0.3 micrometer, 0.5 micrometer, and 0.7 micrometer is each point. Is shown. In each graph, the specific value of the ESD tolerance (magnification) under each condition where the thickness T1 is 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm is 0. It is shown in the vicinity of each point of .05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, and 0.7 μm.

  14 to 19 showing the thickness dependence, FIGS. 14 and 15 are simulation results of a configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, and FIGS. C), FIGS. 15A and 15B, the lateral distances B1 from the end 34a of the STI oxide film 34 are −0.8 μm, −0.4 μm, 0 μm, 0.4 μm, and 1.2 μm, respectively. It is a simulation result of a certain configuration.

  14 and 15, the effect is obtained in any case as long as the thickness T1 of the dielectric layer 50 is in the range of 0.05 μm to 0.7 μm, and the thickness T1 of the dielectric layer 50 is If it is the range of 0.1 micrometer-0.7 micrometer, an effect will increase in any case. Furthermore, if the thickness T1 is in the range of 0.2 μm to 0.7 μm, a higher effect can be obtained.

  As shown in FIGS. 14 and 15, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm to 1 In the configuration in which the thickness T1 of the dielectric layer 50 is in the range of 0.05 μm to 0.7 μm, the ESD resistance is in the range of 1.02 to 1.50. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  14 and 15, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0 μm, and the thickness T1 of the dielectric layer 50 is 0.2 μm to 0.7 μm. And a configuration in which the lateral distance B1 from the end 34a of the STI oxide film 34 is 0.4 μm and the thickness T1 of the dielectric layer 50 is in the range of 0.2 μm to 0.7 μm. Then, ESD tolerance becomes the range of 1.47-1.50. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  Further, as shown in FIGS. 14 and 15, the lateral distance B1 from the end portion 34a of the STI oxide film 34 is 0.4 μm, and the thickness T1 of the dielectric layer 50 is 0.2 μm to 0.2 mm. In the configuration in the range of 7 μm, the ESD tolerance is 1.50. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, it is even more desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges. .

  14 to 19 showing the thickness dependence, FIGS. 16 and 17 are simulation results of the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, and FIGS. C), FIGS. 17A and 17B, the lateral distances B1 from the end 34a of the STI oxide film 34 are −0.8 μm, −0.4 μm, 0 μm, 0.4 μm, and 1.2 μm, respectively. It is a simulation result of a certain configuration.

  16 and 17, the effect can be obtained in any case as long as the thickness T1 of the dielectric layer 50 is in the range of 0.05 μm to 0.7 μm, and the thickness T1 of the dielectric layer 50 is If it is the range of 0.1 micrometer-0.7 micrometer, an effect will increase in any case. Furthermore, if the thickness T1 is in the range of 0.2 μm to 0.7 μm, a higher effect can be obtained.

  As shown in FIGS. 16 and 17, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm. In the configuration in which the thickness T1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm, the ESD resistance is in the range of 1.01 to 1.02. Further, the lateral distance B1 from the end 34a of the STI oxide film 34 is in the range of −0.4 μm to 0.4 μm, and the thickness T1 of the dielectric layer 50 is in the range of 0.05 μm to 0.7 μm. And a configuration in which the lateral distance B1 from the end 34a of the STI oxide film 34 is 1.2 μm and the thickness T1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm. , ESD tolerance is in the range of 1.02-1.27. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  Also, as shown in FIGS. 16 and 17, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0 μm, and the thickness T1 of the dielectric layer 50 is 0.2 μm to 0.7 μm. And a configuration in which the lateral distance B1 from the end 34a of the STI oxide film 34 is 0.4 μm and the thickness T1 of the dielectric layer 50 is in the range of 0.2 μm to 0.7 μm. Then, ESD tolerance becomes the range of 1.24-1.27. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  Further, as shown in FIGS. 16 and 17, the distance B1 in the lateral direction from the end 34a of the STI oxide film 34 is 0.4 μm, and the thickness T1 of the dielectric layer 50 is 0.2 μm to 0.2 mm. In the configuration in the range of 7 μm, the ESD tolerance is 1.27. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, it is even more desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges. .

  14 to 19 showing the thickness dependence, FIGS. 18 and 19 are simulation results of the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, and FIGS. 19C and 19B, the lateral distances B1 from the end portion 34a of the STI oxide film 34 are −0.8 μm, −0.4 μm, 0 μm, 0.4 μm, and 1.2 μm, respectively. It is a simulation result of a certain configuration.

  As shown in FIGS. 18 and 19, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0 μm to 0.4 μm. The effect is more obtained when the thickness T1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm. Therefore, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges under these conditions.

  As shown in FIGS. 18 and 19, in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0 μm, and the dielectric The structure in which the thickness T1 of the body layer 50 is in the range of 0.1 μm to 0.7 μm, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0.4 μm, and the dielectric layer 50 In the configuration in which the thickness T1 is in the range of 0.1 μm to 0.7 μm, the ESD tolerance is in the range of 1.02 to 1.06. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  As shown in FIGS. 18 and 19, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0 μm, and the thickness T1 of the dielectric layer 50 is 0.2 μm to 0.7 μm. The configuration in the range, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0.4 μm, and the thickness T1 of the dielectric layer 50 is in the range of 0.1 μm to 0.7 μm. Then, the ESD tolerance is in the range of 1.03 to 1.06. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges.

  Further, as shown in FIGS. 18 and 19, the lateral distance B1 from the end 34a of the STI oxide film 34 is 0.4 μm, and the thickness T1 of the dielectric layer 50 is 0.2 μm to 0.2 mm. In the configuration in the range of 7 μm, the ESD tolerance is 1.06. Therefore, in order to improve the ESD tolerance in the configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.8 μm, it is even more desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges. .

  20 and 21 are diagrams showing the dependence of the ESD tolerance of the semiconductor device 1 on the distance B1 in the lateral direction from the end 34a of the STI oxide film 34. FIG. 20 and 21 are diagrams relating to a configuration in which the thickness T1 of the dielectric layer 50 is 0.3 μm, the length L1 is 0.2 μm, and the dielectric constant is 3.9. 20A to 20C and FIGS. 21A and 21B, the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, 0.9 μm, 1.3 μm, 1.5 μm, 1 It is a figure regarding the structure which is .8 μm. In each of FIGS. 20 and 21, the lateral distance B1 from the end 34a of the STI oxide film 34 is −2.4 μm, −2.0 μm, −1.6 μm, −1.2 μm, − Each point shows the ESD tolerance under the conditions of 0.8 μm, −0.4 μm, 0.0 μm, 0.4 μm, 0.8 μm, 1.2 μm, 1.4 μm, and 1.6 μm. In each graph, the distance B1 is −2.4 μm, −2.0 μm, −1.6 μm, −1.2 μm, −0.8 μm, −0.4 μm, 0.0 μm, 0.4 μm, and 0.8 μm. Specific values of ESD tolerance (magnification) under the conditions of 1.2 μm, 1.4 μm, 1.6 μm are −2.4 μm, −2.0 μm, −1.6 μm, −1.2 μm, −0. It is shown near each point of 8 μm, −0.4 μm, 0.0 μm, 0.4 μm, 0.8 μm, 1.2 μm, 1.4 μm, and 1.6 μm.

  As shown in FIGS. 20 and 21, when the thickness T1 is 0.3, the distance L1 is 0.2, and the depth D1 is in the range of 0.8 μm to 1.8 μm, the distance B1 is 0 μm to 1 μm. The effect is obtained in the range of 2 μm. Therefore, it is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the configuration included in these ranges under these conditions. Further, when the depth D1 is in the range of 0.8 μm to 1.3 μm, the effect is obtained when the distance B1 is in the range of −0.8 μm to 1.4 μm, and the range of the effect is widened. In addition, when the depth D1 is in the range of 0.8 μm to 1.3 μm, a more remarkable effect is obtained when the distance B1 is in the range of 0 μm to 0.8 μm.

  20 and 21, the arrangement depth D1 of the dielectric layer 50 is 0.8 μm, and the lateral distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm to 1.. The configuration in the range of 4 μm, the arrangement depth D1 of the dielectric layer 50 is 0.9 μm, and the lateral distance B1 from the end 34a of the STI oxide film 34 is −0.8 μm to 1.4 μm. In the configuration within the range, the ESD tolerance is in the range of 1.04 to 1.50. Further, the arrangement depth D1 of the dielectric layer 50 is 1.3 μm, and the lateral distance B1 from the end 34a of the STI oxide film 34 is in the range of −0.8 μm to 1.4 μm, A configuration in which the arrangement depth D1 of the dielectric layer 50 is 1.5 μm and the lateral distance B1 from the end 34a of the STI oxide film 34 is in the range of −0.4 μm to 1.2 μm; In the configuration in which the arrangement depth D1 of the layer 50 is 1.8 μm and the lateral distance B1 from the end 34a of the STI oxide film 34 is in the range of 0 μm to 1.2 μm, the ESD resistance is 1.01 to 1.01. The range is 1.50. Therefore, in the configuration in which the thickness T1 of the dielectric layer 50 is 0.3 μm, the length L1 is 0.2 μm, and the dielectric constant is 3.9, these ranges are included in order to improve the ESD resistance. It is desirable to provide the dielectric layer 50 in the semiconductor device 1 with the included configuration.

  As shown in FIGS. 20 and 21, the arrangement depth of the dielectric layer 50 in the configuration in which the lateral distance B1 from the end 34a of the STI oxide film 34 is in the range of −0.8 μm to 1.4 μm. As the length D1 increases (as D1 approaches from 0.8 μm to 1.8 μm), the ESD tolerance decreases.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
First, an SOI substrate 10 formed by laminating an SOI layer 11 made of silicon via a buried oxide film 13 made of a silicon oxide film (SiO ₂ ) on a support substrate 12 made of silicon is prepared, and a trench isolation portion is prepared. 14 is formed (see FIG. 22A). The SOI layer 11 is configured by epitaxially growing an N − type semiconductor layer 11 b on an N type semiconductor layer 11 a formed on the buried oxide film 13. The trench isolation portion 14 is formed by forming a trench 14a reaching the buried oxide film 13 from the surface of the SOI layer 11, and filling the buried film 14b so as to fill the trench 14a.

Next, a mask M is formed on the upper surface 10b of the SOI substrate 10 by lithography or the like, and phosphorus is ion-implanted so as to have a peak concentration of about 5.0 × 10 ¹⁷ cm ^−3. Then, an N well region 21 having a thickness of about 1.7 μm is formed on the upper surface 10b side of the SOI substrate 10 (FIG. 22B). Then, the surface is thermally oxidized to form an SiO ₂ film 90 of about 425 、, and an SiN film 80 is deposited thereon to about 1650 Å. The SiN film 80 is covered with a resist (mask M) (FIG. 22C), the SiO ₂ film 90 and the SiN film 80 are etched, and the upper surface of the SiO ₂ film 91 is covered with the SiN films 81 and 82. , 92 are formed (FIG. 23A).

Next, the silicon surface (the upper surface 10b of the SOI substrate 10) is oxidized by thermal oxidation to form an STI oxide film or a LOCOS oxide film made of SiO ₂ (FIG. 23B). In the following, the following process will be described as an example in which about 6900 LOCOS oxide films 95 and 96 are formed as in the second embodiment to be described later. However, if an STI oxide film is formed instead of the LOCOS oxide film, The configuration is the same as described above.

  After forming the STI oxide film or the LOCOS oxide film, the SiN film 80 is removed and a gate insulating film 93 is formed on the upper surface 10a of the SOI substrate 10 to a thickness of about 250 mm by thermal oxidation or the like (FIG. 23B). Further, a gate electrode 41 made of a polysilicon film or the like is formed (FIG. 23C).

Subsequently, after forming the mask M, boron is ion-implanted so that the peak concentration is about 5.0 × 10 ¹⁷ cm ^−3, and then activated by heat treatment (annealing) to activate the upper surface 10 a of the SOI substrate 10. A P-type channel region 23 having a thickness of about 1.15 μm is formed on the side (FIG. 24A). Then, the portion of the upper surface 10a of the SOI substrate 10 covered by the mask M is changed so that the peak concentration of arsenic is about 3.0 × 10 ²⁰ cm ^{−3 in} the P-type channel region 23 and the N well region 21, respectively. After ion implantation, activation is performed by heat treatment (annealing) to form an N + source region 24 and an N + drain region 22 having a thickness of about 0.25 μm (FIG. 24B). In this manner, the LDMOS 5 is formed on the upper surface 10a of the SOI substrate 10.

Next, the portion of the upper surface 10a of the SOI substrate 10 covered by the mask M is changed, and oxygen ions are applied to the N − type semiconductor layer 11b of the SOI substrate 10 with high energy and high concentration (for example, a dose amount is 1.0 × 10 6). ¹⁷ / cm ² and energy is about 200 keV) (FIG. 25A). Then, by heat treatment (annealing), the STI oxide film or the LOCOS oxide film (LOCOS oxide film 95 in the example of FIG. 25) inside the SOI substrate 10 is located on the lower side of the oxide film from the SiO _2. A dielectric layer 50 is formed (FIG. 25B). Note that the conditions of the above-described B1, L1, T1, and D1 relating to the arrangement and shape of the dielectric layer 50 can be set in various ways, and particularly preferably set at the above-described desirable values.

  After the LDMOS 5 is formed in this manner, an insulating film or a conductive layer (the above-described insulating films 37, 38, 39, the first wiring layers 61a to 61c, the second wiring layers 62a to 62c are formed on the LDMOS 5 by a known method. , Third wiring layers 63a and 63c, fourth wiring layers 64a and 64c, first vias 71a to 71c, second vias 72a and 72c, and third vias 73a and 73c).

[Modification of First Embodiment]
Next, a method for manufacturing a semiconductor device according to a modification of the first embodiment will be described with reference to FIGS. In the semiconductor device according to the representative example of the first embodiment, the length of the STI oxide film 34 in the left-right direction is, for example, about 1.53 μm. However, the configuration of the STI oxide film 34 is not limited to this, and other configurations of the STI oxide film 34 may be adopted. For example, as shown in FIGS. 26 and 27, the configuration in which the length W3 of the STI oxide film 34 in the left-right direction is 1.4 μm, for example, and the accumulation length W2 is 3.2 μm, for example, is applied to the semiconductor device 1. Good. Even with such a configuration, the same effects as those of the first embodiment can be obtained. In this example as well, B1, L1, T1, and D1 related to the arrangement and shape of the dielectric layer 50 can be set in various ways. For example, the conditions may be set in a desirable range in the first embodiment.

[Second Embodiment]
Next, a semiconductor device 1 according to a second embodiment of the present invention will be described with reference to FIGS. The semiconductor device 1 of the second embodiment is different from the first embodiment in that the second insulator layer is mainly configured as a LOCOS oxide film 95, and is otherwise the same as the first embodiment. For this reason, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted. Hereinafter, a configuration different from the first embodiment will be mainly described.

In the semiconductor device 1 according to the second embodiment, as shown in FIGS. 28 and 29, a LOCOS oxide film 95 is formed between the P-type channel region 23 and the N + drain region 22 on the upper surface side of the SOI substrate 10. It has become the composition. Specifically, as shown in FIGS. 28 and 29, a LOCOS oxide film 95 having a thickness of about 6900 mm made of SiO ₂ is provided on the upper surface of the SOI substrate 10. Further, a gate insulating film 93 of about 250 mm made of SiO ₂ and a gate electrode 41 made of a polysilicon film or the like are provided. 28 and 29, the dielectric layer 50 is located in the SOI substrate 10 at a position away from the surface of the SOI substrate 10 and the P-type channel region 23 and below the LOCOS oxide film 95. It has a configuration arranged on the side. Further, a PSG film 97 having a thickness of about 6700 mm is provided as an oxide film made of SiO ₂ so as to cover a part of the N + source region 24, the gate electrode 41, and a part of the LOCOS oxide film 95 from above. Further, contacts are formed by etching or the like, and first wiring layers 61a and 61b made of an Al film are formed.

  In this example, instead of the distance B1 in the lateral direction (left-right direction) from the left end 34a of the STI oxide film 34 to the left end 50a of the dielectric layer 50 shown in the first embodiment, As shown in FIG. 29, the distance in the horizontal direction (left-right direction) from the position of the left end portion of the LOCOS oxide film 95 (the position of the H line shown in FIG. 29) to the position of the left end portion of the dielectric layer 50 is represented by B1. It is said. In this example as well, B1, L1, T1, and D1 related to the arrangement and shape of the dielectric layer 50 can be set in various ways. For example, the conditions may be set in a desirable range in the first embodiment.

[Third Embodiment]
Next, a semiconductor device 1 according to a third embodiment of the present invention will be described with reference to FIGS. The semiconductor device 1 of the third embodiment is different from the first embodiment in that the dielectric constant of the dielectric layer 50 is changed variously based on the basic configuration of the representative example of the first embodiment. Except for the rate, it is the same as the first embodiment. For this reason, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted. Hereinafter, a configuration different from the first embodiment will be mainly described.

  First, the relationship between the dielectric constant of the dielectric layer 50 and the ESD tolerance will be described. FIG. 30A is a schematic cross-sectional view showing equipotential lines and current density for a representative example of the first embodiment in which the dielectric constant of the dielectric layer 50 is 3.9, and FIG. FIG. 5 is a schematic cross-sectional view showing equipotential lines and current density of the configuration according to the third embodiment in which the dielectric layer 50 has a dielectric constant of 5000. 30A and 30B, the thickness T1 of the dielectric layer 50 is 0.3 μm, the length L1 is 0.2 μm, and the depth D1 is 0.9 μm. . 30A and 30B, as the dielectric constant of the dielectric layer 50 increases, the dielectric layer 50 attracts more lines of electric force in the SOI substrate 10, and the STI oxide film 34 The potential concentration near the end can be further increased.

  FIG. 31 shows the semiconductor device 1 of FIG. 1, in which the dielectric layer 50 has a thickness T1 of 0.3 μm, a length L1 of 0.2 μm, a depth D1 of 0.9 μm, and a dielectric constant of It is a graph which shows the relationship between ESD tolerance and distance B1 (distance between the edge part of STI oxide film 34-dielectric layer 50) in the case of 3.9, 1000, 5000. As described above, the distance B1 is the lateral direction (left-right direction) from the position of the left end 34a of the STI oxide film 34 (the position of the line G shown in FIG. 3) to the left end 50a of the dielectric layer 50. Is the distance. In FIG. 31, when the dielectric constant is 3.9, 1000, and 5000, the distance B1 is −2.4 μm, −2.0 μm, −1.6 μm, −1.2 μm, −0.8 μm, It shows the ESD tolerance under the conditions of −0.4 μm, 0.0 μm, 0.4 μm, 0.8 μm, 1.2 μm, 1.4 μm, and 1.6 μm. As can be seen from FIG. 31, in any configuration in which the dielectric constant of the dielectric layer 50 is 3.9, 1000, and 5000, a sufficient effect is obtained when the distance B1 from the STI end is in the range of −0.8 μm to 1.4 μm. When the dielectric constant of the dielectric layer 50 is larger than 3.9 (specifically, the dielectric constant is 1000 or more), the distance B1 from the STI end is −1.6 μm to 1.. A sufficient effect can be obtained in the range of 6 μm, and the range in which a sufficient effect can be obtained can be expanded. In particular, in any example in which the dielectric constant of the dielectric layer 50 is 3.9 or more, a further effect is obtained when the distance B1 from the STI end is in the range of −0.4 μm to 1.2 μm. In any example where the dielectric constant is 3.9 or more, a remarkable effect is obtained when the distance B1 from the STI end is in the range of 0 μm to 0.8 μm.

[Other Embodiments]
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  In the above embodiment, the SOI substrate 10 is exemplified as the semiconductor substrate, but the substrate is not limited to the SOI structure and may be a substrate having a bulk structure.

  In any configuration of any of the above embodiments, the conditions of B1, L1, T1, and D1 of the dielectric layer 50 can be set variously. More preferably, in any case, it is preferable that at least a part of the dielectric layer 50 is disposed in a region immediately below the second insulator layer inside the SOI substrate 10. More preferably, in any configuration, in the predetermined lateral direction (left-right direction) where the N + source region 24 and the N + drain region 22 face each other, the end of the dielectric layer 50 on the N + source region 24 side is a P-type channel region. It is preferable to be arranged on the N + drain region 22 side with respect to 23. In any case, it is desirable that the upper end portion of the dielectric layer 50 is disposed above the lower end portion of the P-type channel region 23 in the thickness direction (vertical direction) of the SOI substrate 10. In any case, in the lateral direction (left-right direction), the end of the dielectric layer 50 on the N + drain region 22 side is N + source region than the end of the second insulator layer on the N + drain region 22 side. It is good to arrange on the 24 side.

  More specifically, in any configuration of any of the embodiments, the distance (depth) D1 from the second insulator layer to the dielectric layer 50 in the plate thickness direction (vertical direction) of the SOI substrate 10 is 1.8 μm. The following is desirable. In any configuration of any of the embodiments, the length (thickness) T1 of the dielectric layer 50 in the plate thickness direction (vertical direction) is desirably 0.2 μm or more. In any configuration of any embodiment, it is desirable that the length L1 of the dielectric layer 50 in a predetermined lateral direction where the N + source region 24 and the N + drain region 22 face each other is 0.1 μm or more.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... SOI substrate (semiconductor substrate)
11b... N− type semiconductor layer (first semiconductor region)
22 ... N + drain region (fourth semiconductor region)
23... P-type channel region (second semiconductor region)
24... N + source region (third semiconductor region)
32, 93 ... Gate insulating film (first insulator layer)
34 ... STI oxide film (second insulator layer)
40, 41 ... Gate electrode 50 ... Dielectric layer 95 ... LOCOS oxide film (second insulator layer)

Claims (7)

A semiconductor substrate (10) having an upper surface formed on one side in the plate thickness direction, and a first semiconductor region (11b) of the first conductivity type formed on at least the upper surface side;
A second semiconductor region (23) of a second conductivity type disposed on the upper surface side of the semiconductor substrate and configured as a channel region;
A third third layer of the first conductivity type formed at a position away from the first semiconductor region on the upper surface side of the semiconductor substrate and disposed with the second semiconductor region interposed between the first semiconductor region and the second semiconductor region; A semiconductor region (24);
A fourth semiconductor region (22) of the first conductivity type formed at a position away from the second semiconductor region and the third semiconductor region on the upper surface side of the semiconductor substrate;
A first insulator layer (32, 93) disposed at a position covering at least the second semiconductor region above the semiconductor substrate;
A gate electrode layer (40, 41) disposed at least above the second semiconductor region in a configuration covering the upper side of the first insulator layer; and
A second insulator layer (34, 95) formed between the second semiconductor region and the fourth semiconductor region on the upper surface side of the semiconductor substrate;
A dielectric layer (50) made of a dielectric material formed at a position below the second insulator layer and away from the second insulator layer inside the semiconductor substrate;
Equipped with a,
In a predetermined lateral direction in which the third semiconductor region and the fourth semiconductor region face each other, an end portion of the dielectric layer on the third semiconductor region side is closer to the fourth semiconductor region side than the second semiconductor region. It is arranged and wherein a Rukoto (1).   2. The semiconductor device according to claim 1, wherein at least a part of the dielectric layer is disposed in a region immediately below the second insulator layer inside the semiconductor substrate. In the thickness direction, the semiconductor device according to claim 1 or claim 2, characterized in that the upper portion of the dielectric layer is positioned above the lower end portion of the second semiconductor region. In a predetermined lateral direction in which the third semiconductor region and the fourth semiconductor region face each other, an end portion of the dielectric layer on the fourth semiconductor region side is on the fourth semiconductor region side in the second insulator layer. the semiconductor device according to any one of claims 1 to 3, characterized in that from the end is arranged in said third semiconductor region side. The semiconductor device according to any one of claims 1 to 4, the distance from the second insulator layer in the thickness direction until the dielectric layer is equal to or less than 1.8 .mu.m. The semiconductor device according to any one of claims 1 to 5 in which the length of the plate thickness direction of the dielectric layer is equal to or is 0.2μm or more. Any one of claims 1 to 6, wherein the length of the dielectric layer in the third semiconductor region and the fourth semiconductor region and face each other a predetermined horizontal direction is 0.1μm or more A semiconductor device according to 1.

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