JP6333371B2 - Method for implementing bit arrays in cache lines - Google Patents

Description

  The present invention relates to computing systems, and more particularly to a method for implementing bit arrays in cache lines.

  Many multithreaded computer systems become one of the more important technologies for companies of various sizes. These increase the computational efficiency and flexibility of computing hardware platforms. Multithreaded operations on multithreaded computer systems include bit-wise atomic memory operations (AMO) that perform logical operations on individual bits of the bit array. There is. Such AMOs include storeAND, storeOR, storeXOR, which are store-like operations, and fetchAND, fetchOR, and fetchXOR, which are load-like operations.

  An object of embodiments of the present invention is to provide improved methods, computer systems, and computer program products. This object is solved by the subject matter of the independent claims. Advantageous embodiments are described in the dependent claims.

  Atomic memory operation (AMO) as used herein refers to a read-modify-write operation on shared data. AMO is atomic in the sense that a read-modify-write operation of one thread is performed without interference by another thread. In other words, when a thread or processor accesses shared data (eg, accesses simultaneously), each read or write or AMO access is performed atomically without interference from another access.

  In one aspect, the invention relates to a method for implementing a bit array in a cache line of a memory system comprising a memory storage and a controller.

  The method includes configuring a bit array in the cache line, the bit array including an array of bits, and the configuring step further includes defining a value for each bit in the bit array. The method also includes receiving a request for an operation on the bit array by the controller, the request indicating a location of the cache line in the memory storage and information specifying the request. The method also includes the step of using the information by the controller (206) to identify one or more actions on the bit array for operation, wherein the one or more actions are encoded in the controller. The method also includes performing the request by performing one or more encoded actions in response to receiving the request.

  A bit array is a data structure that stores individual bits. That is, each array element corresponds to a single bit. Each element of the bit array stores one of two values 0 and 1. Each element of the bit array is identified by a unique index. Normally, index values 0 to (E-1) are used for bit arrays including E elements.

  Implementing a bit array can allow access to at least a portion of a cache line to perform bitwise logical operations on individual bits as well as a group of bits in the bit array. For example, each bit of the bit array can represent an instance of a computer system resource comprising a memory system. An operation on this bit array is, for example, that the user (eg, thread) atomically “owns” the one or more resource instances by setting the value of the corresponding one or more bits to 1. Can be made possible.

  For example, each bit in the bit array can represent a lock in a set of locks shared by multiple threads. Operations on this bit array can, for example, allow a thread to atomically acquire multiple locks with high performance and low programming effort.

  For example, a 1 or 0 value for each bit in the bit array can indicate the presence or absence of a particular element in the priority queue. Such a priority queue has up to E unique elements, each element having a unique priority numbered from 0 to E-1, corresponding to each index of the bit array.

  These features may be advantageous, especially in the case of simultaneous threads, as it allows for higher rate operations on bit arrays compared to conventional methods. This may be due to the fact that operations on bit arrays can be simple operations that are faster than conventional operations on other data structures.

  These features can allow the bit array to be used as a simultaneous data structure by multiple threads. For example, the requested operation can be AMO. The received request can be one of a plurality of simultaneous requests received by the controller from a plurality of threads seeking operations on the bit array. The received simultaneous requests may be performed sequentially. The controller can be adapted to implement and manage such multiple simultaneous threads. The controller can include a receiver that accepts memory access requests and a transmitter that returns a response, each of which includes a first in first out buffer (FIFO) to accommodate memory access of multiple simultaneous threads. it can.

  These features include a single interface for multiple users or threads to use bit arrays in multithreaded applications where multiple threads issue requests to access the bit arrays simultaneously, such as this request, for example. Can be provided.

  Another advantage would be that the memory system can implement bit arrays using new atomic memory operations that go beyond traditional atomic memory operations. For example, the AMO can be a variation of a processor store or load instruction.

  The requested operation only needs the address of the cache line, not the address of the element of the bit array.

  According to one embodiment, the request includes a “fetch and set first 0-bit” request. The step of performing the request consists of the action of sequentially reading each bit of the bit array from index 0, and if the first bit with value 0 is found, returns the index of the first bit found and the first bit found Performing the action of one or more of: setting the value of to 1 and otherwise returning a predefined failure value.

  The term 0-bit refers to a bit having the value 0. The term 1-bit refers to a bit having the value 1.

  For a bit array containing E elements, a request to “fetch and set first 0-bit” returns an index value from 0 to E-1. If there are no 0-bits in the bit array, the predefined failure value may not correspond to a valid index. For example, the failure value may be E, ie the number of bits in the bit array.

  The cache line can also be accessed by another bit unit AMO. For example, a bit-wise AMO such as storeAND () addresses and modifies an 8-byte word in a 128-byte cache line. For example, a thread issues a “fetch and set first 0-bit” request to obtain the resource corresponding to the index of the first bit having the value 0. After the thread uses the resource, it issues a storeAND () operation on the appropriate word in the cache line to set this bit to the value 0, thus making the resource available again. In this way, the bit arrangement can be used for allocation of memory pages, inodes, disk sectors, and the like.

  According to one embodiment, the request includes a “fetch and set last 0-bit” request and the bit array includes E elements. The step of performing the request returns the action of reading each bit of the bit array sequentially from the index E-1, and if the last bit of the bit array having the value 0 is found, returns the index of the last bit, Performing the action of one or more of setting the value of the last bit to 1 and otherwise returning a predefined failure value.

  According to one embodiment, the request includes a “count 1-bit” request. The step of performing the request includes performing one or more of an action of reading each bit of the bit array, an action of counting the number of bits having a value of 1, and an action of returning the result of the count. Including. For example, such a request is also known as a population count request.

  According to one embodiment, the request includes a “fetch and set orphaned 0-bit” request. The step of performing the request is to read the bit array and determine an action sequence to determine zero or more consecutive sequences of bits having a zero value, and a predefined failure value if zero sequences are found. , Otherwise rank one or more consecutive sequences based on their number of bits, and have the least number of bits in one or more consecutive sequences Selecting a bit of the sequence, returning an index of the selected bit, setting the value of the selected bit to 1 and performing one or more of the following.

  This may be advantageous because it can store the longest possible zero sequence that may be used by other concurrent operations. This may be advantageous when the bit array represents a continuous instance of some resource, such as a memory page or disk block. In this case, by saving a sequence of zeros, a continuously available resource is saved for some future resource acquisition. In such future acquisitions, a request to "fetch and set N consecutive 0-bits" can be used for the bit array.

  According to one embodiment, the request includes a “fetch the first 1-bit” request. The step of performing the request returns the action of reading each bit of the bit array sequentially from index 0, and if the first bit with the value 1 is found, returns the index of the first bit found; Performing one or more of an action that returns a predefined failure value. For example, a “fetch the first 1-bit” request can be used to identify the highest priority element in a priority queue based on bit ordering.

  According to one embodiment, the request includes a “fetch and clear first 1-bit” request. The step of performing the request consists of the action of sequentially reading each bit of the bit array from index 0 and, if the first bit with value 1 is found, returns the index of the first bit found and the first bit found Performing the action of one or more of: setting the value of to zero and otherwise returning a predefined failure value. For example, a request to “fetch and clear the first 1-bit” can be used to identify and remove the highest priority element in the priority queue based on the bit array.

  According to one embodiment, the request includes a “fetch and clear last 1-bit” request and the bit array includes E elements. The step of performing the request includes the action of sequentially reading each bit of the bit array from the index E-1, and if the last bit of the bit array having the value 1 is found, returns the index of the last bit and Performing one or more of the following actions: setting the value of a bit of the to zero to zero, otherwise returning a predefined failure value. For example, a “fetch the last 1-bit and clear” request can be used to identify and remove the lowest priority element in the priority queue based on the bit array.

  According to one embodiment, the request includes a “fetch the Nth 1-bit” request, and the request provides a value of N. The step of performing the request returns the action of reading each bit of the bit array sequentially from index 0 and the Nth 1-bit index found if the Nth occurrence of a bit having value 1 is found; If not, it includes the step of performing one or more of an action that returns a predefined failure value. For example, if the request provides a value of 1 for N, the request is equivalent to a “fetch the first 1-bit” request. For example, in a scenario where there are four threads, a request to “fetch the Nth 1-bit” allows each thread to identify one of the four upper elements in the priority queue.

  According to one embodiment, the request includes a “fetch and clear Nth 1-bit” request, and the request provides a value of N. The step of performing the request returns the action of reading each bit of the bit array sequentially from index 0 and the Nth 1-bit index found if the Nth occurrence of a bit having the value 1 is found. Performing one or more of the following actions: setting the value of the found bit to 0, otherwise returning a predefined failure value. For example, if two threads with different performance process elements in the priority queue, the application performance goal is best met if the fast and slow threads provide values 1 and 2 for N, respectively. Let's go.

  According to one embodiment, the request includes a “fetch and clear isolated 1-bit” request. The step of performing the request is to read the bit array and determine an action of determining zero or more consecutive sequences of bits having a value of 1 and a predefined failure value if no sequence is found. Otherwise, rank one or more consecutive sequences based on their number of bits, select the bits of the consecutive sequence with the least number of bits, and Returning the index and setting the value of the selected bit to 0 and performing one or more of the following.

  According to one embodiment, the request includes a “fetch and set N consecutive 0-bits” request. The step of performing the request is to read the bit array and predetermine if the action to determine zero or more consecutive sequences of N bits having a value of zero and if no sequences are found. Select a sequence that satisfies a predefined condition among one or more consecutive sequences, return the index of the first bit of the selected sequence, and select Setting the set N bits to a value of 1 and performing one or more of the steps.

  This can, for example, allow a thread to atomically take ownership of a sequence of N resources. If N consecutive 0-bits are not present in the bit array, a predefined failure value may be returned. Such a resource sequence can be used when allocating memory pages, inodes, disk sectors, and the like.

  According to one embodiment, the predefined condition includes that the sequence includes the first N consecutive bits of the bit array. According to one embodiment, the bit array can be treated as a circular buffer, so that a continuous sequence of N bits is a continuous sequence at the beginning of the bit array and a continuous sequence at the end of the bit array. And a sequence.

  According to one embodiment, the request includes a “fetch and set N specified 0-bits” request. The step of executing the request is to read the bit array to locate the specified bit at the specified index, and a predefined failure if at least one bit of the specified bit has the value 1. One of an action that returns a value and an action that sets each specified bit to a value 1 and returns a predefined success value if each of the specified bits has a value of 0, or Performing a plurality of steps. This can allow a thread to obtain multiple locks atomically.

  In a “fetch and set N specified 0-bits” request, one or more values in the request can efficiently specify the required 0-bit index. For example, for a bit array containing up to 256 elements, the request can provide an 8-byte value, each of which specifies a bit index. To specify less than 8 bits, some of the bytes specify the same index. In other words, to specify S 0-bits, 8 bytes specify S unique indexes. For example, for a bit array with up to 1024 elements, the request can provide a 64-bit value, with the least significant 60 bits treated as 6 fields of 10 bits each, each of the 6 fields being Specifies the bit index.

  The “fetch and set designated N 0-bits” request of the present invention allows granular locking (where each process or thread must hold multiple locks from a shared set of locks). Address the issue of granular locking. In this case, the number of locks in the set is up to the number E of bits in the bit array, and each lock in the set can be numbered from 0 to E-1. Without the present invention, granular locking can create subtle lock dependencies. This subtlety can increase the opportunity for programmers to introduce deadlocks without their knowledge. Thus, in the absence of the present invention, locks can only be configured with relatively careful software support and full adherence to strict commitments by application programming (eg, atomically Managing multiple simultaneous locks to delete item X from table A and insert X into table B).

  If there are more than E objects in the set, each to be locked, hash each object to a number between 0 and E-1, and use the bit array at the performance cost of coarser lock granularity Can be made possible.

  For example, the bit arrangement may be implemented in two or more cache lines of a memory system, where two or more cache lines are adjacent cache lines. A request for an operation on the bit array can indicate two or more adjacent cache lines and the location of the first of the two or more cache lines in the memory system.

  In another aspect, the present invention relates to a computer program product comprising computer executable instructions for performing the method steps of any one of the preceding embodiments.

  In another aspect, the invention relates to a system for implementing a bit array in a cache line, the system comprising a memory storage and a controller. The system is configured to configure a bit array in the cache line, the bit array including an array of bits, and further including defining a value for each bit in the bit array. The system is also configured to receive a request for an operation on a bit array by a controller, the request indicating a cache line location in memory storage and information specifying the request. The system is also configured to use this information to identify one or more actions on the bit array for operation, and the one or more actions are encoded in the controller. The system is also configured to implement the request by performing one or more encoded actions in response to receiving the request.

  The memory system may be at a level in the cache hierarchy, so when a controller fulfills a request, the result is a memory system access to a lower level in the cache hierarchy, so that metadata and elements are It can be established in a memory cache. The memory system may be separated into two or more parts, and a controller in one part can use the memory in that part to manipulate the dynamic array data structure. The cache level may be replicated as two or more units, and the controller can access any portion of the underlying cache or memory level within the cache unit.

  As used herein, a “computer-readable storage medium” includes any tangible storage medium that can store instructions executable by a processor of a computing device. A computer-readable storage medium may be referred to as a computer-readable non-transitory storage medium. A computer-readable storage medium may also be referred to as a tangible computer-readable medium. In some embodiments, the computer readable storage medium may also be capable of storing data accessible by the processor of the computing device. Examples of computer readable storage media include, but are not limited to, floppy disk, magnetic hard disk drive, solid state hard disk, flash memory, USB thumb drive, random access memory ( RAM), read only memory (ROM), optical disk, magneto-optical disk, and processor register file. Examples of optical disks include compact disks (CD) and digital versatile disks (DVD), such as CD-ROM, CD-RW, CD-R, DVD-ROM, DVD-RW, or DVD-R disk. The term computer readable storage medium also refers to various types of recording media that are accessible by a computer over a network or communication link. For example, data can be retrieved via a modem, the Internet, or a local area network. Computer-executable code incorporated in a computer-readable medium is any suitable including, but not limited to, wireless, wireline, fiber optic cable, RF, etc., or any suitable combination thereof. It can be transmitted using a medium.

  A computer-readable signal medium may include a propagated data signal with computer-executable code incorporated therein, such as in baseband or as part of a carrier wave. Such propagated signals can take any of a variety of forms including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium is any computer readable medium that is not a computer readable storage medium, and communicates, propagates or conveys a program used by or in connection with an instruction execution system, apparatus or device. Any computer-readable medium capable.

  “Computer memory” or “memory” is an example of computer-readable storage media. Computer memory is any memory that is directly accessible from the processor. “Computer storage” or “storage” is yet another example of a computer-readable storage medium. Computer storage is any non-volatile computer readable storage medium. In some embodiments, the computer storage may also be computer memory or vice versa.

  As used herein, “processor” includes electronic components capable of executing programs or machine-executable instructions or computer-executable code. When referring to a computing device comprising a “processor”, this should be interpreted as possibly comprising multiple processors or processing cores. The processor can be, for example, a multi-core processor. A processor may also refer to a collection of processors within a single computer system or distributed among multiple computer systems. The term computing device should also be construed to refer to a collection or network of computing devices, each comprising one or more processors. Computer-executable code may be executed by multiple processors, which may be within the same computing device or even distributed across multiple computing devices.

  Computer-executable code may include machine-executable instructions or programs that cause a processor to implement an aspect of the present invention. Computer-executable code for performing operations relating to aspects of the present invention includes conventional object-oriented programming languages such as Java®, Smalltalk®, C ++, and the like, such as “C” programming language and similar programming languages. It may be written in any combination of one or more programming languages, including procedural programming languages, and compiled into machine-executable instructions. In some cases, the computer-executable code may be in the form of a high-level language or in a pre-compiled form and may be used with an interpreter that generates machine-executable instructions on the fly. .

  The computer executable code may be executed entirely on the user's computer, partially as a stand-alone software package, partially executed on the user's computer, or partially executed on the user's computer and partially It may be executed on a remote computer or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or The connection may be made to an external computer (eg, via the internet using an internet service provider).

  Aspects of the invention are described with reference to flowchart illustrations, block diagrams, or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be appreciated that where appropriate, the flowcharts, descriptions, or block diagrams, or all of them, each block, or portion of a block, can be implemented by computer program instructions in the form of computer-executable code. . Further, it should be understood that when not mutually exclusive, different flowcharts, descriptions, or block diagrams, or blocks within all of them may be combined. These computer program instructions are functions / acts in which instructions executed via a processor of a computer or other programmable data processing device are specified in one or more blocks of a flowchart and / or block diagram. Can be provided to the processor of a general purpose computer, special purpose computer, or other programmable data processing device to create a machine.

  These computer program instructions also include an article of manufacture in which instructions stored on a computer readable medium implement instructions / functions specified in one or more blocks of a flowchart and / or block diagram. As created, it can be stored on a computer readable medium and directed to a computer, other programmable data processing device, or other device to function in a particular manner.

  A computer program instruction is also a process for implementing functions / acts in which instructions executed on a computer or other programmable device are specified in one or more blocks of a flowchart and / or block diagram. To produce a computer-implemented process, loaded into a computer, other programmable data processing device, or other device and having a series of operational steps on the computer, other programmable device, or other device Can be implemented.

  As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as an apparatus, method, or computer program product. Accordingly, aspects of the present invention may be in the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects. All of which may be generally referred to herein as “circuits”, “modules”, or “systems”. Furthermore, aspects of the invention may take the form of a computer program product embodied in one or more computer readable media incorporating computer executable code.

  It should be understood that one or more of the foregoing embodiments can be combined as long as the combined embodiments are not mutually exclusive.

  Hereinafter, preferred embodiments of the present invention will be described in more detail by way of example only with reference to the drawings.

FIG. 2 illustrates a system architecture operable to perform a method for implementing a bit array in a cache line in a memory. 1 is an exemplary block diagram of a memory system. It is a figure which shows the sequence of operation with respect to a bit arrangement | sequence. 3 is a flowchart of a method for implementing a bit array in a cache line in a memory.

  In the following, like-numbered elements in the figures either indicate similar elements or elements that perform equivalent functions. Where functions are equivalent, previously discussed elements are not necessarily discussed in later figures.

  In FIG. 1, a computer system (or server) 112 in computing system 100 is shown in the form of a general purpose computing device. The components of computer system 112 are not limited to the following, but include one or more processors or processing units 116, memory system 128, and various system components including memory system 128 to processor 116. And a bus 118 to be coupled.

  Computer system 112 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by computer system 112 and includes both volatile and non-volatile media, removable and non-removable media.

  The memory system 128 may include a computer system readable medium in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The memory system can include one or more active buffered memory devices. An active buffered device may comprise multiple memory elements (eg, chips). An active buffered memory device may include layers of memory that form a three-dimensional (“3D”) memory device, where individual columns of chips communicate with a vault. ). An active buffered memory device can include partitions that can be accessed simultaneously by multiple processing elements, and these partitions can be any suitable memory segment, including but not limited to a vault. be able to.

  The processing unit 116 can issue requests to the memory system utilizing the dynamic array data structure and associated metadata to implement the application.

  The computer system 112 may also include one or more external devices 114, such as a keyboard, pointing device, display 124; one or more devices that allow a user to interact with the computer system 112; or the computer system Any device that enables 112 to communicate with one or more other computing devices (eg, a network card, modem, etc.) or all of them can be communicated. Such communication can be performed via the I / O interface 122. Further, the computer system 112 may include one or more networks, such as a local area network (LAN), a general wide area network (WAN), a public network (eg, the Internet), or all of them, and a network It can communicate via the adapter 120. As shown, network adapter 120 communicates with other components of computer system / server 112 via bus 118.

  FIG. 2 shows an exemplary block diagram of the memory system 128 in detail. The memory system 128 includes a controller 206 and a memory storage 208. The memory storage 208 may be any suitable physical memory, such as, for example, a cache or random access memory (RAM).

  The controller 206 includes a receiver 214 for request 210 and a transmitter 216 for reply 212 configured to communicate with the bus 118, each of which includes a first in first out buffer. In response to request 210, controller 206 can perform read and write access to storage 208 and return a response 212.

  The memory storage 208 includes one or more cache lines 211. The cache line 211 can be accessed as a bit array, which can contain a bit value 0 or 1. A bit array may be implemented in the cache line 211, for example by configuring this at least part of the cache line to access at least part of the cache line using bitwise operations, Done.

  The described memory system structure is for multi-threaded applications in which multiple threads issue a request to access a cache line, such as request 210, for multiple users or threads to use bit arrays. A single interface can be provided.

  The operation request 210 for the bit array 221 is implemented by the controller 206 executing an action corresponding to the operation request. These actions are encoded in the controller.

  Request 210 from the requestor or user is received from bus 118 by receiver 214 of controller 206. The request source may be a thread executing an application, for example, a thread executing AMO. Request 210 indicates the location of the cache line in memory.

  Request 210 can be any suitable request for an operation on bit array 318, such as an operation request that sets all elements of a bit array to 0 or sets all elements to 1. This can allow initialization of the bit array. The request is an operation request that returns the number of bits set to 1, the first 1-bit, the middle 1-bit, or the first transition bit (ie when leading 0 changes to 1 or vice versa). Can be included. The request may further include an operation request that returns and clears the entire first blip. For example, for array 00001101, position 4 and length 2 are returned, and the resulting array is 00000001. The middle 1-bit indicates a bit having the same number of 1-bits before and after in the array.

  In communication 218, a bit or group of bits of bit array 318 can be accessed by controller 206 based on the operation in request 210. In an example where the request 210 is a “fetch first 0-bit” request, the value of the first bit having a value of 0 read in communication 218 is sent by the controller 206 to the user in a reply 212.

  FIG. 3 shows a diagram for explaining an operation sequence for a bit arrangement (for example, 211). Bit array 318.1 includes a fixed number of bits. For ease of description, bit array 318.1 is shown as including the first 24 bits of the cache line. Bit positions are labeled from left to right as shown in row 333.

  The operations may be requested and received by the memory system controller (eg, 206) as simultaneous requests and may be processed sequentially (eg, one by one) as follows. The order of operations can be arbitrary.

  Sequence operation 301 corresponds to fetchAndSetFirst0Bit (cacheLineAddress) to set the bit to value 1 after returning the index of the first bit having value 0 in bit array 318.1. To this end, the controller 206 can sequentially read the bit array from the bit having the index 00 until the first bit having the value 0 (ie, index 00) is found. The controller can then return index 00. Next, the controller sets the value of bit 00 to 1, resulting in bit array 318.2.

  Sequence operation 303 also corresponds to fetchAndSetFirst0Bit (cacheLineAddress) to return the index of the first bit having value 0 in bit array 318.2 and then set this bit to value 1. To this end, the controller 206 can sequentially read the bit array from the bit having the index 00 until the first bit having the value 0 (ie, index 03) is found. The controller can then return index 03. Next, the controller sets the value of bit 00 to 1, resulting in a bit array 318.3.

  Sequence operation 305 returns the index of the first bit of the first set of two consecutive 0-bits in bit array 318.3, and then fetchAndSetFirstNcontiguous0Bits to set these two bits to the value 1. Corresponds to (cacheLineAddress, 2). To this end, the controller 206 reads the bit array 318.3 sequentially from the bit having the index 00 until the first two consecutive bits each having the value 0 (ie, index 06, 07) are found. it can. The controller can then return index 06, setting the values of the two bits 06 and 07 to 1, resulting in bit array 318.4.

  Sequence operation 307 returns the index of the first bit of the first set of four consecutive 0-bits in bit array 318.4 and then fetchAndSetFirstNcontiguous0Bits to set these four bits to the value 1. Corresponds to (cacheLineAddress, 4). To this end, the controller 206 reads the bit array 318.4 sequentially from the bit having the index 00 until the first four consecutive bits each having the value 0 (ie, the indices 11-14) are found. it can. The controller can then return index 11 and set the value of the four bits 11-14 to 1, resulting in the bit array 318.5.

  The sequence operation 309 corresponds to fetchAndSetNgiven0Bits (cacheLineAddress, 3, x04090F). The second argument 3 indicates that the three bits can be changed from 0 to 1. The third argument 0x040911 indicates that the indices of the three desired bits are 0x04, 0x09, 0x11 == 17. The controller can then read the value of each of these three bits from the bit array 318.5 and determine whether each bit has the value 0. The controller can return 1 to indicate success, and set the value of each of the three bits to 1, resulting in a bit array 318.6.

  The sequence operation 311 corresponds to fetchAndSetNgiven0Bits (cacheLineAddress, 2, x0108). The second argument 2 indicates that the two bits can be changed from 0 to 1. The third argument 0x0108 indicates two desired bit indices 0x01, 0x08. The controller can then read the value of each of these two bits from the bit array 318.6 and determine whether each bit has the value 0. In this case, one of the two bits has the value 1. The controller can return a predefined failure value 0 to indicate a request failure without changing the contents of the bit array 318.6.

  FIG. 4 is an illustrative example for operating a memory system, such as the memory system shown in FIG. 1, to implement a bit array in a cache line, eg, a single cache line in a memory system. 1 is a flowchart of a method and system.

  In step 401, the cache line is configured in memory so that at least a portion of the cache line can be accessed as a bit array. For example, the cache line can be accessed as a bit array including 1024 elements.

  In step 403, a request for an operation on the bit array from a user or requester is received by the controller. Request 210 provides the cache line address location for the operation. The requester that issued the request can be any thread, such as a thread running on a processor, a processing element in a buffered memory stack, or a thread communicating over a network via network interface logic. It can be an appropriate user.

  At step 405, the controller uses this information to identify one or more actions on the bit array for the operation. One or more actions are encoded in the controller. Multiple actions may be encoded in the controller. Identifying the one or more actions can include selecting one or more actions from the plurality of actions.

  At step 407, the controller performs one or more actions to implement the request. For example, the request may include a “fetch and set first 0-bit” request to return the index of the first bit having the value 0 in the bit array and then set this bit to the value 1. Can do.

  As shown, following step 407, the controller waits to respond to the next request 210 and returns to block 403.

  The initial configuration step 401 may be performed once during the initial configuration, and steps 403-407 can be repeated as each request for operation is answered by the controller 206.

100 Computing System 112 Server 114 External Device 116 Processor 120 Network Adapter 122 I / O Interface 124 Display 128 Memory System 206 Controller 208 Memory Storage 210 Request 211 Cache Line 212 Reply 213 Metadata Field 214 Receiver 215 Element Field 216 Transmitter 218 Communication 220 Communication 301 Operation 303 Operation 305 Operation 307 Operation 309 Operation 311 Operation 333 Line 401 Step 403 Step 405 Step 407 Step

Claims (15)

A method for implementing a bit array in a cache line of a memory system comprising a memory storage and a controller, comprising:
-Configuring the bit array in the cache line, wherein the bit array includes an array of bits, the configuring step further comprising defining a value for each bit in the bit array; The step of configuring;
Receiving a request for an operation on the bit array by the controller, the request indicating a location of the cache line in the memory storage and information specifying the request;
-Identifying for the operation one or more actions on the bit array using the information by the controller, wherein the one or more actions are encoded in the controller Steps,
Implementing the request by performing the one or more encoded actions in response to receiving the request. The request includes a “fetch and set first 0-bit” request, and the step of implementing the request comprises:
-An action of sequentially reading each bit of the bit array from index 0;
-If the first bit with the value 0 is found, return the index of the first bit found and set the value of the first bit found to 1; The method of claim 1, comprising performing one or more of an action that returns a failure value. The request includes a “fetch and set last 0-bit” request, the bit array includes E elements, and the step of implementing the request comprises:
-An action of sequentially reading each bit of the bit array from the index E-1,
-If the last bit of the bit array with the value 0 is found, return the index of the last bit and set the value of the last bit to 1, otherwise predefined A method according to claim 1 or 2, comprising the step of performing one or more of the following: The request includes a “fetch and set orphaned 0-bit” request, and the step of implementing the request comprises:
-An action to read the bit array and determine zero or more consecutive sequences of bits having a zero value;
-Returns a predefined failure value if there are zero sequences found, otherwise
Ranking the one or more consecutive sequences based on their number of bits;
Selecting a bit of a continuous sequence having a minimum number of bits of the one or more consecutive sequences;
Return the index of the selected bit;
3. The method of claim 1 or 2, comprising performing one or more of the actions of setting the value of the selected bit to 1. The request includes a “fetch and clear first 1-bit” request, and the step of implementing the request comprises:
-An action of sequentially reading each bit of the bit array from index 0;
-If the first bit with the value 1 is found, return the index of the first bit found and set the value of the first bit found to 0, otherwise a predefined failure 3. The method of claim 1 or 2, comprising performing one or more of an action that returns a value. The request includes a “fetch and clear last 1-bit” request, the bit array includes E elements, and the step of implementing the request comprises:
-An action of sequentially reading each bit of the bit array from the index E-1,
-If the last bit of the bit array with the value 1 is found, return the index of the last bit and set the value of the last bit to 0, otherwise the predefined bit 3. The method of claim 1 or 2, comprising performing one or more of an action that returns a failure value. The request includes a “fetch and clear orphaned 1-bit” request, and the step of implementing the request comprises:
-An action to read the bit array and determine zero or more consecutive sequences of bits having a value of 1;
-Returns a predefined failure value if there are zero sequences found, otherwise
Ranking the one or more consecutive sequences based on their number of bits;
Select a continuous sequence of bits with the least number of bits;
Return the index of the selected bit;
3. The method of claim 1 or 2, comprising performing one or more of the actions of setting the value of the selected bit to 0. The request includes a “fetch and set N consecutive 0-bits” request, and the step of implementing the request comprises:
-An action of reading said bit array to determine zero or more consecutive sequences of N bits having a value of zero;
-Returns a predefined failure value if there are zero sequences found, otherwise
Selecting a sequence satisfying a predefined condition from the one or more combinations,
Return the index of the first bit of the selected sequence of N bits;
3. The method according to claim 1 or 2, comprising performing one or more of the actions of setting the value of the selected N bits to 1.   9. The method of claim 8, wherein the predefined condition includes that the sequence includes the first N consecutive bits of the bit array. The request includes a “fetch and set N specified 0-bits” request, and the step of implementing the request comprises:
-Reading the bit array to locate the specified bit at the specified index;
-An action that returns a predefined failure value if at least one of the specified bits has the value 1;
Performing one or more of the actions of setting each designated bit to a value 1 and returning a predefined success value if each of the designated bits has a value 0 The method according to claim 1, comprising a step. The request includes a “count 1-bit” request, and the step of implementing the request comprises:
-An action to read each bit of the bit array;
-An action of counting the number of bits having the value 1;
The method according to claim 1 or 2, comprising performing one or more of the following actions: returning the count result. The request includes a “fetch the first 1-bit” request, and the step of implementing the request comprises:
-An action of sequentially reading each bit of the bit array from index 0;
Perform one or more of the following actions: return the index of the first bit found if the first bit with value 1 is found, otherwise return a predefined failure value The method according to claim 1 or 2, comprising the step of: The request includes a “fetch the Nth 1-bit” request, the request provides a value of N, and the step of implementing the request comprises:
-An action of sequentially reading each bit of the bit array from index 0;
Returning an index of the Nth 1-bit found when the Nth occurrence of a bit having a value of 1 is found, and returning a predefined failure value otherwise; 3. A method according to claim 1 or 2, comprising performing one or more.   A program that causes a computer to execute the method steps of the method according to any one of claims 1 to 13. A system for implementing a bit array in a cache line, comprising a memory storage and a controller,
-Configuring the bit array in the cache line, the bit array including an array of bits, the configuring further comprising defining a value for each bit in the bit array; Configuring the above;
Receiving a request for an operation on the bit array by the controller, the request indicating a location of the cache line in the memory storage and information specifying the request;
Using the information to identify one or more actions on the bit array for the operation, wherein the one or more actions are encoded in the controller;
A system configured to perform the request by performing the one or more encoded actions in response to receiving the request.

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