JP6331674B2 - Photoelectric conversion element, image reading apparatus, and image forming apparatus - Google Patents

Description

  The present invention relates to a photoelectric conversion element, an image reading apparatus, and an image forming apparatus.

  Conventionally, a CCD (Charge Coupled Device) has been used as a photoelectric conversion element in the scanner, but in recent years, a CMOS linear sensor has attracted attention due to a demand for higher speed. A CMOS linear sensor is the same as a CCD in that incident light is photoelectrically converted by a photodiode, but differs in that charge-voltage conversion is performed near a pixel and output to a subsequent stage. In addition, since the CMOS linear sensor can use a CMOS process, it can incorporate an ADC (Analog to Digital Converter) and a high-speed logic circuit, and can be said to be more advantageous than a CCD in terms of high-speed performance.

  However, when performing a high-speed operation, the CMOS linear sensor is required to shorten not only a simple processing speed but also a charge accumulation time (line cycle). This is because in order to increase the speed of the scanner, it is necessary to shorten the scanning speed per unit time, that is, the accumulation time if the resolution is the same. In PD (Photo-Diode), the amount of charge accumulated by the irradiated light is determined, but the sensitivity and S / N decrease as the charge accumulation time is shortened. In particular, in order to compensate for the S / N, there is a problem that it is absolutely necessary to increase the amount of light.

  For example, Patent Document 1 discloses that the same color is read in subject light at different timings. For example, Patent Document 1 reads a plurality of pixel columns and the pixels in each pixel column have different reading timings. An accumulation unit that accumulates and accumulates signal charges due to exposure of an object, and accumulates each signal charge transferred from the accumulation unit for conversion into a signal voltage, and TDI (Time Delay Integration) ) A solid-state imaging device using an operation is disclosed.

  However, since the conventional TDI type CMOS linear sensor is configured to accumulate only the signal components of each pixel, even if CDS (Correlated Double Sampling) is performed, FPN (Fixed-Pattern-Noise) is sufficient. There was a problem that could not be removed.

  The present invention has been made in view of the above, and an object of the present invention is to provide a photoelectric conversion element, an image reading apparatus, and an image forming apparatus that can improve image reading accuracy.

  In order to solve the above-described problems and achieve the object, the present invention provides a plurality of light-receiving elements that constitute a plurality of pixel rows for each color of light received from a subject and perform photoelectric conversion provided in the pixels. A plurality of first transmission circuits that transmit reference levels output after the pixels are reset, and a plurality of second transmission circuits that transmit signal levels output by the light receiving elements respectively receiving light and performing photoelectric conversion. The reference level transmitted by the first transmission circuit is reset for each of the pixels that are to receive light from the transmission circuit and light from substantially the same position in the subject at different times, and is added for each color. An adder that photoelectrically converts each of the light receiving elements that receive light from a position at different times and adds the signal level transmitted by the second transmission circuit for each color; The difference between the signal level added by the adder for each color and the reference level added by the adder for each color for the plurality of pixels receiving light from substantially the same position in the subject is A plurality of subtraction units that calculate for each color, and the first transmission circuit and the second transmission circuit have substantially the same configuration.

  According to the present invention, it is possible to improve the image reading accuracy.

FIG. 1 is a diagram illustrating a configuration example of an image reading apparatus according to an embodiment. FIG. 2 is a block diagram illustrating a configuration example of the photoelectric conversion element. FIG. 3 is a block diagram showing an outline of the configuration of the first embodiment of the conversion processing unit. FIG. 4 is a diagram illustrating a plurality of photodiodes included in the conversion processing unit and the periphery thereof. FIG. 5 is a timing chart showing the operation of the first embodiment of the conversion processing unit. FIG. 6 is a block diagram showing an outline of the configuration of the second embodiment of the conversion processing unit. FIG. 7 is a diagram illustrating a plurality of photodiodes included in the conversion processing unit and the periphery thereof. FIG. 8 is a diagram illustrating a configuration example of a delay memory included in the delay memory column. FIG. 9 is a diagram illustrating a configuration example of the addition unit included in the addition unit sequence. FIG. 10 is a timing chart showing the operation of the second embodiment of the conversion processing unit. FIG. 11 is a diagram illustrating a configuration example of a first modification of the delay memory. FIG. 12 is a timing chart illustrating an operation example of the conversion processing unit including the first modification of the delay memory. FIG. 13 is a diagram illustrating a configuration example of a second modification of the delay memory. FIG. 14 is a timing chart illustrating an operation example of the conversion processing unit including the second modification of the delay memory. FIG. 15 is a block diagram showing an outline of the configuration of the third embodiment of the conversion processing unit. FIG. 16 is a diagram illustrating a configuration example of an analog memory unit included in an analog memory column. FIG. 17 is a diagram illustrating a configuration example of a delay memory included in the delay memory sequence. FIG. 18 is a diagram illustrating a configuration example of a calculation unit included in the calculation unit sequence. FIG. 19 is a timing chart showing the operation of the third embodiment of the conversion processing unit. FIG. 20 is a diagram illustrating an outline of an image forming apparatus including an image reading apparatus having a photoelectric conversion element.

  Hereinafter, an image reading apparatus according to an embodiment will be described with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a configuration example of an image reading apparatus according to an embodiment. As illustrated in FIG. 1, the image reading apparatus includes a sensor substrate 101 including a photoelectric conversion element 10, a lens unit 102, a first carriage 104, and a second carriage 106 in a main body 100. The photoelectric conversion element 10 is a CMOS color linear sensor, for example. The first carriage 104 includes an LED (Light Emitting Diode) light source 108 and a mirror 110. The second carriage 106 has mirrors 112 and 114. Further, the image reading apparatus is provided with a contact glass 116 and a reference white plate 118 on the upper surface.

  In the image reading apparatus, in the reading operation, the LED light source 108 emits light upward while the first carriage 104 and the second carriage 106 move from the standby position (home position) in the sub-scanning direction. Then, the first carriage 104 and the second carriage 106 form an image of the reflected light from the document on the photoelectric conversion element 10 via the lens unit 102.

  Further, when the power is turned on, the image reading apparatus reads the reflected light from the reference white plate 118 and sets the reference. That is, the image reading apparatus performs gain adjustment by moving the first carriage 104 directly below the reference white plate 118, turning on the LED light source 108, and forming an image of the reflected light from the reference white plate 118 on the photoelectric conversion element 10. .

  Next, the photoelectric conversion element 10 will be described in detail. FIG. 2 is a block diagram illustrating a configuration example of the photoelectric conversion element 10. As illustrated in FIG. 2, the photoelectric conversion element 10 includes, for example, a conversion processing unit 12, a timing control unit (Timing Generator; TG) 14, and a parallel-serial conversion unit (PS) 16.

  When the conversion processing unit 12 receives reflected light from a document by a plurality of pixels (not shown) arranged in one direction (for example, the main scanning direction of the document) for each RGB color, the conversion processing unit 12 performs photoelectric conversion for each RGB color. The image data for each color is output in parallel as digital data in the main scanning direction.

  Further, the conversion processing unit 12 has a TDI (Time Delay Integration) function described in detail with reference to FIG. TDI is a method that is mainly used in linear sensors, photoelectrically converts (reads) reflected light from the same subject (the same position in the subject) with a plurality of pixel columns, and adds (integrates) the results. That is, TDI enables higher sensitivity and higher S / N than the number of pixel columns.

  However, in TDI, it is important to read the same subject with a plurality of pixel columns. For example, in TDI in a CCD, reading of the same subject and addition of charges are realized by making the reading speed of the subject the same as the transfer speed of transferring the accumulated charge to the next line. Charges added at this time are called “time delay integration” because delayed charges are added.

  In general, the CCD sequentially transfers the charges to the subsequent pixel column and adds the charges. On the other hand, the CMOS sensor converts the charges into a voltage near the pixels. It cannot be adopted.

  The timing control unit 14 outputs each control signal for controlling the operation timing of the conversion processing unit 12 and the parallel / serial conversion unit 16. The parallel-serial conversion unit 16 converts the digital data output in parallel by the conversion processing unit 12 into serial data and outputs the serial data.

(First Example of Conversion Processing Unit 12)
Next, a first embodiment of the conversion processing unit 12 will be described with reference to FIGS. FIG. 3 is a block diagram showing an outline of the configuration of the conversion processing unit 12 according to the first embodiment. FIG. 4 is a diagram illustrating a plurality of photodiodes (PD: light receiving elements) included in the conversion processing unit 12 and the periphery thereof. As illustrated in FIG. 3, the conversion processing unit 12 includes a first photoelectric conversion unit 120a to a sixth photoelectric conversion unit 120f, a first pixel circuit column 122a to a sixth pixel circuit column 122f, an addition unit column 124, and a common pixel circuit column. 126, and a subtractor sequence (CDS sequence) 128.

  In the first photoelectric conversion unit 120a (FIG. 3), for example, about 7000 photodiodes (PD1: FIG. 4) that are provided with an R filter (not shown) and perform photoelectric conversion are arranged in one direction (main scanning direction). The second photoelectric conversion unit 120b is arranged in parallel to the first photoelectric conversion unit 120a, and an R filter (not shown) is provided, and about 7000 photodiodes (PD2) for photoelectric conversion are arranged in one direction, for example. Yes. In this manner, the conversion processing unit 12 includes photodiodes that receive one color (for example, R) arranged in, for example, two rows. Hereinafter, for the same configuration (or signal) arranged in two columns such as photodiodes, 1 is added to the end of the configuration included in the first column, and 2 is added to the end of the configuration included in the second column. May be distinguished. Note that the number of columns for each color is not limited to two.

  For example, when the photoelectric conversion element 10 reads the subject at an equal magnification in the image reading apparatus shown in FIG. 1, each PD 2 reads the same position as the position on the subject read by the opposing PD 1 one cycle before. In addition, an interval is provided for each PD1. That is, PD1 and PD2 shown in FIG. 4 receive light from the same position on the subject.

  In the first pixel circuit row 122a (FIG. 3), for example, about 7000 pixel circuits 200a (FIG. 4) that transmit signals photoelectrically converted by the PDs 1 are arranged in one direction (main scanning direction). The pixel circuit 200a includes a transfer transistor TQ1 that transfers charges. In the second pixel circuit array 122b, for example, about 7000 pixel circuits 200b that transmit signals photoelectrically converted by the PDs 2 are arranged in one direction. Each pixel circuit 200b includes a transfer transistor TQ2 that transfers charges.

  Here, the PD 1 and the pixel circuit 200a illustrated in FIG. 4 constitute a pixel 20a that photoelectrically converts R light. Further, the PD 2 and the pixel circuit 200b illustrated in FIG. 4 constitute a pixel 20b that photoelectrically converts R light. In addition, the pixel 20a may be described as R1 as one pixel that the conversion processing unit 12 includes and photoelectrically converts R light. In addition, the pixel 20b may be denoted as R2 as one pixel that the conversion processing unit 12 includes to photoelectrically convert R light. That is, the conversion processing unit 12 includes approximately 7000 pixels R1 and R2 that photoelectrically convert R light.

  For example, about 7000 addition units 204 are arranged in one direction (main scanning direction) in the addition unit row 124. Each adding unit 204 includes a transistor (switch) HQ and a capacitor CX. The capacitance CX is added by accumulating charges photoelectrically converted by PD1 and PD2, respectively. Note that the capacitor CX performs charge accumulation and transfer according to the operation of the switch HQ.

  In the common pixel circuit row 126, for example, about 7000 common pixel circuits 202 are arranged in one direction (main scanning direction). Each common pixel circuit 202 includes a floating diffusion (FD), a reset transistor RQ, a source follower SF, and a color selection switch SQ. The reset transistor RQ resets the FD. The source follower SF buffers the signal and outputs it to the subsequent stage. The color selection switch SQ selects the color of the signal to be output. Each common pixel circuit 202 converts the charge (signal level) accumulated in the capacitor CX into a voltage and transmits it, and resets the FD.

  In the subtractor column 128, for example, about 7000 subtractors 206 are arranged in one direction (main scanning direction). Each subtraction unit 206 is a correlated double sampling (CDS). For example, each subtraction unit 206 includes three memories (capacitors) (not shown), and calculates a difference between a signal level corresponding to the read light amount (charge accumulated in the capacitor CX) and a reset level at which the FD is reset. The subtraction is sequentially performed for each color, and the subtraction result (difference) is output to the parallel-serial conversion unit 16 for each color.

  The third photoelectric conversion unit 120c and the fifth photoelectric conversion unit 120e (FIG. 3) are configured in the same manner as the first photoelectric conversion unit 120a except that the provided filters are G and B, respectively. The fourth photoelectric conversion unit 120d and the sixth photoelectric conversion unit 120f are configured in the same manner as the second photoelectric conversion unit 120b except that the provided filters are G and B, respectively.

  The third pixel circuit column 122c and the fifth pixel circuit column 122e are configured similarly to the first pixel circuit column 122a. The fourth pixel circuit column 122d and the sixth pixel circuit column 122f are configured in the same manner as the second pixel circuit column 122b. That is, the conversion processing unit 12 includes approximately 7000 pixels G1 and G2 that photoelectrically convert G light, and approximately 7000 pixels B1 and B2 that photoelectrically convert B light, respectively.

  The conversion processing unit 12 includes a common pixel circuit 202 and an addition unit 204 for each set of pixels G1 and G2, and includes a common pixel circuit 202 and an addition unit 204 for each set of pixels B1 and B2. The conversion processing unit 12 includes six pixels R1, R2, G1, G2, B1, and B2 that receive light from the same position on the subject in one column, and a subtraction unit 206 is provided for each column. It has a configuration.

  FIG. 5 is a timing chart illustrating the operation of the conversion processing unit 12 according to the first embodiment. As shown in FIG. 5, the conversion processing unit 12 first stores the charge from the PD1 in the capacitor CX when the control signal SH is turned on and the control signal T1 is turned on. Next, when the control signal T2 is turned ON, the conversion processing unit 12 accumulates the charge from the PD2 in the capacitor CX. Here, the capacitor CX adds and accumulates the charge of the pixel R1 and the charge of the pixel R2.

  In the common pixel circuit 202, after the capacitor CX adds the charge, the control signal SH is turned off, the control signal S is turned on, and the color selection switch SQ is turned on, so that the control signal RS is turned on. Then, the FD is reset. The reset level for each color in the conversion processing unit 12 is held in a memory (not shown) of the subtraction unit 206.

  Thereafter, when the control signal SH is turned ON, the conversion processing unit 12 transfers the charge accumulated by the capacitor CX to the FD, and the signal obtained by the FD charge-voltage conversion is input to the subtraction unit 206 as a signal level. Is done. The subtraction unit 206 performs subtraction for calculating the difference between the signal level and the reset level, and outputs the subtraction result to the parallel-serial conversion unit 16.

  Thus, the photoelectric conversion element 10 having the first embodiment of the conversion processing unit 12 realizes TDI by including the addition unit 204 that adds (accumulates) signals. However, the photoelectric conversion element 10 having the first embodiment of the conversion processing unit 12 may not be able to sufficiently remove fixed pattern noise (FPN) which is a problem in the CMOS sensor. This is because the reset level used by the subtraction unit 206 is reset noise when the FD is reset, whereas the signal level is obtained by adding the noise and offset of the switch HQ of the addition unit 204 to the reset noise of the FD. is there. That is, in the photoelectric conversion element 10 having the first embodiment of the conversion processing unit 12, the FPN by the addition unit 204 provided for TDI cannot be removed by the subtraction unit 206.

(Second Example of Conversion Processing Unit 12)
Next, a second embodiment (conversion processing unit 12a) of the conversion processing unit 12 will be described with reference to FIGS. FIG. 6 is a block diagram showing an outline of the configuration of the second embodiment (conversion processing unit 12a) of the conversion processing unit 12. As shown in FIG. FIG. 7 is a diagram illustrating a plurality of photodiodes (PD: light receiving elements) included in the conversion processing unit 12a and the periphery thereof. As illustrated in FIG. 6, the conversion processing unit 12a includes a first photoelectric conversion unit 300a to a sixth photoelectric conversion unit 300f, a first pixel circuit column 302a to a sixth pixel circuit column 302f, a delay memory column 303, and an addition unit column 304. , An ADC column 305, and a subtraction unit column (CDS column) 306.

  In the first photoelectric conversion unit 300a (FIG. 6), for example, about 7000 photodiodes (PD1: FIG. 7) that are provided with an R filter (not shown) and perform photoelectric conversion are arranged in one direction (main scanning direction). The second photoelectric conversion unit 300b is arranged in parallel to the first photoelectric conversion unit 300a, and is provided with an R filter (not shown), and, for example, about 7000 photodiodes (PD2) that perform photoelectric conversion are arranged in one direction. Yes. Thus, in the conversion processing unit 12a, photodiodes that receive one color (for example, R) are arranged in, for example, two rows. Note that the number of columns for each color is not limited to two.

  For example, when the photoelectric conversion element 10 reads the subject at an equal magnification in the image reading apparatus shown in FIG. 1, each PD 2 reads the same position as the position on the subject read by the opposing PD 1 one cycle before. In addition, an interval is provided for each PD1. That is, PD1 and PD2 shown in FIG. 7 receive light from the same position on the subject.

  In the first pixel circuit row 302a (FIG. 6), for example, about 7000 pixel circuits 400a (FIG. 7) that transmit signals photoelectrically converted by the PDs 1 are arranged in one direction (main scanning direction). The pixel circuit 400a includes a transfer transistor TQ1, a floating diffusion 1 (FD1), a reset transistor RQ1, and a source follower SF1. The reset transistor RQ1 resets FD1. The source follower SF1 buffers the signal and outputs it to the subsequent stage. Then, the pixel circuit 400a converts the charge (signal level) photoelectrically converted by the PD1 into a voltage and transmits the voltage, and transmits a reset level obtained by resetting the FD1.

  In the second pixel circuit row 302b, for example, about 7000 pixel circuits 400b that transmit the signals photoelectrically converted by the PDs 2 are arranged in one direction (main scanning direction). The pixel circuit 400b includes a transfer transistor TQ2, a floating diffusion 2 (FD2), a reset transistor RQ2, and a source follower SF2. The reset transistor RQ2 resets FD2. The source follower SF2 buffers the signal and outputs it to the subsequent stage. The pixel circuit 400b converts the charge (signal level) photoelectrically converted by the PD 2 into a voltage and transmits the voltage, and also transmits a reset level after resetting the FD2.

  Here, the PD 1 and the pixel circuit 400a illustrated in FIG. 7 constitute a pixel 40a that photoelectrically converts R light. Further, the PD 2 and the pixel circuit 400b illustrated in FIG. 7 constitute a pixel 40b that photoelectrically converts R light. In addition, the pixel 40a may be referred to as R1 as one pixel that is included in the conversion processing unit 12a and photoelectrically converts R light. In addition, the pixel 40b may be described as R2 as one pixel that is included in the conversion processing unit 12a and photoelectrically converts R light. That is, the conversion processing unit 12a includes approximately 7000 pixels R1 and R2 that photoelectrically convert R light.

  The third photoelectric conversion unit 300c and the fifth photoelectric conversion unit 300e (FIG. 6) are configured in the same manner as the first photoelectric conversion unit 300a except that the provided filters are G and B, respectively. The fourth photoelectric conversion unit 300d and the sixth photoelectric conversion unit 300f are configured in the same manner as the second photoelectric conversion unit 300b except that the provided filters are G and B, respectively.

  The third pixel circuit column 302c and the fifth pixel circuit column 302e are configured in the same manner as the first pixel circuit column 302a. The fourth pixel circuit column 302d and the sixth pixel circuit column 302f are configured in the same manner as the second pixel circuit column 302b. That is, the conversion processing unit 12a includes approximately 7000 pixels G1 and G2 that photoelectrically convert G light, and approximately 7000 pixels B1 and B2 that photoelectrically convert B light, respectively. Here, signals output from the pixels R1 and R2 are PIXOUT_R1 and PIXOUT_R2, respectively. The signals output from the pixels G1 and G2 are PIXOUT_G1 and PIXOUT_G2, respectively, and the signals output from the pixels B1 and B2 are PIXOUT_B1 and PIXOUT_B2, respectively.

  FIG. 8 is a diagram illustrating a configuration example of the delay memory 403 included in the delay memory column 303. In the delay memory column 303, for example, about 7000 delay memories 403 are arranged in one direction (main scanning direction). Each delay memory 403 is configured to receive PIXOUT_R1, PIXOUT_R2, PIXOUT_G1, PIXOUT_G2, PIXOUT_B1, and PIXOUT_B2, respectively.

  The delay memory 403 delays the reset level and signal level of each of the six pixels R1, R2, G1, G2, B1, and B2 that receive light from the same position on the subject in accordance with the control of the timing control unit 14. Hold to communicate. Further, since the delay memory 403 holds the signals of the pixels R1, R2, G1, G2, B1, and B2 for each pixel, simultaneous exposure (global shutter) is also possible.

  Also in the conversion processing unit 12a, as described above, when a plurality of pixel columns of the same color (for example, the column of the pixel R1 and the column of the pixel R2) are physically shifted at intervals corresponding to one line cycle, At the same magnification reading, the position shifted by one line on the document surface is read. Therefore, at the same time, the reading positions of the pixel R1 and the pixel R2 are different. That is, after one line period when the pixel R1 reads an arbitrary reading position, the pixel R2 also reads the same reading position. Therefore, the delay memory 403 delays the signal so that the signal of the pixel R1 is delayed by one line period and added to the signal of the pixel R2. In TDI to which signals that are not from pixels that receive light from the same subject are added, effects of improving sensitivity and S / N can be obtained, but resolution and MTF (Modulation Transfer Function) are deteriorated.

  As shown in FIG. 8, the delay memory 403 is configured by combining a plurality of capacitors (storage units), switches, and buffers. The delay memory 403 is provided with reset level analog memories Crr1 and Crr2 and signal level analog memories Csr1 and Csr2 for PIXOUT_R1 and PIXOUT_R2, for example. The reset level analog memories Crr1 and Crr2 accumulate and hold signals via a switch that operates in accordance with the control signal WR. The signal level analog memories Csr1 and Csr2 accumulate and hold (store) signals through a switch that operates in accordance with the control signal WS.

  Further, a switch that operates according to the control signal TD and a buffer b are connected to Crr1 and Csr1 that hold the signal of PIXOUT_R1, and extra memories Cxrr1 and Cxsr1 are provided on the output side of the buffer b, respectively. . The extra memories Cxrr1 and Cxsr1 respectively delay the signal from the pixel R1 by one line period. That is, the extra memory Cxrr1 resets the reset level output by the FD1 corresponding to the PD1 until the reset level output by the FD2 corresponding to the PD2 that should receive light from substantially the same position on the subject is stored in the analog memory Crr2. Remember the level. Further, the extra memory Cxsr1 stores the signal level output by the PD1 until the signal level output by the PD2 that lastly received light from substantially the same position in the subject is stored in the analog memory Csr2.

  The control signal TD is a signal for transferring (moving) signals from the analog memories Crr1 and Csr1 to the extra memories Cxrr1 and Cxsr1, respectively. Signals held in the extra memories Cxrr1 and Cxsr1 and the analog memories Crr2 and Csr2 (that is, the signal of the pixel R1 delayed by one line period with respect to the pixel R2 (the signal of the pixel R1 one line before) and the signal of the pixel R2) Are sequentially read out in synchronization with the read control signals RDR_R1, RDR_R2, RDS_R1, RDS_R2, and output as an output signal RDOUT.

  The delay memory 403 has a configuration that delays PIXOUT_G1, PIXOUT_G2, PIXOUT_B1, and PIXOUT_B2 in the same manner as the delay for PIXOUT_R1 and PIXOUT_R2.

  Here, the analog memory Crr1, the buffer b, the extra memory Cxrr1, and the like constitute a transmission circuit that transmits the reset level of the pixel R1 to the adding unit 404. The analog memory Csr1, the buffer b, the extra memory Cxsr1, and the like constitute a transmission circuit that transmits the signal level of the PD1 of the pixel R1 to the adding unit 404. The analog memory Crr2 is a transmission circuit that transmits the reset level of the pixel R2, and the analog memory Csr2 is a transmission circuit that transmits the signal level of the PD2 of the pixel R2.

  Note that the delay memory 403 is not limited to delaying the signal of the pixel R1 with respect to the signal of the pixel R2, and the order may be reversed. Further, the delay time of the delay memory 403 is not limited to one line period, but for example, an extra memory corresponding to the delay time may be provided and the delay may be delayed by two line periods or more.

  FIG. 9 is a diagram illustrating a configuration example of the addition unit 404 included in the addition unit sequence 304. In the addition unit row 304, for example, about 7000 addition units 404 are arranged in one direction (main scanning direction). Each adding unit 404 is configured by combining two capacitors C1 and C2 having the same number as the number of pixel columns for each color and a plurality of switches, and sequentially outputting an output signal RDOUT (reset level and output signal) output from the delay memory 403. The signal levels are sequentially added for each color.

  For example, the adding unit 404 holds the reset level of the pixel R1 read from the delay memory 403 in the capacitor C1 according to the control signals SEL1 and SEL2, and sets the reset level of the pixel R2 according to the control signals SEL1 and SEL2 Hold at C2. Then, the adding unit 404 adds the reset level of the capacitor C1 and the reset level of the capacitor C2 (voltage addition) by connecting the capacitors C1 and C2 in series according to the control signal ADD, and outputs the result. Similarly, the addition unit 404 sequentially adds and outputs the R signal level, the G and B reset levels, and the signal level.

  In the ADC row 305, for example, about 7000 AD converters (not shown) for AD-converting the addition results sequentially output by the adders 404 are arranged in one direction (main scanning direction). For example, about 7000 PGAs (Programmable Gain Amplifiers) for amplifying analog signals may be provided in the preceding stage of the ADC row 305.

  In the subtractor column 306, for example, about 7000 D-CDS circuits (digital CDS circuits: not shown) that perform CDS with digital values are arranged in one direction (main scanning direction). Each D-CDS circuit includes a memory (not shown), sequentially performs subtraction for each color to calculate the difference between the signal level output from the ADC string 305 and the reset level, and parallelizes the subtraction result (difference) for each color. The data is output to the serial conversion unit 16. Note that the subtraction unit string 306 can also remove the FPN in the ADC string 305. However, the subtraction unit sequence 306 may be configured to perform CDS using an analog value.

  FIG. 10 is a timing chart showing the operation of the second embodiment (conversion processing unit 12a) of the conversion processing unit 12. In FIG. 10, the operations of the ADC column 305 and the subtraction unit column 306 are not shown.

  As shown in FIG. 10, in the conversion processing unit 12a, for example, when the control signals RS1 and RS2 are first turned on for the pixels R1 and R2, FD1 and FD2 are respectively reset. When the control signal WR is turned ON, the reset levels of the pixels R1 and R2 are held in the analog memories Crr1 and Crr2.

  Next, when the control signals T1 and T2 are turned on to transfer the charges photoelectrically converted by the PD1 and PD2 to the reset FD1 and FD2, and the control signal WS is turned on, the pixels R1 and R2 are respectively turned on. Are held in the analog memories Csr1 and Csr2, respectively.

  The reset level and signal level of the pixel R1 transferred to and held in the extra memories Cxrr1 and Cxsr1, and the reset level and signal level of the pixel R2 held in the analog memories Crr2 and Csr2 are the control signals RDR_R1, RDR_R2, Data are sequentially read in synchronization with RDS_R1 and RDS_R2. Here, the reset level and the signal level are sequentially read out for each color as RDR_R1 → RDR_R2 → RDS_R1 → RDS_R2 → RDR_G1 → RDR_G2 →.

  When each signal (each RDOUT) is read from the delay memory 403, the addition unit 404 switches the control signals SEL1 and SEL2 according to the control of the timing control unit 14. The reset level and signal level of the pixels R1, G1, and B1 are sequentially held in the capacitor C1, and the reset level and signal level of the pixels R2, G2, and B2 are sequentially held in the capacitor C2. The reset level and the signal level held in the capacitors C1 and C2 are added (voltage addition) in the order in which they are held according to the control signal ADD, and are output.

  When the reset levels (or signal levels) of the pixels R1, G1, and B1 are sequentially held in the capacitor C1, the control signal TD is turned on to hold the analog memory Crr1 (or the analog memory Csr1). The reset level (or signal level) that has been transferred is transferred to the extra memory Cxrr1 (or the extra memory Cxsr1), and is read by the read operation of the next line. Note that the control signals RS1 and RS2 and the control signals T1 and T2 are simultaneously turned on to realize all-pixel simultaneous exposure.

(First Modification of Delay Memory 403)
FIG. 11 is a diagram illustrating a configuration example of a first modification (delay memory 413) of the delay memory 403. In the delay memory 403 shown in FIG. 8, the extra memories Cxrr1 and Cxsr1 are provided only on the pixel R1 side. The delay memory 403 has no problem since the reset level and the signal level are transmitted by the same configuration from the viewpoint of FPN. However, as described above, in performing TDI, it is important to add the signal levels of light received from the same subject. Since the delay memory 403 has a different configuration on the pixel R1 side and the pixel R2 side, it is difficult to obtain the same characteristics for each pixel. That is, there are cases where the accuracy of addition in TDI is not always sufficient.

  The delay memory 413 illustrated in FIG. 11 is provided with extra memories Cxrr2 and Cxsr2 not only on the pixels R1, G1, and B1 sides but also on the pixels R2, G2, and B2 sides. Here, the analog memory Crr2, the buffer b, the extra memory Cxrr2, and the like constitute a transmission circuit that transmits the reset level of the FD2 corresponding to the PD2 of the pixel R2. In addition, the analog memory Csr2, the buffer b, the extra memory Cxsr2, and the like constitute a transmission circuit that transmits the signal level of the PD2 of the pixel R2.

  Thereby, the delay memory 413 has the same circuit configuration for each color on the pixel R1, G1, B1 side and the pixel R2, G2, B2 side, so that the addition accuracy in TDI can be increased.

  FIG. 12 is a timing chart illustrating an operation example of the conversion processing unit 12a including the first modification (delay memory 413) of the delay memory 403. In the timing chart shown in FIG. 12, a control signal TD2 for transferring a reset level and a signal level to the extra memories Cxrr2 and Cxsr2 for the pixels R2, G2, and B2 is added to the timing chart shown in FIG. Note that the control signal TD1 in FIG. 12 is substantially the same as the control signal TD in FIG.

  As shown in FIG. 12, in the delay memory 413, the control signal TD2 is turned on immediately after the control signal WR for holding the signal level in the analog memory Crr2 is turned on (without delay for one line period). The reset level and the signal level are transferred to the extra memories Cxrr2 and Cxsr2 for the pixels R2, G2, and B2. The delay memory 413 transfers the reset level and the signal level with the same circuit configuration as the pixel R1 side while setting the delay to 0 by turning ON the control signal TD2.

(Second Modification of Delay Memory 403)
FIG. 13 is a diagram illustrating a configuration example of a second modification (delay memory 423) of the delay memory 403. In the conversion processing unit 12a shown in FIG. 6, a delay memory column 303 and an adding unit column 304 are provided independently. On the other hand, the delay memory 423 is configured to serve both as the function of the delay memory column 303 and the function of the adder column 304.

  Specifically, in the delay memory 423, a switch that operates according to the control signal TD1 or the control signal TD2 is added to the output side of the buffer b with respect to the delay memory 413 illustrated in FIG. Further, in the delay memory 423, a switch that operates according to the control signal TD2 and a switch that operates according to the control signal RDR_R or the control signal RDS_R are added to the GND side of the extra memories Cxrr2 and Cxsr2.

  The switch operated by the control signal RDR_R is a switch that connects the buffer b side of the extra memory Cxrr1 and the GND side of the extra memory Cxrr2. The switch operated by the control signal RDS_R is a switch for connecting the buffer b side of the extra memory Cxsr1 and the GND side of the extra memory Cxsr2. The delay memory 423 has the same configuration as that of R for G and B.

  The delay memory 423 adds a reset level by connecting the extra memory Cxrr1 and the extra memory Cxrr2 in series. Further, the delay memory 423 adds the signal level by connecting the extra memory Cxsr1 and the extra memory Cxsr2 which are capacitive loads in series.

  That is, when the conversion processing unit 12a includes the delay memory 423, it is not necessary to provide the addition unit string 304. Further, the output signal from the delay memory 423 becomes the reset level and the signal level (that is, six) after the addition of RGB, which is ½ of the number of signals of the delay memory 413. Further, the number of readout switches from the delay memory 423 is two for each color, which is ½ of the number of readout switches in the delay memory 413.

  FIG. 14 is a timing chart illustrating an operation example of the conversion processing unit 12a including the second modification (delay memory 423) of the delay memory 403. The timing chart shown in FIG. 14 differs from the timing chart shown in FIG. 12 in that there are no control signals SEL1, SEL2, and ADD. The delay memory 423 holds signals in the analog memories Crr1, Csr1, Crr2, Csr2 or the extra memories Cxrr1, Cxsr1, Cxrr2, and Cxsr2 for addition, and the addition result is read by the control signals RDR_R and RDS_R.

(Third embodiment of the conversion processor 12)
Next, a third embodiment (conversion processing unit 12b) of the conversion processing unit 12 will be described with reference to FIGS. FIG. 15 is a block diagram showing an outline of the configuration of the third embodiment (conversion processing unit 12b) of the conversion processing unit 12. As shown in FIG. As illustrated in FIG. 15, the conversion processing unit 12b includes a first photoelectric conversion unit 300a to a sixth photoelectric conversion unit 300f, a first pixel circuit column 302a to a sixth pixel circuit column 302f, an analog memory column 307, an ADC column 308, It has a subtraction unit sequence (CDS sequence) 309, a delay memory sequence 310, and an operation unit sequence 312. Note that, among the components of the conversion processing unit 12b illustrated in FIG. 15, the same components as those illustrated in the conversion processing unit 12a (FIG. 6) are denoted by the same reference numerals.

  FIG. 16 is a diagram illustrating a configuration example of the analog memory unit 420 included in the analog memory column 307. In the analog memory column 307, for example, about 7000 analog memory units 420 are arranged in one direction (main scanning direction). Each analog memory unit 420 is configured to receive PIXOUT_R1, PIXOUT_R2, PIXOUT_G1, PIXOUT_G2, PIXOUT_B1, and PIXOUT_B2, respectively.

  The analog memory unit 420 has a configuration in which the extra memories Cxrr1, Cxrr2, Cxsr1, and Cxsr2 are deleted from the delay memory 413 illustrated in FIG. 11, and the capacity, switch, buffer b, and control signals thereof are reduced. . The analog memory unit 420 does not need a function of delaying a signal for TDI, and has a function of holding a signal to enable simultaneous exposure. Here, each of the analog memories Crr1 and Crr2 is a transmission circuit that transmits a reset level. The analog memories Csr1 and Csr2 are transmission circuits that transmit signal levels.

  In the ADC row 308, for example, about 7000 AD converters (not shown) for AD-converting signals sequentially output from the analog memory unit 420 are arranged in one direction (main scanning direction).

  In the subtractor column 309, for example, about 7000 D-CDS circuits (digital CDS circuits: not shown) that perform CDS with digital values are arranged in one direction (main scanning direction). Each D-CDS circuit includes a memory (not shown), sequentially performs subtraction for each color to calculate the difference between the signal level output from the ADC string 308 and the reset level, and parallelizes the subtraction result (difference) for each color. The data is output to the serial conversion unit 16. Note that the subtraction unit string 309 can also remove the FPN in the ADC string 308.

  FIG. 17 is a diagram illustrating a configuration example of the delay memory 422 included in the delay memory column 310. In the delay memory column 310, for example, about 7000 delay memories 422 are arranged in one direction (main scanning direction). As illustrated in FIG. 17, the delay memory 422 includes line memories (storage units) 430 and 432 that hold signals for each color. The line memory 430 first holds data as R (0), G (0), and B (0) for each color. The line memory 432 holds the data one line before transferred from the line memory 430 as R (1), G (1), and B (1) for each color.

  Here, the line memories 430 and 432 first hold the data of the pixels R1, G1, and B1, and then hold the data of the pixels R2, G2, and B2. That is, the data of the pixels R2, G2, and B2 on the current line and the data of the pixels R1, G1, and B1 one line before are read out simultaneously. The line memories 430 and 432 may be configured by a latch or the like.

  FIG. 18 is a diagram illustrating a configuration example of the calculation unit 425 included in the calculation unit sequence 312. For example, about 7000 calculation units 425 are arranged in one direction (main scanning direction) in the calculation unit row 312. As illustrated in FIG. 18, the calculation unit 425 includes an addition unit 426, an averaging unit 427, and a selection unit 428.

  The adder 426 adds the data of the pixels R1, G1, and B1 one line before and the data of the pixels R2, G2, and B2 of the current line, respectively. That is, the adding unit 426 adds signals corresponding to light from the same subject for each color. The averaging unit 427 calculates average values of the data of the pixels R1, G1, and B1 of the previous line and the data of the pixels R2, G2, and B2 of the current line, respectively. That is, the averaging unit 427 calculates an average value of signals corresponding to light from the same subject for each color. The selection unit 428 selects and outputs either the result added by the addition unit 426 or the result calculated by the averaging unit 427 according to the control of the timing control unit 14.

  Therefore, the conversion processing unit 12b makes it possible to switch operation modes such as a high sensitivity mode (signal increase) by signal addition and a high S / N mode (noise reduction) by signal averaging.

  In this way, the conversion processing unit 12b performs the same processing for each pixel until the subtraction unit sequence 309 performs digital CDS, and performs TDI with a digital value, so that the configuration is simpler than that of the conversion processing unit 12a. The conversion processing unit 12b has a reduced circuit scale because the number of capacities for delaying data is reduced. Further, since the conversion processing unit 12b performs processing such as TDI using a digital value, the influence of noise can be reduced.

  FIG. 19 is a timing chart showing the operation of the third example (conversion processing unit 12b) of the conversion processing unit 12. The conversion processing unit 12b is substantially the same as the conversion processing unit 12a in the operations from RS1 to RDS_R2..., And the signals of all the pixels are sequentially read from the analog memory column 307.

  The signal read from the analog memory column 307 is sequentially AD converted by the ADC column 308, and the difference data between the signal level and the reset level is calculated by the subtraction unit column 309. In FIG. 19, it is described that the signal is read out from the analog memory column 307 and simultaneously AD-converted to perform CDS.

  When the data of the pixels R1, G1, and B1 one line before output from the subtraction unit column 309 are input to the delay memory column 310, the control signals WM_R1, WM_G1, and WM_B1 in the delay memory 422 are turned on, and the line memory 430 The data of the pixels R1, G1, and B1 are held in the memory.

  Next, when the data of the pixels R2, G2, and B2 are input to the delay memory column 310, RM_RGB2 in the delay memory 422 is turned ON, and the input data is read as it is. At this time, the control signals RM_R1, RM_G1, and RM_B1 are turned ON, and the transferred data of the previous line is simultaneously read from the line memory 432.

  When the data held in the line memory 432 is read, the control signal TM is turned ON, and the data held in the line memory 430 is transferred to the line memory 432. That is, the delay memory 422 reads the data of the input pixels R2, G2, and B2 of the current line as they are, and simultaneously reads the data of the pixels R1, G1, and B1 of the previous line.

  Data read from the delay memory column 310 is input to the arithmetic unit column 312. Then, when the control signal ADD_ON is turned ON, the result of addition or averaging by the arithmetic unit column 312 is output.

  Next, an image forming apparatus including the image reading apparatus according to the embodiment will be described. FIG. 20 is a diagram illustrating an outline of an image forming apparatus 50 including an image reading device 60 having the photoelectric conversion element 10. The image forming apparatus 50 is, for example, a copying machine or an MFP (Multifunction Peripheral) having an image reading device 60 and an image forming unit 70.

  The image reading device 60 includes, for example, a photoelectric conversion element 10, an LED driver (LED_DRV) 600, and an LED 602. The LED driver 600 drives the LED 602 in synchronization with a line synchronization signal output from the timing control unit (TG) 14. The LED 602 irradiates the original with light. The photoelectric conversion element 10 receives reflected light from the document in synchronization with a line synchronization signal or the like, and a plurality of PDs (not shown) generate electric charges and start accumulation. The photoelectric conversion element 10 outputs the image data to the image forming unit 70 after performing TDI, parallel serial conversion, and the like.

  The image forming unit 70 includes a processing unit 80 and a printer engine 82, and the processing unit 80 and the printer engine 82 are connected via an interface (I / F) 84.

  The processing unit 80 includes an LVDS 800, an image processing unit 802, and a CPU 804. The CPU 804 controls each part of the image forming apparatus 50 such as the photoelectric conversion element 10. In addition, the CPU 804 (or the timing control unit 14) controls each PD to start generating charges according to the amount of received light substantially simultaneously.

  The photoelectric conversion element 10 outputs, for example, image data of an image read by the image reading device 60, a line synchronization signal, a transmission clock, and the like to the LVDS 800. The LVDS 800 converts received image data, a line synchronization signal, a transmission clock, and the like into parallel 10-bit data. The image processing unit 802 performs image processing using the converted 10-bit data, and outputs image data and the like to the printer engine 82. The printer engine 82 performs printing using the received image data.

  As described above, since the configuration for adding the reset level and the configuration for adding the signal level are substantially the same in the photoelectric conversion element according to the embodiment, CDS can be executed with high accuracy, and the image Reading accuracy can be improved. Further, the above-described plurality of embodiments and examples can be further arbitrarily combined. In the photoelectric conversion element according to the embodiment, the signal transmitted when the floating diffusion is reset is described as an example of the reset level. However, the reset level is not limited to this. The reset level is a reference level that serves as a reference for indicating the true charge amount (true signal level by light reception) photoelectrically converted by the light receiving element (photodiode) by light reception for each pixel. That is, the reference level is a level of a signal transmitted for each pixel regardless of light reception (a level of a signal when the pixel is reset). For example, the reference level can also be obtained when the photodiode is reset.

DESCRIPTION OF SYMBOLS 10 Photoelectric conversion element 12, 12a, 12b Conversion process part 14 Timing control part 16 Parallel serial conversion part 40a, 40b Pixel 50 Image forming apparatus 60 Image reading apparatus 70 Image formation part 300a-300f 1st photoelectric conversion part-6th photoelectric conversion Units 302a to 302f first pixel circuit column to sixth pixel circuit column 303, 310 delay memory column 304 adder column 305, 308 ADC column 306, 309 subtractor column 307 analog memory column 312 arithmetic unit column 400a, 400b pixel circuit 403 413, 422, 423 Delay memory 404, 426 Addition unit 420 Analog memory unit 425 Operation unit 427 Averaging unit 428 Selection unit 430, 432 Line memory

JP 2010-199989 A

Claims (10)

A plurality of light-receiving elements that form a plurality of pixel rows for each color of light received from the subject and that perform photoelectric conversion provided in the pixels,
A plurality of first transmission circuits for transmitting respective reference levels reset and outputted by the pixels;
A plurality of second transmission circuits each transmitting a signal level output by receiving and photoelectrically converting each of the light receiving elements;
The reference level transmitted from the first transmission circuit is reset for each of the pixels that should receive light from substantially the same position in the subject at different times, and light from the substantially same position in the subject is added. An adder for photoelectrically converting each of the light receiving elements that received light at different times and adding the signal level transmitted by the second transmission circuit for each color;
The difference between the signal level added by the adder for each color and the reference level added by the adder for each color for the plurality of pixels receiving light from substantially the same position in the subject is A plurality of subtraction units for each color;
Have
The first transmission circuit and the second transmission circuit have substantially the same configuration, respectively. The first transmission circuit includes:
A first storage unit for storing each of the reference levels output by resetting the pixels;
The second transmission circuit includes:
A second storage unit that stores each of the signal levels output by the light receiving element receiving light and performing photoelectric conversion;
The first storage unit
Each of the reference levels output by the pixels is stored until the reference level output by the pixel to be finally received light from substantially the same position in the subject is stored,
The second storage unit
2. The signal level output by the light receiving element is stored until the signal level output by the light receiving element that has received light from substantially the same position in the subject last is stored. Photoelectric conversion element. The first storage unit
Each time one of the light receiving elements receives light from substantially the same position in the subject, the reference level is sequentially moved and stored,
The second storage unit
The photoelectric conversion element according to claim 2, wherein each time one of the light receiving elements receives light from substantially the same position on the subject, the signal level is stored while being sequentially moved. The first transmission circuit includes:
With substantially the same configuration provided for each of the light receiving elements, each transmits a reference level,
The second transmission circuit includes:
4. The photoelectric conversion element according to claim 2, wherein a signal level is transmitted by substantially the same configuration provided for each of the light receiving elements. 5. The first storage unit and the second storage unit are
5. The photoelectric conversion element according to claim 2, wherein each of the photoelectric conversion elements also functions as the addition unit by a capacitive load that can be connected in series. A plurality of light-receiving elements that form a plurality of pixel rows for each color of light received from the subject and that perform photoelectric conversion provided in the pixels,
A plurality of first transmission circuits for transmitting respective reference levels reset and outputted by the pixels;
A plurality of second transmission circuits each transmitting a signal level output by receiving and photoelectrically converting each of the light receiving elements;
An AD converter that sequentially AD converts the reference level transmitted by the first transmission circuit and the signal level transmitted by the second transmission circuit;
A plurality of subtraction units for calculating a difference between the signal level AD-converted by the AD conversion unit and the reference level AD-converted by the AD conversion unit for each pixel;
An adder that adds the result calculated by the subtractor for each of the plurality of pixels that receive light from substantially the same position in the subject at different times; and
Have
The first transmission circuit and the second transmission circuit have substantially the same configuration, respectively. The subtraction unit calculates until the difference between the signal level of the pixel that received light last and the reference level is calculated for a plurality of the pixels that received light from substantially the same position in the subject at different times. The photoelectric conversion element according to claim 6, further comprising a storage unit that stores a result for each color. An averaging unit that averages the results calculated by the subtraction unit for each of the plurality of pixels that receive light from substantially the same position in the subject at different times;
A selection unit that selects which of the result of addition by the addition unit or the result of averaging by the averaging unit is output;
The photoelectric conversion element according to claim 6 or 7, characterized by comprising: An image reading apparatus comprising the photoelectric conversion element according to claim 1. An image reading apparatus according to claim 9,
An image forming apparatus comprising: an image forming unit that forms an image based on image data read by the image reading apparatus.

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