JP6314562B2 - Image processing apparatus and image forming apparatus - Google Patents

Description

  The present invention relates to an image processing apparatus and an image forming apparatus.

  In general, an image processing command in a printer as an image forming apparatus includes an instruction for executing image processing on a part of a page at random as well as processing in order from the top of the page in line units. In such an instruction, a process of performing image processing on a part of an image once read according to an image processing command and writing to the same address is repeated. However, when image processing commands to the same address are consecutive, if the image to be processed by the next command is read before the image processed by the previous command is written, it is executed by the previous command. Image processing may not be reflected in the image processed by the next command and may become an abnormal image. In order to avoid such an abnormal image, a process (RMW (Read Modify Write) process) of reading an image by the next command after the writing of the image processed by the previous command is completed. ) Is already known. In such an RMW process, the image processing by the next command cannot be started until the image processing by the previous command is reflected in the memory. Therefore, as a system, the read response time (hereinafter referred to as latency) from the image processing means to the memory. ) Becomes longer, the performance of image processing is degraded.

  In an image processing apparatus such as an image forming apparatus, a plurality of devices (bus masters) often execute processing by accessing a shared memory via a bus. In this way, in a system configuration in which there are multiple bus masters, and one of the bus masters obtains the right to use the bus and accesses the shared memory, arbitration as to which of the bus masters is given the right to use the bus appropriately There is a need to do. Without such proper arbitration, multiple bus masters may write to the same memory space at the same time, and the order of writing may not be the order in which the right to use the bus is obtained by arbitration There is sex.

  In order to access the memory in the order in which the right to use the bus from a plurality of bus masters connected to the bus is obtained, a plurality of transfer paths are provided, a plurality of transfer paths are efficiently selected, a plurality of A technique has been proposed in which the write request from the bus master is prevented from reversing the order of writing to the memory by passing through different transfer paths (see Patent Document 1).

  However, the technique described in Patent Document 1 does not touch on the problem of shortening the latency of the RMW process in the above-described image processing, and the memory access efficiency is reduced by increasing the latency in the RMW process. This problem has not been solved.

  The present invention has been made in view of the above, and an object thereof is to provide an image processing apparatus and an image forming apparatus that reduce latency in image processing.

In order to solve the above-described problems and achieve the object, the present invention includes a storage unit that stores an image, an image processing unit that executes image processing on the image stored in the storage unit, and the image A first communication path for the processing means to access the storage means as a first bus master, and a communication path for the image processing means to access the storage means as the first bus master, from the first communication path The first communication path having a long latency and the image processing includes at least a first process which is a read-modify-write process in which the process of the next command is not performed until the process based on the previous command is completed. select a communication path, the image processing, if it contains the second processing is not the first processing, a selection means for selecting the second communication path, by said selection means And switching means for switching to-option has been said communication path, characterized by comprising a.

  According to the present invention, latency in image processing can be shortened.

FIG. 1 is a main part configuration diagram of the image forming apparatus according to the first embodiment. FIG. 2 is a diagram for explaining pipeline processing. FIG. 3 is a diagram for explaining the RMW process. FIG. 4 is a diagram for explaining RMW processing in a communication path with a short latency. FIG. 5 is a diagram illustrating a block configuration of the image processing unit according to the first embodiment. FIG. 6 is a flowchart for explaining a communication path switching operation in the image processing apparatus according to the first embodiment. FIG. 7 is a main part configuration diagram of an image forming apparatus according to the second embodiment. FIG. 8 is a diagram for explaining a block configuration and the like of the image processing means according to the third embodiment. FIG. 9 is a main part configuration diagram of an image forming apparatus according to the fourth embodiment. FIG. 10 is a diagram for explaining the block configuration and the like of the image processing means of the fourth embodiment. FIG. 11 is a flowchart for explaining a communication path switching operation in the image processing apparatus according to the fourth embodiment.

  Hereinafter, embodiments of an image processing apparatus and an image forming apparatus according to the present invention will be described in detail with reference to the drawings. As an image forming apparatus according to the present invention, for example, an electrophotographic image forming apparatus or a multifunction peripheral (MFP) can be applied. Note that a multifunction peripheral is an apparatus having at least two functions of a printing function, a copying function, a scanner function, and a facsimile function.

  In addition, the present invention is not limited by the following embodiments, and constituent elements in the following embodiments are easily conceivable by those skilled in the art, substantially the same, and so-called equivalent ranges. Is included. Furthermore, various omissions, substitutions, changes, and combinations of the constituent elements can be made without departing from the scope of the following embodiments.

[First Embodiment]
(Configuration of main parts of image forming apparatus)
FIG. 1 is a main part configuration diagram of the image forming apparatus according to the first embodiment. With reference to FIG. 1, the configuration of the main part of the image forming apparatus 1 will be described in the present embodiment.

  As shown in FIG. 1, the image forming apparatus 1 includes a controller unit 10 (image processing device) and an engine unit 20.

  The controller unit 10 executes various image processing on the scanner image read by the scanner unit in the engine unit 20 to form a format that can be output, and then transmits the image to the plotter unit of the engine unit 20 as a plotter image. Part. The controller unit 10 includes a scanner image transfer unit 101, a plotter image transfer unit 102, a CPU (Central Processing Unit) 103, an image processing unit 104 (first bus master), a memory 105 (storage unit), an arbiter 106, 107, a selector 108 (switching means), and image processing means 109 and 110. Among these, the scanner image transfer unit 101, the plotter image transfer unit 102, the CPU 103, and the image processing units 104, 109, and 110 are connected to the arbiter 106 or arbiter 107, and are bus masters whose order for accessing the memory 105 is controlled. Function as.

  The engine unit 20 is a processing unit that transmits a scanner image read by the scanner unit to the controller unit 10, receives a plotter image that has been subjected to image processing in a format that can be output by the controller unit 10, and executes a printing operation. is there. The engine unit 20 includes a scanner unit 201, an image transmission unit 202, a plotter unit 203, and an image reception unit 204.

  The scanner image transfer unit 101 is a processing unit that receives a scanner image read by the scanner unit 201 of the engine unit 20, transfers it to the arbiter 106, and stores it in the memory 105. The scanner image transfer unit 101 is realized by an input interface circuit or the like.

  The plotter image transfer unit 102 performs image processing on the scanner image by the image processing unit 104, 109, or 110, reads out the plotter image in a format that can be output from the memory 105, and receives the image receiving unit 204 of the engine unit 20. It is a processing part to transfer to. The plotter image transfer unit 102 is realized by an output interface circuit or the like.

  The CPU 103 is an arithmetic device that performs operation mode setting and activation instruction to each processing unit such as the scanner image transfer unit 101 and the arbiters 106 and 107, address management of the memory 105, and the like.

  The image processing unit 104 is a functional unit that executes image processing by RMW processing or pipeline processing described later. As the RMW process, the image processing unit 104 executes, for example, a process of forming an image by interpreting PDL (Page Description Language). The image processing unit 104 transmits a communication path instruction (instruction information) to the selector 108 based on whether the access is performed by the RMW process or the pipeline process, and the first operation is performed by the selector 108 switching operation based on the communication path instruction. Read access to the memory 105 via the communication path output unit 1081 or read access to the memory 105 via the second communication path output unit 1082 is performed. The image processing means 104 is realized by a dedicated hardware circuit. Note that the number of image processing means having the same function as that of the image processing means 104 is not limited to one, and may be plural. In this case, the selector 108 connected to the image processing unit 104 requires the same number of image processing units having the same function as the image processing unit 104.

  The memory 105 is a main storage device that temporarily stores image data and a program executed by the CPU 103. The memory 105 stores the scanner image received by the scanner image transfer unit 101. The memory 105 is realized by a storage medium such as a RAM (Random Access Memory).

  The arbiter 106 is a circuit that controls an access request of each bus master that accesses the memory 105, and has a function of adjusting the priority order so that the memory 105 can be used efficiently. The arbiter 106 includes a first port 1061, a second port 1062, a third port 1063, a fourth port 1064 and a fifth port 1065 as master ports, and a target 1066 as a target port. The CPU 103 is connected to the first port 1061, the scanner image transfer unit 101 is connected to the second port 1062, and the plotter image transfer unit 102 is connected to the third port 1063. The fourth port 1064 is connected to a first communication path output unit 1081 of a selector 108 described later, and the fifth port 1065 is connected to a target 1075 of an arbiter 107 described later. The target 1066 is connected to the memory 105. Each of the master port and the target port of the arbiter 106 includes a FIFO (First In First Out) type buffer for improving the efficiency of data transfer. Specifically, the first port 1061, the second port 1062, the third port 1063, the fourth port 1064, and the fifth port 1065 are provided with FIFO buffers 1061a to 1065a, respectively. The target 1066 includes a FIFO buffer 1066a.

  The arbiter 107 is a circuit that controls an access request of each bus master that accesses the fifth port 1065 that is the master port of the arbiter 106, and has a function as a sub-arbiter that adjusts the priority order so that the memory 105 can be used efficiently. Have. As shown in FIG. 1, the arbiter 107 is arranged in front of the arbiter 106 with respect to the memory 105. The arbiter 107 includes a first port 1071, a second port 1072, and a third port 1073 as master ports, and a target 1075 as a target port. The first port 1071 is connected to a second communication path output unit 1082 of the selector 108 (to be described later), the second port 1072 is connected to the image processing means 109, and the third port 1073 is connected to the image processing means 110. Yes. The target 1075 is connected to the fifth port 1065 of the arbiter 106. Like the arbiter 106, the master port and the target port of the arbiter 107 are each provided with a FIFO buffer for improving data transfer efficiency. Specifically, the first port 1071, the second port 1072, and the third port 1073 are provided with FIFO buffers 1071a to 1073a, respectively. Further, the target 1075 includes a FIFO buffer 1075a.

  In accordance with the communication path instruction received from the image processing unit 104, the selector 108 outputs data (read access request or received scanner image) transmitted and received by the image processing unit 104 to the first communication path output unit 1081 or the second communication path. This is a functional unit that selects whether to transmit / receive to / from any of the units 1082. Here, a communication path from the first communication path output unit 1081 to the memory 105 via the arbiter 106 is referred to as a “first communication path”. A communication path from the second communication path output unit 1082 to the memory 105 via the arbiter 107 and the arbiter 106 is referred to as a “second communication path”. Access to the memory 105 via the first communication path is to access the memory 105 via the fourth port 1064 of the arbiter 106, and the first port 1071 of the arbiter 107 and the fifth port 1065 of the arbiter 106. The latency to the memory 105 is shorter than the access to the memory 105 via the second communication path for accessing the memory 105 via. The selector 108 is realized by a dedicated hardware circuit. Note that the image processing unit 104 may access the memory 105 via the first communication path via the first communication path output unit 1081 of the selector 108 for write access. Further, the arbiter 106 sets the priority of access to the memory 105 for the fourth port 1064 in the first communication path higher than the priority of access to the memory 105 for the fifth port 1065 in the second communication path. It is good also as what to do. As a result, the latency of access to the memory 105 via the first communication path can be made shorter than the latency of access to the memory 105 via the second communication path.

  The image processing units 109 and 110 are functional units that execute image processing such as image compression / expansion processing, image rotation processing, image encryption processing, or image processing processing, respectively. Among these, the image processing means 109 is connected to the second port 1072 of the arbiter 107, and the image processing means 110 is connected to the third port 1073 of the arbiter 107. The image processing units 109 and 110 are functional units that are assumed to sequentially access the memory 105 with incremental addresses and execute image processing without duplicate access to the same address. Image processing by pipeline processing to be described later is executed. Therefore, in the image processing means 109 and 110, the access to the memory 105 is via the arbiter 107 and the arbiter 106, and is longer than the latency in the access to the memory 105 via the first communication path described above. Become. As shown in FIG. 1, the number of image processing means connected to the arbiter 107 is two, ie, image processing means 109 and 110, but is not limited to this. One or three or more image processing means are provided. Also good.

  As described above, the image processing unit 104 is described as an example of a bus master that executes RMW processing. However, the present invention is not limited thereto, and the bus master that executes RMW processing may be an HDD (Hard with a timeout rule). A disk drive (NIC) controller or a network interface NIC (Network Interface Card) may be included. As described above, when the HDD controller or NIC with the timeout rule is included as a bus master for executing the RMW process, when the HDD controller or NIC accesses the memory 105, the first communication path having a shorter latency than the second communication path. It is desirable to go through. As a result, it is possible to suppress the occurrence of a timeout retransmission operation and improve the communication efficiency.

  The scanner unit 201 is an apparatus that reads document data and generates a scanner image. The image transmission unit 202 is a processing unit that transfers the scanner image read by the scanner unit 201 to the scanner image transfer unit 101 of the controller unit 10. The image transmission unit 202 is realized by an output interface circuit or the like.

  The plotter unit 203 is a device that performs image processing on the scanner image by the image forming apparatus 1 and prints a plotter image in a form that can be output on a printing sheet that is a printing medium. The image receiving unit 204 is a processing unit that receives a plotter image from the plotter image transfer unit 102 of the image forming apparatus 1 and transfers the plotter image to the plotter unit 203. The image receiving unit 204 is realized by an input interface circuit or the like.

(Pipeline processing and RMW processing)
FIG. 2 is a diagram for explaining pipeline processing. First, the pipeline processing will be described with reference to FIG.

  A series of processing including image processing (hereinafter referred to as image processing cycle) includes a read access request (read command), an image read from memory, an image processing, a write access request (ride command), and an image processed image. Like writing to memory, it consists of multiple stages. Normally, the next image processing cycle cannot be started unless the previous image processing cycle ends. However, when images are sequentially read from the memory with incremental addresses, image processing is executed in the order of reading, and data is written to the memory, the addresses of data to be subjected to image processing cycles do not overlap. Therefore, as shown in FIG. 2, each stage of the image processing cycle (shown as pipeline processing A1 to A5 in FIG. 2) can be operated independently, and the previous image processing cycle ends. Before, it is possible to start the next image processing cycle, which is called pipeline processing. In such pipeline processing, the read response period in each image processing cycle, that is, latency is concealed, and the processing performance of the image processing cycle depends on the data processing time.

  FIG. 3 is a diagram for explaining the RMW process. FIG. 4 is a diagram for explaining RMW processing in a communication path with a short latency. Next, the RMW process will be described with reference to FIGS.

  As described above, when image processing commands for the same address are consecutive, an image processing cycle based on the image processing command cannot be executed by pipeline processing, but must be performed by RMW processing. In the case of RMW processing, since the next image processing cycle cannot be started until the previous image processing cycle is completed, as shown in FIG. 3, each image processing cycle (in FIG. 3, as RMW processing B1 and B2). The read processing period (latency) is greatly affected by the data processing period during which image processing is performed.

  The RMW process shown in FIG. 4 is a process when the read response period (latency) in the RMW process shown in FIG. 3 is shortened, and the entire image processing cycle (shown as RMW processes C1 to C3 in FIG. 4). Processing time is shortened and processing performance is improved. Also, in the RMW process, access to the same address in the memory does not occur during the image processing cycle, so that access to the memory is not occupied. On the other hand, since the pipeline processing shown in FIG. 2 executes each successive image processing cycle, there is a possibility that access to the memory will be occupied if the priority is increased. In RMW processing, even when priority is high, there is a gap for other bus masters to access the memory, so other bus masters can also access the memory, and the balance of processing speed performance in each bus master is maintained. It is relatively easy to do. That is, in the case of RMW processing in which processing performance has been largely suppressed by the read response period (latency) in the past, by shortening the read response period, the processing performance of image processing is dramatically improved, and the RMW processing Even if the frequency of access to the memory increases slightly, access to the memory of other bus masters is not significantly hindered.

(Block configuration of image processing means)
FIG. 5 is a diagram illustrating a block configuration of the image processing unit according to the first embodiment. A block configuration and the like of the image processing unit 104 will be described with reference to FIG.

  As shown in FIG. 5, the image processing unit 104 includes a condition setting unit 1041, an access determination unit 1042, and a communication path determination unit 1043 (selection unit).

  When the image processing unit 104 accesses the memory 105, the condition setting unit 1041 holds the determination condition information set by the CPU 103 as to under what conditions the first communication path or the second communication path is used. The condition information is passed to the communication path determination unit 1043. Here, the determination condition information is selected when the image processing of the image processing unit 104 is RMW processing (first processing), and the first communication path with a short latency is selected, and processing other than RMW processing (pipeline processing, etc.) In the case of (second processing), it is assumed that the information indicates a determination condition for selecting the second communication path. Note that the determination condition information is information including a determination condition that the first communication path is selected when information on the next operation mode of the image processing unit 104 or setting information of the processing target image is read from the memory 105. It may be.

  The access determination unit 1042 determines whether or not the next access request transmitted by the image processing unit 104 is due to RMW processing. If the access request is due to RMW processing, the access determination unit 1042 sends an RMW processing notification to the communication path determination unit 1043. It is a function part to pass.

  Based on the determination condition information received from the condition setting unit 1041 and the RMW processing notification received from the access determination unit 1042, the communication path determination unit 1043 is configured so that the image processing unit 104 communicates with the memory 105 the first communication path or the second communication path. A communication path instruction for instructing whether to access via the communication path is generated and transmitted to the selector 108.

  The selector 108 switches the communication path for the image processing means 104 to access the memory 105 to the first communication path or the second communication path in accordance with the communication path instruction received from the communication path determination means 1043.

  As shown in FIG. 5, the image processing unit 104 transmits a transfer path instruction to the selector 108 separately from the access request transmitted to the selector 108, but the present invention is not limited to this. For example, the image processing unit 104 may include a transfer path instruction in the access request and transmit the instruction to the selector 108, and the selector 108 may select the transfer path according to the transfer path instruction included in the access request.

  In addition, the condition setting unit 1041, the access determination unit 1042, and the communication path determination unit 1043 are included in the image processing unit 104, but are not limited thereto, and are configured outside the image processing unit 104. The processing unit 104 may have a similar function.

(Communication path switching and access operations)
FIG. 6 is a flowchart for explaining a communication path switching operation in the image processing apparatus according to the first embodiment. With reference to FIG. 6, an operation for switching the communication path for the image processing unit 104 in the image forming apparatus 1 to access the memory 105 and an operation for accessing the memory 105 via the communication path will be described in detail.

<Step S01>
When the image processing unit 104 executes the RMW process, the CPU 103 improves the processing performance of the image processing by accessing the memory 105 via the first communication path whose latency is shorter than that of the second communication path. In view of the decrease in memory access speed of the bus master, priority is given to improving the processing performance of the image processing means 104, and in the case of RMW processing, whether to transfer data (access the memory 105) via the first communication path. Determine whether. When the image processing unit 104 executes the RMW process, when it is determined to transfer data via the first communication path (step S01: Yes), the process proceeds to step S02. On the other hand, if it is determined that all commands of the image processing unit 104 are to be transferred via a normal communication path (here, the second communication path) (No in step S01), the process proceeds to step S03.

<Step S02>
The CPU 103 accesses the memory 105 via the first communication path when the image processing unit 104 executes the RMW process, and executes the second communication path when executing processing other than the RMW process (for example, pipeline processing). The condition that the memory 105 is accessed via is set. The CPU 103 transmits the set condition information as determination condition information to the condition setting means 1041, and the condition setting means 1041 holds the determination condition information. The condition setting unit 1041 passes the held determination condition information to the communication path determination unit 1043. Then, the process proceeds to step S04.

<Step S03>
The CPU 103 sets a condition that the image processing unit 104 accesses the memory 105 via the second communication path for all commands (all processes). The CPU 103 transmits the set condition information as determination condition information to the condition setting means 1041, and the condition setting means 1041 holds the determination condition information. The condition setting unit 1041 passes the held determination condition information to the communication path determination unit 1043. Then, the process proceeds to step S04.

<Step S04>
The CPU 103 activates the image processing unit 104 to execute image processing. Then, the process proceeds to step S05.

<Step S05>
The access determination unit 1042 determines whether or not the next access request to the memory 105 to be transmitted is due to RMW processing. When the access request is due to the RMW process (step S05: Yes), the access determination unit 1042 passes the RMW process notification to the communication path determination unit 1043, and proceeds to step S06. When the access request is not based on the RMW process (step S05: No), the process proceeds to step S07.

<Step S06>
The communication path determination unit 1043 uses the determination condition information received from the condition setting unit 1041 as the condition setting content that the memory 105 is accessed via the first communication path when the image processing unit 104 executes the RMW process. It is determined whether or not there is. When the communication path determination unit 1043 receives the RMW processing notification from the access determination unit 1042 and the determination condition information indicates that the image processing unit 104 executes RMW processing, the memory 105 is accessed via the first communication path. If it is the content of the condition setting to do (step S06: Yes), the process proceeds to step S08. The communication path determination unit 1043 has not received the RMW processing notification from the access determination unit 1042 or the determination condition information has passed through the second communication path for all commands (all processes) by the image processing unit 104. If it is the content of the condition setting to access the memory 105 (step S06: No), the process proceeds to step S07.

<Step S07>
The communication path determination unit 1043 transmits to the selector 108 a communication path instruction that instructs the image processing unit 104 to access the memory 105 via the second communication path having a longer latency than the first communication path. The selector 108 switches the communication path from which the image processing unit 104 accesses the memory 105 to the second communication path in accordance with the communication path instruction received from the communication path determination unit 1043. Then, the process proceeds to step S09.

<Step S08>
The communication path determination unit 1043 transmits to the selector 108 a communication path instruction that instructs the image processing unit 104 to access the memory 105 via the first communication path having a shorter latency than the second communication path. The selector 108 switches the communication path from which the image processing means 104 accesses the memory 105 to the first communication path in accordance with the communication path instruction received from the communication path determination means 1043. Then, the process proceeds to step S09.

<Step S09>
The image processing unit 104 issues and transmits an access request to the memory 105, and accesses the memory 105 via the communication path switched by the selector 108 in step S07 or step S08. Then, the process proceeds to step S10.

<Step S10>
When the image processing unit 104 completes image processing for one page (step S10: Yes), the processing ends, and when the image processing unit 104 does not complete image processing for one page (step S10: No). Return to step S05.

  Through the above-described operation flow, the image processing unit 104 in the image forming apparatus 1 performs an operation of switching the communication path for accessing the memory 105 and an operation for accessing the memory 105 via the communication path.

  As described above, when the access request to the memory 105 is based on the RMW process, the image processing unit 104 switches the selector 108 to the first communication path having a shorter latency than the second communication path according to the transfer path instruction. It is supposed to let you. Then, the image processing unit 104 accesses the memory 105 via the first communication path switched by the selector 108 in the RMW process. Thereby, the read response period (latency) to the memory 105 in the RMW process can be shortened, and the processing performance of the image processing by the RMW process can be improved. Further, since the selector 108 switches to the first communication path or the second communication path based on the processing content of the image processing unit 104, the balance of processing performance with each bus master can be maintained.

[Second Embodiment]
The image forming apparatus according to the second embodiment will be described focusing on differences from the image forming apparatus 1 according to the first embodiment. In the first embodiment, the configuration in which the selector 108 is directly connected to the arbiter 106 in the first communication path has been described. In the present embodiment, a configuration in which the first communication path is a path that passes through the sub-arbiter will be described.

(Configuration of main parts of image forming apparatus)
FIG. 7 is a main part configuration diagram of an image forming apparatus according to the second embodiment. With reference to FIG. 7, a configuration of main parts of the image forming apparatus 1a according to the present embodiment will be described.

  As shown in FIG. 7, the image forming apparatus 1 a includes a controller unit 10 a (image processing device) and an engine unit 20. The configuration and operation of the engine unit 20 are the same as those in the first embodiment.

  The controller unit 10a performs various image processing on the scanner image read by the scanner unit in the engine unit 20 to be in a format that can be output, and then transmits the image to the plotter unit of the engine unit 20 as a plotter image. Part. The controller unit 10a includes a scanner image transfer unit 101, a plotter image transfer unit 102, a CPU 103, an image processing unit 104, a memory 105, arbiters 106a and 107a, a selector 108, image processing units 109 and 110, An image processing unit 111, an arbiter 112, and a selector 113 are provided. Among these, the scanner image transfer unit 101, the plotter image transfer unit 102, the CPU 103, and the image processing units 104 and 109 to 111 are connected to the arbiter 107a or the arbiter 112 as bus masters that are controlled in order for accessing the memory 105. Function.

  The scanner image transfer unit 101 is a processing unit that receives a scanner image read by the scanner unit 201 of the engine unit 20, transfers it to the arbiter 106 a, and stores it in the memory 105. The scanner image transfer unit 101 is realized by an input interface circuit or the like.

  The plotter image transfer unit 102 performs image processing on the scanner image by the image processing units 104 and 109 to 111, reads the plotter image in a format that can be output from the memory 105, and the image receiving unit 204 of the engine unit 20. It is a processing part to transfer to. The plotter image transfer unit 102 is realized by an output interface circuit or the like.

  The CPU 103 is an arithmetic unit that performs operation mode setting and activation instructions for each processing unit such as the scanner image transfer unit 101 and the arbiters 106 a, 107 a, and 112, address management of the memory 105, and the like.

  The image processing units 104 and 111 are functional units that execute image processing by RMW processing or pipeline processing described later. The image processing unit 104 transmits a communication path instruction to the selector 108 based on whether the access is performed by the RMW process or the pipeline process, and the first communication path output unit is operated by the switching operation of the selector 108 based on the communication path instruction. Read access to the memory 105 via 1081a or read access to the memory 105 via the second communication path output unit 1082 is performed. The image processing unit 111 transmits a communication path instruction to the selector 113 based on whether the access is performed by the RMW process or the pipeline process, and the first communication path output unit is operated by the switching operation of the selector 113 based on the communication path instruction. Read access to the memory 105 via 1131a or read access to the memory 105 via the second communication path output unit 1132 is performed. The image processing means 104 and 111 are realized by a dedicated hardware circuit.

  The arbiter 106a is a circuit that controls an access request of each bus master that accesses the memory 105, and has a function of adjusting the priority so that the memory 105 can be used efficiently. The arbiter 106a has a first port 1061, a second port 1062, a third port 1063, a fourth port 1064 and a fifth port 1065 as master ports, and a target 1066 as a target port. The CPU 103 is connected to the first port 1061, the scanner image transfer unit 101 is connected to the second port 1062, and the plotter image transfer unit 102 is connected to the third port 1063. A fourth port 1064 is connected to a target 1123 of an arbiter 112 described later, and a fifth port 1065 is connected to a target 1075 of an arbiter 107a described later. The target 1066 is connected to the memory 105. Each of the master port and the target port of the arbiter 106a includes a FIFO (First In First Out) type buffer for improving the efficiency of data transfer. Specifically, the first port 1061, the second port 1062, the third port 1063, the fourth port 1064, and the fifth port 1065 include FIFO buffers 1061a to 1063a, 1064b, and 1065a, respectively. Among these, the FIFO buffer 1064b has a smaller number of buffer stages than the FIFO buffers 1061a to 1063a and 1065a. The target 1066 includes a FIFO buffer 1066a.

  The arbiter 107a is a circuit that controls an access request of each bus master that accesses the fifth port 1065 that is the master port of the arbiter 106a, and has a function as a sub-arbiter that adjusts the priority so that the memory 105 can be used efficiently. Have. As shown in FIG. 7, the arbiter 107 a is arranged in front of the arbiter 106 a with respect to the memory 105. The arbiter 107a includes a first port 1071, a second port 1072, a third port 1073, a fourth port 1074 as a master port, and a target 1075 as a target port. The first port 1071 is connected to a second communication path output unit 1082 of the selector 108 described later, the second port 1072 is connected to a second communication path output unit 1132 of the selector 113 described later, and the third port 1073 is The image processing means 109 is connected, and the image processing means 110 is connected to the fourth port 1074. The target 1075 is connected to the fifth port 1065 of the arbiter 106a. Similar to the arbiter 106a, the master port and the target port of the arbiter 107a are each provided with a FIFO buffer for improving data transfer efficiency. Specifically, the first port 1071, the second port 1072, the third port 1073, and the fourth port 1074 have FIFO buffers 1071a to 1074a, respectively. Further, the target 1075 includes a FIFO buffer 1075a.

  The arbiter 112 is a circuit that controls an access request of each bus master that accesses the fourth port 1064 that is the master port of the arbiter 106a, and has a function as a sub-arbiter that adjusts the priority order so that the memory 105 can be used efficiently. Have. As shown in FIG. 7, the arbiter 112 is arranged in front of the arbiter 106 a with respect to the memory 105. The arbiter 112 has a first port 1121 and a second port 1122 as master ports, and a target 1123 as a target port. The first port 1121 is connected to a first communication path output unit 1081a of a selector 108 described later, and the second port 1122 is connected to a first communication path output unit 1131a of a selector 113 described later. The target 1123 is connected to the fourth port 1064 of the arbiter 106a. Similar to the arbiter 106a, the master port and the target port of the arbiter 112 are each provided with a FIFO buffer for efficient data transfer. Specifically, the first port 1121 and the second port 1122 are provided with FIFO buffers 1121a and 1122a, respectively. The FIFO buffers 1121a and 1122a have a smaller number of buffer stages than the FIFO buffers 1071a to 1074a of the arbiter 107a. The target 1123 includes a FIFO buffer 1123a. The FIFO buffer 1123a has a smaller number of buffer stages than the FIFO buffer 1075a of the arbiter 107a.

  In accordance with the communication path instruction received from the image processing unit 104, the selector 108 outputs data (read access request or received scanner image) transmitted and received by the image processing unit 104 to the first communication path output unit 1081a or the second communication path. This is a functional unit that selects whether to transmit / receive to / from any of the units 1082. Here, a communication path from the first communication path output unit 1081a to the memory 105 via the arbiter 112 and the arbiter 106a is referred to as a “first communication path”. A communication path from the second communication path output unit 1082 to the memory 105 via the arbiter 107a and the arbiter 106a is referred to as a “second communication path”. The selector 108 is realized by a dedicated hardware circuit.

  In general, if the number of buffer stages of each port of the arbiter is increased for the purpose of efficient access to the memory 105, the amount of buffered data increases, and as a result, the read response period (latency) becomes longer. Become. As described above, the number of buffer stages of each port of the arbiter 107a is larger than the number of buffer stages of each port of the arbiter 112, and the number of buffer stages of the FIFO buffer 1065a of the arbiter 106a is larger than the number of buffer stages of the FIFO buffer 1064b. As a result, the access to the memory 105 via the first communication path is to access the memory 105 via the arbiter 112 and the fourth port 1064 of the arbiter 106a, and the arbiter 107a and the fifth of the arbiter 106a. The latency to the memory 105 is shorter than the access to the memory 105 via the second communication path that accesses the memory 105 via the port 1065.

  For example, the RMW process for accessing the memory 105 through the first communication path occurs when a process such as writing a line in the vertical direction is performed on an image. When drawing a line in the horizontal direction, it is possible to efficiently read the image from the memory by increasing the burst length of one read access. However, in the vertical direction, one line access is thick. The amount of data is sufficient, and it is generated continuously for a plurality of lines. Therefore, the burst length of one read access may be short, and the number of buffer stages can be reduced even when the sub-arbiter (arbiter 112) is inserted in a path with a short latency (first communication path).

  The arbiter 106a sets the priority of access to the memory 105 for the fourth port 1064 in the first communication path higher than the priority of access to the memory 105 for the fifth port 1065 in the second communication path. It is good also as what to do. As a result, the latency of access to the memory 105 via the first communication path can be made shorter than the latency of access to the memory 105 via the second communication path.

  The image processing units 109 and 110 are functional units that execute image processing such as image compression / expansion processing, image rotation processing, image encryption processing, or image processing processing, respectively. Among these, the image processing means 109 is connected to the third port 1073 of the arbiter 107a, and the image processing means 110 is connected to the fourth port 1074 of the arbiter 107a. The image processing units 109 and 110 are functional units that are assumed to sequentially access the memory 105 with incremental addresses and execute image processing without duplicate access to the same address. Image processing by pipeline processing to be described later is executed. Therefore, in the image processing means 109 and 110, the access to the memory 105 is via the arbiter 107a and the arbiter 106a, and is longer than the latency in the access to the memory 105 via the first communication path described above. Become.

  In accordance with the communication path instruction received from the image processing unit 111, the selector 113 outputs data (read access request or received scanner image) transmitted and received by the image processing unit 111 to the first communication path output unit 1131a or the second communication path output. This is a functional unit that selects whether to transmit / receive to / from any of the units 1132. The selector 113 is realized by a dedicated hardware circuit. Since the function of the selector 113 with respect to the image processing unit 111 is the same as that of the selector 108 with respect to the image processing unit 104, description thereof will be omitted.

  In the image forming apparatus 1a according to the present embodiment, the image processing unit 104 (or the image processing unit 111) switches the communication path for accessing the memory 105 and the operation for accessing the memory 105 via the communication path. This is the same as the image forming apparatus 1 according to the first embodiment.

  As described above, the first communication path having a latency lower than that of the second communication path is realized by arranging the arbiter 112 having the number of FIFO buffer buffers of the port smaller than that of the arbiter 107a as a sub-arbiter in the preceding stage of the arbiter 106a. Yes. As described above, since the amount of buffered data is reduced by accessing the memory 105 via the arbiter 112 having a small number of buffer stages in the first communication path, the read response period (latency) is longer than that in the second communication path. ) Can be shortened. Therefore, when the image processing unit 104 executes RMW processing, the latency can be shortened by accessing the memory 105 via the first communication path, and the processing performance of image processing by RMW processing is improved. be able to. Further, since the selector 108 switches to the first communication path or the second communication path based on the processing content of the image processing unit 104, the balance of processing performance with each bus master can be maintained.

  Further, as shown in FIG. 7, even if a plurality of image processing means (image processing means 104 and 111) for executing RMW processing are mounted, the arbiter 106a is arranged after the access requests from the respective image processing means are collected by the arbiter 112. Can be transferred to. Therefore, the number of master ports in the arbiter 106a can be reduced. For example, there is an advantage that the circuit layout becomes easy when the arbiter 106a is implemented as an ASIC (Application Specific Integrated Circuit).

[Third Embodiment]
The image forming apparatus according to the third embodiment will be described focusing on differences from the image forming apparatus 1a according to the second embodiment. In the second embodiment, the communication path determination unit 1043 passes the first communication path or the second communication path from the image processing unit 104 to the memory 105 based on the RMW processing notification received from the access determination unit 1042. The communication path instruction for instructing whether to access is transmitted to the selector 108. In the present embodiment, an operation in which the communication path determination unit 1043 generates a communication path instruction based on not only the RMW processing notification but also the burst length of the image processing unit will be described. The main configuration of the image forming apparatus according to the present embodiment is the same as the main configuration of the image forming apparatus 1a according to the second embodiment shown in FIG. 7, but in this embodiment, image processing is performed. The means 104 is replaced with an image processing means 104a described later.

(Block configuration of image processing means)
FIG. 8 is a diagram for explaining a block configuration and the like of the image processing means according to the third embodiment. A block configuration and the like of the image processing unit 104a will be described with reference to FIG.

  As shown in FIG. 8, the image processing unit 104a (first bus master) includes a condition setting unit 1041, an access determination unit 1042a, and a communication path determination unit 1043.

  When the image processing unit 104 accesses the memory 105, the condition setting unit 1041 holds the determination condition information set by the CPU 103 as to under what conditions the first communication path or the second communication path is used. The condition information is passed to the communication path determination unit 1043. For the determination condition information, when the image processing of the image processing unit 104a is RMW processing (first processing), the first communication path with a short latency is selected, and processing other than RMW processing (pipeline processing, etc.) (second processing) In addition to the condition of selecting the second communication path, the following condition information is included. That is, when the burst length of the data from the image processing unit 104a exceeds the number of buffer stages of the port of the arbiter 112, the determination condition information selects the second communication path even in the RMW process, and the RMW process. In addition, when the burst length is equal to or less than the buffer stage number of the port of the arbiter 112, information on a condition for selecting the first communication path is included. The determination condition information is information including a determination condition that the first communication path is selected when information on the next operation mode of the image processing unit 104a or setting information of the processing target image is read from the memory 105. It may be.

  The access determination unit 1042a determines whether the next access request transmitted by the image processing unit 104a is due to RMW processing. If the access request is due to RMW processing, the access determination unit 1042a sends an RMW processing notification to the communication path determination unit 1043. It is a function part to pass. Further, the access determination unit 1042a passes a burst length notification including the burst length information of the access request to be transmitted next by the image processing unit 104a to the communication path determination unit 1043.

  Based on the determination condition information received from the condition setting unit 1041 and the RMW processing notification and burst length notification received from the access determination unit 1042a, the communication path determination unit 1043 performs the first communication with the memory 105. A communication path instruction for instructing whether to access via the path or the second communication path is generated and transmitted to the selector 108.

  The selector 108 switches the communication path from which the image processing means 104a accesses the memory 105 to the first communication path or the second communication path in accordance with the communication path instruction received from the communication path determination means 1043.

(Communication path switching and access operations)
Next, with reference to FIG. 6, the first embodiment and the second embodiment will be described with respect to the operation for switching the communication path for the image processing unit 104 a to access the memory 105 and the operation for accessing the memory 105 via the communication path. The description will focus on the differences from the image forming apparatus according to the embodiment.

<Step S01>
When the image processing unit 104a executes the RMW process, the CPU 103 improves the processing performance of the image processing by accessing the memory 105 via the first communication path having a latency lower than that of the second communication path. Considering the decrease in memory access speed of the bus master. Then, the CPU 103 gives priority to improving the processing performance of the image processing unit 104, and in the case of RMW processing, and when the burst length of data from the image processing unit 104a is equal to or less than the number of buffer stages of the port of the arbiter 112, It is determined whether or not to transfer data (access to the memory 105) via one communication path. When the image processing unit 104a executes RMW processing, and when the burst length is equal to or less than the number of buffer stages of the port of the arbiter 112, when it is determined to transfer data via the first communication path (step S01: Yes) The process proceeds to step S02. On the other hand, when it is determined that all the commands of the image processing unit 104a are to be transferred via the normal communication path (here, the second communication path) (step S01: No), the process proceeds to step S03.

<Step S02>
When the image processing unit 104a executes RMW processing and the burst length is equal to or less than the number of buffer stages of the port of the arbiter 112, the CPU 103 accesses the memory 105 via the first communication path and performs processing other than RMW processing. When processing (for example, pipeline processing) is executed, or when the burst length exceeds the number of buffer stages of the port of the arbiter 112, a condition is set such that the memory 105 is accessed via the second communication path. The CPU 103 transmits the set condition information as determination condition information to the condition setting means 1041, and the condition setting means 1041 holds the determination condition information. The condition setting unit 1041 passes the held determination condition information to the communication path determination unit 1043. Then, the process proceeds to step S04.

<Step S03>
The CPU 103 sets a condition that the image processing unit 104a accesses the memory 105 via the second communication path for all commands (all processes). The CPU 103 transmits the set condition information as determination condition information to the condition setting means 1041, and the condition setting means 1041 holds the determination condition information. The condition setting unit 1041 passes the held determination condition information to the communication path determination unit 1043. Then, the process proceeds to step S04.

<Step S04>
The CPU 103 activates the image processing unit 104a to execute image processing. Then, the process proceeds to step S05.

<Step S05>
The access determination unit 1042a determines whether or not the next access request to the memory 105 to be transmitted is due to RMW processing, and the burst length of the access request. The access determination unit 1042a passes the RMW notification to the communication path determination unit 1043 when the access request is based on the RMW process. The access determination unit 1042a passes a burst length notification including the burst length information of the access request to the communication path determination unit 1043. If the communication path determination unit 1043 does not receive the RMW processing notification or determines that the burst length indicated by the received burst length notification exceeds the number of buffer stages of the port of the arbiter 112 (step S05: No), the processing proceeds to step S07. . If the communication path determination unit 1043 receives the RMW processing notification and determines that the burst length indicated by the received burst length notification is equal to or less than the number of buffer stages of the port of the arbiter 112 (step S05: Yes), the processing proceeds to step S06. .

<Step S06>
The communication path determination unit 1043 uses the determination condition information received from the condition setting unit 1041 when the image processing unit 104a executes RMW processing, and the burst length of the data from the image processing unit 104a is the buffer of the port of the arbiter 112. When the number of stages is less than or equal to the number of stages, it is determined whether or not the condition setting is that the memory 105 is accessed via the first communication path. When the communication path determination unit 1043 receives the RMW process notification from the access determination unit 1042a, and the determination condition information executes the RMW process, and the burst length is equal to or less than the buffer stage number of the port of the arbiter 112, If it is the content of the condition setting to access the memory 105 via the first communication path (step S06: Yes), the process proceeds to step S08. If the communication path determination unit 1043 has not received the RMW processing notification from the access determination unit 1042a, or the determination condition information indicates that the burst length exceeds the number of buffer stages of the port of the arbiter 112, the communication path determination unit 1043 passes through the second communication path. When the contents of the condition setting that the memory 105 is accessed or the image processing unit 104a accesses the memory 105 via the second communication path for all commands (all processes) (step S06: No), Proceed to step S07.

<Step S07>
The communication path determination unit 1043 transmits to the selector 108 a communication path instruction that instructs the image processing unit 104a to access the memory 105 via the second communication path having a longer latency than the first communication path. In accordance with the communication path instruction received from the communication path determination unit 1043, the selector 108 switches the communication path for the image processing unit 104a to access the memory 105 to the second communication path. Then, the process proceeds to step S09.

<Step S08>
The communication path determination unit 1043 transmits to the selector 108 a communication path instruction that instructs the image processing unit 104a to access the memory 105 via the first communication path having a shorter latency than the second communication path. In accordance with the communication path instruction received from the communication path determination unit 1043, the selector 108 switches the communication path for the image processing unit 104a to access the memory 105 to the first communication path. Then, the process proceeds to step S09.

<Step S09>
The image processing unit 104a issues and transmits an access request to the memory 105, and accesses the memory 105 via the communication path switched by the selector 108 in step S07 or step S08. Then, the process proceeds to step S10.

<Step S10>
When the image processing unit 104a completes image processing for one page (step S10: Yes), the processing ends, and when the image processing unit 104a does not complete image processing for one page (step S10: No). Return to step S05.

  Through the above-described operation flow, the image processing unit 104a performs the operation of switching the communication path for accessing the memory 105 and the operation of accessing the memory 105 via the communication path.

  With the configuration and operation as described above, the same effects as those of the second embodiment can be obtained. Further, when the number of buffer stages of the port of the arbiter 112 is made smaller than that of the port of the arbiter 107a, transfer of data having a long burst length exceeding the number of buffer stages to the port of the arbiter 112 may reduce transfer efficiency. However, as described above, the determination condition information includes a condition that the second communication path is selected when the burst length exceeds the number of buffer stages of the port of the arbiter 112, so that a decrease in transfer efficiency is suppressed. Can do.

[Fourth Embodiment]
An image forming apparatus according to the fourth embodiment will be described focusing on differences from the image forming apparatus 1 according to the first embodiment. When the plotter unit 203 prints a plotter image on a printing paper, if the data transfer of the plotter image is not in time for a fixed period by the laser, the printed image becomes an abnormal image due to line missing or the like. Reading of plotter images from the top must be given top priority. In the present embodiment, while the plotter image transfer unit 102b described later transfers the plotter image, the image processing unit 104b described later passes through the second communication path including the arbiter 107 even in the RMW process. An operation for controlling to access the memory 105 will be described.

(Configuration of main parts of image forming apparatus)
FIG. 9 is a main part configuration diagram of an image forming apparatus according to the fourth embodiment. With reference to FIG. 9, the configuration of the main part of the image forming apparatus 1b will be described in the present embodiment.

  As shown in FIG. 9, the image forming apparatus 1 b includes a controller unit 10 b (image processing device) and an engine unit 20. The configuration and operation of the engine unit 20 are the same as those in the first embodiment.

  The controller unit 10b performs various image processing on the scanner image read by the scanner unit in the engine unit 20 to form a format that can be output, and then transmits the image to the plotter unit of the engine unit 20 as a plotter image. Part. The controller unit 10b includes a scanner image transfer unit 101, a plotter image transfer unit 102b (second bus master, transfer unit), a CPU 103, an image processing unit 104b (first bus master), a memory 105, and arbiters 106, 107. , A selector 108 and image processing means 109 and 110 are provided. Among these, the scanner image transfer unit 101, the plotter image transfer unit 102b, the CPU 103, and the image processing units 104b, 109, and 110 are connected to the arbiter 106 or the arbiter 107, and are bus masters whose order for accessing the memory 105 is controlled. Function as.

  The plotter image transfer unit 102 b performs image processing on the scanner image by the image processing unit 104 b, 109, or 110, reads out the plotter image in a format that can be output from the memory 105, and the image receiving unit 204 of the engine unit 20. It is a processing part to transfer to. Further, when the plotter image transfer unit 102b transfers the plotter image to the image reception unit 204, the plotter image transfer unit 102b passes operation information indicating that the plotter image is being transferred to the image processing unit 104b. The plotter image transfer unit 102b is realized by an output interface circuit or the like.

  The image processing unit 104b is a functional unit that executes image processing by RMW processing or pipeline processing described later. The image processing unit 104b transmits a communication path instruction to the selector 108 based on whether access is performed by RMW processing or pipeline processing, and whether operation information is received from the plotter image transfer unit 102b. Then, the image processing unit 104b performs read access to the memory 105 via the first communication path output unit 1081 or the second communication path output unit 1082 through the switching operation of the selector 108 based on the communication path instruction. Read access to the memory 105 is performed. The image processing unit 104b is realized by a dedicated hardware circuit.

  The arbiter 106 is a circuit that controls an access request of each bus master that accesses the memory 105, and has a function of adjusting the priority order so that the memory 105 can be used efficiently. The CPU 103 is connected to the first port 1061, the scanner image transfer unit 101 is connected to the second port 1062, and the plotter image transfer unit 102b is connected to the third port 1063. The fourth port 1064 is connected to the first communication path output unit 1081 of the selector 108, and the fifth port 1065 is connected to the target 1075 of the arbiter 107. The target 1066 is connected to the memory 105.

  In accordance with the communication path instruction received from the image processing unit 104b, the selector 108 outputs the data (read access request or received scanner image) transmitted and received by the image processing unit 104b to the first communication path output unit 1081 or the second communication path. This is a functional unit that selects whether to transmit / receive to / from any of the units 1082. Here, a communication path from the first communication path output unit 1081 to the memory 105 via the arbiter 106 is referred to as a “first communication path”. A communication path from the second communication path output unit 1082 to the memory 105 via the arbiter 107 and the arbiter 106 is referred to as a “second communication path”. The selector 108 is realized by a dedicated hardware circuit.

(Block configuration of image processing means)
FIG. 10 is a diagram for explaining the block configuration and the like of the image processing means of the fourth embodiment. A block configuration and the like of the image processing unit 104b will be described with reference to FIG.

  As shown in FIG. 10, the image processing unit 104b includes a condition setting unit 1041b, an access determination unit 1042, and a communication path determination unit 1043b (selection unit).

  When the image processing unit 104b accesses the memory 105, the condition setting unit 1041b holds the determination condition information set by the CPU 103 as to under what conditions the first communication path or the second communication path is used. The condition information is passed to the communication path determination unit 1043b. For the determination condition information, when the image processing of the image processing unit 104b is RMW processing (first processing), the first communication path with a short latency is selected, and processing other than RMW processing (pipeline processing, etc.) (second processing) In the case of (processing), it is assumed that the information includes a determination condition for selecting the second communication path. Note that the determination condition information is information including a determination condition that the first communication path is selected when information on the next operation mode of the image processing unit 104 or setting information of the processing target image is read from the memory 105. It may be. The determination condition information includes a determination condition that, when the operation information is received from the plotter image transfer unit 102b, the second communication path is selected regardless of whether or not the image processing of the image processing unit 104b is RMW processing. including.

  Based on the determination condition information received from the condition setting unit 1041b, the operation information received from the plotter image transfer unit 102b, and the RMW processing notification received from the access determination unit 1042, the communication path determination unit 1043b is stored in the memory 105. A communication path instruction for instructing whether to access via the first communication path or the second communication path is generated and transmitted to the selector 108.

  The communication path determination unit 1043b receives operation information from the plotter image transfer unit 102b, but is not limited thereto. That is, the communication path determination unit 1043b may receive the operation information from the scanner image transfer unit 101 instead of receiving the operation information from the plotter image transfer unit 102b, and other images whose operation priority is higher than that of the image processing unit 104b. It may be received from the processing means.

  The selector 108 switches the communication path for the image processing unit 104b to access the memory 105 to the first communication path or the second communication path in accordance with the communication path instruction received from the communication path determination unit 1043b.

(Communication path switching and access operations)
FIG. 11 is a flowchart for explaining a communication path switching operation in the image processing apparatus according to the fourth embodiment. With reference to FIG. 11, an operation for switching the communication path for the image processing unit 104b in the image forming apparatus 1b to access the memory 105 and an operation for accessing the memory 105 via the communication path will be described in detail.

<Step S21>
When the image processing unit 104b executes the RMW process, the CPU 103 improves the processing performance of the image processing by accessing the memory 105 via the first communication path having a latency lower than that of the second communication path. In view of the decrease in memory access speed of the bus master, priority is given to improving the processing performance of the image processing unit 104b, and in the case of RMW processing, whether to transfer data (access the memory 105) via the first communication path. Determine whether. When the image processing unit 104b executes RMW processing, when it is determined that data is transferred via the first communication path (step S21: Yes), the process proceeds to step S22. On the other hand, when it is determined that all the commands of the image processing unit 104b are to be transferred via a normal communication path (here, the second communication path) (step S21: No), the process proceeds to step S23.

<Step S22>
When the image processing unit 104b executes RMW processing, the CPU 103 accesses the memory 105 via the first communication path, and when executing processing other than RMW processing (for example, pipeline processing), the second communication path. The condition for accessing the memory 105 via is set, and the determination condition information is generated. Then, the process proceeds to step S24.

<Step S23>
The CPU 103 sets a condition that the image processing unit 104b accesses the memory 105 via the second communication path for all commands (all processes), and generates determination condition information. Then, the process proceeds to step S24.

<Step S24>
In addition, when the CPU 103 receives operation information from the plotter image transfer unit 102b for the determination condition information, the CPU 103 sets the second communication path regardless of whether the image processing of the image processing unit 104b is RMW processing. Add a condition to select. The CPU 103 transmits the generated determination condition information to the condition setting unit 1041b, and the condition setting unit 1041b holds the determination condition information. The condition setting unit 1041b passes the held determination condition information to the communication path determination unit 1043. Then, the process proceeds to step S25.

<Step S25>
The CPU 103 activates the image processing unit 104b to execute image processing. Then, the process proceeds to step S26.

<Step S26>
The access determination unit 1042 determines whether or not the next access request to the memory 105 to be transmitted is due to RMW processing. When the access request is due to the RMW process (step S26: Yes), the access determination unit 1042 passes the RMW process notification to the communication path determination unit 1043b, and proceeds to step S27. When the access request is not based on the RMW process (step S26: No), the process proceeds to step S29.

<Step S27>
The communication path determination unit 1043b uses the determination condition information received from the condition setting unit 1041b as a condition setting content for accessing the memory 105 via the first communication path when the image processing unit 104b executes the RMW process. Judge whether to include. When the communication path determination unit 1043b receives the RMW processing notification from the access determination unit 1042 and the determination condition information is executed by the image processing unit 104b, the memory 105 is accessed via the first communication path. If the content of the condition setting to do is included (step S27: Yes), the process proceeds to step S28. The communication path determination unit 1043b has not received the RMW processing notification from the access determination unit 1042, or the determination condition information is passed through the second communication path for all commands (all processes) by the image processing unit 104b. If it is the content of the condition setting to access the memory 105 (step S27: No), the process proceeds to step S29.

<Step S28>
When the determination condition information received from the condition setting unit 1041b has received operation information from the plotter image transfer unit 102b, the communication path determination unit 1043b sets the condition to access the memory 105 via the second communication path. It is determined whether or not the contents are included. If the communication path determination unit 1043b has received the operation information from the plotter image transfer unit 102b (step S28: Yes), the process proceeds to step S29. If the communication path determination unit 1043b has not received the operation information from the plotter image transfer unit 102b (step S28: No), the process proceeds to step S30.

<Step S29>
The communication path determination unit 1043b transmits to the selector 108 a communication path instruction that instructs the image processing unit 104b to access the memory 105 via the second communication path having a longer latency than the first communication path. The selector 108 switches the communication path for the image processing means 104b to access the memory 105 to the second communication path in accordance with the communication path instruction received from the communication path determination means 1043b. Then, the process proceeds to step S31.

<Step S30>
The communication path determination unit 1043b transmits to the selector 108 a communication path instruction that instructs the image processing unit 104b to access the memory 105 via the first communication path having a shorter latency than the second communication path. The selector 108 switches the communication path for the image processing means 104b to access the memory 105 to the first communication path in accordance with the communication path instruction received from the communication path determination means 1043b. Then, the process proceeds to step S31.

<Step S31>
The image processing unit 104b issues and transmits an access request to the memory 105, and accesses the memory 105 via the communication path switched by the selector 108 in step S29 or step S30. Then, the process proceeds to step S32.

<Step S32>
When the image processing unit 104b completes image processing for one page (step S32: Yes), the processing ends, and when the image processing unit 104b does not complete image processing for one page (step S32: No). Return to step S26.

  Through the above operation flow, the image processing unit 104b in the image forming apparatus 1b performs an operation of switching a communication path for accessing the memory 105 and an operation of accessing the memory 105 via the communication path.

  As described above, in the image forming apparatus 1b according to the present embodiment, the determination condition information set by the CPU 103 selects the first communication path when the image processing of the image processing unit 104b is RMW processing. In the case of processing other than RMW processing, a determination condition for selecting the second communication path is included, and when operation information is received from the plotter image transfer unit 102b, image processing by the image processing unit 104b is performed. Regardless of whether the RMW process is performed or not, a determination condition of selecting the second communication path is included. As a result, the effects of the first embodiment can be obtained, and when processing that must be given the highest priority, such as reading of a plotter image from the memory 105, has occurred, the memory 105 of the image processing means 104b is transferred to the memory 105. The second communication path is longer than the latency of the first communication path. As a result, it is possible to suppress problems such as the occurrence of an abnormal image due to a delay in the operation of reading the plotter image from the memory 105 by the plotter image transfer unit 102b, which is regarded as the highest priority.

1, 1a, 1b Image forming apparatus 10, 10a, 10b Controller unit 20 Engine unit 101 Scanner image transfer unit 102, 102b Plotter image transfer unit 103 CPU
104, 104a, 104b Image processing means 105 Memory 106, 106a Arbiter 107, 107a Arbiter 108 Selector 109-111 Image processing means 112 Arbiter 113 Selector 201 Scanner part 202 Image transmission part 203 Plotter part 204 Image reception part 1041, 1041b Condition setting means 1042, 1042a Access determination means 1043, 1043b Communication path determination means 1061 1st port 1062 2nd port 1063 3rd port 1064 4th port 1065 5th port 1066 Target 1061a-1066a FIFO buffer 1064b FIFO buffer 1071 1st port 1072 2nd Port 1073 Third port 1074 Fourth port 1075 Target 1071a-1075a FIFO bar File 1081,1081a first communication path output section 1082 second communication path output section 1121 first port 1122 second port 1123 target 1121A～1123a FIFO buffer 1131a first communication path output section 1132 second communication path output section

JP 2004-046851 A

Claims (10)

Storage means for storing images;
Image processing means for executing image processing on the image stored in the storage means;
A first communication path for the image processing means to access the storage means as a first bus master ;
A communication path for the image processing means to access the storage means as the first bus master, a second communication path having a longer latency than the first communication path;
When the image processing includes at least a first process that is a read-modify-write process that does not perform a process of a next command until a process based on a previous command is completed, the first communication path is selected, and the image process is performed A selection means for selecting the second communication path when including a second process that is not the first process ;
Switching means for switching to the communication path selected by the selection means;
An image processing apparatus. Before Symbol first communication path, the image processing apparatus according to claim 1 comprising a number of arbiter less than the number of the arbiter included in the second communication path. Before SL least one of buffer stages of the ports of the arbiter included in the first communication path, the image processing apparatus according to claim 1 less than the number of stages of the buffer port of the arbiter included in the second communication path . Claim wherein the selecting means, the image processing, if it contains the first processing, selects the first communication path, the image processing, if it contains the second processing, for selecting the second communication path The image processing apparatus according to 2 or 3. The selection means includes
Wherein the image processing comprises the first processing, and, when the burst length of the command of the first process is less than the number of stages of the buffer port of the arbiter included in the first communication path, the first communication path Selected,
The image processing, if it contains the second processing, or, if the burst length exceeds the number of stages of the buffer port of the arbiter included in the first communication path, claim 2 selects the second communication path, or The image processing apparatus according to 3. A second bus master different from the image processing means for transmitting operation information to the selection means when in operation;
The selection means includes
Wherein the image processing comprises the first processing, and, if from the second bus master does not receive the operation information, selects the first communication path,
If the image processing is, including the second processing, or, if from the second bus master has received the operation information, the image processing apparatus according to claim 2 or 3 selects the second communication path.   The image processing apparatus according to claim 6, wherein the second bus master is a transfer unit that reads a plotter image from the storage unit and transfers the plotter image to the plotter device. It said selection means, said image processing means, when executing a process of reading the operation mode information of said image processing means stored in the storage means, any one of claims 1 to 7 for selecting said first communication path The image processing apparatus according to one item. The selection means generates instruction information for instructing the selected communication path,
The image processing means includes the instruction information in an access request transmitted to access the storage means,
The image according to any one of claims 1 to 8 , wherein the switching unit switches the communication path for the image processing unit to access the storage unit based on the instruction information included in the access request. Processing equipment. The image processing apparatus according to any one of claims 1 to 9 ,
A plotter device for printing the plotter image stored in the storage means on a print medium;
An image forming apparatus.

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