JP6313509B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  GaN (gallium nitride) -based semiconductors are expected as materials for next-generation power semiconductor devices. A GaN-based semiconductor device has a wider band gap than Si (silicon), and can achieve higher breakdown voltage and lower loss than Si devices.

  In a GaN-based semiconductor transistor, a HEMT (High Electron Mobility Transistor) using a two-dimensional electron gas (2DEG) as a carrier is generally employed. However, a normal HEMT is a normally-on transistor that conducts without applying voltage to the gate. Therefore, there is a problem that it is difficult to realize a normally-off transistor that does not conduct unless a voltage is applied to the gate. In particular, it is difficult to realize a normally-off transistor with a high threshold voltage.

Japanese Patent No. 4282708

  An object of the present invention is to provide a semiconductor device capable of realizing normally-off with a high threshold voltage.

The semiconductor device of the embodiment is provided with a first semiconductor layer of a first GaN-based semiconductor, and a second GaN-based semiconductor having a band gap smaller than that of the first GaN-based semiconductor, provided above the first semiconductor layer. A second semiconductor layer of a semiconductor; a third semiconductor layer of a third GaN-based semiconductor which is provided above the second semiconductor layer and has a band gap larger than that of the second GaN-based semiconductor; A fourth semiconductor layer of a fourth GaN-based semiconductor having a band gap smaller than that of the third GaN-based semiconductor, and a fourth semiconductor layer provided above the fourth semiconductor layer. A fifth semiconductor layer of a fifth GaN-based semiconductor having a band gap larger than that of the GaN-based semiconductor, the fourth semiconductor layer, a gate insulating film in contact with the fifth semiconductor layer, and the fourth semiconductor Layers, and A gate electrode provided between the fifth semiconductor layer and the gate insulating film, a source electrode provided on the fifth semiconductor layer, and a gate electrode provided on the fifth semiconductor layer. And a drain electrode provided on the opposite side of the source electrode, and the first GaN-based semiconductor is Al _X1 In _Y1 Ga _{1- (X1 + Y1)} N (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1, 0 ≦ X1 + Y1 <1), and the second GaN-based semiconductor is Al _X2 In _{Y2Ga 1- (X2 + Y2)} N (0 ≦ X2 ≦ 1, 0 ≦ Y2 ≦ 1, 0 ≦ X2 + Y2 <1), The third GaN-based semiconductor is Al _X3 In _Y3 Ga _{1- (X3 + Y3)} N (0 ≦ X3 ≦ 1, 0 ≦ Y3 ≦ 1, 0 ≦ X3 + Y3 <1), and the fourth GaN-based semiconductor is Al _X4 In _Y4 Ga _{1- (X4 + Y4)} N (0 ≦ X4 ≦ 1, 0 ≦ Y4 ≦ 1, 0 ≦ X4 + Y4 <1), and the fifth GaN-based semiconductor is Al _X5 In _Y5 Ga _{1− (X5 + Y5)} N (0 ≦ X5 ≦ 1) 0 ≦ Y5 ≦ 1, 0 ≦ X5 + Y5 <1), and X1, X3, and X5 satisfy the relationship of X5>X3> X1.

1 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment. It is a figure which shows the raise effect of the threshold voltage of the semiconductor device of 1st Embodiment. It is explanatory drawing of the effect | action and effect of the semiconductor device of 1st Embodiment. It is a figure which shows the relationship between a composition and film thickness of the barrier layer of HEMT, and a two-dimensional electron gas density. It is a schematic cross section which shows the structure of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the structure of the semiconductor device of 3rd Embodiment. It is a schematic cross section which shows the structure of the semiconductor device of 4th Embodiment.

  In this specification, “GaN-based semiconductor” is a generic term for semiconductors having GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and intermediate compositions thereof.

  In this specification, the “channel region” means a semiconductor region in which the potential is positively controlled by the bias applied to the gate electrode and the carrier density changes. In this specification, the “access region” means a semiconductor region in which carriers flow between the source electrode and the gate electrode and between the gate electrode and the drain electrode.

  Further, in the present specification, “upper” and “lower” are terms indicating the relative positional relationship between components, and are not necessarily terms based on the direction of gravity.

(First embodiment)
The semiconductor device according to the present embodiment includes a first semiconductor layer of a first GaN-based semiconductor, and a second GaN-based semiconductor that is provided above the first semiconductor layer and has a smaller band gap than the first GaN-based semiconductor. A second semiconductor layer, a third semiconductor layer of a third GaN-based semiconductor having a band gap larger than that of the second GaN-based semiconductor, and a third semiconductor layer A fourth semiconductor layer of a fourth GaN-based semiconductor which is provided above and has a band gap smaller than that of the third GaN-based semiconductor, and a band gap which is provided above the fourth semiconductor layer and which is provided above the fourth GaN-based semiconductor. A fifth semiconductor layer of a large fifth GaN-based semiconductor, a third semiconductor layer, a fourth semiconductor layer, a gate insulating film provided on the fifth semiconductor layer, a third semiconductor layer, A fourth semiconductor layer, and a fifth A gate electrode provided between the semiconductor layer and a gate insulating film; a source electrode provided on the fifth semiconductor layer; and on the fifth semiconductor layer, on the opposite side of the gate electrode with respect to the source electrode. And a drain electrode provided.

  FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device of this embodiment. The semiconductor device of this embodiment is a lateral transistor using a GaN-based semiconductor.

  The transistor 100 of this embodiment includes a substrate 10, a buffer layer 12 formed on the substrate 10, a first semiconductor layer 14 formed on the buffer layer 12, and a second formed on the first semiconductor layer 14. Semiconductor layer 16, third semiconductor layer 18 formed on second semiconductor layer 16, fourth semiconductor layer 20 formed on third semiconductor layer 18, and formed on fourth semiconductor layer 20. The fifth semiconductor layer 22 is provided.

The substrate 10 is made of, for example, silicon (Si). In addition to silicon, for example, sapphire (Al ₂ O ₃ ) or silicon carbide (SiC) can be applied.

The buffer layer 12 has a function of relaxing lattice mismatch between the substrate 10 and the first semiconductor layer 14. The buffer layer 12 is formed with a multilayer structure such as aluminum gallium nitride (Al _x Ga _1-x N (0 <X <1)) or aluminum nitride (AlN), for example.

  The first semiconductor layer 14, the second semiconductor layer 16, the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 are a first GaN-based semiconductor and a second GaN-based semiconductor, respectively. It is formed of a semiconductor, a third GaN semiconductor, a fourth GaN semiconductor, and a fifth GaN semiconductor. The second GaN-based semiconductor has a smaller band gap than the first GaN-based semiconductor. The third GaN-based semiconductor has a larger band gap than the second GaN-based semiconductor. The fourth GaN-based semiconductor has a smaller band gap than the third GaN-based semiconductor. The fifth GaN-based semiconductor has a larger band gap than the fourth GaN-based semiconductor.

  Therefore, in the transistor 100, the second semiconductor layer 16 having a relatively small band gap is sandwiched between the first semiconductor layer 14 and the third semiconductor layer 18 having a relatively large band gap, and the second semiconductor layer 16 having a relatively small band gap is included. The fourth semiconductor layer 20 has a layer structure sandwiched between the third semiconductor layer 18 and the fifth semiconductor layer 22 having a relatively large band gap. Note that the magnitude relationship of the band gap of the GaN-based semiconductor can be determined by analyzing the composition of the GaN-based semiconductor.

For example, the first GaN-based semiconductor is Al _X1 In _Y1 Ga _{1- (X1 + Y1)} N (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1, 0 ≦ X1 + Y1 <1), and the second GaN-based semiconductor is Al _X2 In _{Y2 Ga 1- (X2 + Y2)} N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1,0 ≦ X2 + Y2 <1), the third GaN-based semiconductor _{Al X3 in Y3 Ga 1- (X3} + Y3) N (0 ≦ X3 ≦ 1, 0 ≦ Y3 ≦ 1, 0 ≦ X3 + Y3 <1), the fourth GaN-based semiconductor is Al _X4 In _Y4 Ga _{1− (X4 + Y4)} N (0 ≦ X4 ≦ 1, 0 ≦ Y4 ≦ 1, 0 ≦ X4 + Y4) <1) The fifth GaN-based semiconductor has a composition represented by Al _X5 In _Y5 Ga _{1- (X5 + Y5)} N (0 ≦ X5 ≦ 1, 0 ≦ Y5 ≦ 1, 0 ≦ X5 + Y5 <1).

  For example, X1 + Y1, X2 + Y2, X3 + Y3, X4 + Y4, and X5 + Y5 satisfy the relationship of X1 + Y1> X2 + Y2, X3 + Y3> X2 + Y2, and X5 + Y5> X4 + Y4, thereby satisfying the above-mentioned band gap magnitude relationship.

The first semiconductor layer 14, the second semiconductor layer 16, the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 have a film thickness (d ₁ ) and a film thickness ( d ₂ ), film thickness (d ₃ ), film thickness (d ₄ ), and film thickness (d ₅ ).

The first GaN-based semiconductor forming the first semiconductor layer 14 is, for example, undoped AlGaN (aluminum gallium nitride). The first GaN-based semiconductor may contain impurities such as C (carbon) for the purpose of increasing the breakdown voltage. The film thickness (d ₁ ) of the first semiconductor layer 14 is, for example, not less than 0.5 μm and not more than 3 μm.

The first semiconductor layer 14 functions as a threshold control layer that raises the potential of the second semiconductor 16 and increases the threshold voltage of the transistor 100. From the viewpoint of increasing the threshold voltage of the transistor 100, it is desirable that the film thickness (d ₁ ) of the first semiconductor layer 14 is larger than the film thickness (d ₂ ) of the second semiconductor layer 16.

The second GaN-based semiconductor forming the second semiconductor layer 16 is, for example, undoped GaN (gallium nitride). The film thickness (d ₂ ) of the second semiconductor layer 16 is, for example, not less than 3 nm and not more than 300 nm.

The third GaN-based semiconductor forming the third semiconductor layer 18 is, for example, undoped AlGaN (aluminum gallium nitride). The film thickness (d ₃ ) of the third semiconductor layer 18 is, for example, not less than 5 nm and not more than 30 nm.

  A heterojunction is formed at the interface between the second semiconductor layer 16 and the third semiconductor layer 18. A two-dimensional electron gas (2DEG) is formed at this interface and becomes a carrier of the transistor 100. That is, the second semiconductor layer 16 functions as a HEMT operation layer (carrier layer), and the third semiconductor layer 18 functions as a HEMT barrier layer (electron supply layer).

The fourth GaN-based semiconductor forming the fourth semiconductor layer 20 is, for example, undoped GaN (gallium nitride). The film thickness (d ₄ ) of the fourth semiconductor layer 20 is, for example, 3 nm or more and 50 nm or less.

The fifth GaN-based semiconductor forming the fifth semiconductor layer 22 is, for example, undoped AlGaN (aluminum gallium nitride). The fifth GaN-based semiconductor may contain an n-type impurity such as Si (silicon) or Ge (germanium). The film thickness (d ₅ ) of the fifth semiconductor layer 22 is, for example, not less than 3 nm and not more than 30 nm.

  A heterojunction is formed at the interface between the fourth semiconductor layer 20 and the fifth semiconductor layer 22. A two-dimensional electron gas (2DEG) is formed at this interface and becomes a carrier of the transistor 100. That is, the fourth semiconductor layer 20 functions as a HEMT operation layer (carrier layer), and the fifth semiconductor layer 22 functions as a HEMT barrier layer (electron supply layer).

  The transistor 100 includes a trench 24 having one end located in the fifth semiconductor layer 22 and the other end located in the third semiconductor layer 18. The trench 24 is formed so as to penetrate the fourth semiconductor layer 20 and reach the third semiconductor layer 18 from the surface of the fifth semiconductor layer 22 by the RIE (Reactive Ion Etching) method, for example.

  A gate insulating film 26 is provided on the inner wall of the trench 24. The gate insulating film 26 is continuously provided on the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 on the inner wall of the trench 24. The gate insulating film 24 is, for example, a silicon oxide film. In addition to the silicon oxide film, other materials such as a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film can be applied. The film thickness of the gate insulating film 26 is, for example, not less than 10 nm and not more than 100 nm.

  A gate electrode 28 is formed on the gate insulating film 26. The gate electrode 28 fills the trench 24. The gate electrode 28 is provided between the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 via the gate insulating film 26. The gate electrode 28 is, for example, p-type polysilicon doped with B (boron) or n-type polysilicon doped with P (phosphorus). In addition to polysilicon, metal silicide, metal, or the like can be applied to the gate electrode 30.

  Then, the source electrode 30 and the drain electrode 32 are formed on the fifth semiconductor layer 22. The drain electrode 32 is formed on the opposite side of the gate electrode 28 with respect to the source electrode 30.

  The source electrode 30 and the drain electrode 32 are, for example, metal electrodes, and the metal electrode is, for example, an electrode containing aluminum (Al) as a main component. An ohmic contact is desirable between the source electrode 30 and the drain electrode 32 and the fifth semiconductor layer 22. The distance between the source electrode 30 and the drain electrode 32 is, for example, about 10 μm.

FIG. 2 is a diagram showing the effect of increasing the threshold voltage of the semiconductor device of this embodiment. FIG. 2 shows the effect of increasing the threshold voltage of the transistor 100 caused by the first semiconductor layer 14 being the threshold control layer. In a HEMT composed of a GaN operating layer and an AlGaN barrier layer, the threshold voltage of a transistor may or may not have an AlGaN threshold control layer under the GaN operating layer as in this embodiment (comparative mode). It is the result of having measured. The film thickness (d ₂ ) of the operation layer (corresponding to the second semiconductor layer 16) on the threshold control layer is used as a parameter.

  As is clear from FIG. 2, the threshold voltage is increased by providing the threshold control layer. This is presumably because the two-dimensional electron gas density at the heterojunction at the interface between the operating layer and the barrier layer is lowered by raising the potential of the operating layer by the threshold control layer.

The threshold voltage depends on the film thickness (d ₂ ) of the operating layer (corresponding to the second semiconductor layer 16). When the film thickness (d ₂ ) exceeds 100 nm, the effect of increasing the threshold voltage is reduced. Therefore, the film thickness (d ₂ ) of the second semiconductor layer 16 is desirably 100 nm or less, and more desirably 50 nm or less.

  FIG. 3 is an explanatory diagram of operations and effects of the semiconductor device of this embodiment. As described above, by providing the first semiconductor layer 14 having a band gap larger than that of the second semiconductor layer 16 as a threshold control layer below the second semiconductor layer 16, the threshold voltage of the normally-off transistor can be increased. It becomes possible to raise. This is because, as described above, the density of the two-dimensional electron gas (indicated by the first 2DEG region in FIG. 3) at the interface between the second semiconductor layer 16 and the third semiconductor layer 18 is reduced, and the carrier density is reduced. This is thought to be due to a decrease.

  Therefore, if the first 2DEG region is used as an access region between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the on-resistance of the transistor increases due to the low carrier density, There arises a problem that the on-current is reduced.

  In the transistor 100 of this embodiment, a second 2DEG region in which a two-dimensional electron gas is generated is also provided at the interface between the fourth semiconductor layer 20 and the fifth semiconductor layer 22. The second 2DEG region is farther from the first semiconductor layer 14 than the first 2DEG region. Accordingly, the influence of the potential lifting effect by the first semiconductor layer 14 is small. Therefore, the density of the two-dimensional electron gas does not decrease and a high carrier density is maintained.

  In FIG. 3, a current path when the transistor 100 is on is indicated by an arrow. As indicated by arrows, in the access region between the source electrode and the gate electrode and between the gate electrode and the drain electrode, current flows through the second 2DEG region having a high carrier density. Accordingly, the on-resistance is low and the on-current is high.

  On the other hand, the channel region immediately below the gate electrode becomes a first 2DEG region in which the potential lifting effect by the first semiconductor layer 14 becomes remarkable. Therefore, the threshold voltage of the transistor 100 can be kept high.

FIG. 4 is a diagram showing the relationship between the composition and thickness of the HEMT barrier layer and the two-dimensional electron gas density. The operating layer is GaN, and the barrier layer is aluminum gallium nitride (Al _X Ga _1-X N (0 <X <1)). The horizontal axis represents the thickness of the barrier layer, and the vertical axis represents the two-dimensional electron gas density of the heterojunction. The Al composition of aluminum gallium nitride is changed in the range of X = 0.05 to X = 0.35.

  As is clear from FIG. 4, the higher the proportion of Al (aluminum) and the thicker the film thickness, the higher the two-dimensional electron gas density. Therefore, from the viewpoint of making the two-dimensional electron gas density of the second 2DEG region higher than the two-dimensional electron gas density of the first 2DEG region, the proportion of Al in the fifth semiconductor layer 22 is set to be the third semiconductor layer. It is desirable that the ratio is higher than 20 Al. Therefore, it is desirable that the above X3 and X5 indicating the Al ratio satisfy the relationship of X5> X3.

  Further, it is desirable that the Al ratio of the first semiconductor layer 14 is low from the viewpoint of lattice matching with the second semiconductor layer 16. Therefore, it is desirable that the above X1, X3, and X5 satisfy the relationship of X5> X3 ≧ X1.

  Further, it is desirable that the fifth semiconductor layer 22 contains an n-type impurity, for example, Si (silicon). When the fifth semiconductor layer 22 contains an n-type impurity, the electron concentration in the fifth semiconductor layer 22 increases. Therefore, the amount of electrons supplied to the second 2DEG region increases, and the two-dimensional electron gas density in the second 2DEG region becomes higher. Thus, the on-resistance of the transistor 100 is further reduced.

  Further, it is desirable that the ratio of In (indium) in the fifth semiconductor layer 22 is higher than the ratio of In (indium) in the third semiconductor layer 20. That is, it is desirable that Y3 and Y5 indicating the In ratio satisfy the relationship of Y5> Y3. As the In ratio increases, the two-dimensional electron gas density increases. Therefore, the two-dimensional electron gas density in the second 2DEG region becomes higher. Thus, the on-resistance of the transistor 100 is further reduced. Alternatively, the fifth semiconductor layer 22 can be thinned, and productivity is improved.

The film thickness (d ₁ ) of the first semiconductor layer 14 that is the threshold control layer is desirably 0.5 μm or more and 3 μm or less, and more desirably 1 μm or more. Below the above range, there is a possibility that the effect of raising the potential cannot be obtained sufficiently. Moreover, when it exceeds the said range, there exists a possibility that the productivity in the case of manufacture may fall.

The film thickness (d ₂ ) of the second semiconductor layer 16 that is the operation layer is desirably 3 nm to 300 nm, more desirably 100 nm, and still more desirably 50 nm. Below the above range, it may be difficult to control the film thickness. Moreover, when it exceeds the above range, there is a possibility that the effect of raising the potential cannot be obtained sufficiently.

The film thickness (d ₃ ) of the third semiconductor layer 18 that is a barrier layer is desirably 3 nm to 30 nm, and more desirably 5 nm to 10 nm. Below the above range, it may be difficult to control the film thickness. On the other hand, below the above range, it may be difficult to control the bottom of the trench 24 to be positioned in the third semiconductor layer 18 when the trench 24 is formed. On the other hand, if the above range is exceeded, the resistance when electrons flow through the sidewall of the trench 24 increases, and the on-resistance of the transistor 100 may increase.

The film thickness (d ₄ ) of the fourth semiconductor layer 20 that is the operation layer is preferably 3 nm to 50 nm, more preferably 5 nm to 20 nm. Below the above range, it may be difficult to control the film thickness. On the other hand, if the above range is exceeded, the resistance when electrons flow through the sidewall of the trench 24 increases, and the on-resistance of the transistor 100 may increase.

The film thickness (d ₅ ) of the fifth semiconductor layer 22 that is a barrier layer is desirably 3 nm or more and 30 nm or less, and more desirably 5 nm or more and 10 nm or less. Below the above range, it may be difficult to control the film thickness. On the other hand, if it falls below the above range, the electron density of the second 2DEG region may decrease. Moreover, when it exceeds the said range, there exists a possibility that a film thickness may become too thick and productivity may fall.

  As described above, according to the transistor 100 of the present embodiment, two heterojunctions are provided together with the threshold control layer to form two 2DEG regions. As a result, it is possible to achieve both increase in the threshold voltage of the channel region and reduction in resistance of the access region. Therefore, a normally-off transistor having a high threshold voltage and a high on-current can be realized.

(Second Embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that an aluminum nitride (AlN) layer is provided between the third semiconductor layer and the fourth semiconductor layer. Therefore, the description overlapping with the first embodiment is omitted.

  FIG. 5 is a schematic cross-sectional view showing the configuration of the semiconductor device of this embodiment. The semiconductor device of this embodiment is a lateral transistor using a GaN-based semiconductor.

  As shown in FIG. 5, in the transistor 200, an aluminum nitride (AlN) layer 40 is provided between the third semiconductor layer 18 and the fourth semiconductor layer 20. The bottom of the trench 24 is located in the third semiconductor layer 18. AlN can lower the etching rate when forming the trench 24 compared to AlGaN or GaN containing Ga. In other words, AlN can easily obtain a high etching selectivity with respect to AlGaN and GaN.

Therefore, the semiconductor device of this embodiment can stop the etching with the AlN layer 40 when the trench 24 is formed. Thereafter, the third semiconductor layer 18 is etched. Therefore, the controllability of the trench depth when forming the trench 24 is improved. Therefore, the film thickness controllability of the third semiconductor layer 18 below the trench 24 is also improved. Therefore, the controllability of the threshold voltage is also improved. In addition, the thickness (d ₃ ) of the third semiconductor layer 18 can be reduced, and the on-resistance of the transistor 200 can be reduced.

  The film thickness of the AlN layer 40 is desirably 1 nm or more and 10 nm or less, and more desirably 5 nm or more and 8 nm or less. Below the above range, it may be difficult to control the film thickness. Further, there is a possibility that a problem does not occur in the stopper property when the trench 24 is formed. On the other hand, when the above range is exceeded, the resistance when electrons flow to the side wall of the trench 24 increases, and the on-resistance of the transistor 200 may increase.

(Third embodiment)
The semiconductor device according to the present embodiment includes a first semiconductor layer of a first GaN-based semiconductor, and a second GaN-based semiconductor that is provided above the first semiconductor layer and has a smaller band gap than the first GaN-based semiconductor. A second semiconductor layer, a third semiconductor layer of a third GaN-based semiconductor having a band gap larger than that of the second GaN-based semiconductor, and a third semiconductor layer A fourth semiconductor layer of a fourth GaN-based semiconductor which is provided above and has a band gap smaller than that of the third GaN-based semiconductor, and a band gap which is provided above the fourth semiconductor layer and which is provided above the fourth GaN-based semiconductor. A fifth semiconductor layer of a fifth GaN-based semiconductor having a large thickness, an AlN layer provided between the third semiconductor layer and the fourth semiconductor layer, an AlN layer, a fourth semiconductor layer, and a fifth semiconductor layer Gate provided on the semiconductor layer of A gate electrode provided between the edge film and the AlN layer, the fourth semiconductor layer, and the fifth semiconductor layer via a gate insulating film; a source electrode provided on the fifth semiconductor layer; And a drain electrode provided on the opposite side of the gate electrode with respect to the source electrode.

  The first embodiment, except that an aluminum nitride (AlN) layer is provided between the third semiconductor layer and the fourth semiconductor layer, and the bottom of the trench is located in the aluminum nitride (AlN) layer. It is the same. Therefore, the description overlapping with the first embodiment is omitted.

  FIG. 6 is a schematic cross-sectional view showing the configuration of the semiconductor device of this embodiment. The semiconductor device of this embodiment is a lateral transistor using a GaN-based semiconductor.

  As shown in FIG. 6, the transistor 250 includes an aluminum nitride (AlN) layer 40 between the third semiconductor layer 18 and the fourth semiconductor layer 20. The bottom of the trench 24 is located in the aluminum nitride (AlN) layer 40. The gate insulating film 26 is provided on the AlN layer 40, the fourth semiconductor layer 20, and the fifth semiconductor layer 22. The gate electrode 28 is provided between the AlN layer 40, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 via a gate insulating film.

  A heterojunction is formed at the interface between the second semiconductor layer 16 and the third semiconductor layer 18. A two-dimensional electron gas (2DEG) is formed at this interface and becomes a carrier of the transistor 250. That is, the second semiconductor layer 16 functions as a HEMT operation layer (carrier layer), and the third semiconductor layer 18 functions as a HEMT barrier layer (electron supply layer).

  AlN can lower the etching rate when forming the trench 24 compared to AlGaN or GaN containing Ga. In other words, AlN can easily obtain a high etching selectivity with respect to AlGaN and GaN.

Therefore, the semiconductor device of this embodiment can stop the etching with the AlN layer 40 when the trench 24 is formed. Therefore, the controllability of the trench depth when forming the trench 24 is improved. Therefore, the controllability of the threshold voltage is also improved. In addition, the thickness (d ₃ ) of the third semiconductor layer 18 can be reduced, and the on-resistance of the transistor 250 can be reduced.

  From the viewpoint of reducing the influence of the heterointerface between the AlN layer 40 and the third semiconductor layer 18 on the operation of the transistor 250, the thickness of the AlN layer 40 at the bottom of the trench 24 is desirably thin. The thickness of the AlN layer 40 at the bottom of the trench 24 is desirably 0.5 nm or more and 2 nm or less.

The film thickness (d ₃ ) of the third semiconductor layer 18 is preferably 5 nm or more and 10 nm or less, for example, from the viewpoint of ensuring controllability of the threshold voltage of the transistor 250.

(Fourth embodiment)
The semiconductor device according to the present embodiment includes a first semiconductor layer of a first GaN-based semiconductor, and a second GaN-based semiconductor that is provided above the first semiconductor layer and has a smaller band gap than the first GaN-based semiconductor. A second semiconductor layer, a third semiconductor layer of a third GaN-based semiconductor having a band gap larger than that of the second GaN-based semiconductor, and a third semiconductor layer A fourth semiconductor layer of a fourth GaN-based semiconductor which is provided above and has a band gap smaller than that of the third GaN-based semiconductor, and a band gap which is provided above the fourth semiconductor layer and which is provided above the fourth GaN-based semiconductor. The fifth semiconductor layer of the fifth GaN-based semiconductor having a large thickness, the AlN layer provided between the second semiconductor layer and the third semiconductor layer, the AlN layer, the third semiconductor layer, and the fourth semiconductor On the layer and the fifth semiconductor layer Gate electrode provided between the gate insulating film, the AlN layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer with the gate insulating film interposed therebetween, and a fifth semiconductor layer A source electrode provided on the second semiconductor layer; and a drain electrode provided on a side opposite to the gate electrode with respect to the source electrode on the fifth semiconductor layer.

  FIG. 7 is a schematic cross-sectional view showing the configuration of the semiconductor device of this embodiment. The semiconductor device of this embodiment is a lateral transistor using a GaN-based semiconductor.

  The transistor 300 of this embodiment includes a substrate 10, a buffer layer 12 formed on the substrate 10, a first semiconductor layer 14 formed on the buffer layer 12, and a second formed on the first semiconductor layer 14. Semiconductor layer 16, third semiconductor layer 18 formed on second semiconductor layer 16, fourth semiconductor layer 20 formed on third semiconductor layer 18, and formed on fourth semiconductor layer 20. The fifth semiconductor layer 22 and the AlN layer 42 provided between the second semiconductor layer 16 and the third semiconductor layer 18 are provided.

The substrate 10 is made of, for example, silicon (Si). In addition to silicon, for example, sapphire (Al ₂ O ₃ ) or silicon carbide (SiC) can be applied.

The buffer layer 12 has a function of relaxing lattice mismatch between the substrate 10 and the first semiconductor layer 14. The buffer layer 12 is formed with a multilayer structure such as aluminum gallium nitride (Al _x Ga _1-x N (0 <X <1)) or aluminum nitride (AlN), for example.

  The first semiconductor layer 14, the second semiconductor layer 16, the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 are a first GaN-based semiconductor and a second GaN-based semiconductor, respectively. It is formed of a semiconductor, a third GaN semiconductor, a fourth GaN semiconductor, and a fifth GaN semiconductor. The second GaN-based semiconductor has a smaller band gap than the first GaN-based semiconductor. The third GaN-based semiconductor has a larger band gap than the second GaN-based semiconductor. The fourth GaN-based semiconductor has a smaller band gap than the third GaN-based semiconductor. The fifth GaN-based semiconductor has a larger band gap than the fourth GaN-based semiconductor.

  Therefore, in the transistor 100, the second semiconductor layer 16 and the fourth semiconductor layer 20 having a relatively small band gap include the first semiconductor layer 14, the third semiconductor layer 18, and the fifth semiconductor layer 20 having a relatively large band gap. A layer structure sandwiched between the semiconductor layers 22 is provided. Note that the magnitude relationship of the band gap of the GaN-based semiconductor can be determined by analyzing the composition of the GaN-based semiconductor.

For example, the first GaN-based semiconductor is Al _X1 In _Y1 Ga _{1- (X1 + Y1)} N (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1, 0 ≦ X1 + Y1 <1), and the second GaN-based semiconductor is Al _X2 In _{Y2 Ga 1- (X2 + Y2)} N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1,0 ≦ X2 + Y2 <1), the third GaN-based semiconductor _{Al X3 in Y3 Ga 1- (X3} + Y3) N (0 ≦ X3 ≦ 1, 0 ≦ Y3 ≦ 1, 0 ≦ X3 + Y3 <1), the fourth GaN-based semiconductor is Al _X4 In _Y4 Ga _{1− (X4 + Y4)} N (0 ≦ X4 ≦ 1, 0 ≦ Y4 ≦ 1, 0 ≦ X4 + Y4) <1) The fifth GaN-based semiconductor has a composition represented by Al _X5 In _Y5 Ga _{1- (X5 + Y5)} N (0 ≦ X5 ≦ 1, 0 ≦ Y5 ≦ 1, 0 ≦ X5 + Y5 <1).

  For example, X1 + Y1, X2 + Y2, X3 + Y3, X4 + Y4, and X5 + Y5 satisfy the relationship of X1 + Y1> X2 + Y2, X3 + Y3> X2 + Y2, and X5 + Y5> X4 + Y4, thereby satisfying the above-mentioned band gap magnitude relationship.

The first semiconductor layer 14, the second semiconductor layer 16, the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 have a film thickness (d ₁ ) and a film thickness ( d ₂ ), film thickness (d ₃ ), film thickness (d ₄ ), and film thickness (d ₅ ).

The first GaN-based semiconductor forming the first semiconductor layer 14 is, for example, undoped AlGaN (aluminum gallium nitride). The first GaN-based semiconductor may contain impurities such as C (carbon) for the purpose of increasing the breakdown voltage. The film thickness (d ₁ ) of the first semiconductor layer 14 is, for example, not less than 0.5 μm and not more than 3 μm.

The first semiconductor layer 14 functions as a threshold control layer that raises the potential of the second semiconductor 16 and increases the threshold voltage of the transistor 300. From the viewpoint of increasing the threshold voltage of the transistor 300, it is desirable that the film thickness (d ₁ ) of the _first semiconductor layer 14 is larger than the film thickness (d ₂ ) of the second semiconductor layer 16.

The second GaN-based semiconductor forming the second semiconductor layer 16 is, for example, undoped GaN (gallium nitride). The film thickness (d ₂ ) of the second semiconductor layer 16 is, for example, not less than 3 nm and not more than 300 nm.

  An aluminum nitride (AlN) layer 42 is provided between the second semiconductor layer 16 and the third semiconductor layer 18.

  A heterojunction is formed at the interface between the second semiconductor layer 16 and the AlN layer 42. A two-dimensional electron gas (2DEG) is formed at this interface and becomes a carrier of the transistor 300. That is, the second semiconductor layer 16 functions as a HEMT operation layer (carrier layer), and the AlN layer 42 functions as a HEMT barrier layer (electron supply layer). Of course, when the AlN layer 42 is thin, a two-dimensional electron gas (2DEG) may not be sufficiently formed.

The third GaN-based semiconductor forming the third semiconductor layer 18 is, for example, undoped AlGaN (aluminum gallium nitride). The film thickness (d ₃ ) of the third semiconductor layer 18 is, for example, not less than 5 nm and not more than 30 nm.

The fourth GaN-based semiconductor forming the fourth semiconductor layer 20 is, for example, undoped GaN (gallium nitride). The film thickness (d ₄ ) of the fourth semiconductor layer 20 is, for example, 3 nm or more and 50 nm or less.

The fifth GaN-based semiconductor forming the fifth semiconductor layer 22 is, for example, undoped AlGaN (aluminum gallium nitride). The fifth GaN-based semiconductor may contain an n-type impurity such as Si (silicon) or Ge (germanium). The film thickness (d ₅ ) of the fifth semiconductor layer 22 is, for example, not less than 3 nm and not more than 30 nm.

  A heterojunction is formed at the interface between the fourth semiconductor layer 20 and the fifth semiconductor layer 22. A two-dimensional electron gas (2DEG) is formed at this interface and becomes a carrier of the transistor 100. That is, the fourth semiconductor layer 20 functions as a HEMT operation layer (carrier layer), and the fifth semiconductor layer 22 functions as a HEMT barrier layer (electron supply layer).

  The transistor 300 includes a trench 24 whose one end is located in the fifth semiconductor layer 22 and whose other end is in contact with the AlN layer 42. The trench 24 is formed so as to penetrate the fourth semiconductor layer 20 and the third semiconductor layer 18 and reach the AlN layer 42 from the surface of the fifth semiconductor layer 22 by the RIE (Reactive Ion Etching) method, for example. .

  AlN can lower the etching rate when forming the trench 24 compared to AlGaN or GaN containing Ga. In other words, AlN can easily obtain a high etching selectivity with respect to AlGaN and GaN.

  Therefore, the semiconductor device of this embodiment can stop etching with the AlN layer 42 when the trench 24 is formed. Therefore, the depth controllability when forming the trench 24 is improved.

  A gate insulating film 26 is provided on the inner wall of the trench 24. The gate insulating film 26 is continuously provided on the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 on the inner wall of the trench 24. The gate insulating film 26 is provided on the AlN layer 42, the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22. The gate insulating film 24 is, for example, a silicon oxide film. In addition to the silicon oxide film, other materials such as a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film can be applied. The film thickness of the gate insulating film 26 is, for example, not less than 10 nm and not more than 100 nm.

  A gate electrode 28 is formed on the gate insulating film 26. The gate electrode 28 fills the trench 24. The gate electrode 28 is provided between the AlN layer 42, the third semiconductor layer 18, the fourth semiconductor layer 20, and the fifth semiconductor layer 22 via the gate insulating film 26. The gate electrode 28 is, for example, p-type polysilicon doped with B (boron) or n-type polysilicon doped with P (phosphorus). In addition to polysilicon, metal silicide, metal, or the like can be applied to the gate electrode 30.

  Then, the source electrode 30 and the drain electrode 32 are formed on the fifth semiconductor layer 22. The drain electrode 32 is formed on the opposite side of the gate electrode 28 with respect to the source electrode 30.

  The source electrode 30 and the drain electrode 32 are, for example, metal electrodes, and the metal electrode is, for example, an electrode containing aluminum (Al) as a main component. An ohmic contact is desirable between the source electrode 30 and the drain electrode 32 and the fifth semiconductor layer 22. The distance between the source electrode 30 and the drain electrode 32 is, for example, about 10 μm.

  In the transistor 300 of this embodiment, the vicinity of the interface between the AlN layer 42 and the second semiconductor layer 16 immediately below the trench 24 is a channel region. Carriers in the channel region are two-dimensional electron gas generated at the heterojunction at the interface between the AlN layer 42 and the second semiconductor layer 16 or a gate voltage is applied to the interface between the AlN layer 42 and the second semiconductor layer 16. The electrons are stored by When carriers are stored electrons, the channel region of the transistor 300 operates as a MISFET (Metal Insulator Field Effect Transistor) instead of a HEMT.

  In any case, as in the first embodiment, by providing the first semiconductor layer 14 as a threshold control layer below the second semiconductor layer 16, the potential of the channel region is increased and the electron density is increased. Decreases. Therefore, the threshold voltage of the normally-off transistor can be increased.

  In the transistor 300 of this embodiment, an access region in which a two-dimensional electron gas is generated is provided at the interface between the fourth semiconductor layer 20 and the fifth semiconductor layer 22 as in the first embodiment. This region is farther from the first semiconductor layer 14 than the channel region. Accordingly, the influence of the potential lifting effect by the first semiconductor layer 14 is small. Therefore, the density of the two-dimensional electron gas does not decrease and a high carrier density is maintained.

  As in the first embodiment, from the viewpoint of increasing the two-dimensional electron gas density in the access region, the Al ratio in the fifth semiconductor layer 22 is preferably higher than the Al ratio in the third semiconductor layer 20. Therefore, it is desirable that the above X3 and X5 indicating the Al ratio satisfy the relationship of X5> X3.

  Further, it is desirable that the Al ratio of the first semiconductor layer 14 is low from the viewpoint of lattice matching with the second semiconductor layer 16. Therefore, it is desirable that the above X1, X3, and X5 satisfy the relationship of X5> X3 ≧ X1.

  Further, it is desirable that the fifth semiconductor layer 22 contains an n-type impurity, for example, Si (silicon). When the fifth semiconductor layer 22 contains an n-type impurity, the electron concentration in the fifth semiconductor layer 22 increases. Therefore, the amount of electrons supplied to the access region increases, and the two-dimensional electron gas density in the access region becomes higher. Thus, the on-resistance of the transistor 300 is further reduced.

  Further, it is desirable that the ratio of In (indium) in the fifth semiconductor layer 22 is higher than the ratio of In (indium) in the third semiconductor layer 20. That is, it is desirable that Y3 and Y5 indicating the In ratio satisfy the relationship of Y5> Y3. As the In ratio increases, the two-dimensional electron gas density increases. Therefore, the two-dimensional electron gas density in the access region becomes higher. Thus, the on-resistance of the transistor 300 is further reduced. Alternatively, the fifth semiconductor layer 22 can be thinned, and productivity is improved.

The film thickness (d ₁ ) of the first semiconductor layer 14 that is the threshold control layer is desirably 0.5 μm or more and 3 μm or less, and more desirably 1 μm or more. Below the above range, there is a possibility that the effect of raising the potential cannot be obtained sufficiently. Moreover, when it exceeds the said range, there exists a possibility that the productivity in the case of manufacture may fall.

The film thickness (d ₂ ) of the second semiconductor layer 16 that is the operation layer is desirably 3 nm or more and 200 nm or less, more desirably 100 nm or less, and further desirably 50 nm or less. 5 to 3 μm, more preferably 1 μm or more. Below the above range, it may be difficult to control the film thickness. Moreover, when it exceeds the above range, there is a possibility that the effect of raising the potential cannot be obtained sufficiently.

The film thickness (d ₄ ) of the fourth semiconductor layer 20 that is the operation layer is preferably 3 nm to 50 nm, more preferably 5 nm to 20 nm. Below the above range, it may be difficult to control the film thickness. Further, if the above range is exceeded, the resistance when electrons flow to the side wall of the trench 24 increases, and the on-resistance of the transistor 300 may increase.

The film thickness (d ₅ ) of the fifth semiconductor layer 22 that is a barrier layer is desirably 3 nm or more and 30 nm or less, and more desirably 5 nm or more and 10 nm or less. Below the above range, it may be difficult to control the film thickness. On the other hand, if it falls below the above range, the electron density in the access region may decrease. Moreover, when it exceeds the said range, there exists a possibility that productivity may fall.

  From the viewpoint of reducing the influence of the heterointerface between the AlN layer 42 and the second semiconductor layer 16 on the operation of the transistor 300, the thickness of the AlN layer 42 at the bottom of the trench 24 is desirably thin. The thickness of the AlN layer 42 at the bottom of the trench 24 is desirably 0.5 nm or more and 2 nm or less.

  As described above, according to the transistor 300 of this embodiment, by introducing the threshold control layer and separating the channel region and the access region, both increase in the threshold voltage of the channel region and reduction in resistance of the access region are achieved. can do. Therefore, a normally-off transistor having a high threshold voltage and a high on-current can be realized. Further, by providing the AlN layer 42, the controllability of trench formation is improved, and the transistor 300 having stable characteristics is realized.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 substrate 12 buffer layer 14 first semiconductor layer 16 second semiconductor layer 18 third semiconductor layer 20 fourth semiconductor layer 22 fifth semiconductor layer 24 trench 26 gate insulating film 28 gate electrode 30 source electrode 32 drain electrode 40 AlN layer 42 AlN layer 100 Transistor 200 Transistor 300 Transistor

Claims (8)

A first semiconductor layer of a first GaN-based semiconductor;
A second semiconductor layer of a second GaN-based semiconductor provided above the first semiconductor layer and having a smaller band gap than the first GaN-based semiconductor;
A third semiconductor layer of a third GaN-based semiconductor provided above the second semiconductor layer and having a larger band gap than the second GaN-based semiconductor;
A fourth semiconductor layer of a fourth GaN-based semiconductor provided above the third semiconductor layer and having a smaller band gap than the third GaN-based semiconductor;
A fifth semiconductor layer of a fifth GaN-based semiconductor provided above the fourth semiconductor layer and having a larger band gap than the fourth GaN-based semiconductor;
A gate insulating film in contact with the fourth semiconductor layer and the fifth semiconductor layer;
A gate electrode provided via the gate insulating film between the fourth semiconductor layer and the fifth semiconductor layer;
A source electrode provided on the fifth semiconductor layer;
A drain electrode provided on the opposite side of the source electrode with respect to the gate electrode on the fifth semiconductor layer;
With
The first GaN-based semiconductor is Al _X1 In _Y1 Ga _{1- (X1 + Y1)} N (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1, 0 ≦ X1 + Y1 <1),
The second GaN-based semiconductor is Al _X2 In _{Y2Ga1- (X2 + Y2)} N (0 ≦ X2 ≦ 1, 0 ≦ Y2 ≦ 1, 0 ≦ X2 + Y2 <1),
Wherein the third GaN-based semiconductor _{Al X3 In Y3 Ga 1- (X3} + Y3) a N (0 ≦ X3 ≦ 1,0 ≦ Y3 ≦ 1,0 ≦ X3 + Y3 <1),
The fourth GaN-based semiconductor _{Al X4 In Y4 Ga 1- (X4} + Y4) a N (0 ≦ X4 ≦ 1,0 ≦ Y4 ≦ 1,0 ≦ X4 + Y4 <1),
The fifth is a GaN-based semiconductor _Al X5 _In Y5 _{Ga 1-} of _{(X5 + Y5) N (0} ≦ X5 ≦ 1,0 ≦ Y5 ≦ 1,0 ≦ X5 + Y5 <1),
A semiconductor device in which X1, X3, and X5 satisfy a relationship of X5>X3> X1.   The semiconductor device according to claim 1, wherein the thickness of the first semiconductor layer is 0.5 μm or more.   The semiconductor device according to claim 1, wherein a film thickness of the second semiconductor layer is 100 nm or less.   4. The semiconductor device according to claim 1, wherein the thickness of the second semiconductor layer is 50 nm or less.   5. The semiconductor device according to claim 1, wherein a thickness of the third semiconductor layer is not less than 5 nm and not more than 30 nm.   The semiconductor device according to claim 1, wherein the fifth semiconductor layer contains Si (silicon).   The semiconductor device according to claim 1, further comprising an AlN layer provided between the third semiconductor layer and the fourth semiconductor layer. The semiconductor device according to claim 1, wherein the gate insulating film is in contact with the third semiconductor layer.

Images