JP6305360B2 - Patch antenna and array antenna - Google Patents

Patch antenna and array antenna Download PDF

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JP6305360B2
JP6305360B2 JP2015038309A JP2015038309A JP6305360B2 JP 6305360 B2 JP6305360 B2 JP 6305360B2 JP 2015038309 A JP2015038309 A JP 2015038309A JP 2015038309 A JP2015038309 A JP 2015038309A JP 6305360 B2 JP6305360 B2 JP 6305360B2
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dielectric layer
patch
formed
ground
conductor
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JP2016163120A (en
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丸山 貴史
貴史 丸山
森本 康夫
康夫 森本
北村 洋一
洋一 北村
西村 俊雄
俊雄 西村
大和田 哲
哲 大和田
田原 志浩
志浩 田原
大塚 昌孝
昌孝 大塚
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三菱電機株式会社
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  The present invention relates to a patch antenna and an array antenna mounted on, for example, a communication device or a radar device that transmits and receives signals.

For example, in the case of an antenna that transmits and receives a signal with a frequency of about 10 GHz or less, it is manufactured using, for example, a conductor pattern on a resin substrate, metal processing, or the like.
In the case of an antenna that transmits and receives a signal of a frequency such as a millimeter wave band higher than the above frequency, the antenna can be downsized because the wavelength is short. Therefore, the integrated circuit may be formed in an IC or an IC package.

Patent Document 1 below discloses a method of forming an antenna on an IC package which is a small-sized IC.
In this method, since the antenna is formed in the IC package, a three-dimensional structure can be obtained. Therefore, there is a degree of freedom in design and impedance matching is easy.
Non-Patent Document 1 below discloses a method of forming an antenna feeding portion on an IC itself and forming an antenna radiating portion on a dielectric provided above the feeding portion.
If the methods described in Patent Document 1 and Non-Patent Document 1 are used, the antenna can be manufactured within the IC or IC package manufacturing process without separately manufacturing the antenna.

JP 2009-278005 A (FIG. 1)

A 108-114 GHz 44 Wafer-Scale Phased Array Transmitter With High-Efficiency On-Chip Antennas, IEEE Journal of solid-state circuits, vol. 48, no. 9, Sept 2013

Since the conventional patch antenna is configured as described above, in the case of Patent Document 1, the antenna is formed in an IC package. For this reason, if a large number of IC packages are arranged, a large-scale array antenna can be manufactured. However, in order to reduce the size of the array antenna, it is necessary to narrow the interval between the IC packages. Depending on the interval, it is difficult to arrange the IC packages, which makes it impossible to manufacture the array antenna.
In the case of Non-Patent Document 1, a large number of antennas can be formed as long as the area of the IC wafer permits. However, since antennas and transmission lines are formed on the thin film of the IC, There is little freedom. Therefore, since the thickness direction cannot be adjusted, there is a problem that an increase in loss may be caused or impedance matching between the antenna and the transmission line may become difficult.

The present invention has been made to solve the above-described problems, and it is possible to easily manufacture a large-scale array antenna and to obtain a low-loss patch antenna that can easily achieve impedance matching. With the goal.
Another object of the present invention is to obtain a low-loss array antenna that can easily achieve impedance matching.

A patch antenna according to the present invention includes a high-frequency circuit for transmitting and receiving a radio frequency signal on a surface thereof, a semiconductor wafer on which input / output terminals for inputting and outputting a radio frequency signal to and from the high-frequency circuit are formed, and an upper portion of the semiconductor wafer a first dielectric layer formed on, provided above the first dielectric layer, a conductor layer ground is formed, it is provided on top of the conductor layer on the surface, a radio frequency signal A second dielectric layer formed with a transmission line formed of a conductor for radiating the light into the space and having a transmission line electrically connected to the excitation patch at one end ; and a second dielectric A third dielectric layer provided on the body layer, wherein a non-excitation patch made of a conductor is formed on the surface facing the excitation patch, and the first dielectric layer is electrically disconnected from the ground through in transmission And a first interlayer connection conductor for electrically connecting the other end with the output terminal of the road, the first dielectric layer, a rewiring layer formed on the surface of the semiconductor wafer by a second dielectric layer The double patch antenna is configured by the excitation patch, the ground, and the non-excitation patch .

According to the present invention, a high-frequency circuit for transmitting and receiving a radio frequency signal on the surface, a semiconductor wafer on which an input / output terminal for inputting and outputting a radio frequency signal to and from the high-frequency circuit is formed, and an upper portion of the semiconductor wafer a first dielectric layer is provided on top of the first dielectric layer, a conductor layer ground is formed, is provided on top of the conductor layer on the surface, the space radiofrequency signals A second dielectric layer in which an excitation patch made of a conductor for radiating to the antenna is formed, and a transmission line in which one end of the excitation patch is electrically connected is formed; and a second dielectric layer A non-excited patch made of a conductor is formed on the surface of the non-excited patch facing the excited patch, and the first dielectric layer is electrically disconnected from the ground. other end inlet of the through to the transmission line And a first interlayer connection conductor for electrically connecting the power terminal, the first dielectric layer, constitute a rewiring layer formed on the surface of the semiconductor wafer by a second dielectric layer, and the excitation patches Since the double patch antenna is constituted by the ground and the non-excited patch, it is possible to easily manufacture a large-scale array antenna and to obtain a low-loss patch antenna that can easily achieve impedance matching. is there.

It is a disassembled perspective view which shows the patch antenna by Embodiment 1 of this invention. It is a disassembled perspective view which shows the patch antenna by Embodiment 2 of this invention. It is a disassembled perspective view which shows the other patch antenna by Embodiment 2 of this invention. It is a disassembled perspective view which shows the patch antenna by Embodiment 3 of this invention. It is a disassembled perspective view which shows the other patch antenna by Embodiment 3 of this invention. It is a disassembled perspective view which shows the other patch antenna by Embodiment 3 of this invention. It is a disassembled perspective view which shows the array antenna by Embodiment 4 of this invention. It is a disassembled perspective view which shows the array antenna by Embodiment 5 of this invention.

  Hereinafter, in order to describe the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG.
1 is an exploded perspective view showing a patch antenna according to Embodiment 1 of the present invention.
In FIG. 1, a high frequency circuit for transmitting and receiving radio frequency signals is formed on a semiconductor wafer 1, and an input for inputting and outputting a radio frequency signal to the semiconductor wafer 1 is also provided on the semiconductor wafer 1. An output terminal 2 is formed.
The dielectric layer 11 is a first dielectric layer provided on the semiconductor wafer 1.
The conductor layer 12 is provided on the top of the dielectric layer 11, and a ground 12a is formed. The conductor layer 12 is provided with a small hole 12 b for avoiding a short circuit with the interlayer connection conductor 31.

The dielectric layer 13 is a second dielectric layer provided on the conductor layer 12, and a ring patch 14 which is an excitation patch made of a conductor is formed on the surface of the dielectric layer 13, and the ring A transmission line 15 connected to the patch 14 is formed.
The dielectric layer 11, the conductor layer 12, and the dielectric layer 13 constitute a redistribution layer (RDL: Redistribution layer).

The dielectric layer 21 which is a dielectric substrate is a third dielectric layer provided on the top of the dielectric layer 13, and a non-excitation patch 22 made of a conductor is formed on the surface of the dielectric layer 21. Yes.
The dielectric layer 21 may be a dielectric made of a low-loss material having a low dielectric loss tangent, and the thickness of the dielectric layer 21 is flexible.
The interlayer connection conductor 31 is a first interlayer connection conductor that electrically connects the transmission line 15 and the input / output terminal 2.
The interlayer connection conductor 31 is passed through a small hole 12b provided in the conductor layer 12 so as not to short-circuit the ground 12a formed in the conductor layer 12.

Next, the operation will be described.
For example, when a high frequency circuit formed on the semiconductor wafer 1 outputs a radio frequency signal to the input / output terminal 2, the input / output terminal 2 is electrically connected to the transmission line 15 via the interlayer connection conductor 31. Since the transmission line 15 is electrically connected to the ring patch 14, the radio frequency signal is fed to the ring patch 14 which is an excitation patch.
Thereby, the ring patch 14 is excited to radiate a radio frequency signal to the space.

In the first embodiment, since the non-excited patch 22 formed on the surface of the dielectric layer 21 is disposed above the ring patch 14, the ring patch 14, the non-excited patch 22, and the conductor layer 12 are provided. A double patch antenna is formed by the formed ground 12a.
In the configuration in which the non-excitation patch 22 is not disposed, the input impedance of the antenna becomes low, and therefore, for example, it may be difficult to connect the transmission line 15 having an impedance of about 50Ω to the ring patch 14. Alternatively, in order to connect the transmission line 15 and the ring patch 14, it may be necessary to connect an impedance converter having a large impedance conversion ratio to the transmission line 15.
In addition, the usable frequency band may be narrowed due to the narrow distance between the ground 12a formed in the conductor layer 12 and the ring patch 14.
As described above, it may be difficult to manufacture a practical antenna in a configuration in which the non-excitation patch 22 is not disposed.

  In the first embodiment, since the non-excitation patch 22 is disposed, the input impedance of the antenna is increased, and the ring patch is provided even when the distance between the ground 12a formed in the conductor layer 12 and the ring patch 14 is narrow. The adjustment between the transmission line 15 and the ring patch 14 can be easily achieved only by adjusting the inner diameter and the outer diameter of 14. Therefore, in order to connect the transmission line 15 and the ring patch 14, there is no need to connect an impedance converter having a large impedance conversion ratio to the transmission line 15.

In general, a double patch antenna has a wider band than a simple patch antenna, and can expand a usable frequency band.
In this Embodiment 1, since the double patch antenna is formed, the usable frequency band can be expanded.
In general, the patch antenna can reduce loss as the thickness between the patch and the ground increases.
In the first embodiment, the dielectric layers 11 and 13 which are the dielectrics of the rewiring layer are thicker than the layers in the semiconductor wafer 1, and therefore, compared with the case where the antenna is formed on the semiconductor wafer 1, Loss can be reduced.

A high-frequency circuit for transmitting and receiving radio frequency signals is formed on the semiconductor wafer 1. When an antenna is formed on the semiconductor wafer 1, the high-frequency circuit is formed by an area necessary for forming the antenna. The possible area is reduced and the layout of the high-frequency circuit becomes difficult.
In the first embodiment, as described above, since no antenna is formed on the semiconductor wafer 1, a high-frequency circuit can be formed on the entire surface of the semiconductor wafer 1, and the layout of the high-frequency circuit is facilitated. Therefore, a large-scale array antenna can be easily manufactured.

  As apparent from the above, according to the first embodiment, the double patch antenna is formed by the ring patch 14 and the non-excited patch 22 and the ground 12a formed on the conductor layer 12. Therefore, it is possible to easily manufacture a large-scale array antenna and to obtain a low-loss patch antenna that can easily achieve impedance matching.

In the first embodiment, the surface of the dielectric layer 13 has the ring patch 14 having pores formed therein as the excitation patch. However, the inner diameter of the ring patch 14 is not adjusted. When the alignment between the transmission line 15 and the ring patch 14 can be achieved only by adjusting the outer diameter of the ring patch 14, the opening inside the ring patch 14 is eliminated, and a circular or rectangular patch is used as the excitation patch. Alternatively, it may be formed on the surface of the dielectric layer 13.
In addition, the dielectric material layer 21 should just be a dielectric material, for example, a glass substrate, a resin substrate, etc. may be sufficient as it.

In the first embodiment, the ground 12a is formed on the conductor layer 12. However, the ground 12a may be a mesh ground. The mesh ground can be formed, for example, by wiring conductors in a mesh pattern on the front surface, side surface, and back surface of the dielectric.
In the case where the ground 12a is a mesh ground, the impedance of the transmission line 15 rises and it may be difficult to achieve matching with the antenna. In the first embodiment, the inner diameter and the outer diameter of the ring patch 14 may be used. It is possible to easily match between the transmission line 15 and the ring patch 14 only by adjusting.

Embodiment 2. FIG.
2 is an exploded perspective view showing a patch antenna according to Embodiment 2 of the present invention. In FIG. 2, the same reference numerals as those in FIG.
However, in the second embodiment, the conductor layer 12 constitutes the first conductor layer, and the dielectric layer 21 constitutes the fourth dielectric layer.

The dielectric layer 41 is a second dielectric layer provided on the conductor layer 12, and a transmission line 42 is formed on the surface of the dielectric layer 41.
In the portion of the dielectric layer 41 that is sandwiched between the ground 12a formed in the conductor layer 12 and the ground 44a formed in the conductor layer 44 and the transmission line 42 is not formed, For example, a power line or a control line for driving a high frequency circuit formed on the semiconductor wafer 1 may be formed. The power supply line, the control line, and the like are assumed to be connected to a high frequency circuit formed on the semiconductor wafer 1 by an interlayer connection conductor (not shown), for example.

The dielectric layer 43 is a third dielectric layer provided on top of the dielectric layer 41.
The conductor layer 44 is a second conductor layer provided on the upper side of the dielectric layer 43. The conductor layer 44 is provided with a ground 44a, and an opening 44b formed on the ground 44a is provided with a conductor. A ring patch 45 which is an excitation patch made of is formed.
A rewiring layer is composed of the dielectric layer 11, the conductor layer 12, the dielectric layers 41 and 43, and the conductor layer 44.

The interlayer connection conductor 51 is a first interlayer connection conductor that electrically connects the transmission line 42 and the input / output terminal 2.
The interlayer connection conductor 51 is passed through a small hole 12b provided in the conductor layer 12 so as not to short-circuit with the ground 12a formed in the conductor layer 12.
The interlayer connection conductor 52 is a second interlayer connection conductor that electrically connects the ring patch 45 and the transmission line 42.
The interlayer connection conductor 53 is a third interlayer connection conductor that electrically connects the ground 12 a formed in the conductor layer 12 and the ground 44 a formed in the conductor layer 44.
FIG. 2 shows an example in which several interlayer connection conductors 53 are arranged to make the drawing easy to see. For example, the opening 44b extends along the opening 44b formed on the ground 44a. The interlayer connection conductor 53 may be arranged over the entire circumference.

Next, the operation will be described.
For example, when a high frequency circuit formed on the semiconductor wafer 1 outputs a radio frequency signal to the input / output terminal 2, the input / output terminal 2 is electrically connected to the transmission line 42 via the interlayer connection conductor 51. Since the transmission line 42 is electrically connected to the ring patch 45 via the interlayer connection conductor 52, the radio frequency signal is fed to the ring patch 45 which is an excitation patch.
Thereby, the ring patch 45 is excited, and a radio frequency signal is radiated into the space.

In the second embodiment, since the non-excited patch 22 formed on the surface of the dielectric layer 21 is disposed above the ring patch 45, the ring patch 45 and the non-excited patch 22, the conductor layers 12, A double patch antenna is formed by the grounds 12 a and 44 a formed on 44.
Also in the second embodiment, since the double patch antenna is formed, impedance matching between the transmission line 42 and the antenna can be easily achieved for the same reason as in the first embodiment.

  In the second embodiment, since the two dielectric layers 41 and 43 are provided between the conductor layer 44 in which the ring patch 45 is formed and the conductor layer 12 in which the ground 12a is formed, Compared to the first embodiment, the distance between the ring patch 45 and the ground 12a is increased. For this reason, signal loss can be further reduced as compared with the first embodiment.

In the second embodiment, not only the ground 12a formed in the conductor layer 12 but also the ground 44a formed in the conductor layer 44 plays a role of the ground of the double patch antenna.
That is, since the ground 12a is disposed on the lower surface of the transmission line 42 and the ground 44a is disposed on the upper surface of the transmission line 42, a triplate line is formed. Since the transmission line is a triplate line, signal loss in the transmission line 42 can be further reduced as compared with the first embodiment.

In the second embodiment, the grounds 12a and 44a are formed on the conductor layers 12 and 44. However, at least one of the grounds 12a and 44a may be a mesh ground.
In the case where the grounds 12a and 44a are mesh grounds, the impedance of the transmission line 42 increases and it may be difficult to achieve matching with the antenna. Matching between the transmission line 42 and the ring patch 45 can be easily achieved only by adjusting the outer diameter.

In the second embodiment, an example in which there is one input / output terminal 2 formed on the semiconductor wafer 1 and one transmission line 42 electrically connected to the ring patch 45 and the input / output terminal 2 is used. As shown in FIG. 3, there are two input / output terminals 2 formed on the semiconductor wafer 1 and two transmission lines 42 electrically connected to the ring patch 45 and the input / output terminals 2. It may be.
According to the configuration of FIG. 3, for example, the signal amplitudes at the two input / output terminals 2 are the same, and the line lengths of the two transmission lines 42 are adjusted, so By adjusting the phase of the signal, it is possible to transmit and receive a specific polarization such as a circular polarization. In addition, by adjusting the amplitude and phase of the signal at the two input / output terminals 2 to adjust the phase of the signal at the two feeding points in the ring patch 45, specific polarization such as circular polarization is transmitted and received. It becomes possible to do.

  In the second embodiment, a ring patch 45 having holes inside is formed as an excitation patch in the opening 44b formed in the ground 44a. However, the inner diameter of the ring patch 45 is adjusted. In the case where the alignment between the transmission line 42 and the ring patch 45 can be achieved only by adjusting the outer diameter of the ring patch 45, the opening inside the ring patch 45 is eliminated, and the circular or rectangular patch May be formed in the opening 44b formed in the ground 44a.

Embodiment 3 FIG.
In the first and second embodiments, the input / output terminal 2 is formed on the semiconductor wafer 1. However, in addition to the input / output terminal 2, a ground may be formed on the semiconductor wafer 1. Good.

4 is an exploded perspective view showing a patch antenna according to Embodiment 3 of the present invention. In FIG. 4, the same reference numerals as those in FIG.
The conductor layer 12 is provided with an opening 12 c having the same shape as the opening 44 b of the conductor layer 44.
A ground 1 a having the same shape as the opening 44 b of the conductor layer 44 is formed on the surface of the semiconductor wafer 1.
FIG. 4 shows an example in which the opening 44b, the opening 12c, and the ground 1a have the same shape. However, the opening 12c and the ground 1a need only be larger than the ring patch 45, and are necessarily the same shape as the opening 44b. There is no need.
The interlayer connection conductor 61 electrically connects the ground 1 a formed on the semiconductor wafer 1, the ground 12 a formed on the conductor layer 12, and the ground 44 a formed on the conductor layer 44. FIG. 4 shows an example in which the interlayer connection conductor 61 is a straight line vertically, but it may be bent in the middle or may be a straight line diagonally. The interlayer connection conductor 61 constitutes a third interlayer connection conductor and a fourth interlayer connection conductor.
FIG. 4 shows an example in which several interlayer connection conductors 61 are arranged to make the drawing easy to see. For example, the opening 44b extends along the opening 44b formed on the ground 44a. The interlayer connection conductor 61 may be arranged over the entire circumference.

Next, the operation will be described.
For example, when a high frequency circuit formed on the semiconductor wafer 1 outputs a radio frequency signal to the input / output terminal 2, the input / output terminal 2 is electrically connected to the transmission line 42 via the interlayer connection conductor 51. Since the transmission line 42 is electrically connected to the ring patch 45 via the interlayer connection conductor 52, the ring patch whose radio frequency signal is an excitation patch as in the second embodiment. 45 is fed.
Thereby, the ring patch 45 is excited, and a radio frequency signal is radiated into the space.

The configuration of the patch antenna of FIG. 4 is basically the same as the configuration of the patch antenna of FIG. 2, and the same effect as the patch antenna of FIG. 2 can be obtained.
However, in the patch antenna of FIG. 2, the ground 44a formed in the conductor layer 44 and the ground 12a formed in the conductor layer 12 play the role of the ground of the double patch antenna. The patch antenna of FIG. 4 is different in that the ground 44a formed on the conductor layer 44 and the ground 1a formed on the semiconductor wafer 1 serve as the ground of the double patch antenna.
In the third embodiment, the ground patch 1a is used as the ground on the lower side of the ring patch 45 among the grounds of the double patch antenna due to the above-described differences. Therefore, the ring patch 45 is more than in the second embodiment. The distance between the ground 44a that is the upper ground and the ground on the lower side is increased. Therefore, signal loss in the transmission line 42 can be further reduced as compared with the second embodiment.

  In the third embodiment, since the ground 1a is formed on the surface of the semiconductor wafer 1, the area where a high frequency circuit can be formed on the surface of the semiconductor wafer 1 is reduced as compared with the second embodiment. However, in the semiconductor wafer 1, when a conductor layer exists below the layer on which the ground 1a is formed, a high-frequency circuit may be formed in the conductor layer.

5 is an exploded perspective view showing another patch antenna according to Embodiment 3 of the present invention.
In the patch antenna of FIG. 5, the ground formed on the conductor layer 44 is a mesh ground 44c, the ground formed on the conductor layer 12 is a mesh ground 12d, and the conductor layer 12 has an opening 12c. Is different from the patch antenna of FIG.
Thereby, the ground below the ring patch 45 among the grounds of the double patch antenna has a double structure of the mesh ground 12d and the ground 1a. Also in this case, the signal loss in the transmission line 42 can be reduced as in the patch antenna of FIG.

In the third embodiment, the ground 1a is formed on the surface of the semiconductor wafer 1 in the patch antenna of FIG. 2, but the ground 1a is formed on the surface of the semiconductor wafer 1 in the patch antenna of FIG. It may be.
FIG. 6 is an exploded perspective view showing another patch antenna according to Embodiment 3 of the present invention.
In the example of FIG. 6, the interlayer connection conductor 62 as the second interlayer connection conductor electrically connects the ground 1 a formed on the semiconductor wafer 1 and the ground 12 a formed on the conductor layer 12. .
In this case, since the ground 1a formed on the semiconductor wafer 1 serves as the ground of the double patch antenna, the distance between the ring patch 14 and the ground is larger than that in the first embodiment. For this reason, it is possible to further reduce signal loss in the transmission line 15 than in the first embodiment.

Embodiment 4 FIG.
In the first to third embodiments, one patch antenna is shown. However, an array antenna is configured by integrally forming any one of the patch antennas of FIG. 1 to FIG. You may make it do.

FIG. 7 is an exploded perspective view showing an array antenna according to Embodiment 4 of the present invention.
In the example of FIG. 7, four openings 44b are formed in the ground 44a formed in the conductor layer 44, and ring patches 45 are formed in the four openings 44b, respectively. In addition, four non-excitation patches 22 are formed on the surface of the dielectric layer 21.
The configuration is almost the same as that of the patch antenna of FIG. 2 except that four ring patches 45 and four non-excited patches 22 are formed. However, since the four ring patches 45 are formed, the four input / output terminals 2, the four transmission lines 42, and the four interlayer connection conductors 51 are partially hidden in the drawing. Four small holes 12b are provided.

The operation of the four patch antennas constituting the array antenna is the same as the operation of the patch antenna of FIG. 2, and the same effect as in the second embodiment can be obtained.
In general, when an array antenna is configured by arranging a plurality of patch antennas, the ground between adjacent patch antennas may be cut depending on manufacturing conditions and the like.
When the ground between the patch antennas is cut, the performance of the array antenna may deteriorate due to diffracted waves leaking from the cut portion.
In the fourth embodiment, four openings 44b are provided with respect to the ground 44a formed in the conductor layer 44, and then ring patches 45 are formed in the four openings 44b. Since the grounds 44a of the four ring patches 45 are integrated, the grounds 44a between the adjacent ring patches 45 are not cut.
For this reason, according to the fourth embodiment, the deterioration of the radiation pattern due to the cutting of the ground does not occur.

Here, as an example, an array antenna in which a plurality of patch antennas in FIG. 2 are formed is shown, but an array antenna in which a plurality of patch antennas in FIG. 1 or FIGS. For the same reason, the same effect as the array antenna of FIG. 7 can be obtained.
In the array antenna of FIG. 7, four patch antennas are formed. However, since the rewiring layer is formed with an area that is the same as or close to the area of the semiconductor wafer 1, the area of the rewiring layer is shown. As many as possible, a large number of patch antennas may be formed.

  In the array antenna of the fourth embodiment, the high-frequency circuit formed on the semiconductor wafer 1 fixes the signal phase at each patch antenna so that the antenna is directed in a specific direction. Alternatively, it may be a phased array antenna apparatus that can electrically control the directivity of the antenna by changing the phase of the signal at each patch antenna.

Embodiment 5. FIG.
In the fourth embodiment, four non-excitation patches 22 are formed on the surface of one dielectric layer 21, but the dielectric layer 21 is divided for each non-excitation patch 22. It may be.
8 is an exploded perspective view showing an array antenna according to Embodiment 5 of the present invention.

The material used for the dielectric layer 21 may be smaller than that of the semiconductor wafer 1.
Moreover, even if the material used for the dielectric layer 21 is the same size as the semiconductor wafer 1, the semiconductor wafer 1 and the dielectric layer 21 are too large. When the semiconductor wafer 1 and the dielectric layer 21 are bonded, a uniform finish may not be obtained.
In the case as described above, the dielectric layer 21 is divided into small pieces so that one non-excitation patch 22 is formed on one dielectric layer 21 so that the plurality of dielectric layers 21 are arranged. May be.
Even if the dielectric layer 21 is made smaller, since the ground 44a of the four ring patches 45 is integrated as in the fourth embodiment, the deterioration of the radiation pattern due to the cutting of the ground, etc. Does not occur.
Here, the dielectric layer 21 is divided into small pieces and one non-excited patch 22 is formed on one dielectric layer 21, but there is a problem that a uniform finish cannot be obtained. Two or more non-excited patches 22 may be formed in one piece of the dielectric layer 21 within a range that does not exist.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  DESCRIPTION OF SYMBOLS 1 Semiconductor wafer, 1a ground, 2 Input / output terminal, 11 Dielectric layer (1st dielectric layer), 12 Conductor layer (1st conductor layer), 12a Ground, 12b Small hole, 12c Opening part, 12d Mesh ground , 13 Dielectric layer (second dielectric layer), 14 Ring patch (excitation patch), 15 Transmission line, 21 Dielectric layer (third dielectric layer, fourth dielectric layer), 22 Non-excitation patch , 31 Interlayer connection conductor (first interlayer connection conductor), 41 Dielectric layer (second dielectric layer), 42 Transmission line, 43 Dielectric layer (third dielectric layer), 44 Conductor layer (second Conductor layer), 44a ground, 44b opening, 44c mesh ground, 45 ring patch (excitation patch), 51 interlayer connection conductor (first interlayer connection conductor), 52 interlayer connection conductor (second interlayer connection conductor), 53 layers Inter-layer connection conductor, 61 interlayer connection conductor (third interlayer connection conductor, fourth interlayer connection conductor), 62 interlayer connection conductor (second interlayer connection conductor).

Claims (12)

  1. A high-frequency circuit for transmitting and receiving radio frequency signals on the surface, and a semiconductor wafer on which input / output terminals for inputting and outputting radio frequency signals to and from the high-frequency circuit are formed;
    A first dielectric layer provided on top of the semiconductor wafer;
    A conductor layer provided on top of the first dielectric layer and having a ground formed thereon;
    An excitation patch made of a conductor for radiating the radio frequency signal to space is formed on the surface of the conductor layer, and one end of the excitation patch is electrically connected to the conductor layer. A second dielectric layer in which a transmission line is formed;
    A third dielectric layer provided on top of the second dielectric layer and having a non-excited patch made of a conductor formed on the surface facing the excited patch ;
    A first interlayer connection conductor that penetrates the first dielectric layer in an electrically unconnected state with the ground and electrically connects the other end of the transmission line and the input / output terminal ;
    A rewiring layer provided on the surface of the semiconductor wafer is constituted by the first dielectric layer and the second dielectric layer, and a double patch antenna is constituted by the excitation patch, the ground, and the non-excitation patch. patch antenna.
  2. A high-frequency circuit for transmitting and receiving radio frequency signals on the surface, and a semiconductor wafer on which input / output terminals for inputting and outputting radio frequency signals to and from the high-frequency circuit are formed;
    A first dielectric layer provided on top of the semiconductor wafer;
    A first conductor layer provided on top of the first dielectric layer and having a ground formed thereon;
    A second dielectric layer provided on top of the first conductor layer and forming a transmission line;
    A third dielectric layer provided on top of the second dielectric layer;
    An excitation patch is provided on the third dielectric layer, and a ground is formed. An excitation patch made of a conductor for radiating the radio frequency signal to the space is provided in an opening provided in the ground. A formed second conductor layer;
    A fourth dielectric layer provided on the second conductor layer and having a non-excitation patch made of a conductor formed on a surface thereof facing the excitation patch ;
    A first interlayer connection conductor that penetrates the first dielectric layer in an electrically unconnected state with the ground by the first conductor layer and electrically connects one end of the transmission line and the input / output terminal. When,
    A second interlayer connection conductor that penetrates the third dielectric layer and electrically connects the excitation patch and the other end of the transmission line;
    The ground formed in the first conductor layer and the ground formed in the second conductor layer are electrically connected through the third dielectric layer and the second dielectric layer. and a third interlayer connection conductor,
    The first dielectric layer, the second dielectric layer, and the third dielectric layer constitute a redistribution layer provided on the surface of the semiconductor wafer, and the excitation patch and the first conductor layer A patch antenna that constitutes a double patch antenna with the ground formed on the ground, the ground formed on the second conductor layer, and the non-excited patch .
  3.   The patch antenna according to claim 1 or 2, wherein the excitation patch is a ring patch having a hole inside.
  4.   The patch antenna according to claim 1 or 2, wherein the excitation patch is a circular or rectangular patch.
  5. An opening is applied to the ground formed in the conductor layer, and a ground having the same shape as the opening is formed in the semiconductor wafer.
    The patch antenna according to claim 1, further comprising a second interlayer connection conductor that electrically connects a ground formed on the semiconductor wafer and a ground formed on the conductor layer.
  6.   The patch antenna according to claim 1 or 5, wherein the ground formed in the conductor layer is a mesh ground in which conductors are wired in a mesh pattern.
  7. An opening having the same shape as the opening formed in the ground formed in the second conductor layer is formed in the ground formed in the first conductor layer and has the same shape as the opening. Is formed on the semiconductor wafer,
    3. The patch antenna according to claim 2, further comprising a fourth interlayer connection conductor that electrically connects a ground formed on the semiconductor wafer and a ground formed on the first conductor layer.
  8.   At least one of the ground formed in the first conductor layer and the ground formed in the second conductor layer is a mesh ground in which conductors are wired in a mesh shape. The patch antenna according to claim 2 or 7.
  9. A high-frequency circuit for transmitting and receiving radio frequency signals on the surface, and a semiconductor wafer on which input / output terminals for inputting and outputting radio frequency signals to and from the high-frequency circuit are formed;
    A first dielectric layer provided on top of the semiconductor wafer;
    A conductor layer provided on top of the first dielectric layer and having a ground formed thereon;
    An excitation patch made of a conductor for radiating the radio frequency signal to space is formed on the surface of the conductor layer, and one end of the excitation patch is electrically connected to the conductor layer. A second dielectric layer in which a transmission line is formed;
    A third dielectric layer provided on top of the second dielectric layer and having a non-excited patch made of a conductor formed on the surface facing the excited patch ;
    A first interlayer connection conductor that penetrates the first dielectric layer in an electrically unconnected state with the ground and electrically connects the other end of the transmission line and the input / output terminal ;
    A rewiring layer provided on the surface of the semiconductor wafer is constituted by the first dielectric layer and the second dielectric layer, and a double patch antenna is constituted by the excitation patch, the ground, and the non-excitation patch. An array antenna in which a plurality of patch antennas are integrally formed.
  10.   10. The array according to claim 9, wherein a third dielectric layer in the plurality of patch antennas is divided, and the non-excited patch is formed in the divided third dielectric layer. antenna.
  11. A high-frequency circuit for transmitting and receiving radio frequency signals on the surface, and a semiconductor wafer on which input / output terminals for inputting and outputting radio frequency signals to and from the high-frequency circuit are formed;
    A first dielectric layer provided on top of the semiconductor wafer;
    A first conductor layer provided on top of the first dielectric layer and having a ground formed thereon;
    A second dielectric layer provided on top of the first conductor layer and forming a transmission line;
    A third dielectric layer provided on top of the second dielectric layer;
    An excitation patch is provided on the third dielectric layer, and a ground is formed. An excitation patch made of a conductor for radiating the radio frequency signal to the space is provided in an opening provided in the ground. A formed second conductor layer;
    A fourth dielectric layer provided on the second conductor layer and having a non-excitation patch made of a conductor formed on a surface thereof facing the excitation patch ;
    A first interlayer connection conductor that penetrates the first dielectric layer in an electrically unconnected state with the ground by the first conductor layer and electrically connects one end of the transmission line and the input / output terminal. When,
    A second interlayer connection conductor that penetrates the third dielectric layer and electrically connects the excitation patch and the other end of the transmission line;
    The ground formed in the first conductor layer and the ground formed in the second conductor layer are electrically connected through the third dielectric layer and the second dielectric layer. A third interlayer connection conductor; and
    The first dielectric layer, the second dielectric layer, and the third dielectric layer constitute a redistribution layer provided on the surface of the semiconductor wafer, and the excitation patch and the first conductor layer An array antenna in which a plurality of patch antennas constituting a double patch antenna are integrally formed by the ground formed on the second conductor layer, the ground ground formed on the second conductor layer, and the non-excited patch .
  12.   12. The array according to claim 11, wherein a fourth dielectric layer in the plurality of patch antennas is divided, and the non-excited patch is formed in the divided fourth dielectric layer. antenna.
JP2015038309A 2015-02-27 2015-02-27 Patch antenna and array antenna Active JP6305360B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356623A (en) * 2016-12-02 2017-01-25 北京富奥星电子技术有限公司 High-grain and broad-beam antenna

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FR2651926B1 (en) * 1989-09-11 1991-12-13 Alcatel Espace Flat antenna.
US5006859A (en) * 1990-03-28 1991-04-09 Hughes Aircraft Company Patch antenna with polarization uniformity control
US5745079A (en) * 1996-06-28 1998-04-28 Raytheon Company Wide-band/dual-band stacked-disc radiators on stacked-dielectric posts phased array antenna
US6292143B1 (en) * 2000-05-04 2001-09-18 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Multi-mode broadband patch antenna
NL1035878C (en) * 2008-08-28 2010-03-11 Thales Nederland Bv An array antenna comprising means to establish galvanic contacts between its radiator elements while allowing for their thermal expansion.
JP5983769B2 (en) * 2012-12-20 2016-09-06 株式会社村田製作所 Multiband antenna

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356623A (en) * 2016-12-02 2017-01-25 北京富奥星电子技术有限公司 High-grain and broad-beam antenna

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