JP6302386B2 - Protection device and protection method for power conversion device - Google Patents

Description

  The present invention relates to a protection device and a protection method for a power conversion device including a plurality of power switching elements, and more particularly, to a protection device and a protection method for a power conversion device having a configuration suitable for element breakdown detection and subsequent recovery.

  The power conversion device has an AC power generation function for converting DC power into a voltage equivalent to an AC voltage command having an arbitrary amplitude and frequency by operating a plurality of switching elements.

  There are several power switching element configurations of such a power conversion device. Among these, for example, in a three-level power conversion device that employs a circuit configuration having four types of switching elements, switching is performed in response to an AC voltage command. By supplying the pattern command signal to the gate driver, the switching element is turned ON and OFF, and a voltage equivalent to the AC voltage command is output at the AC output terminal.

  In addition, by increasing the voltage that can be applied by multi-stage each switching element in two or more series, in the power converter that aims to increase the power capacity, the same switching command is given to the multi-stage switching elements to turn on and off, A voltage equivalent to the AC voltage command is output.

  For example, Patent Literature 1 and Patent Literature 2 describe in detail the switching element configuration and the control method thereof in these power conversion devices.

JP 2009-165348 A JP 2008-86096 A

  In the power conversion device composed of these plural switching elements, if one of the switching elements is operated differently from the ON / OFF command due to damage or malfunction, a DC short circuit is induced and the main circuit is damaged. Secondary damage will occur. Moreover, there is a problem that short circuit energy increases due to high pressure, and damage at the time of malfunction is great.

  On the other hand, conventionally, detection of a short circuit by a fuse and prevention of damage expansion, as in Patent Document 1, a command pulse signal to a voltage control type element, and a gate feedback signal indicating an on / off state of the voltage control element, There is a method of detecting an abnormality of the voltage control type element by counting the time of the mismatch, and observing the mismatch for a certain time or more.

  However, with the protection method using a fuse, the damage range can be suppressed as compared with the case without a fuse, but since the time until the fuse blows is longer than the time until the switching element is damaged, all the switching elements in the current short circuit path There is a problem that it causes some damage.

  In addition, in the method of detecting and comparing the command pulse signal and feedback signal of the damaged element, the influence of secondary damage such as element damage and DC short-circuit due to element damage extends to the detection circuit, and the failure of the damaged element is detected. When a situation that cannot be performed occurs, there is a problem that a DC short circuit occurs and secondary damage cannot be prevented.

  In view of the above, an object of the present invention is to provide a power conversion device and a protection method capable of more reliably detecting element breakage, preventing secondary damage from spreading, and reducing recovery time and cost. is there.

  In order to achieve the above object, in the present invention, upper and lower arms are respectively formed by a series circuit of a plurality of switching elements, grounded via a diode from each intermediate portion of the upper and lower arms, and from the connection point of the upper and lower arms. A protection device for a power conversion device that is grounded via a load and connected to a DC power source at both ends of the upper and lower arms, and a clamp element connected between the collector and the gate for each of a plurality of switching elements forming the arm. Including an overvoltage suppression circuit, a signal generation circuit that applies a gate signal to the gate, and an overvoltage detection circuit that is arranged in parallel with the signal generation circuit. The overcurrent duration is monitored from the obtained clamp current to detect the breakage of the switching element.

  As described above, according to the present invention, it is possible to provide a power conversion device that can reduce secondary damage when a switching element is damaged and can reduce recovery time and cost. .

The figure which shows Example 1 of this invention for preventing the progress of a failure. The figure which shows each part electric current and voltage waveform at the time of the progressive failure in a conventional circuit. The figure which shows each part electric current at the time of the progress failure in Example 1, and a voltage waveform. The figure which showed the main body structure and control apparatus structure of 1 phase among the 3 phases of a power converter. The figure which showed the example of each part signal waveform of the power converter device of FIG. The figure which shows the progress condition of the failure mode when QNC2 of FIG. 4 is damaged. The figure which showed the other structural example of the 1 phase main body and control apparatus among the three phases of a power converter. The figure which shows the progress condition of the failure mode when QNC of FIG. 7 is damaged. The figure which shows Example 2 of this invention for preventing the progress of a failure. The figure which shows each part electric current and voltage waveform at the time of the progressive failure in a conventional circuit. The figure which shows each part electric current at the time of the progress failure in Example 2, and a voltage waveform.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings and description of the embodiments, an IGBT and a Zener diode are described as an example of the switching element, but the IGBT of the switching element is replaced with a MOS gate semiconductor other than the IGBT, and a voltage exceeding a certain threshold is applied to the Zener diode. The same effect can be obtained even if it is replaced with a clamp element that sometimes causes a current to flow.

  First, the basic configuration and operation of a power conversion device to which the present invention can be applied will be described. FIG. 4 shows a main body configuration (100a) and a control device (200) configuration of one phase (U phase) out of the three phases (U phase, V phase, W phase) of the power converter. Since the main body and the control device have the same configuration in the U phase, the V phase, and the W phase, only the U phase will be described below.

  In FIG. 4, the power converter (100a) as the main body is composed of a plurality of switching elements connected in series. In the embodiment of the present invention, the switching element is composed of an IGBT and forms a series circuit of IGBTs (QP1, QP2, QPC1, QPC2, QNC1, QNC2, QN1, QN2). In the IGBT series circuit, the upper four elements QP1, QP2, QPC1, and QPC2 form an upper arm, and the lower four elements QNC1, QNC2, QN1, and QN2 form a lower arm, and an intermediate point P12 between the upper and lower arms. A load 3 is connected between the ground and the ground. In addition, a diode series circuit including clamp diodes DCP1, DCP2, DCN1, and DCN2 is provided between an intermediate point P13 of the upper four elements QP1, QP2, QPC1, and QPC2 and an intermediate point P14 of the lower four elements QNC1, QNC2, QN1, and QN2. I have.

  The voltage E is taken in from the DC voltage sources 1pa and 1na at both ends of the series circuit by the IGBT. In addition, the intermediate point P15 of the diode series circuit and the intermediate point P16 of the DC voltage source are commonly grounded.

  The power converter side of the main body is configured as described above, and the control-side pulse width modulation circuit 200 is configured as follows. First, four sets of gate amplifiers (GA1u, GA2u, GA3u, GA4u) are provided in the final stage of the pulse width modulation circuit 200 which is a control circuit. Among these, the switching pulse G1u from the gate amplifier GA1u is given to the gate driver 110 of the upper elements QP1 and QP2 of the IGBT series circuit, and the switching pulse G2u from the gate amplifier GA2u is supplied to the lower elements QNC1 and QNC2 of the IGBT series circuit. The switching pulse G3u from the gate amplifier GA3u is applied to the gate driver 110 of the upper elements QPC1 and QPC2 of the IGBT series circuit, and the switching pulse G4u from the gate amplifier GA4u is applied to the lower part of the IGBT series circuit. This is applied to the gate drivers 110 of the side elements QN1 and QN2. According to this ignition method, the upper elements QP1 and QP2, the lower elements QNC1 and QNC2, the upper elements QPC1 and QPC2, and the lower elements QN1 and QN2 of the IGBT series circuit are integrated as one element driven by the same switching pulse. Configured and used.

  Further, the gate amplifiers GA1u and GA2u, and GA3u and GA4u receive switching pulses from the comparison circuits Cmp1 and Cmp2, respectively. I am receiving a signal. As a result, when a switching pulse is applied to the upper elements QP1 and QP2, the inverted switching pulse is applied to the lower elements QNC1 and QNC2, and when a switching pulse is applied to the lower elements QN1 and QN2, the upper element QPC1. QPC2 is given its inverted switching pulse.

  FIG. 5 is a diagram illustrating a signal waveform example of each part of the power conversion device in FIG. 4. According to this figure, the inverted signal relationship among the switching pulse signals G1u, G2u, G3u, G4u is clearly shown. The switching pulse signals G1u, G2u, G3u, and G4u are displayed as binary values of ON and OFF.

  In the configuration of the control device in FIG. 4, the comparison circuits Cmp1 and Cmp2 turn on and off the switching pulse signals G1u, G2u, G3u, and G4u by comparing the triangular wave Cr31 and the U-phase AC voltage commands Vu * p and Vu * N. Is stipulated. In FIG. 4, G31 is a carrier wave generator for triangular wave Cr31, B1 is a bias circuit, 2f is an adder, M1 is a multiplier circuit for applying a desired DC voltage Er, and triangular wave Cr31 is shown in FIG. It is a triangular waveform that changes between potential 0 and potential + Er / 2. The AC voltage command Vu * p has a sinusoidal waveform centered on the potential 0, and the AC voltage command Vu * N obtained by adding the potential + Er / 2 to the AC voltage command Vu * p has the potential + Er / 2 as the center value. A sinusoidal waveform.

  According to the signal waveform example of each part of the power conversion device in FIG. 5, the pulse width modulation circuit 200 is supplied with the AC voltage waveform (Vu *, Vv *, Vw *) to be output, and the triangular wave Cr31 and the U-phase AC voltage. The switching pulse signals G1u, G2u, G3u, and G4u are turned on and off by comparing the magnitudes of the commands Vu * p and Vu * N, and finally the voltage Vu at the output terminal of the inverter is determined.

  As shown in the lower part of FIG. 5, the output pattern of the inverter output terminal voltage Vu includes the pattern A when the switching pulses G1u and G3u are ON and the output voltage is + E, and the output voltage is the switching voltage G2u and G3u is ON. There are a total of three patterns: a pattern B when 0, and a pattern C when the switching pulses G2u and G4u are ON and the output voltage is -E. Since the time during which the potential is + E or -E is controlled, a sinusoidal waveform is obtained as the AC waveform after filtering.

  FIG. 6 is a diagram showing the progress of the failure mode when the QNC 2 which is one of the IGBTs in the circuit shown in FIG. 4 is damaged. Here, it is assumed that the switching pattern example is A in FIG. Note that this event can occur in the same manner when the switching pattern is B or C in FIG. 3, and therefore the following description will be made specifically for the pattern A.

  In the switching pattern example A, when the switching pulses G1u, G3u are ON and the output voltage is + E, the upper elements QP1, QP2, QPC1, QPC2 are in the ON state. At this time, the current is as shown by the route AA1 in the upper stage of FIG. Is flowing. A current flows along a route from the ground to the terminal P16, the DC voltage source 1pa, the upper elements QP1, QP2, QPC1, QPC2, the terminal P12, and the load 3.

  Assume that the lower element QNC2 is broken in conduction as shown in the upper part of FIG. In other words, it is assumed that the element QNC2 out of the two elements QNC1 and QNC2 that are operated in an integrated manner is damaged. In this case, the voltage for two elements QNC1 and QNC2 is applied to QNC1, which is one element connected in series, the applied voltage of QNC1 rises, and QNC1 eventually breaks down due to overvoltage. Sometimes. If both QNC1 and QNC2 are damaged, the current flows as shown by route AA2 in the lower part of FIG. A current flows in a route from the terminal P16 to the terminal P16 via the DC voltage source 1pa, the upper elements QP1, QP2, QPC1, QPC2, the terminal P12, the lower elements QNC1, QNC2, the clamp diodes DCN1, DCN2. The direct current short circuit in this state may cause damage to QP1, QP2, QPC1, QPC2, QNC1, QNC2, DCN2, and DCN1 on the route.

  In order to prevent the progress of such a failure, in one embodiment of the present invention, as shown in FIG. 1, an overvoltage suppression circuit 112, an overvoltage detection circuit 111, and a signal generation circuit 110 are mounted on the gate driver 110 of each switching element. doing. Although FIG. 1 shows an example of two series elements QNC1 and QNC2 that are operated in an integrated manner, the same overvoltage suppression circuit 112, overvoltage detection circuit 111, and signal generation circuit 110 are also provided in other elements. .

  According to the circuit configuration of FIG. 1, a switching pulse signal G3u is commonly applied to two series elements QNC1 and QNC2 that are operated in an integrated manner, and each signal generation circuit 110 responds to reception of G3U with a gate current. Ig1 and Ig2 are applied to the gate g of the IGBT elements QNC1 and QNC2.

  On the other hand, the IGBT elements QNC1 and QNC2 are turned off by application of the negative gate currents Ig1 and Ig2, and the collector current Ic flowing through the collector c decreases, and the collector voltage increases. The Zener diode 112 of the overvoltage suppression circuit 112 configured by a series circuit of the Zener diode 112a and the resistor 112b limits this when the collector voltage becomes a predetermined voltage or higher, and the clamp currents Igc1 and Igc2 flow. As a result, the clamp currents Igc1 and Igc2 flow separately from the gate currents Ig1 'and Ig2' and the gate currents Ig1 and Ig2. The overvoltage detection circuit 111 monitors the potential due to the gate currents Ig1 and Ig2, and detects an abnormality from the overvoltage of the IGBT elements QNC1 and QNC2. Here, the clamp currents Igc1 and Igc2, the gate currents Ig1 and Ig2, and the gate currents Ig1 'and Ig2' are positive in the direction of the arrows in FIG.

  Under the condition that an overvoltage is applied between the collector c and the emitter e of the switching element IGBT, the voltage between the collector c and the emitter e is sufficiently higher than the voltage between the gate g and the emitter e, and between the collector c and the emitter e. Since the voltage and the voltage between the collector c and the gate g can be regarded as substantially equal, both are called collector voltages here.

  In addition, the Zener diode 112 of the overvoltage suppression circuit 112 in FIG. 1 may be a clamp element in a broad sense, and may have any function that allows a current to flow when a voltage exceeding a certain threshold is applied. The zener diode 112 is an example of a clamp element.

  FIG. 2 shows the current and voltage waveforms of each part at the time of the above-described progressive failure in the case of a conventional circuit that does not include the overvoltage suppression circuit 112. 2, in order from the top, (a) is the collector current Ic, (b) is the collector voltage Vce1, (c) is the collector voltage Vce2, (d) is the clamp current Igc1, (e) is the gate current Ig1, and (f). Is a gate current Ig1 ′, (g) is a clamp current Igc2, (h) is a gate current Ig2, (i) a gate current Ig2 ′, (j) is a failure detection signal.

  In the time axis of the horizontal axis in FIG. 2, time t1 indicates the time when the element QNC2 is broken in conduction, and time t2 indicates the time when the element QNC1 is broken due to conduction failure. Therefore, in the normal operation state without failure in FIG. 2, the waveforms of the respective parts before time t1 are repeatedly generated. That is, when the negative gate current (f) (i) by the switching pulse G1u3 flows while the collector current Ic of (a) is flowing in the series elements QNC1 and QNC2, the IGBT elements QNC1 and QNC2 are turned off, The collector current Ic is reduced. In this state, Ig1 (e) = Ig1 ′ (f) and Igc2 ′ (h) = Ig2 ′ (i). As the turn-off shifts, the collector voltages (b) and (c) of the series elements QNC1 and QNC2 rise, and the collector voltages (b) of the series elements QNC1 and QNC2 disappear when the negative gate currents (f) and (i) disappear. A repetitive waveform in which (c) is reduced is generated.

  On the other hand, due to conduction failure of element QNC2 at time t1, collector voltage Vce1 (b) of element QNC1 is applied together with the burden of element QNC2 after time t1. By continuing the high voltage application state, the time when the element QNC1 further progresses and the conduction failure of the element QNC1 is t2, and a large current continues as the collector current Ic of FIG. In element QNC1 after time t2, collector voltage Vce1 (b) decreases rapidly. In this conventional example, since no overvoltage detection circuit is provided, the failure detection of (j) is not performed.

  As shown in this example, when the collector current Ic flowing through the element QNC1 is cut off from the conduction state and becomes 0, the collector voltages Vce1 and Vce2 applied to the IGBT are changed according to the wiring inductance of the main circuit as shown in FIGS. Jump up like this. If the element QNC2 is broken in conduction at time t1, the voltage borne by the element QNC2 becomes 0 as shown in FIG. 1C, and the voltage applied to the damaged element QNC2 is applied to the element QNC1, and the collector of the element QNC1 The voltage Vce1 rises as shown in FIG. As a result, at time t2, the element QN is damaged by overvoltage, and as shown in FIG. 2B, a DC short circuit occurs in the path from the power source 1pa to QP1-QP2-QPC1-QPC2-QNC1-QNC2-DCN2-DCN1. Secondary damage will spread.

  The operation of the circuit to which the present invention is applied is shown in FIG. Since the vertical axis and horizontal axis items in the case of this waveform are the same as those in FIG. 2, detailed descriptions of items (a) to (j) are omitted.

  In the case of the present invention including the overvoltage suppressing circuit 112, when the collector voltages Vce1 and Vce2 reach a high voltage determined by the Zener diode 112, the clamp currents Igc1 and Igc2 are generated, and the collector voltages Vce1 and Vce2 are generated by the Zener diode 112. Maintain and limit to a fixed high voltage. The resulting clamp currents Igc1 and Igc2 are divided into the gate currents Ig1 and Ig2 and the gate currents Ig1 'and Ig2'.

  FIG. 3 shows gate currents Ig1, Ig2 and gate currents Ig1 ', Ig2' associated with the shunting of the clamp currents Igc1, Igc2. 3 (E), (F), (H), and (I), the period from time t10 to t11 is the same as the conventional one, but the clamp current is added during the period from time t11 to time t12 when the clamp current is divided. It has a gate current waveform. According to this, the gate currents Ig1 and Ig2 increase to the negative side, and the gate currents Ig1 'and Ig2' shift to the 0 potential side.

  In the normal operation state in which the circuit of FIG. 1 is fault-free, the respective waveforms before time t1 in FIG. That is, the negative gate current (f) (i) by the switching pulse G1u3 flows while the collector current Ic of (a) is flowing through the series elements QNC1 and QNC2, thereby reducing the collector current Ic. The collector voltages (b) and (c) of the series elements QNC1 and QNC2 rise, but their values are limited by the clamp voltage, and the gate currents Ig1 and Ig2 and the gate currents Ig1 ′ and Ig2 are divided by the shunt current at this time. 'Is fixed. Thereafter, after the gate current disappears, a repetitive waveform is generated in which the collector voltages (b) and (c) of the series elements QNC1 and QNC2 are reduced.

  On the other hand, the operation of the series of FIG. 1 circuits when the QNC2 conduction failure is further caused from the normal operation state is as follows. In FIG. 3, first, at the normal time, the elements QNC1 and QNC2 perform a normal switching operation, and the collector current Ic flowing through the elements QNC1 and QNC2 becomes 0 when cut off from the conduction state (FIG. 3A). This phenomenon is a phenomenon in normal switching operation. At this time, the collector voltages Vce1 and Vce2 applied to the elements QNC1 and QNC2 jump up as shown in FIGS. 3B and 3C due to the wiring inductance of the main circuit. In this case, when the collector voltages Vce1 and Vce2 applied to the Zener diode 112a of the overvoltage suppressing circuit 112 of the gate driver 110 become equal to or higher than the set clamp voltage value Vm, the clamp currents Igc1 and Igc2 flow through the resistor 112b. The clamp currents Igc1 and Igc2 are shunted and currents Ig1 and Ig2 'flow through the gates g of the elements QNC1 and QNC2, and currents Ig1 and Ig2 flow through the overvoltage detection circuit 111.

  As described above, according to the circuit of FIG. 1, by supplying Ig1 ′ and Ig2 ′ as gate charging currents from the overvoltage suppressing circuit 112 to the gates g of the elements QNC1 and QNC2, and increasing the gate voltage, the elements QNC1 and QNC2 The impedance is reduced to protect against overvoltage, and the collector voltages of the elements QNC1 and QNC2 are balanced.

  At this time, the overvoltage detection circuit 111 observes the gate currents Ig1 and Ig2 flowing into the overvoltage detection circuit 111, and checks whether or not a current equal to or greater than the clamp detection threshold value In flows for a period equal to or greater than the abnormality detection time tf. In a state before time t1, a period tf1 that is greater than or equal to the clamp detection threshold value In occurs from time t11 to time t12. However, since this phenomenon occurs periodically in the correct switching operation, the abnormal operation is not detected by confirming that the phenomenon is below the reference value tf.

  On the other hand, when the element QNC2 continues to break at time t1, the voltage borne by the element QNC2 becomes 0 as shown in FIG. 1C, and the corresponding voltage is applied to the element QNC1, and the collector voltage of the element QNC1 Vce1 rises as shown in FIG. At this time, similarly to the voltage clamp at the time of normal switching, when the clamp voltage value Vm becomes equal to or higher than the set clamp voltage value Vm, the clamp current Igc1 flows through the resistor 112b and then shunts to the current Ig1 ′ to the gate g of the element QNC1. However, the current Ig1 flows through the overvoltage detection circuit 111.

  Thus, by supplying Ig1 as a gate charging current to the gate g, the impedance of the element QNC1 is lowered and the element QNC1 is protected from overvoltage. At the same time, the overvoltage detection circuit 111 observes the gate current Ig1 flowing into the overvoltage detection circuit 111, and checks whether a current equal to or higher than the clamp detection threshold value In flows for a period equal to or longer than the abnormality detection time tf.

  At this time, the period tf2 that is equal to or greater than the clamp detection threshold In is detected as being a failure by detecting that it is equal to or greater than the reference value tf. Incidentally, since tf1 is about 5 μS, and tf2 is 15 μS or more, both can be easily identified. As a result, when the gate current flows for more than the abnormality detection time tf, the failure detection signal is turned on as shown in FIG. 1 (j), and it is determined that the nearby element is damaged, and before the DC short circuit occurs, Operation can be stopped and the spread of secondary damage can be suppressed.

  In order to balance the voltage sharing between MOS gate semiconductor elements with the same switching operation that are connected in series in multiple stages, the number of clamp elements that allow current to flow when a voltage exceeding a certain threshold is applied is actively increased. By adjusting the number to be suppressed, the series voltage of the MOS gate semiconductor can be balanced during normal switching operation.

  In FIG. 3, after time t1, a positive gate current ig1 (e) due to the divided clamp current flows to the gate g. This is a current in the conduction direction of the semiconductor element, but the constants and the like of each part of the switching element are determined so as to be a low value that does not actually operate with the current at this time.

  As described above, according to the first embodiment, the collector voltage is monitored for each of the plurality of series switching elements forming the arm, and the period during which the collector voltage is equal to or higher than the predetermined value is equal to or longer than the predetermined period. Judge as abnormal.

  Next, a second embodiment of the present invention will be described. The second embodiment is a configuration in the case where the IGBT elements that are in the two-series configuration for each switching pulse G in the first embodiment are one in series. A basic configuration of the power converter 100b according to the second embodiment will be described with reference to FIG.

  In FIG. 7, one of the three phases (U phase, V phase, W phase) of the power converter is extracted as 100b, and the U phase, V phase, and W phase have the same configuration. Only the phase will be described. The power converter 100b includes a plurality of switching elements connected in series. In Embodiment 2 of the present invention, the switching element is composed of an IGBT and forms a series circuit of IGBTs (QP, QPC, QNC, QN). In the IGBT series circuit, an upper arm is formed by the upper two elements QP and QPC, and a lower arm is formed by the lower two elements QNC and QN, and a load is placed between the middle point P12 of the upper and lower arms and the ground. 3 is connected. A diode series circuit including clamp diodes DCP and DCN is provided between the intermediate point P13 of the upper two elements QP and QPC and the intermediate point P14 of the lower two elements QNC and QN.

  The voltage E is taken in from the DC voltage sources 1pb and 1nb at both ends of the IGBT series circuit. In addition, the intermediate point P15 of the diode series circuit and the intermediate point P16 of the DC voltage source are commonly grounded.

  The power converter side of the main body is configured as described above, and the control-side pulse width modulation circuit 200 is configured as follows. First, four sets of gate amplifiers (GA1u, GA2u, GA3u, GA4u) are provided in the final stage of the pulse width modulation circuit 200 which is a control circuit. Among these, the switching pulse G1u from the gate amplifier GA1u is given to the gate driver 110 of the upper element QP of the IGBT series circuit, and the switching pulse G2u from the gate amplifier GA2u is given to the gate driver 110 of the lower element QNC of the IGBT series circuit. The switching pulse G3u from the gate amplifier GA3u is supplied to the gate driver 110 of the upper element QPC of the IGBT series circuit, and the switching pulse G4u from the gate amplifier GA4u is supplied to the gate driver of the lower element QN of the IGBT series circuit. 110.

  Further, the gate amplifiers GA1u and GA2u, and GA3u and GA4u receive switching pulses from the comparison circuits Cmp1 and Cmp2, respectively. I am receiving a signal. As a result, when a switching pulse is given to the upper element QP, its inverted switching pulse is given to the lower element QNC. When a switching pulse is given to the lower element QN, its inverted switching pulse is given to the upper element QPC. Will give.

  The relationship between the switching pulse (G1u, G2u, G3u, G4u) and the voltage at the output terminal of the power converter in the case of the second embodiment is as shown in FIG.

  FIG. 8 shows a failure mode when a QNC that is one of the IGBTs in the circuit shown in FIG. 7 is damaged. As an example of the failure mode, when the switching pattern is A in FIG. 3, the current flows as shown by route BB1 in FIG. If the switching element QNC is broken in this state, a DC short circuit such as the route BB2 in FIG. 8b may occur, and the QP, QPC, QNC, and DCN on the route may be damaged. Note that this event can occur in the same manner when the switching pattern is B or C in FIG. 3, and therefore the following description will be made specifically for the pattern A.

  In addition, the voltage of four elements QP, QPC, QNC, and QN is applied to one QN connected in series to increase the voltage, and the QN eventually leads to overvoltage damage. When QN breaks, the current flows as shown by BB3 in FIG. 8c due to a DC short circuit, and the voltage of the short circuit route becomes twice that of FIG. 8b, increasing the short-circuit energy and increasing the damage.

  In order to prevent the progress of such a failure, in the second embodiment of the present invention, as shown in FIG. 8, an overvoltage suppression circuit 112, an overvoltage detection circuit 111, and a signal generation circuit 110 are mounted on the gate driver 110 of each switching element. doing. The circuit configuration of FIG. 8 is basically the same as that of FIG. The other configuration and operation are the same as those in FIG. 1 except that the signal generation circuit 110 is individually provided and different from the first embodiment.

  Under the condition that an overvoltage is applied between the collector and emitter of the IGBT, the collector-emitter voltage is sufficiently higher than the gate-emitter voltage, and the collector-emitter voltage and the collector-gate voltage are almost equal. Both are hereinafter referred to as collector voltages.

  FIG. 10 shows the current and voltage waveforms of each part at the time of the above-described progressive failure in the case of a conventional circuit that does not include the overvoltage suppression circuit 112. 2, (a) and (b) are the collector current Ic, (c) is the collector voltage Vce1, (d) is the collector voltage Vce2, (e) is the clamp current Igc1, (f) is the gate current Ig1, in order from the top. (G) is a gate current Ig1 ′, (h) is a clamp current Igc2, (i) is a gate current Ig2, (j) a gate current Ig2 ′, (k) is a failure detection signal.

  In the time axis on the horizontal axis in FIG. 10, time t1 indicates the time when the element QNC is damaged in conduction, and time t2 indicates the time when the element QN is damaged due to progress failure. Therefore, in the normal operation state without failure in FIG. 10, the waveforms of the respective parts before time t1 are repeatedly generated. That is, when the negative gate current (f) (g) due to the switching pulse G1u3 flows while the collector current Ic of (a) and (b) is flowing through the series elements QNC and QN, the IGBT element QNC shifts to turn-off. The collector current Ic is reduced. In this state, Ig1 (f) = Ig1 ′ (g) and Igc2 ′ (i) = Ig2 ′ (j). As the turn-off shifts, the rector voltage (c) of the series element QNC rises, and a repetitive waveform is generated in which the collector voltage (c) of the element QNC decreases due to the disappearance of the negative gate current (f) (g). .

  On the other hand, due to conduction failure of element QNC at time t1, collector voltage Vce2 (d) of element QN is applied together with the burden of element QNC after time t1. Due to the continuation of the high voltage application state, the time when the element QN further progresses and the conduction failure occurs is t2, and a large current continues as the collector current Ic of (a). In element QNC after time t2, collector voltage Vce2 (d) decreases rapidly. In this conventional example, since no overvoltage detection circuit is provided, the failure detection of (k) is not performed.

  As shown in this example, when the collector current Ic flowing through the element QNC is cut off from the flowing state and becomes 0, the collector voltage Vce1 applied to the IGBT jumps as shown in FIG. 2C due to the wiring inductance of the main circuit. When the element QNC is broken in conduction at time t1, the voltage borne by the element QNC becomes 0 as shown in FIG. 1C, and the voltage applied to the broken element QNC is applied to the element QN, and the collector of the element QN The voltage Vce2 rises as shown in FIG. As a result, the element QN is damaged by overvoltage at time t2, and a DC short circuit occurs from the power source 1pa to the QP-QPC-QNC-DCN path as shown in FIG. .

  Next, the operation of the circuit to which the present invention is applied is shown in FIG. As is apparent from the description of FIG. 3, according to FIG. 11, when the current Ic1 flowing through the element QNC is cut off from the conduction state and becomes 0 (FIG. 11 (a): normal switching operation), it is applied to the QNC. The collector voltage Vce1 jumps as shown in FIG. 11C due to the wiring inductance of the main circuit. However, when the collector voltage Vce1 applied to the Zener diode 112a of the overvoltage suppression circuit 112 of the gate driver 110 becomes equal to or higher than the set clamp voltage value Vc. After the clamp current Igc1 flows through the resistor 112b, the current is shunted, the gate current Ig1 ′ (FIG. 11g) flows to the gate g of the QNC, and the gate current Ig1 (FIG. 11f) flows to the overvoltage detection circuit 111.

  By supplying the current Ig1 'as the gate charging current to the gate g of the QNC in this way, the gate voltage is increased, thereby reducing the impedance and protecting the QNC from overvoltage. Further, the overvoltage detection circuit 111 observes the gate current Ig1 flowing into the overvoltage detection circuit 111, and checks whether or not a current equal to or higher than the clamp detection threshold value In is flowing for a period equal to or longer than the abnormality detection time tf.

  When QNC breaks conduction at time t1, the voltage borne by QNC becomes 0 as shown in FIG. 11C, and the voltage applied to other elements is applied to QN as described in FIG. The collector voltage Vce2 rises as shown in FIG. At this time, similarly to the voltage clamp at the time of normal switching before the conduction breakage, when the clamp voltage value Vc becomes equal to or higher than the set clamp voltage value Vc, the clamp current Igc2 flows through the resistor 112b and then is shunted to the gate g of the QN. The current Ig2 ′ flows into the overvoltage detection circuit 111.

  Then, by supplying a current Ig2 'as a gate charging current to the gate g, the impedance of the QN is lowered and protected from overvoltage. At the same time, the overvoltage detection circuit 111 observes the gate current Ig2 flowing into the overvoltage detection circuit 111, and checks whether or not the current exceeding the clamp detection threshold I flows for a period exceeding the abnormality detection time tf. When the gate current flows for more than the abnormality detection time tf as shown in FIG. 2, the failure detection signal is turned on as shown in FIG. 2 (k), and it is determined that nearby elements are damaged, and the operation of the power converter is stopped. The expansion of the next damage can be suppressed.

  As described above, according to the second embodiment, the collector voltage is monitored for each of the plurality of series switching elements forming the arm, and when the period during which the collector voltage is equal to or higher than the predetermined value is equal to or longer than the predetermined period, Judge as abnormal.

  As described above, according to the present invention, when the switching element of the power conversion device is broken, when the voltage is biased to the nearby element and the voltage rises, the overvoltage is suppressed by the overvoltage suppression circuit, and the overvoltage is generated for a certain time or more. By detecting that the overvoltage detection circuit detects that a nearby element has been damaged, the operation of the apparatus is stopped before the occurrence of a DC short circuit, thereby suppressing the spread of secondary damage.

  Here, the overvoltage suppression circuit is constituted by a circuit in which a clamp element such as a Zener diode is connected in series so that a current flows when a voltage is applied, and as in Patent Document 2, between the collector and the gate of the switching element. When an overvoltage is applied between the collector and the gate, a current flows through the Zener diode, and the charging current is supplied to the gate of the switching element to reduce the impedance of the switching element. It is a circuit to protect.

  The overvoltage detection circuit recognizes the current flowing from the overvoltage suppression circuit to the gate driver as an inconsistent signal with the command signal flowing from the gate driver to the switching element as in Patent Document 1 when an overvoltage occurs. It is a circuit that judges that the occurrence has occurred.

  As described above, in the present invention, by combining the overvoltage suppression circuit using the method of Patent Document 2 and the overvoltage detection circuit using the method of Patent Document 1, and further adjusting the number of series stages of the clamp elements of the overvoltage suppression circuit, Overvoltage can be suppressed during normal operation, and when a nearby element is damaged, the current from the clamp element of the overvoltage suppression circuit is set to flow for a certain period of time, and after the overvoltage detection circuit detects that it has been flowing for a certain period of time Determines that a nearby element has been damaged and stops the power conversion device, so that even if the damaged element itself cannot detect a failure, it can quickly detect the damage to the element and increase secondary damage. Can be suppressed.

1pa, 1na, 1pb, 1nb: DC voltage source P12: AC output terminal 2f: Adder 3: Load 100a: U phase 100b of 2 series specification power converter: U phase 110 of 1 series specification power converter: gate Driver 111: Overvoltage detection circuit 112: Overvoltage suppression circuit 112a: Zener diode 112b: Resistor 200: Pulse width modulation circuit AA1, AA2, BB1, BB2, BB3: Current flow route B1: Bias circuit c: IGBT collector Cmp1, Cmp2 : Comparator Cr31: Carrier e: IGBT emitters DCP1, DCP2, DCN1, DCN2, DCP, DCN: Clamp diode E: DC voltage value Er: Desired DC voltage value g: IGBT gate G31: Carrier generators G1u to G4u : U-phase switching pulses GA1u to GA4u: U-phase gate Amplifier Ic: Collector current Ig1, Ig2: Gate current Ig1 ′ flowing through the overvoltage detection circuit, Ig2 ′: Gate current Igc1 flowing through the gate of the IGBT, Igc2: Current flowing through the overvoltage suppression circuit In: Clamp detection threshold current M1: Multiplication circuit Not1 , Not2: NOT circuit t1: Clamping time t1: Switching element failure time tf: Clamping abnormality detection time threshold Vce1, Vce2: Collector voltage Vc: Clamping voltage Vu: U-phase inverter output voltage Vu *: U-phase AC voltage command Vv * : V-phase AC voltage command Vw *: W-phase AC voltage command Vu * P, Vu * N: Branched U-phase AC voltage command Vv * P, Vv * N: Branched V-phase AC voltage command Vw * P, Vw * N: Branched W-phase AC voltage commands QP1, QP2, QPC1, QPC2, QNC1, QNC2, Q N1, QN2: IGBT elements QP, QPC, QNC, QN: IGBT elements

Claims (7)

Upper and lower arms are formed by a series circuit of a plurality of switching elements, respectively, and grounded from a middle portion of each of the upper and lower arms via a diode, and grounded via a load from a connection point of the upper and lower arms. A protection device for a power converter connected to a DC power source,
For each of the plurality of switching elements forming the arm, an overvoltage suppressing circuit including a clamp element connected between the collector and the gate, a signal generating circuit for supplying a gate signal to the gate, and the signal generating circuit are arranged in parallel. Overvoltage detection circuit
The overvoltage detection circuit includes a shunt current obtained by shunting the clamp current obtained by the overvoltage suppression circuit when the switching element is overvoltaged to the signal generation circuit side, and a potential based on a combined current of the gate signal from the signal generation circuit . A protection device for a power conversion device, characterized by detecting a breakage of a switching element by monitoring a duration time. It is a protection apparatus of the power converter device of Claim 1, Comprising:
The power conversion device includes a plurality of switching elements arranged between the intermediate portion of the upper and lower arms and the DC power supply side terminal or the connection point of the upper and lower arms, and the switching elements are connected to the same switching pulse. A power converter protective device, which is driven by It is a protection apparatus of the power converter device of Claim 1, Comprising:
In the power conversion device, a single switching element is disposed between the intermediate portion of the upper and lower arms and the DC power supply side terminal or the connection point of the upper and lower arms, respectively. Device protection device. It is a protection apparatus of the power converter device of any one of Claims 1-3, Comprising:
A protective device for a power converter, wherein a duration time of the potential due to the combined current is set longer than a duration time of an overvoltage of a collector voltage of the switching element generated when a gate signal is applied to the gate . It is a protection apparatus of the power converter device of Claim 2, Comprising:
As a switching element of the same switching operation connected in multiple stages, a MOS gate semiconductor element is adopted, and in order to balance the voltage sharing between the MOS gate semiconductor elements, a clamp element that allows a current to flow when a voltage exceeding a certain threshold is applied. A protection device for a power conversion device, wherein the number of stages is adjusted to a number that actively suppresses a jump in voltage to balance the series voltage of MOS gate semiconductors during normal switching operation. As a plurality of switching elements, upper and lower arms are formed by a series circuit of MOS gate semiconductors, grounded from the middle of each of the upper and lower arms via a diode, and grounded via a load from a connection point of the upper and lower arms, A method for protecting a power converter in which a DC power source is connected to both ends of an arm,
When the signal generating circuit for applying a gate current to the gate of the MOS gate semiconductor and the other second switching element in the same arm connected in series with the first switching element are damaged, the first switching element Provide a clamp element that allows current to flow when a voltage exceeding the threshold is applied,
By lowering the impedance to supply the current flowing from the clamp element to the gate of the MOS gate semiconductor, suppresses the overvoltage of the MOS gate semiconductor, current of the clamp element is branched into the signal generating circuit side distributor A method for protecting a power converter, comprising detecting a breakage of a second switching element by detecting that a combined current of a current and a gate signal from the signal generation circuit has flowed for a predetermined time or more. It is a protection method of the power converter device of Claim 6, Comprising:
When the second switching element is damaged, an abnormality is detected by counting the time of the gate current flowing from the clamp element due to an overvoltage applied to the second switching element. A method for protecting a power converter, wherein the number of stages of the clamp elements is determined so that the time of the flowing gate current is shortened and an abnormality is not erroneously detected.

Images