JP6265962B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to an imaging element and an imaging apparatus.

  In recent years, functions of image pickup devices have been remarkably improved, and the number of functions has been increased to meet various needs. As automatic focus adjustment (hereinafter referred to as AF), imaging plane phase difference AF in which pixels for focus detection are arranged in an imaging element is known. The imaging plane phase difference AF is a method in which a plurality of photoelectric conversion units that divide and receive the pupil of the imaging optical system are arranged on the imaging element, and AF is performed using signals from the plurality of photoelectric conversion units. As one form of an imaging device that realizes imaging plane phase difference AF, a plurality of photoelectric conversion units are arranged in a unit pixel, so that light obtained by dividing a pupil region can be photoelectrically converted and output. Although it is difficult to manufacture a configuration capable of reading signals from a plurality of photoelectric conversion units, it can be used as a normal captured image by mixing signals read from the plurality of photoelectric conversion units. Further, when the imaging plane phase difference AF is not performed, it is possible to mix the signals of a plurality of photoelectric conversion units in the imaging element and read them as unit pixel signals used for a captured image.

  On the other hand, the image signal has a very large amount of data, and even if a high-speed interface is used, it takes time, which is a bottleneck for determining the frame rate. Therefore, when imaging plane phase difference AF is performed, the time required to output the signals of all the photoelectric conversion units since the signals of the plurality of photoelectric conversion units are read out and the respective signals are output to the outside of the imaging device. However, there is a problem that the frame rate is lowered due to a longer period. In response to this problem, the signals of the plurality of photoelectric conversion units are mixed in the imaging device, and the captured image obtained by the mixing and the plurality of photoelectric conversion units used for the imaging plane phase difference AF obtained regardless of the mixing Patent Document 1 discloses that these signals are output in parallel.

JP 2014-72541 A

  In the imaging device of Patent Document 1, although the pixel signal for imaging surface phase difference AF is read in parallel with the pixel signal for captured image, when all the pixel signals for imaging surface phase difference AF are read, It takes about twice as long as the pixel signal. Although it is possible to increase the speed by increasing the parallel number when reading to the outside of the image sensor in parallel, the number of pixel signal communication interfaces is limited by the camera system such as the receiving device, so it can be easily increased is not. In Patent Document 1, the readout pixel signal for imaging plane phase difference AF is a method of reducing the amount of data by thinning out reading or reading out only a specific area, or a plurality of photoelectric conversion units only for pixels of a specific color in a Bayer array. Reduce the amount of data. However, if thinning-out reading is performed, the density of pixels from which signals for imaging plane phase difference AF are read decreases, and it is not possible to perform imaging plane phase difference AF with high accuracy. In addition, it is necessary to set the area to be read out in advance for reading out the specific area, and for example, highly accurate AF using subject detection cannot be performed. If subject detection is performed, it is necessary to output signals for imaging plane phase difference AF in all regions, and it is difficult to maintain the frame rate. In addition, in the method of arranging a plurality of photoelectric conversion units only for pixels of a specific color, the AF accuracy with respect to subjects of different colors is significantly reduced.

  In the future, the number of photoelectric conversion units per unit pixel will increase, and when performing high-accuracy imaging plane phase difference AF, it is expected that the data amount of signals for imaging plane phase difference AF will further increase. In that case, since it takes time to communicate signals for imaging plane phase difference AF, it is difficult to perform imaging plane phase difference AF with high accuracy without reducing the frame rate.

  An object of the present invention is to provide an image pickup device and an image pickup apparatus capable of suppressing a decrease in frame rate and performing high-precision focus adjustment without increasing a communication interface for pixel signals output to the outside of the image pickup device. .

The image sensor of the present invention is an image sensor that makes light incident through an optical system, and is arranged in a matrix, each of which includes a plurality of photoelectric conversion units that convert light incident through the optical system into charges. A plurality of unit pixels, and a control unit that generates a control signal for controlling a relative distance on the optical axis between the optical system and the imaging element, based on signals of the plurality of unit pixels. have a, the unit pixel includes a first photoelectric conversion unit and the second photoelectric conversion unit, the first of the first signal based on the electric charge converted by the photoelectric conversion portion and the first A second signal based on a charge obtained by mixing a photoelectric conversion unit and a charge converted by the second photoelectric conversion unit is output in a time-sharing manner, and the control unit outputs the first signal from the second signal. By subtracting the third signal based on the electric charge converted by the second photoelectric conversion unit. Generates, and generates the control signal based on said third signal and said first signal.

  According to the present invention, it is possible to suppress a decrease in the frame rate and perform high-precision focus adjustment without increasing the communication interface for pixel signals output to the outside of the image sensor.

It is a block diagram showing an example of composition of an imaging device concerning a 1st embodiment. It is a figure showing an example of composition of an image sensor concerning a 1st embodiment. It is a circuit diagram which shows the structural example of the unit pixel which concerns on 1st Embodiment. It is a figure in which the light beam emitted from the exit pupil of the photographing lens enters the unit pixel. It is a figure which shows the structural example of the signal processing circuit which concerns on 1st Embodiment. It is a figure which shows the structural example of the focus control circuit which concerns on 1st Embodiment. It is a timing chart which shows the drive method of an image pick-up element. It is a figure which shows the shape of the photoelectric conversion part of the unit pixel which concerns on 2nd Embodiment. It is a circuit diagram which shows the structural example of the unit pixel which concerns on 2nd Embodiment. It is a figure which shows the structural example of the image pick-up element which concerns on 2nd Embodiment. It is a figure which shows the structural example of the signal processing circuit which concerns on 2nd Embodiment. It is a timing chart which shows the drive method of an image pick-up element. It is a block diagram which shows the structural example of the imaging device which concerns on 3rd Embodiment.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to the first embodiment of the present invention. The imaging apparatus includes a lens unit 111 and a camera unit 112. The lens unit 111 includes a focus lens 101, a focus actuator 102, a lens position detection unit 103, and a lens information holding unit 104. The camera unit 112 includes an image sensor 100, an overall control calculation unit 106, a memory unit 107, a display unit 108, a recording unit 109, and an operation unit 110. The lens unit 111 is connected to the camera unit 112 via the mount 105. The lens group including the focus lens 101 is an optical system that forms an optical image on the image sensor 100. The image sensor 100 receives light through an optical system and converts an optical image into an image signal (electric signal). The focus actuator 102 is controlled by the image sensor 100 and performs focus control by driving the focus lens 101 forward and backward along the optical axis OA. The lens position detection unit 103 detects the position of the focus lens 101 and outputs the detected lens position information to the image sensor 100. The image sensor 100 controls the focus actuator 102 with high accuracy based on the detected position. The lens information holding unit 104 holds lens information indicating the type of lens (optical system) and the state of the aperture of the lens, and outputs the lens information to the image sensor 100. The overall control calculation unit 106 controls the image sensor 100, performs correction processing and development processing on the image signal output from the image sensor 100, and controls other blocks. The memory unit 107 stores an image signal. The display unit 108 displays various information and images. The recording unit 109 is a detachable recording unit such as a semiconductor memory for writing and reading an image. The operation unit 110 is various interfaces of the imaging device. The overall control calculation unit 106 controls each block using a signal from the operation unit 110.

  FIG. 2 is a diagram illustrating a configuration example of the image sensor 100 according to the present embodiment. The image sensor 100 is a CMOS image sensor, and is configured by stacking an image pickup substrate 214 and a signal processing substrate 215. The imaging substrate 214 and the signal processing substrate 215 are connected to each other through, for example, TSV (Through Silicon Via). The imaging substrate 214 is a first semiconductor substrate on which the pixel portion 200, the vertical scanning circuit 202, and the column circuit 203 are provided. The signal processing board 215 includes a timing control circuit 206, a column memory circuit 207, a signal processing circuit 208, an image signal output circuit 209, a defocus amount calculation circuit 210, a focus control circuit 211, a lens information input circuit 212, and a position signal input. A circuit 213 is provided. The signal processing board 215 is a second semiconductor substrate, and the circuit on the signal processing board 215 is a control unit.

  The pixel unit 200 includes a plurality of unit pixels 201 arranged in a matrix, and converts an optical image formed on the image sensor 100 into an electrical signal. The vertical scanning circuit 202 and the column circuit 203 are connected to the pixel portion 200. The drive signal lines 204 in each row are commonly connected to the unit pixels 201 in each row. The vertical scanning circuit 202 outputs a drive signal for driving the unit pixel 201 in each row via the drive signal line 204 in each row. The signal line 205 in each column is commonly connected to the unit pixel 201 in each column. As shown in FIG. 3, each of the plurality of unit pixels 201 includes a first photoelectric conversion unit 300A and a second photoelectric conversion unit 300B that convert light incident through the focus lens 101 into electric charges. A pixel signal is output to the signal line 205 in the column. The column circuit 203 includes an analog-to-digital converter (hereinafter referred to as ADC) that converts the signals of the plurality of unit pixels 201 from analog to digital. The column circuit 203 performs subtraction processing by correlated double sampling, signal amplification, and analog-digital (AD) conversion on the signal of the signal line 205 in each column, and outputs a digital signal to the column memory circuit 207 via the TSV. . Hereinafter, the output signal of the unit pixel 201 after the reset of the unit pixel 201 is referred to as an N signal. The output signal of the unit pixel 201 based on the charge converted by the first photoelectric conversion unit 300A in the unit pixel 201 is referred to as an A signal (first signal). The output signal of the unit pixel 201 based on the charge converted by the second photoelectric conversion unit 300B in the unit pixel 201 is referred to as a B signal (third signal). The output signal of the unit pixel 201 based on the charge obtained by mixing the charges converted by the first photoelectric conversion unit 300A and the second photoelectric conversion unit 300B in the unit pixel 201 is referred to as an A + B signal (second signal). The unit pixel 201 outputs the N signal, the A signal (first signal), and the A + B signal (second signal) to the column circuit 203 in a time division manner. The column circuit 203 performs AD conversion on the N signal, the A signal, and the A + B signal. Thereafter, the column circuit 203 outputs a pixel signal A obtained by subtracting the N signal from the A signal to the column memory circuit 207, and outputs a pixel signal A + B obtained by subtracting the N signal from the A + B signal to the column memory circuit 207. The column memory circuit 207 holds the pixel signal A and the pixel signal A + B.

  The timing control circuit 206 receives an image sensor control signal from the overall control calculation unit 106 and outputs control signals to the vertical scanning circuit 202, the column circuit 203, the column memory circuit 207, and the signal processing circuit 208. The signal processing circuit 208 performs a correction process on the pixel signals held in the column memory circuit 207 to generate a captured image and a focus detection signal. The signal processing circuit 208 performs correction processing such as peripheral light amount drop correction or black level correction in which the light amount is reduced in the peripheral portion of the image sensor 100 with respect to the pixel signal A + B used as the captured image, and outputs it to the image signal output circuit 209. To do. Further, the signal processing circuit 208 generates a pixel signal B that is a focus detection signal by subtracting the pixel signal A from the pixel signal A + B, and corrects the black level or the like for the pixel signal A and the pixel signal B. And output to the defocus amount calculation circuit 210. The pixel signal B is a third signal based on the charges converted by the second photoelectric conversion unit 300B. Details of the signal processing circuit 208 will be described later with reference to FIG.

  The image signal output circuit 209 outputs the pixel signal A + B subjected to correction processing by the signal processing circuit 208 to the overall control calculation unit 106 as a captured image. The defocus amount calculation circuit 210 is a defocus amount calculation unit, which receives the pixel signal A and the pixel signal B for focus detection from the signal processing circuit 208 and outputs the pixel signal A and the pixel signal B for focus detection. Correlation calculation processing is performed. Then, the defocus amount calculation circuit 210 calculates the pixel shift amount between the pixel signal A and the pixel signal B as the defocus amount and outputs the calculated defocus amount to the focus control circuit 211. The focus control circuit 211 is a focus control unit, calculates a drive amount of the focus lens 101 based on the input defocus amount, and outputs a focus drive signal for driving the focus actuator 102. The lens information input circuit 212 receives lens information indicating the lens type and lens aperture state from the lens information holding unit 104 of the lens unit 111, and outputs the lens information to the signal processing circuit 208 and the focus control circuit 211. . The position signal input circuit 213 is a position information input unit, which receives lens position information (position information of the optical system) of the focus lens 101 from the lens position detection unit 103 and outputs the lens position information to the focus control circuit 211. . The focus control circuit 211 inputs lens information and lens position information, and performs high-precision focus control by switching the format of the drive signal of the focus actuator 102 and feeding back the lens position information. The focus control circuit 211 outputs a focus drive signal (control signal) for controlling the relative distance on the optical axis OA between the focus lens 101 and the image sensor 100 to the focus actuator 102. The focus actuator 102 controls the relative distance on the optical axis OA between the focus lens 101 and the image sensor 100 according to the focus drive signal.

  FIG. 3 is a circuit diagram illustrating a configuration example of the unit pixel 201 according to the present embodiment. The unit pixel 201 includes a first photoelectric conversion unit 300A, a second photoelectric conversion unit 300B, and five n-type field effect transistors 301A, 301B, 303, 304, and 305. The photoelectric conversion units 300A and 300B are, for example, photodiodes, and convert light incident on the unit pixel 201 into electric charges. The first transfer transistor 301A outputs the charge of the first photoelectric conversion unit 300A to a floating diffusion (hereinafter referred to as FD) 302. The second transfer transistor 301B outputs the charge of the second photoelectric conversion unit 300B to the FD 302. The FD 302 converts charges into a voltage by a parasitic capacitance connected to the FD 302. The reset transistor 303 connects the FD 302 to the node of the power supply potential VDD, and resets the potential of the FD 302 to the power supply potential VDD. The amplification transistor 304 amplifies the signal of the FD 302 and outputs it. The selection transistor 305 connects the output node of the amplification transistor 304 to the signal output line 306. The signal output line 306 is connected to the signal line 205 in FIG. By turning off / off the selection transistor 305, only the signal of the unit pixel 201 in the selected row among the unit pixels 201 arranged on the matrix is output. The transfer transistors 301A and 301B, the reset transistor 303, and the selection transistor 305 are controlled by drive signals φTXA, φTXB, φRST, and φSEL, respectively. Moreover, the same drive signal is given to the unit pixels 201 arranged in the same row among the unit pixels 201 arranged on the matrix.

  In the present embodiment, a configuration in which two photoelectric conversion units are arranged in one unit pixel 201 will be described as an example. However, a larger number of photoelectric conversion units may be arranged. By increasing the number of photoelectric conversion units, it is possible to perform imaging surface phase difference AF with higher accuracy.

  FIG. 4 is a conceptual diagram in which the light beam emitted from the exit pupil 400 of the optical system including the focus lens 101 enters the unit pixel 201. Hereinafter, the principle of focus detection by the pupil division method of the imaging apparatus will be described. The unit pixel 201 includes a first photoelectric conversion unit 300A and a second photoelectric conversion unit 300B. The light beam emitted from the exit pupil 400 enters the unit pixel 201 through the microlens 401 and the color filter 402 with the optical axis OA as the center. Each of the plurality of unit pixels 201 is provided with a plurality of microlenses 401. The exit pupil 400 has pupil regions 403A and 403B. The light beams passing through the pupil regions 403A and 403B are incident on the photoelectric conversion units 300A and 300B, respectively. Therefore, the photoelectric conversion units 300A and 300B receive light in different pupil regions 403A and 403B of the exit pupil 400 of the photographing lens, respectively. Thereby, the phase difference can be detected by comparing the signal of the first photoelectric conversion unit 300A and the signal of the second photoelectric conversion unit 300B. The pixel signal A is a signal photoelectrically converted by the first photoelectric conversion unit 300A, and the pixel signal B is a signal photoelectrically converted by the second photoelectric conversion unit 300B. The pixel signal A + B is a signal obtained by mixing the pixel signal A and the pixel signal B in the FD 302.

  FIG. 5 is a diagram illustrating a configuration example of the signal processing circuit 208 of FIG. The signal processing circuit 208 is controlled by a control signal output from the timing control circuit 206. The image memory readout circuit 500 outputs a memory control signal to the column memory circuit 207, sequentially reads out the held pixel signals A + B of each column, and outputs the readout pixel signals A + B to the image correction circuit 501. At this time, the reading speed of the pixel signal is limited by the speed of the communication interface when the image signal 100 is output to the outside. The image correction circuit 501 performs correction processing on the input pixel signal A + B. Specifically, the image correction circuit 501 performs peripheral light amount drop correction, which is a correction of a phenomenon in which the light amount is dropped at the peripheral portion of the image sensor 100, and between columns due to characteristic variations of ADCs arranged for each column in the column circuit 203. Perform black level correction. The image correction circuit 501 performs F-number correction, which is a correction of a phenomenon in which the output deviates from the theoretical value when the aperture is changed based on the input lens information. The image correction circuit 501 selects from a correction value table prepared in advance according to lens information, and determines parameters used for correction. The image correction circuit 501 outputs the corrected pixel signal A + B to the image output circuit 209 as an image signal.

  The focus detection memory reading circuit 502 outputs a memory control signal to the column memory circuit 207, and sequentially reads the pixel signal A and the pixel signal A + B of each column held. The pixel signal A and the pixel signal A + B are not limited in speed by a communication interface between devices in addition to a plurality of pixel signals being read out in parallel. Therefore, the focus detection memory reading circuit 502 can read at a higher speed than the image memory reading circuit 500. The focus detection memory reading circuit 502 outputs the read pixel signal A and pixel signal A + B to the focus detection signal generation circuit 503. The focus detection signal generation circuit 503 generates the pixel signal B by subtracting the pixel signal A from the pixel signal A + B. Then, the focus detection signal generation circuit 503 outputs the generated pixel signal B and pixel signal A to the frame memory 504.

  The subject detection memory reading circuit 505 outputs a memory control signal to the column memory circuit 207 in the subject automatic detection mode, and sequentially reads the pixel signals A + B held in each column. At this time, since the subject detection does not require a resolution that is used for an image, the subject detection memory read circuit 505 may read out the pixel signal A + B by thinning it out. Further, in addition to the thinning out of the pixel signals A + B, the speed is not limited by the simultaneous reading of a plurality of pixel signals A + B in parallel and the communication interface between devices. Accordingly, the subject detection memory readout circuit 505 completes the readout of the pixel signal A + B earlier than the image memory readout circuit 500 and the focus detection memory readout circuit 502. The subject detection circuit 506 holds the pixel signal A + B read by the subject detection memory readout circuit 505, and performs subject detection processing on the image based on the held pixel signal A + B. Then, the subject detection circuit 506 outputs coordinate information indicating in which region in the pixel unit 200 the pixel information of the subject is present to the region selection circuit 507. The area selection circuit 507 outputs area information for calculating the defocus amount to the frame memory 504. In the automatic object detection mode, the area selection circuit 507 generates area information based on the object coordinate information input from the object detection circuit 506 and outputs the area information to the frame memory 504. On the other hand, in the manual setting mode in which the user designates the position to be focused, the area selection circuit 507 displays the entire focus control coordinate information (image height information) as the area information to be focused set by the user. Input from the control calculation unit 106. Then, the region selection circuit 507 outputs the focus control coordinate information to the frame memory 504 as region information.

  The frame memory 504 holds the pixel signal A and the pixel signal B for one frame output from the focus detection amount signal generation circuit 503, and the pixel signal A and the pixel signal B in the region designated by the region selection circuit 507 The signal is output to the signal correction circuit 508. At this time, the frame memory 504 can output at a high speed by outputting a plurality of pixel signals in parallel. The pixel signal correction circuit 508 performs correction processing on the pixel signal A and the pixel signal B input from the frame memory 504, and outputs them to the defocus amount calculation circuit 210. Specifically, the pixel signal correction circuit 508 performs black level correction for each column and correction of a phenomenon in which the output is biased to one pixel signal depending on the position in the pixel unit 200. Since the correction of the bias depends on the state of the diaphragm of the lens, the parameter used for the correction is switched according to the lens information.

  FIG. 6 is a diagram illustrating a configuration example of the focus control circuit 211 in FIG. The K value selection circuit 601 receives focus control coordinates and lens information as image height information, selects a coefficient K from a coefficient table prepared in advance according to the exit pupil distance and image height determined from the lens type, The result is output to the multiplication circuit 600. The focus control coordinates are area information for performing the focusing set by the user. The lens information includes lens type and lens aperture information. The K value selection circuit 601 is a coefficient determination unit, and determines the coefficient K according to at least one of the lens type, the lens diaphragm, and the focus control coordinates. The multiplication circuit 600 is a multiplication unit, and multiplies the defocus amount output from the defocus amount calculation circuit 210 by a coefficient K, thereby moving the lens from the defocus amount that is a pixel shift amount. And output to the driver control circuit 602. The driver control circuit 602 inputs lens position information, lens driving amount, and lens information, and controls the driver output selection circuit 606. The driver control circuit 602 holds the lens drive amounts of a plurality of frames, calculates how much the distance to the subject changes during the next frame shooting based on the lens drive amounts of the immediately preceding plurality of frames, and inputs the change amount The lens driving amount is mixed. Accordingly, the driver control circuit 602 obtains an optimum lens driving amount at the time of shooting the next frame. The focus control circuit 211 includes a VCM (Voice Coil Motor) driver circuit 603, an STM (Stepping Motor) driver circuit 604, and a USM (Ultrasonic Motor) driver circuit 605. The driver control circuit 602 drives the lens to select and use one of the VCM driver circuit 603, the STM driver circuit 604, and the USM driver circuit 605 according to the type (lens information) of the focus actuator 102. Output quantity. The driver control circuit 602 controls the driver output selection circuit 606 and connects only one selected driver circuit to the output terminal. The driver control circuit 602 inputs lens position information of the focus lens 101 and performs highly accurate focus control.

  FIG. 7 is a timing chart showing a method for driving the image sensor 100 of FIG. The drive signals φRST_1, φRST_2, and φRST_n are drive signals φRST of the unit pixels 201 in the first row, the second row, and the n-th row, respectively. The drive signals φTXA_1, φTXA_2, and φTXA_n are drive signals φTXA for the unit pixels 201 in the first row, the second row, and the n-th row, respectively. The drive signals φTXB_1, φTXB_2, and φTXB_n are the drive signals φTXB of the unit pixels 201 in the first row, the second row, and the n-th row, respectively. The drive signals φSEL_1, φSEL_2, and φSEL_n are the drive signals φSEL of the unit pixels 201 in the first row, the second row, and the n-th row, respectively. The drive signals φRST, φTXA, φTXB, and φSEL are assumed to be in either a high level or a low level. ADC represents the state of processing in the ADC in the column circuit 203. N represents a state in which AD conversion is performed on the N signal from which the state after reset is read, and A represents a state in which AD conversion is performed on the A signal from which charges accumulated in the photoelectric conversion unit 300A are read out. AB represents a state in which AD conversion is performed on the A + B signal from which the charges accumulated in the photoelectric conversion unit 300A and the photoelectric conversion unit 300B are read. The focus drive signal indicates whether the focus drive signal is output from the focus control circuit 211.

  At timings t0 to t1, the vertical synchronization signal and the horizontal synchronization signal become high level pulses, the drive signals φRST of all the rows become high level, and reset vertical scanning of the photoelectric conversion units 300A and 300b is started. The vertical scanning is performed by performing common driving for the unit pixels 201 arranged in the same row every time the horizontal synchronization signal becomes high level, and repeating the driving per row for the number of rows. Specifically, when the drive signals φTXA and φTXB are sequentially set to the high level from the first row, the charges accumulated in the photoelectric conversion unit 300A and the photoelectric conversion unit 300B of the unit pixel 201 in the row are reset. The driving per row is repeated for n rows, the resetting of all the photoelectric conversion units 300A and 300B in the pixel unit 200 is completed, and accumulation of charges generated by the photoelectric conversion of the photoelectric conversion units 300A and 300B is started. To do.

  At timings t <b> 2 to t <b> 6, readout of the entire pixel portion 200 is performed by repeatedly performing readout per row n times by readout vertical scanning. At timing t2, the vertical synchronization signal and the horizontal synchronization signal become high level pulses, the drive signal φRST_1 becomes low level, and the drive signal φSEL_1 becomes high level. When the drive signal φRST_1 is at a low level, the reset transistor 303 is turned off in the unit pixel 201 in the first row, and the FD 302 is in a floating state. When the drive signal φSEL_1 becomes high level, the selection transistor 305 in the unit pixel 201 in the first row is turned on, and each unit pixel 201 in the first row sends an N signal to the column circuit 203 via the signal line 205. Output. After that, the ADC in the column circuit 203 performs AD conversion on the N signal corresponding to the potential of the FD 302 after reset. The AD converted N signal is held in the column circuit 203.

  At timing t3, the drive signal φTXA_1 becomes high level, the transfer transistor 301A is turned on in the unit pixel 201 in the first row, and the charge accumulated in the photoelectric conversion unit 300A is transferred to the FD 302. In the FD 302, the potential changes according to the transferred charge. The unit pixel 201 in the first row outputs an A signal to the column circuit 203 in accordance with a change in the potential of the FD 302. Thereafter, the ADC in the column circuit 203 performs AD conversion on the A signal. The column circuit 203 subtracts the held N signal from the A signal subjected to AD conversion, and records the pixel signal A in the column memory circuit 207.

  At timing t4, the driving signals φTXA_1 and φTXB_1 become high level, the transfer transistors 301A and 301B are turned on in the unit pixel 201 in the first row, and the charges accumulated in the photoelectric conversion units 300A and 300B are transferred to the FD 302. In the FD 302, the potential changes according to the transferred charge. The unit pixel 201 in the first row outputs an A + B signal to the column circuit 203 in accordance with the change in the potential of the FD 302. Thereafter, the ADC in the column circuit 203 performs AD conversion on the A + B signal. The column circuit 203 subtracts the held N signal from the AD converted A + B signal, and records the pixel signal A + B in the column memory circuit 207. Thereafter, the column memory circuit 207 sequentially outputs the pixel signal A and the pixel signal A + B to the signal processing circuit 208. Then, the focus detection signal generation circuit 503 generates the pixel signal B by subtracting the pixel signal A from the pixel signal A + B, and holds it in the frame memory 504. The image correction circuit 501 corrects the pixel signal A + B and sequentially outputs it to the outside of the image sensor 100 via the image signal output circuit 209. The subject detection circuit 506 reads out and holds the pixel signal A + B held in the column memory circuit 207.

  At timing t5, the drive signal φRST_1 becomes high level, the drive signal φSEL_1 becomes low level, and at the same time, the drive signal φRST_2 becomes low level and the drive signal φSEL_2 becomes high level. Thereby, the reading of the unit pixels 201 in the first row is completed, and the reading of the unit pixels 201 in the second row is started. When the drive signal φRST_2 becomes low level, the reset transistor 303 is turned off in the unit pixel 201 in the second row, and the FD 302 is in a floating state. When the drive signal φSEL_2 becomes high level, the selection transistor 305 in the unit pixel 201 in the second row is turned on, and each unit pixel 201 in the second row sends an N signal to the column circuit 203 via the signal line 205. Output. The ADC in the column circuit 203 performs AD conversion on the N signal corresponding to the potential of the FD 302 after reset.

  Thereafter, the drive signal φTXA_2 becomes high level, the transfer transistor 301A is turned on in the unit pixel 201 in the second row, and the charge accumulated in the photoelectric conversion unit 300A is transferred to the FD 302. The unit pixel 201 in the second row outputs an A signal to the column circuit 203 in accordance with the change in the potential of the FD 302. Thereafter, the ADC in the column circuit 203 performs AD conversion on the A signal. The column circuit 203 subtracts the held N signal from the A signal subjected to AD conversion, and records the pixel signal A in the column memory circuit 207.

  Thereafter, the drive signals φTXA_2 and φTXB_2 become high level, the transfer transistors 301A and 301B are turned on in the unit pixels 201 in the second row, and the charges accumulated in the photoelectric conversion units 300A and 300B are transferred to the FD 302. The unit pixel 201 in the second row outputs an A + B signal to the column circuit 203 in accordance with the change in the potential of the FD 302. Thereafter, the ADC in the column circuit 203 performs AD conversion on the A + B signal. The column circuit 203 subtracts the held N signal from the AD converted A + B signal, and records the pixel signal A + B in the column memory circuit 207. Thereafter, the same processing as the reading of the first row is performed.

  At timings t5 to t6, driving similar to that at timings t2 to t5 is performed for the second to nth rows. As a result, an image of one frame is acquired. Further, while the pixel signal is being read, the pixel signal A + B in the previous row is output to the outside of the image sensor 100 as an image output. At the same time as the pixel signal A + B in the nth row, which is the final row, is output to the outside of the image sensor 100, the subject detection circuit 506 reads the pixel signal A + B for subject detection. The pixel signal A + B for subject detection is read out by thinning out, in addition to reading out a plurality of pixel signals in parallel, and because the speed is not limited by the communication interface between devices, reading is completed earlier than image output, A subject detection circuit 506 performs subject detection.

  At the timing t6, the output of the image signal of the nth row that is the last row is completed, and at the same time, the signal processing circuit 208 outputs the pixel signal A and the pixel signal B used for focus detection to the defocus amount calculation circuit 210. start. At this time, the pixel signal A and the pixel signal B are communications within the image sensor 100 and output a plurality of pixel signals in parallel, so that high-speed signal transmission is possible. The defocus amount calculation circuit 210 sequentially calculates the defocus amount from the input pixel signal A and pixel signal B, and outputs the defocus amount to the focus control circuit 211. The focus control circuit 211 calculates a lens driving amount based on the calculated defocus amounts of a plurality of rows, predicts a focus position at the time of shooting the next frame from a plurality of lens driving amounts including the frame, and actually A lens driving amount to be controlled is calculated.

  At timings t7 to t8, the focus control circuit 211 outputs a focus drive signal according to the calculated lens drive amount. As a result, the focus lens 101 moves and focusing is performed. After timing t9, similarly to timings t0 to t8, driving of the next frame is repeated. By repeating these steps, it is possible to acquire a focused image.

  In the driving method of the image sensor in FIG. 7, the driving example in the automatic detection mode of the subject in which the subject is automatically detected and focused is shown. In the manual setting mode in which the user designates the position for focusing, since the area for focus detection is determined in advance, the defocus amount can be calculated as soon as AD conversion of the area is completed. In that case, since the drive amount can be calculated while the image signal is output, the focus drive signal is output as soon as the AD conversion of the nth row is completed. As a result, higher-speed focusing is possible.

  In the present embodiment, processing necessary for focus control can be completed inside the image sensor 100, so that it is not necessary to output the pixel signal A and the pixel signal B outside the image sensor 100. That is, since transmission is performed on the same semiconductor substrate, it is easy to transmit pixel signals in parallel through a large number of signal lines. Further, there is no need to increase the number of communication interfaces for outputting image signals to the outside of the image sensor 100. Furthermore, since there is no restriction on the speed of the communication interface, the transmission speed of each signal line can be increased compared to the case of outputting to the outside. For this reason, signals can be transmitted from the frame memory 504 to the focus control circuit 211 at high speed. Further, since the above speed can be increased, a large amount of pixel signal A and pixel signal B are used for calculation of the defocus amount without significantly increasing the processing time of the focus control, and high-precision focus control is performed. Can be possible.

  Furthermore, since the image sensor 100 includes the timing control circuit 206, it is easy to perform synchronous control of the focus control timing and the drive timing of the image sensor 100. For example, in the present embodiment, the timing at which the focus control circuit 211 outputs the focus drive signal is a timing that does not overlap the read drive time of the image sensor 100. This prevents the focus actuator 102 of the lens unit 111 from affecting the output of the image sensor 100 during reading due to fluctuations in the power supply voltage caused by, for example, external noise of magnetic noise or rush current of the driver circuit. It becomes possible.

  The imaging substrate 214 including the pixel portion 200 and the signal processing substrate 215 including the signal processing circuit 208 and the focus control circuit 211 are formed and stacked on different semiconductor substrates. However, the present invention is not limited to this. Instead, they may be formed on the same semiconductor substrate. However, in a configuration including a number of circuits that perform signal processing as in this embodiment, it is desirable to have a stacked structure. Further, in this embodiment, the pixel signal A and the pixel signal B are held in the frame memory 504 in the signal processing circuit 208, and after subject detection, the pixel signal of the region based on the detection result is read, and the defocus amount Calculation was performed. However, the defocus amount may be calculated sequentially from the pixel signal A and the pixel signal B in advance, and the result may be stored in the memory, and the defocus amount used after the subject detection may be selected.

(Second Embodiment)
An imaging apparatus according to a second embodiment of the present invention will be described with reference to FIGS. Hereinafter, the points of the present embodiment different from the first embodiment will be described. FIG. 8A is a diagram illustrating a layout example of the microlens 401 and the two photoelectric conversion units 300A and 300B in the unit pixel 201 according to the first embodiment. FIG. 8B is a diagram illustrating a layout example of the microlens 401 and the 16 photoelectric conversion units 801A to 801P in the unit pixel 800 according to the second embodiment. FIGS. 8A and 8B show four unit pixels near the center of the pixel portion as an example. In FIG. 8A, the microlens 401 is disposed so as to overlap the unit pixel 201. In FIG. 8A, the unit pixel 201 and the micro lens 401 overlap each other to show the unit pixel 201 near the center of the pixel unit 200. However, in the region other than the center of the pixel unit 200, the micro lens 401 is a unit pixel. The position is shifted with respect to 201. In addition, inside the unit pixel 201, two photoelectric conversion units 300A and 300B are arranged so as to divide the region in the unit pixel 201 into two in the horizontal direction. On the other hand, in FIG. 8B, 16 photoelectric conversion units 801 </ b> A to 801 </ b> P are arranged in a matrix in the unit pixel 800.

  FIG. 9 is a circuit diagram illustrating a configuration example of the unit pixel 800 of FIG. The unit pixel 800 has 16 divided pixels 900A to 900P. The divided pixels 900A to 900P have photoelectric conversion units 801A to 801P, respectively. The divided pixel 900A includes a photoelectric conversion unit 801A, transfer transistors 901A, FD902A, a reset transistor 903A, an amplification transistor 904A, and a signal output line 905A. In FIG. 9, the details of the divided pixel 900A are shown, but the divided pixels 900B to 900P also have the same configuration as the divided pixel A. The divided pixels 900A to 900P include photoelectric conversion units 801A to 801P, transfer transistors 901A to 901P, FD902A to 902P, reset transistors 903A to 903P, amplification transistors 904A to 904P, and output lines 905A to 905P, respectively. The transfer transistors 901A to 901P are controlled by a common drive signal φTX, and the reset transistors 903A to 903P are controlled by a common drive signal φRST. The unit pixel 800 outputs signals based on the charges converted by the plurality of photoelectric change units 801A to 801P in parallel via the output lines 905A to 905P.

  FIG. 10 is a diagram illustrating a configuration example of the image sensor 100 according to the present embodiment. The imaging element 100 has a three-layer configuration in which an imaging substrate 1011, an AD substrate 1012, and a signal processing substrate 1013 are stacked. The imaging board 1011, the AD board 1012, and the signal processing board 1013 are connected via a TSV. The imaging substrate 1011 is a first semiconductor substrate on which the pixel portion 1000 and the pixel driving circuit 1001 are provided. The AD substrate 1012 is a second semiconductor substrate on which an AD conversion / memory circuit 1003 and a timing control circuit 1004 are provided. The signal processing substrate 1013 is a third semiconductor substrate on which a signal processing circuit 1005, an image signal output circuit 1006, a defocus amount calculation circuit 1007, a focus control circuit 1008, a lens information input circuit 1009, and a position signal input circuit 1010 are provided. . Also in the first embodiment (FIG. 2), the column circuit 203 may be provided on an AD substrate different from the imaging substrate 214 and the signal processing substrate 215, and three semiconductor substrates may be stacked.

  The pixel unit 1000 includes a plurality of unit pixels 800 arranged in a matrix. The pixel drive circuit 1001 outputs a drive signal to the unit pixel 800 via the drive signal line 1002. As described above, the unit pixel 800 includes the signal output lines 905A to 905P of the divided pixels 900A to 900P. The divided pixels 900A to 900P output signals to the AD conversion / memory circuit 1003 via the signal output lines 905A to 905P, respectively. Specifically, the divided pixels 900 </ b> A to 900 </ b> P output N signals that are states after the resetting of the FDs 902 </ b> A to 902 </ b> P, respectively. Thereafter, the divided pixels 900A to 900P turn on the transfer transistors 901A to 901P, respectively, to output an S signal that is in a state after the charge of the photoelectric conversion unit 801 is transferred.

  The AD conversion / memory circuit 1003 is an ADC and is driven by the timing control circuit 1004 to convert the N signal and the S signal from analog to digital, respectively. Thereafter, the AD conversion / memory circuit 1003 subtracts the N signal from the S signal, thereby individually holding the signals based on the charges converted by the photoelectric conversion units 801A to 801P as the pixel signal A to the pixel signal P in the memory. To do. Further, the AD conversion / memory circuit 903 mixes the pixel signals A to P of the same unit pixel 800, and holds the pixel signal ALL in the memory.

  The signal processing circuit 1005 is driven by the timing control circuit 1004, reads the pixel signal ALL and the pixel signals A to P from the AD conversion / memory circuit 1003 in parallel, and generates a signal for correction processing and focus detection. The signal processing circuit 1005 performs correction processing such as peripheral light amount drop correction and black level correction in which the light amount is reduced at the peripheral portion of the image sensor 100 with respect to the pixel signal ALL used as a captured image, and outputs the correction result to the image output circuit 1006. . Further, the signal processing circuit 1005 generates a focus detection signal using the pixel signals A to P, corrects the black level, and outputs the signal to the defocus amount calculation circuit 1007. The focus detection signals to be output are two types of focus detection signals: a focus detection vertical signal and a focus detection horizontal signal. Details will be described later.

  The defocus amount calculation circuit 1007 calculates the defocus amount from the focus detection vertical signal and the focus detection horizontal signal output from the signal processing circuit 1005, and outputs the calculation result to the focus control circuit 1008. The defocus amount calculation circuit 1007 switches the focus detection signal to be used according to the evaluation value of the focus detection reliability of the two types of focus detection signals or is calculated from each of the two types of focus detection signals. Whether to calculate the defocus amount separately based on the defocus amount. Specifically, when one of the focus detection horizontal signal and the focus detection vertical signal has high reliability, the defocus amount calculation circuit 1007 determines the defocus amount based on the highly reliable focus detection signal. Is calculated. In addition, when the reliability of both the focus detection horizontal signal and the focus detection vertical signal is high, the defocus amount calculation circuit 1007 actually uses the average value of the defocus amounts calculated based on the defocus amount horizontal signal and the focus detection vertical signal. Amount. The focus control circuit 1008 generates a focus drive signal based on the defocus amount, similarly to the focus control circuit 211 in FIG.

  FIG. 11 is a diagram illustrating a configuration example of the signal processing circuit 1005 of FIG. The signal processing circuit 1005 includes an image memory reading circuit 1100 that reads a signal used for an image signal, a subject detection memory reading circuit 1101 that reads a signal used for subject detection, and a focus detection memory reading circuit 1102 used to generate a focus detection signal. Have Each of the memory reading circuits 1100 to 1102 is controlled by a control signal input from the timing control circuit 1004. The image memory readout circuit 1100 sequentially reads out the pixel signal ALL immediately after the image signal ALL is generated in the AD conversion / memory circuit 1003, and outputs it to the image correction circuit 1103. At this time, the image memory reading circuit 1100 appropriately selects whether to output all the pixel signals ALL or to read a part of the pixel signals ALL in accordance with the output format. For example, the image memory readout circuit 1100 reads out all the pixel signals ALL during still image shooting, and reads out only the pixel signals ALL arranged at a certain interval in accordance with the moving image format during moving image shooting.

  The subject detection memory readout circuit 1101 reads out the pixel signal ALL of the unit pixel 800 necessary for subject detection and outputs it to the subject detection circuit 1104 in the subject automatic detection mode. In the subject detection, since the resolution used for the image is not necessary, the subject detection memory reading circuit 1101 may read out more thinly than the image memory reading circuit 1100. Further, the speed of the image memory readout circuit 1100 is limited by the communication interface between devices when outputting to the outside of the image sensor 100, whereas the subject detection memory readout circuit 1101 is not limited to this, and the speed is high. It is possible to transmit. Also, the subject detection memory readout circuit 1101 has fewer pixel signals ALL to be read out for each frame than the image memory readout circuit 1100, and the readout ends earlier. The subject detection circuit 1104 receives the read pixel signal ALL, performs subject detection, and outputs subject coordinate information to the region selection circuit 1105. The area selection circuit 1105 outputs area information for calculating the defocus amount to the focus detection memory reading circuit 1102. In the automatic object detection mode, the area selection circuit 1105 generates area information based on the object coordinate information input from the object detection circuit 1104. In the manual setting mode in which the user designates the position for focusing, the area selection circuit 1105 receives focus control coordinate information as area information set by the user from the overall control calculation unit 106, and the coordinate information Generate region information based on

  Based on the region information input from the region selection circuit 1105, the focus detection memory readout circuit 1102 reads out the pixel signals A to P of the region and outputs them to the focus detection signal generation circuit 1106. Unlike the image memory readout circuit 1100, the focus detection memory readout circuit 1102 is not limited in speed by the communication interface between devices, and only the region designated by the region selection circuit 1105 is read out. Are read in parallel. Therefore, the focus detection memory reading circuit 1102 finishes reading earlier than the image memory reading circuit 1100. Further, the pixel signal A to the pixel signal P read out in parallel at the same time are signals of the same unit pixel 800.

  The focus detection signal generation circuit 1106 generates a focus detection signal based on the pixel signals A to P read simultaneously. The generated signal is a single pixel signal or a signal obtained by mixing a plurality of pixel signals, and a focus detection vertical signal for detecting a vertical line and a horizontal line for focus detection for detecting a horizontal line by a combination of pixel signals to be mixed. Signal. The focus detection signal generation circuit 1106 mixes a plurality of pixel signals A to P in different combinations. Further, the focus detection signal generation circuit 1106 switches the combination of pixel signals to be mixed according to the lens aperture, that is, the F-number information, which is the input lens information. Specifically, when the F number is small, the pixel signal A + E + I + M and the pixel signal D + H + L + P are used as the focus detection vertical signal, and the pixel signal A + B + C + D and the pixel signal M + N + O + P are used as the focus detection horizontal signal. As described above, when the F number is small and the exit pupil diameter of the photographing lens is large, if the defocus amount is calculated based on the pixel signal outside the pupil, focus control with higher accuracy can be performed. On the other hand, when the F number is large and the exit pupil diameter is small, almost no light is incident on the outer photoelectric conversion unit 801 in the unit pixel 800. Therefore, the combination of the focus detection vertical signal and the focus detection horizontal signal Then, it becomes difficult to calculate the defocus amount. Therefore, when the F number is large, the focus detection vertical signal uses the pixel signal A + B + E + F + I + J + M + N and the pixel signal C + D + G + H + K + L + O + P. Similarly, the pixel signal A + B + C + D + E + F + G + H and the pixel signal I + J + K + L + M + N + O + P are used as the focus detection horizontal signal. The pixel signal correction circuit 1107 corrects the focus detection vertical signal and the focus detection horizontal signal generated in this way, and outputs them to the defocus amount calculation circuit 1007.

  FIG. 12 is a timing chart showing a method for driving the image sensor 100 according to the present embodiment. In FIG. 12, ADC indicates the type of signal AD-converted by the AD conversion / memory circuit 1003, and the image output indicates the position in the pixel unit 1000 of the signal output by the image signal output circuit 1006. The focus drive signal indicates whether or not the focus drive signal output from the focus control circuit 1008 is output. The signal processing circuit, the defocus amount calculation circuit, and the focus control circuit indicate operation states in the respective circuits.

  At timing t0, the frame synchronization signal becomes a high level pulse, and the drive signal φRST is at high level. At timings t0 to t1, resetting of the photoelectric conversion units 801A to 801P is started. The gates of all the transfer transistors 901A to 901P in the pixel unit 1000 receive the drive signal φTX, and the drive signal φTX becomes high level, so that they are accumulated in all the photoelectric conversion units 801A to 801P in the pixel unit 1000. The charged charge is reset.

  At timing t1, the frame synchronization signal becomes a high level pulse, the drive signal φRST becomes a low level, and the FDs 902A to 902P are in a floating state. The divided pixels 900A to 900P output N signals corresponding to the potentials of the FDs 902A to 902P after reset to the AD conversion / memory circuit 1003, respectively. The AD conversion / memory circuit 1003 AD-converts the N signal and holds it in the memory.

  At timing t2, the drive signal φTX goes high, and the charges accumulated in the photoelectric conversion units 801A to 801P are transferred to the FDs 902A to 902P. Thereafter, the drive signal φTX becomes a low level. The divided pixels 900A to 900P output S signals corresponding to the potentials of the FDs 902A to 902P to the AD conversion / memory circuit 1003. The AD conversion / memory circuit 1003 AD-converts the S signal, subtracts the N signal from the AD-converted S signal, and holds the pixel signals A to P in the memory. The AD conversion / memory circuit 1003 mixes the pixel signals A to P for each unit pixel 800 and holds the pixel signal ALL in the memory. Since the above driving is performed for all the unit pixels 800, AD conversion of all the pixel signals is completed by one AD conversion driving.

  At timing t3, the signal processing circuit 1005 sequentially inputs the pixel signal ALL, performs correction processing by the image correction circuit 1103, and starts outputting an image to the outside of the image sensor 100 via the image signal output unit 1006. The output of the image is sequentially output from the pixel signal ALL of the unit pixel 800 arranged in the first row in the pixel unit 1000. At the same time, the signal processing circuit 1005 reads out the pixel signal ALL for subject detection by thinning out as necessary. Thereafter, the signal processing circuit 1005 performs subject detection and determines an area from which pixel signals used for focus detection are read. Subsequently, the focus detection signal generation circuit 1106 generates a focus detection vertical signal and a focus detection horizontal signal based on the pixel signals A to P corresponding to the determined region, and via the pixel signal correction circuit 1107, Output to the defocus amount calculation circuit 1007. At this time, the pixel signal ALL for subject detection, the pixel signals A to P for focus detection, the vertical signal for focus detection, and the horizontal signal for focus detection have a data amount only for information necessary for subject detection and accurate focus control. Has been reduced. Unlike the image output, the pixel signal ALL for object detection, the pixel signals A to P for focus detection, the vertical signal for focus detection, and the horizontal signal for focus detection are not limited by the communication interface between devices. Therefore, it can be transmitted in a shorter time than image output. The defocus amount calculation circuit 1007 calculates the defocus amount using the focus detection vertical signal and the focus detection horizontal signal that are sequentially input, and outputs the defocus amount to the focus control circuit 1008. As soon as the defocus amount is calculated, the focus control circuit 1008 calculates the lens drive amount. Thereafter, the driver control circuit 602 calculates an optimum lens driving amount based on the lens driving amounts of a plurality of frames.

  At timings t4 to t5, the focus control circuit 1008 outputs a focus drive signal according to the calculated lens drive amount. As a result, the focus lens 101 moves and focusing is performed. After timing t6, the processing for the next frame is performed in the same manner as driving at timings t0 to t5. By repeating this process, an in-focus image is acquired. The image output is sequentially performed after timing t3, and the calculation of the defocus amount and the output of the focus control signal are performed simultaneously with the image output.

  In the present embodiment, since processing necessary for focus control can be completed inside the image sensor 100, there is no need to output a focus detection signal outside the image sensor 100, and thus communication for outputting an image signal to the outside of the image sensor 100. There is no need to increase the number of interfaces. Furthermore, since this embodiment is not limited by the speed of the communication interface, it is possible to transmit a signal from the AD conversion / memory circuit 1003 to the focus control circuit 1008 at high speed. As a result, the present embodiment completes the processing necessary for focus control while outputting the image signal, even if many focus detection signals necessary for accurate focus control are used. Is possible. That is, in the present embodiment, it is possible to perform focus control with high accuracy without reducing the frame rate.

  In this embodiment, the signal processing circuit 1006 generates the focus detection vertical signal and the focus detection horizontal signal, but the AD conversion / memory circuit 1003 may generate them. In addition, the AD conversion / memory circuit 1003 is configured to simultaneously perform AD conversion on the signals of the photoelectric conversion units 801A to 801P in all the unit pixels 800. The AD conversion circuit may be shared and AD conversion may be performed in a time division manner. Even in this case, since the image sensor 100 does not need to output a focus detection signal to the outside of the image sensor 100, it is possible to perform focus control with high accuracy without reducing the frame rate.

(Third embodiment)
An imaging apparatus according to a third embodiment of the present invention will be described with reference to FIG. Hereinafter, differences of the present embodiment from the first and second embodiments will be described. FIG. 13 is a block diagram illustrating a configuration example of an imaging apparatus according to the third embodiment of the present invention. The imaging apparatus in FIG. 13 is different from the imaging apparatus in FIG. 1 in that a focus actuator 1302 and an imaging element position detection unit 1303 are provided instead of the focus actuator 102 and the lens position detection unit 103. In the first and second embodiments, the focus lens 101 is moved for focus control, but in the present embodiment, the image sensor 100 is moved for focus detection. In the present embodiment, the focus actuator 1302 moves the image sensor 100 along the optical axis OA under the control of the image sensor 100. The image sensor position detection unit 1303 detects the position of the image sensor 100 and outputs it to the image sensor 100. The image sensor 100 uses the position information of the image sensor 100 to perform focus control with high accuracy. A focus control circuit 211 in the image sensor 100 outputs a focus drive signal (control signal) for controlling the relative distance on the optical axis OA between the focus lens 101 and the image sensor 100 to the focus actuator 1302. . The focus actuator 1302 controls the relative distance on the optical axis OA between the focus lens 101 and the image sensor 100 according to the focus drive signal. This embodiment can obtain the same effects as those of the first and second embodiments.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100 Image sensor, 101 Focus lens, 200 Pixel part, 201 Unit pixel, 203 Column circuit, 208 Signal processing circuit, 210 Defocus amount calculation circuit, 211 Focus control circuit

Claims (13)

An image sensor that makes light incident through an optical system,
A plurality of unit pixels arranged in a matrix and each having a plurality of photoelectric conversion units that convert light incident through the optical system into charges;
Based on the signals of the plurality of unit pixels, it has a control unit for generating a control signal for controlling the relative distance on the optical axis between the optical system and the imaging element,
The unit pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit, a first signal based on the electric charge converted by the first photoelectric conversion unit, the first photoelectric conversion unit, A second signal based on a charge obtained by mixing the charges converted by the second photoelectric conversion unit is output in a time-sharing manner;
The control unit generates a third signal based on the electric charge converted by the second photoelectric conversion unit by subtracting the first signal from the second signal, and the first signal and An image pickup device that generates the control signal based on the third signal . And an analog-to-digital converter that converts the signals of the plurality of unit pixels from analog to digital.
The controller is
A defocus amount calculation unit that calculates a defocus amount based on a digital signal converted by the analog-digital conversion unit;
A focus control unit that generates a control signal for controlling a relative distance on the optical axis between the optical system and the imaging element based on the defocus amount calculated by the defocus amount calculation unit; The image pickup device according to claim 1, comprising: The controller is
A coefficient determination unit that determines a coefficient in accordance with at least one of the type of the optical system and the area information for focusing and focusing of the optical system;
The imaging device according to claim 2, further comprising: a multiplication unit that multiplies the defocus amount calculated by the defocus amount calculation unit by the coefficient determined by the coefficient determination unit.   The said control part selects and uses one of several drivers according to the kind of actuator which outputs the said control signal, The any one of Claims 1-3 characterized by the above-mentioned. Image sensor.   5. The image sensor according to claim 1, wherein each of the unit pixels outputs a signal based on the charges converted by the plurality of photoelectric conversion units in parallel.   The control unit mixes signals based on the charges converted by the plurality of photoelectric conversion units in a plurality of different combinations, and generates the control signal based on a result of the mixing. 5. The imaging device according to any one of 4 above. Furthermore, it has a position information input part which inputs the position information of an optical system, The imaging device of any one of Claims 1-6 characterized by the above-mentioned. The plurality of unit pixels are provided on a first semiconductor substrate, the control unit is provided on a second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are stacked. The imaging device according to any one of claims 1 to 7 . And an analog-to-digital converter that converts the signals of the plurality of unit pixels from analog to digital.
The plurality of unit pixels and the analog-digital conversion unit are provided on a first semiconductor substrate, the control unit is provided on a second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are stacked. imaging device according to any one of claims 1,4～ 7, characterized in that it is. And an analog-to-digital converter that converts the signals of the plurality of unit pixels from analog to digital.
The plurality of unit pixels are provided on a first semiconductor substrate, the analog-digital conversion unit is provided on a second semiconductor substrate, the control unit is provided on a third semiconductor substrate, and the first semiconductor substrate imaging device according to any one of claims 1,4～ 7, wherein the third semiconductor substrate and the second semiconductor substrate is characterized in that it is laminated with.   The plurality of unit pixels and the analog-digital conversion unit are provided on a first semiconductor substrate, the control unit is provided on a second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are stacked. The imaging device according to claim 2, wherein the imaging device is formed.   The plurality of unit pixels are provided on a first semiconductor substrate, the analog-digital conversion unit is provided on a second semiconductor substrate, the control unit is provided on a third semiconductor substrate, and the first semiconductor substrate The imaging device according to claim 2, wherein the second semiconductor substrate and the third semiconductor substrate are stacked. An imaging element according to any one of claims 1 to 1 2,
The optical system;
An image pickup apparatus comprising: an actuator that controls a relative distance on an optical axis between the optical system and the image pickup element.

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