JP6261709B2 - Multi-chip semiconductor device - Google Patents

Multi-chip semiconductor device Download PDF

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JP6261709B2
JP6261709B2 JP2016233132A JP2016233132A JP6261709B2 JP 6261709 B2 JP6261709 B2 JP 6261709B2 JP 2016233132 A JP2016233132 A JP 2016233132A JP 2016233132 A JP2016233132 A JP 2016233132A JP 6261709 B2 JP6261709 B2 JP 6261709B2
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semiconductor chip
connection portion
main surface
semiconductor device
multichip
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JP2017041659A (en
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三上　正人
正人 三上
孝典 関戸
孝典 関戸
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Olympus Corp
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Description

本発明は、個別の機能を備えた半導体チップを接続するマルチチップ半導体装置に関する。   The present invention relates to a multichip semiconductor device that connects semiconductor chips having individual functions.

従来、個別の機能を備えた半導体チップを接続することにより、複数の機能を備えるマルチチップ半導体装置が製造されている。   Conventionally, a multi-chip semiconductor device having a plurality of functions has been manufactured by connecting semiconductor chips having individual functions.

マルチチップ半導体装置の製造において、マルチチップ半導体装置を構成する１の半導体チップの電極形成面に溝加工を施し、他の半導体チップを、形成した溝に挿入することにより、アライメント精度よく２つの半導体チップを垂直接続するとともに、マルチチップ半導体装置の放熱効率を向上する技術が開示されている（たとえば、特許文献１参照）。   In the manufacture of a multichip semiconductor device, two semiconductors are aligned with high precision by performing groove processing on the electrode forming surface of one semiconductor chip constituting the multichip semiconductor device and inserting another semiconductor chip into the formed groove. A technique for vertically connecting chips and improving the heat dissipation efficiency of a multichip semiconductor device is disclosed (for example, see Patent Document 1).

特開２００２−７６２４４号公報JP 2002-76244 A

しかしながら、特許文献１に記載のマルチチップ半導体装置では、半導体チップ間の電気的接続面積が小さく、接続部の抵抗による伝送信号変質のおそれがある。   However, the multi-chip semiconductor device described in Patent Document 1 has a small electrical connection area between the semiconductor chips, and there is a risk of transmission signal alteration due to the resistance of the connection portion.

本発明は、上記に鑑みてなされたものであって、半導体チップ間のアライメントを容易かつ高精度にするとともに、伝送信号の変質を軽減しうるマルチチップ半導体装置を提供することを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to provide a multi-chip semiconductor device that can easily and accurately align semiconductor chips and reduce the quality of transmission signals.

上述した課題を解決し、目的を達成するために、本発明に係るマルチチップ半導体装置は、板状をなし、主面または主面と直交する側面に第１半導体チップ電極が形成された第１接続部を有する第１半導体チップと、板状をなし、主面と直交する側面に第２半導体チップ電極が形成された第２接続部を有する第２半導体チップと、を備え、前記第１接続部および前記第２接続部は、それぞれ主面に対し傾斜する傾斜面を少なくとも有し、前記第１半導体チップの主面と前記第２半導体チップの主面とが垂直となるように、前記第１接続部と前記第２接続部とを接続してなることを特徴とする。   In order to solve the above-described problems and achieve the object, a multichip semiconductor device according to the present invention has a plate shape, and a first semiconductor chip electrode is formed on a main surface or a side surface orthogonal to the main surface. A first semiconductor chip having a connection portion; and a second semiconductor chip having a second connection portion having a plate shape and having a second semiconductor chip electrode formed on a side surface orthogonal to the main surface. Each of the first connecting portion and the second connecting portion has at least an inclined surface inclined with respect to the main surface, and the main surface of the first semiconductor chip and the main surface of the second semiconductor chip are perpendicular to each other. One connection portion and the second connection portion are connected to each other.

また、本発明に係るマルチチップ半導体装置は、上記発明において、前記第１接続部は、前記第１半導体チップの側面に形成され、前記第１半導体チップの主面に対し傾斜する傾斜面と、前記第１半導体チップの主面に対し平行な平行面とからなり、前記第２接続部は、前記第２半導体チップの側面に形成され、前記第２半導体チップの主面に対し傾斜する傾斜面と、前記第２半導体チップの主面に対し垂直な垂直面とからなり、前記平行面と前記垂直面とを対向するように接続して、前記第１半導体チップの主面と前記第２半導体チップの主面とが垂直となるように接続してなることを特徴とする。   In the multichip semiconductor device according to the present invention, in the above invention, the first connection portion is formed on a side surface of the first semiconductor chip, and is inclined with respect to a main surface of the first semiconductor chip; The inclined surface is formed of a parallel surface parallel to the main surface of the first semiconductor chip, and the second connection portion is formed on a side surface of the second semiconductor chip and is inclined with respect to the main surface of the second semiconductor chip. And a vertical surface perpendicular to the main surface of the second semiconductor chip, and the parallel surface and the vertical surface are connected to face each other, the main surface of the first semiconductor chip and the second semiconductor It is characterized by being connected so that the main surface of the chip is perpendicular.

また、本発明に係るマルチチップ半導体装置は、上記発明において、前記第１接続部は、前記第１半導体チップの側面に形成され、前記第１半導体チップの主面に対し傾斜する傾斜面と、前記第１半導体チップの主面に対し垂直な垂直面とからなり、前記第２接続部は、前記第２半導体チップの側面に形成され、前記第２半導体チップの主面に対し傾斜する傾斜面と、前記第２半導体チップの主面に対し垂直な垂直面とからなり、前記第１接続部の傾斜面と前記第２接続部の傾斜面とを対向するように接続して、前記第１半導体チップの主面と前記第２半導体チップの主面とが垂直となるように接続してなることを特徴とする。   In the multichip semiconductor device according to the present invention, in the above invention, the first connection portion is formed on a side surface of the first semiconductor chip, and is inclined with respect to a main surface of the first semiconductor chip; The inclined surface is formed of a vertical surface perpendicular to the main surface of the first semiconductor chip, and the second connection portion is formed on a side surface of the second semiconductor chip and is inclined with respect to the main surface of the second semiconductor chip. And a vertical plane perpendicular to the main surface of the second semiconductor chip, the inclined surface of the first connection portion and the inclined surface of the second connection portion are connected to face each other, and the first The main surface of the semiconductor chip and the main surface of the second semiconductor chip are connected so as to be perpendicular to each other.

また、本発明に係るマルチチップ半導体装置は、上記発明において、対向接続する接続面以外の面で囲まれた補強部材補充空間内に補強部材を充填することを特徴とする。   The multi-chip semiconductor device according to the present invention is characterized in that, in the above-described invention, the reinforcing member is filled in a reinforcing member supplementary space surrounded by a surface other than the connection surface that is oppositely connected.

また、本発明に係るマルチチップ半導体装置は、上記発明において、前記第１接続部は、前記第１半導体チップの主面上に凹状に形成され、前記第１半導体チップの主面に対し傾斜する第１傾斜面および第２傾斜面と、前記第１半導体チップの主面に対し平行な底面とからなり、前記第２接続部は、前記第１半導体チップの側面に形成され、前記第２半導体チップの主面に対し傾斜する第３傾斜面および第４傾斜面と、前記第２半導体チップの主面に対し垂直な底面とからなり、前記第２接続部を前記第１接続部に嵌合接続することにより、前記第１半導体チップの主面と前記第２半導体チップの主面とが垂直となるように接続してなることを特徴とする。   In the multichip semiconductor device according to the present invention, in the above invention, the first connection portion is formed in a concave shape on the main surface of the first semiconductor chip, and is inclined with respect to the main surface of the first semiconductor chip. The second inclined surface includes a first inclined surface and a second inclined surface, and a bottom surface parallel to the main surface of the first semiconductor chip, and the second connection portion is formed on a side surface of the first semiconductor chip, and the second semiconductor A third inclined surface and a fourth inclined surface that are inclined with respect to the main surface of the chip, and a bottom surface that is perpendicular to the main surface of the second semiconductor chip, and the second connection portion is fitted to the first connection portion. By connecting, the main surface of the first semiconductor chip and the main surface of the second semiconductor chip are connected so as to be vertical.

本発明によれば、半導体チップの主面に対し傾斜する接続面を有する接続部を介して簡易、かつ高精度に位置合わせできるとともに、伝送信号の変質を軽減することができる。   According to the present invention, alignment can be performed easily and with high accuracy through a connection portion having a connection surface inclined with respect to the main surface of the semiconductor chip, and alteration of a transmission signal can be reduced.

図１は、本発明の実施の形態１に係るマルチチップ半導体装置の断面図である。FIG. 1 is a cross-sectional view of a multichip semiconductor device according to Embodiment 1 of the present invention. 図２は、本発明の実施の形態２に係るマルチチップ半導体装置の断面図である。FIG. 2 is a cross-sectional view of the multichip semiconductor device according to the second embodiment of the present invention. 図３は、図２に示す第２半導体チップの斜視図である。FIG. 3 is a perspective view of the second semiconductor chip shown in FIG. 図４は、本発明の実施の形態２の変形例１に係るマルチチップ半導体装置の断面図である。FIG. 4 is a cross-sectional view of a multichip semiconductor device according to Modification 1 of Embodiment 2 of the present invention. 図５は、本発明の実施の形態２の変形例２に係るマルチチップ半導体装置の断面図である。FIG. 5 is a cross-sectional view of a multichip semiconductor device according to Modification 2 of Embodiment 2 of the present invention. 図６は、本発明の実施の形態３に係るマルチチップ半導体装置の断面図である。FIG. 6 is a cross-sectional view of the multichip semiconductor device according to the third embodiment of the present invention. 図７は、本発明の実施の形態３の変形例に係るマルチチップ半導体装置の断面図である。FIG. 7 is a cross-sectional view of a multichip semiconductor device according to a modification of the third embodiment of the present invention.

以下、添付図面を参照して、本発明を実施するための形態（以下、「実施の形態」という）を説明する。なお、この実施の形態によりこの発明が限定されるものではない。また、図面の記載において、同一部分には同一の符号を付している。また、図面は模式的なものであり、各部材の厚みと幅との関係、各部材の比率などは、現実と異なることに留意する必要がある。図面の相互間においても、互いの寸法の関係や比率が異なる部分が含まれている。   DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as “embodiments”) will be described with reference to the accompanying drawings. Note that the present invention is not limited to the embodiments. In the description of the drawings, the same parts are denoted by the same reference numerals. The drawings are schematic, and it is necessary to note that the relationship between the thickness and width of each member, the ratio of each member, and the like are different from the actual ones. Also in the drawings, there are included portions having different dimensional relationships and ratios.

（実施の形態１）
図１は、本発明の実施の形態１に係るマルチチップ半導体装置の断面図である。本発明の実施の形態１に係るマルチチップ半導体装置１００は、第１半導体チップ１に形成された溝状の第１接続部３に第２半導体チップ２の側面に形成された第２接続部４を嵌合接続してなる。 (Embodiment 1)
FIG. 1 is a cross-sectional view of a multichip semiconductor device according to Embodiment 1 of the present invention. The multichip semiconductor device 100 according to the first embodiment of the present invention includes a second connection portion 4 formed on a side surface of the second semiconductor chip 2 in a groove-like first connection portion 3 formed in the first semiconductor chip 1. Is formed by fitting and connecting.

第１半導体チップ１は、板状をなし、主面ａ上に、溝状の第１接続部３が形成される。第１接続部３は、第１半導体チップ１の主面ａに対し傾斜する第１傾斜面５および第２傾斜面６と、第１半導体チップ１の主面ａに対し平行な底面７からなる。また、第１接続部３には、複数の第１半導体チップ電極８が、絶縁部材により絶縁された状態で、所定間隔毎に形成されている。   The first semiconductor chip 1 has a plate shape, and a groove-shaped first connection portion 3 is formed on the main surface a. The first connection portion 3 includes a first inclined surface 5 and a second inclined surface 6 that are inclined with respect to the main surface a of the first semiconductor chip 1, and a bottom surface 7 that is parallel to the main surface a of the first semiconductor chip 1. . In the first connection portion 3, a plurality of first semiconductor chip electrodes 8 are formed at predetermined intervals while being insulated by an insulating member.

第２半導体チップ２は、板状をなし、主面ａと直行する側面に、第２接続部４が形成される。第２接続部４は、第２半導体チップ２の主面ｂに対し傾斜する第３傾斜面９および第４傾斜面１０と、第２半導体チップ２の主面ｂに対し平行な底面１１からなる。また、第２接続部４には、第１半導体チップ電極８と同数の第２半導体チップ電極１２が、絶縁部材により絶縁された状態で、図面と直交する方向に沿って所定間隔毎に形成されている。   The second semiconductor chip 2 has a plate shape, and a second connection portion 4 is formed on a side surface orthogonal to the main surface a. The second connection portion 4 includes a third inclined surface 9 and a fourth inclined surface 10 that are inclined with respect to the main surface b of the second semiconductor chip 2, and a bottom surface 11 that is parallel to the main surface b of the second semiconductor chip 2. . Further, the same number of second semiconductor chip electrodes 12 as the first semiconductor chip electrodes 8 are formed in the second connection portion 4 at predetermined intervals along a direction orthogonal to the drawing in a state of being insulated by an insulating member. ing.

マルチチップ半導体装置１００は、第２接続部４を第１接続部３に嵌合接続することにより、第１半導体チップ１の主面ａと第２半導体チップ２の主面ｂとが垂直となるように接続される。本明細書において、第１半導体チップ１の主面ａと第２半導体チップ２の主面ｂとが垂直とは、主面ａと主面ｂとのなす角度θが、８０°＜θ＜１１０°であることを意味する。第１半導体チップ１と第２半導体チップ２とのなす角度θは、９０°であることが好ましい。第１接続部３と第２接続部４とは、はんだ等の導電部材により接続される。これにより、第１半導体チップ電極８と第２半導体チップ電極１２とを電気的に接続する。   In the multichip semiconductor device 100, the main surface a of the first semiconductor chip 1 and the main surface b of the second semiconductor chip 2 become vertical by fitting and connecting the second connection portion 4 to the first connection portion 3. So that they are connected. In the present specification, the main surface a of the first semiconductor chip 1 and the main surface b of the second semiconductor chip 2 are perpendicular to each other. The angle θ formed by the main surface a and the main surface b is 80 ° <θ <110. Means °. The angle θ formed by the first semiconductor chip 1 and the second semiconductor chip 2 is preferably 90 °. The first connection portion 3 and the second connection portion 4 are connected by a conductive member such as solder. Thereby, the first semiconductor chip electrode 8 and the second semiconductor chip electrode 12 are electrically connected.

また、第１接続部３と第２接続部４との接続部周辺は、補強部材１３により補強されることが好ましい。補強部材１３は、補強樹脂等を使用することができ、補強部材１３により接続部周辺を補強することにより、マルチチップ半導体装置１００の機械的強度を向上することができる。   Moreover, it is preferable that the periphery of the connection portion between the first connection portion 3 and the second connection portion 4 is reinforced by the reinforcing member 13. A reinforcing resin or the like can be used for the reinforcing member 13, and the mechanical strength of the multichip semiconductor device 100 can be improved by reinforcing the periphery of the connecting portion by the reinforcing member 13.

本発明の実施の形態１に係るマルチチップ半導体装置１００は、傾斜面を備えた第１接続部３および第２接続部４を介して第１半導体チップ１と第２半導体チップ２とを接続するため、電気的接続面積を大きくすることが可能となり、接続部の抵抗値が下がり、伝送信号への影響を軽減することができる。また、マルチチップ半導体装置１００は、第１接続部３および第２接続部４の形状がテーパ形状であるため、接続部に外力が加わった際の応力集中を低減でき、半導体チップの破損を防止することができる。さらに、第１半導体チップ１と第２半導体チップ２との接続は、溝状の第１接続部３に第２接続部４を嵌合することにより行うため、アライメントを容易行うことができ、かつ精度を向上することも可能となる。   The multi-chip semiconductor device 100 according to the first embodiment of the present invention connects the first semiconductor chip 1 and the second semiconductor chip 2 via the first connection part 3 and the second connection part 4 having inclined surfaces. Therefore, the electrical connection area can be increased, the resistance value of the connection portion can be reduced, and the influence on the transmission signal can be reduced. In the multichip semiconductor device 100, since the first connection portion 3 and the second connection portion 4 are tapered, stress concentration when an external force is applied to the connection portion can be reduced, and damage to the semiconductor chip can be prevented. can do. Furthermore, since the connection between the first semiconductor chip 1 and the second semiconductor chip 2 is performed by fitting the second connection part 4 into the groove-shaped first connection part 3, alignment can be easily performed, and It is also possible to improve accuracy.

（実施の形態２）
図２は、本発明の実施の形態２に係るマルチチップ半導体装置の断面図である。図３は、図２に示す第２半導体チップの斜視図である。本発明の実施の形態２に係るマルチチップ半導体装置１００Ａは、第１半導体チップ１Ａと第２半導体チップ２Ａとを、側面で接続してなる。 (Embodiment 2)
FIG. 2 is a cross-sectional view of the multichip semiconductor device according to the second embodiment of the present invention. FIG. 3 is a perspective view of the second semiconductor chip shown in FIG. The multichip semiconductor device 100A according to the second embodiment of the present invention is formed by connecting the first semiconductor chip 1A and the second semiconductor chip 2A at the side surfaces.

第１半導体チップ１Ａは、板状をなし、主面ａと直交する側面に、第１半導体チップ電極８Ａが形成された第１接続部３Ａを有する。第１接続部３Ａは、第１半導体チップ１Ａの主面ａに対し傾斜する傾斜面１４と、第１半導体チップ１Ａの主面ａに対し垂直な垂直面１５とからなる。第１半導体チップ電極８Ａは、傾斜面１４上に複数の第１半導体チップ電極８Ａが絶縁部材により絶縁された状態で、後述する第２半導体チップ電極と同数、所定の間隔で形成されている。   The first semiconductor chip 1A has a plate-like shape, and has a first connection portion 3A in which a first semiconductor chip electrode 8A is formed on a side surface orthogonal to the main surface a. The first connection portion 3A includes an inclined surface 14 that is inclined with respect to the main surface a of the first semiconductor chip 1A, and a vertical surface 15 that is perpendicular to the main surface a of the first semiconductor chip 1A. The first semiconductor chip electrodes 8A are formed on the inclined surface 14 with a plurality of first semiconductor chip electrodes 8A insulated by an insulating member at the same number as the second semiconductor chip electrodes described later at a predetermined interval.

第２半導体チップ２Ａは、板状をなし、図３に示すように、主面ｂと直交する側面に、第２半導体チップ電極１２Ａが形成された第２接続部４Ａを有する。第２接続部４Ａは、第２半導体チップ２Ａの主面ｂに対し傾斜する傾斜面１６と、第２半導体チップ２Ａの主面ｂに対し垂直な垂直面１７とからなる。図３では、第２半導体チップ電極１２Ａは傾斜面１６上に、所定の間隔で４つ形成された例を示しているが、これに限定されるものではない。複数の第２半導体チップ電極１２Ａは、絶縁部材１９により絶縁された状態で形成されている。   As shown in FIG. 3, the second semiconductor chip 2A has a plate shape, and has a second connection portion 4A in which a second semiconductor chip electrode 12A is formed on a side surface orthogonal to the main surface b. The second connection portion 4A includes an inclined surface 16 that is inclined with respect to the main surface b of the second semiconductor chip 2A, and a vertical surface 17 that is perpendicular to the main surface b of the second semiconductor chip 2A. FIG. 3 shows an example in which four second semiconductor chip electrodes 12A are formed on the inclined surface 16 at a predetermined interval, but the present invention is not limited to this. The plurality of second semiconductor chip electrodes 12 </ b> A are formed in a state of being insulated by the insulating member 19.

実施の形態２に係るマルチチップ半導体装置１００Ａは、第１半導体チップ１Ａの主面ａに対し傾斜する傾斜面１４と、第２半導体チップ２Ａの主面ｂに対し傾斜する傾斜面１６とを対向するように接続することにより、第１半導体チップ１Ａの主面ａと第２半導体チップ２Ａの主面ｂとが垂直になるように接続される。傾斜面１４と傾斜面１６との接続は、はんだ等の導電部材により接続され、これにより、第１半導体チップ電極８Ａと第２半導体チップ電極１２Ａとが電気的に接続される。   The multichip semiconductor device 100A according to the second embodiment opposes the inclined surface 14 inclined with respect to the main surface a of the first semiconductor chip 1A and the inclined surface 16 inclined with respect to the main surface b of the second semiconductor chip 2A. By connecting in such a manner, the main surface a of the first semiconductor chip 1A and the main surface b of the second semiconductor chip 2A are connected so as to be vertical. The inclined surface 14 and the inclined surface 16 are connected by a conductive member such as solder, whereby the first semiconductor chip electrode 8A and the second semiconductor chip electrode 12A are electrically connected.

また、マルチチップ半導体装置１００Ａは、第１半導体チップ１Ａの主面ａに対し垂直な垂直面１５と、第２半導体チップ２Ａの主面ｂに対し垂直な垂直面１７により囲まれた空間である補強部材充填空間１８を備える。補強部材充填空間１８に充填した補強部材１３、および第１半導体チップ１Ａと第２半導体チップ２Ａとの接続面の他方側を補強部材１３で補強することにより、マルチチップ半導体装置１００Ａの機械的強度を向上することが可能となる。なお、補強部材１３としては、補強樹脂等が使用できるほか、はんだ等の導電部材も使用可能である。   The multichip semiconductor device 100A is a space surrounded by a vertical surface 15 perpendicular to the main surface a of the first semiconductor chip 1A and a vertical surface 17 perpendicular to the main surface b of the second semiconductor chip 2A. A reinforcing member filling space 18 is provided. By reinforcing the reinforcing member 13 filled in the reinforcing member filling space 18 and the other side of the connection surface between the first semiconductor chip 1A and the second semiconductor chip 2A with the reinforcing member 13, the mechanical strength of the multi-chip semiconductor device 100A. Can be improved. In addition, as the reinforcing member 13, a reinforcing resin or the like can be used, and a conductive member such as solder can also be used.

マルチチップ半導体装置１００Ａは、補強部材充填空間１８を備えることにより、機械的強度を向上できるほか、補強部材充填空間１８は、垂直接続面１５と垂直接続面１７とにより囲まれた空間に形成されるため、マルチチップ半導体装置１００Ａの高さＨを低減することが可能となる。   The multi-chip semiconductor device 100A includes the reinforcing member filling space 18 so as to improve mechanical strength, and the reinforcing member filling space 18 is formed in a space surrounded by the vertical connection surface 15 and the vertical connection surface 17. Therefore, the height H of the multichip semiconductor device 100A can be reduced.

本発明の実施の形態２に係るマルチチップ半導体装置１００Ａは、各半導体チップの主面に対し傾斜する接続面を介して半導体チップを接続するため、電気的接続面積を大きくすることが可能となり、接続部の抵抗値が下がり、伝送信号への影響を軽減することができる。また、マルチチップ半導体装置１００Ａは、補強部材充填空間１８に補強部材１３を充填することにより、大型化を抑制しながら接続強度を向上することが可能となる。   Since the multi-chip semiconductor device 100A according to the second embodiment of the present invention connects the semiconductor chips via connection surfaces that are inclined with respect to the main surface of each semiconductor chip, it is possible to increase the electrical connection area. The resistance value of the connection portion decreases, and the influence on the transmission signal can be reduced. In addition, the multichip semiconductor device 100A can improve the connection strength while suppressing an increase in size by filling the reinforcing member filling space 18 with the reinforcing member 13.

また、本実施の形態２の変形例１として図４に示すマルチチップ半導体装置を例示することができる。マルチチップ半導体装置１００Ｂにおいて、補強部材充填空間１８に補強部材１３として導電部材が使用される。また、第１半導体チップ電極８Ｂは、傾斜面１４Ｂおよび垂直面１５Ｂ上に形成されるとともに、第２半導体チップ電極１２Ｂは、傾斜面１６Ｂおよび垂直面１７Ｂ上に形成され、実施の形態２にかかるマルチチップ半導体装置１００Ａよりも電気的接続面積を大きくすることができる。これにより、接続部の抵抗をさらに低減することができる。   Further, a multichip semiconductor device shown in FIG. 4 can be exemplified as a first modification of the second embodiment. In the multichip semiconductor device 100B, a conductive member is used as the reinforcing member 13 in the reinforcing member filling space 18. The first semiconductor chip electrode 8B is formed on the inclined surface 14B and the vertical surface 15B, and the second semiconductor chip electrode 12B is formed on the inclined surface 16B and the vertical surface 17B. The electrical connection area can be made larger than that of the multichip semiconductor device 100A. Thereby, the resistance of the connection portion can be further reduced.

さらにまた、小型化の要求が大きくない用途に対しては、図５に示すようなマルチチップ半導体装置であってもよい。図５に示すマルチチップ半導体装置１００Ｃは、傾斜面１４Ｃのみからなる第１接続部３Ｃと、傾斜面１６Ｃのみからなる第２接続部４Ｃとを接続してなる。マルチチップ半導体装置１００Ｃは、実施の形態２に係るマルチチップ半導体装置１００Ａと同様に、各半導体チップの主面に対し傾斜する傾斜接続面１４Ｃおよび傾斜接続面１６Ｃを対向するように半導体チップを接続するため、電気的接続面積を大きくすることが可能となり、接続部の抵抗値が下がり、伝送信号への影響を軽減することができる。   Furthermore, a multichip semiconductor device as shown in FIG. 5 may be used for applications where the demand for miniaturization is not large. A multi-chip semiconductor device 100C shown in FIG. 5 is formed by connecting a first connection portion 3C composed only of an inclined surface 14C and a second connection portion 4C composed only of an inclined surface 16C. Similarly to multichip semiconductor device 100A according to the second embodiment, multichip semiconductor device 100C connects the semiconductor chips so that inclined connection surface 14C and inclined connection surface 16C are inclined with respect to the main surface of each semiconductor chip. Therefore, it is possible to increase the electrical connection area, the resistance value of the connection portion is reduced, and the influence on the transmission signal can be reduced.

（実施の形態３）
図６は、本発明の実施の形態３に係るマルチチップ半導体装置の断面図である。本発明の実施の形態３に係るマルチチップ半導体装置１００Ｄは、第１半導体チップ１Ｄと第２半導体チップ２Ｄとを、側面で接続してなる。 (Embodiment 3)
FIG. 6 is a cross-sectional view of the multichip semiconductor device according to the third embodiment of the present invention. A multichip semiconductor device 100D according to Embodiment 3 of the present invention is formed by connecting a first semiconductor chip 1D and a second semiconductor chip 2D at the side surfaces.

第１半導体チップ１Ｄは、板状をなし、主面ａと直交する側面に、第１半導体チップ電極８Ｄが形成された第１接続部３Ｄを有する。第１接続部３Ｄは、第１半導体チップ１Ｄの主面ａに対し傾斜する傾斜面１４Ｄと、第１半導体チップ１Ｄの主面ａに対し平行な平行面２０とからなる。第１半導体チップ電極８Ｄは、傾斜面１４Ｄおよび平行面２０上に各第１半導体チップ電極８Ｄが絶縁部材により絶縁された状態で、所定の間隔で形成されている。   The first semiconductor chip 1D has a plate shape and includes a first connection portion 3D in which a first semiconductor chip electrode 8D is formed on a side surface orthogonal to the main surface a. The first connection portion 3D includes an inclined surface 14D that is inclined with respect to the main surface a of the first semiconductor chip 1D, and a parallel surface 20 that is parallel to the main surface a of the first semiconductor chip 1D. The first semiconductor chip electrodes 8D are formed at predetermined intervals on the inclined surface 14D and the parallel surface 20 with the first semiconductor chip electrodes 8D insulated by an insulating member.

第２半導体チップ２Ｄは、板状をなし、主面ｂと直交する側面に、第２半導体チップ電極１２Ｄが形成された第２接続部４Ｄを有する。第２接続部４Ｄは、第２半導体チップ２Ｄの主面ｂに対し傾斜する傾斜面１６Ｄと、第２半導体チップ２Ｄの主面ｂに対し垂直な垂直面１７Ｄとからなる。第２半導体チップ電極１２Ｄは傾斜面１６Ｄおよび垂直面１７Ｄ上に、第１半導体チップ電極８Ｄと同数、絶縁部材により絶縁された状態で、所定の間隔で形成される。   The second semiconductor chip 2D has a plate shape and has a second connection portion 4D in which a second semiconductor chip electrode 12D is formed on a side surface orthogonal to the main surface b. The second connection portion 4D includes an inclined surface 16D that is inclined with respect to the main surface b of the second semiconductor chip 2D, and a vertical surface 17D that is perpendicular to the main surface b of the second semiconductor chip 2D. The second semiconductor chip electrodes 12D are formed on the inclined surface 16D and the vertical surface 17D at a predetermined interval in the same number as the first semiconductor chip electrodes 8D and insulated by an insulating member.

第１接続部３Ｄは、エッチング等により形成することができる。たとえば、シリコンからなる第１半導体チップ１Ｄに、エッチングにより平行面２０と傾斜面１４Ｄとを備える第１接続部３Ｄを形成する場合、結晶面の方向によってエッチング速度が異なるため、所定の傾斜角度の傾斜面１４Ｄを形成することができる。   The first connection portion 3D can be formed by etching or the like. For example, when the first connection portion 3D including the parallel surface 20 and the inclined surface 14D is formed by etching on the first semiconductor chip 1D made of silicon, the etching rate varies depending on the direction of the crystal plane, and thus a predetermined inclination angle is obtained. The inclined surface 14D can be formed.

実施の形態３に係るマルチチップ半導体装置１００Ｄは、第１半導体チップ１Ｄの主面ａに対し平行な平行面２０と、第２半導体チップ２Ｄの主面ｂに対し垂直な垂直面１７Ｄとを対向するように接続することにより、第１半導体チップ１Ｄの主面ａと第２半導体チップ２Ｄの主面ｂとが垂直になるように接続される。平行面２０と垂直面１７Ｄとの接続は、はんだ等の導電部材により接続される。   In the multichip semiconductor device 100D according to the third embodiment, the parallel surface 20 parallel to the main surface a of the first semiconductor chip 1D faces the vertical surface 17D perpendicular to the main surface b of the second semiconductor chip 2D. By connecting in such a manner, the main surface a of the first semiconductor chip 1D and the main surface b of the second semiconductor chip 2D are connected so as to be vertical. The parallel surface 20 and the vertical surface 17D are connected by a conductive member such as solder.

また、マルチチップ半導体装置１００Ｄは、第１半導体チップ１Ｄの主面ａに対し傾斜する傾斜面１４Ｄと、第２半導体チップ２Ｄの主面ｂに対し傾斜する傾斜面１６Ｄにより主として囲まれた空間である補強部材充填空間１８Ｄを備える。補強部材充填空間１８Ｄに、補強部材１３として導電部材を充填することにより、マルチチップ半導体装置１００Ｄの機械的強度を向上するとともに、第１半導体チップ電極８Ｄと第２半導体チップ電極１２Ｄとの接続面積を大きくして、接続部の抵抗値を下げ、伝送信号への影響を軽減することができる。   The multi-chip semiconductor device 100D is a space mainly surrounded by an inclined surface 14D inclined with respect to the main surface a of the first semiconductor chip 1D and an inclined surface 16D inclined with respect to the main surface b of the second semiconductor chip 2D. A reinforcing member filling space 18D is provided. By filling the reinforcing member filling space 18D with the conductive member as the reinforcing member 13, the mechanical strength of the multichip semiconductor device 100D is improved and the connection area between the first semiconductor chip electrode 8D and the second semiconductor chip electrode 12D is increased. Can be increased to reduce the resistance value of the connection portion and reduce the influence on the transmission signal.

本発明の実施の形態３に係るマルチチップ半導体装置１００Ｄは、平行面２０と垂直面１７Ｄとを対向するようにして半導体チップを接続し、また、補強部材充填空間１８Ｄに導電部材を充填することにより、マルチチップ半導体装置１００Ｄの機械的強度を向上し、接続部の抵抗を下げることが可能となる。   The multichip semiconductor device 100D according to the third embodiment of the present invention connects the semiconductor chips so that the parallel surface 20 and the vertical surface 17D face each other, and fills the reinforcing member filling space 18D with a conductive member. As a result, the mechanical strength of the multichip semiconductor device 100D can be improved and the resistance of the connection portion can be lowered.

また、本実施の形態３の変形例として図７に示すマルチチップ半導体装置を例示することができる。マルチチップ半導体装置１００Ｅにおいて、傾斜面１４Ｅと平行面２０Ｅとの長さの比、および傾斜面１６Ｅと垂直面１７Ｅとの長さの比を調整することにより、垂直接続面１７Ｅ上に平行接続面２０Ｅと接続しない空間が形成される。該空間には、補強部材１３を充填してマルチチップ半導体装置１００Ｅの機械的強度を向上させるほか、他のチップ等の実装等も可能となる。   Further, as a modification of the third embodiment, a multichip semiconductor device shown in FIG. 7 can be exemplified. In the multichip semiconductor device 100E, the parallel connection surface is formed on the vertical connection surface 17E by adjusting the length ratio between the inclined surface 14E and the parallel surface 20E and the length ratio between the inclined surface 16E and the vertical surface 17E. A space not connected to 20E is formed. The space is filled with the reinforcing member 13 to improve the mechanical strength of the multichip semiconductor device 100E, and other chips can be mounted.

以上のように、本発明のマルチチップ半導体装置は、デジタルカメラおよびデジタルビデオカメラを始め、撮像機能を備えた携帯電話機、被検者の臓器内部を観察するための内視鏡システムなど、各種に対応した撮像モジュールに有用である。   As described above, the multi-chip semiconductor device of the present invention can be applied to various types such as a digital camera and a digital video camera, a mobile phone having an imaging function, an endoscope system for observing the inside of a subject's organ, and the like. Useful for compatible imaging modules.

１、１Ａ、１Ｂ、１Ｃ、１Ｄ、１Ｅ 第１半導体チップ
２、２Ａ、２Ｂ、２Ｃ、２Ｄ、２Ｅ 第２半導体チップ
３、３Ａ、３Ｂ、３Ｃ、３Ｄ、３Ｅ 第１接続部
４、４Ａ、４Ｂ、４Ｃ、４Ｄ、４Ｅ 第２接続部
５ 第１傾斜面
６ 第２傾斜面
７ 底面
８ 第１半導体チップ電極
９ 第３傾斜面
１０ 第４傾斜面
１１ 底面
１２ 第２半導体チップ電極
１３ 補強部材
１４、１６ 傾斜面
１５、１７ 垂直面
１８ 補強部材充填空間
１９ 絶縁部材
２０ 平行面
１００、１００Ａ、１００Ｂ、１００Ｃ、１００Ｄ、１００Ｅ マルチチップ半導体装置 1, 1A, 1B, 1C, 1D, 1E First semiconductor chip 2, 2A, 2B, 2C, 2D, 2E Second semiconductor chip 3, 3A, 3B, 3C, 3D, 3E First connection portion 4, 4A, 4B 4C, 4D, 4E Second connecting portion 5 First inclined surface 6 Second inclined surface 7 Bottom surface 8 First semiconductor chip electrode 9 Third inclined surface 10 Fourth inclined surface 11 Bottom surface 12 Second semiconductor chip electrode 13 Reinforcing member 14 , 16 Inclined surface 15, 17 Vertical surface 18 Reinforcing member filling space 19 Insulating member 20 Parallel surface 100, 100A, 100B, 100C, 100D, 100E Multichip semiconductor device

Claims (2)

板状をなし、主面に第１半導体チップ電極が形成された第１接続部を有する第１半導体チップと、
板状をなし、主面と直交する側面に第２半導体チップ電極が形成された第２接続部を有する第２半導体チップと、
を備え、
前記第１接続部は、前記第１半導体チップの主面上に凹状に形成され、前記第１半導体チップの主面に対し傾斜する第１傾斜面および第２傾斜面と、前記第１半導体チップの主面に対し平行な底面とからなり、前記第１半導体チップ電極は、前記第１接続部上の第１傾斜面、第２傾斜面、および底面上に形成され、
前記第２接続部は、前記第２半導体チップの側面に形成され、前記第２半導体チップの主面に対し傾斜する第３傾斜面および第４傾斜面と、前記第２半導体チップの主面に対し垂直な底面とからなり、前記第２半導体チップ電極は、前記第２接続部上の第３傾斜面、第４傾斜面、および底面上に形成され、
前記第２接続部を前記第１接続部に嵌合接続することにより、前記第１半導体チップの主面と前記第２半導体チップの主面とが垂直となるように接続してなることを特徴とするマルチチップ半導体装置。 A first semiconductor chip having a plate-like shape and having a first connection portion in which a first semiconductor chip electrode is formed on a main surface;
A second semiconductor chip having a plate-like shape and having a second connection portion in which a second semiconductor chip electrode is formed on a side surface orthogonal to the main surface;
With
The first connection portion is formed in a concave shape on the main surface of the first semiconductor chip, and includes a first inclined surface and a second inclined surface that are inclined with respect to the main surface of the first semiconductor chip, and the first semiconductor chip. And the first semiconductor chip electrode is formed on the first inclined surface, the second inclined surface, and the bottom surface on the first connection portion,
It said second connecting portion is formed on a side surface of the second semiconductor chip, and a third inclined surface and a fourth inclined surface inclined with respect to the main surface of the second semiconductor chip, on the main surface of the second semiconductor chip The second semiconductor chip electrode is formed on the third inclined surface, the fourth inclined surface, and the bottom surface on the second connection portion;
The main surface of the first semiconductor chip and the main surface of the second semiconductor chip are connected so as to be perpendicular by fitting and connecting the second connection portion to the first connection portion. Multi-chip semiconductor device. 対向接続する接続面以外の面で囲まれた補強部材補充空間内に充填されてなる補強部材を有することを特徴とする請求項１に記載のマルチチップ半導体装置。
The multichip semiconductor device according to claim 1, further comprising a reinforcing member filled in a reinforcing member supplementary space surrounded by a surface other than the connection surface facing each other.
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