JP6258899B2 - Semiconductor device - Google Patents

Description

  The present specification relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device including a semiconductor element layer, a multilayer wiring layer formed on the semiconductor element layer, and an active electrode that is disposed near the upper surface of the multilayer wiring layer and receives an active potential. Has been. In this semiconductor device, the MEMS structure including the movable electrode is disposed so as to face the active electrode, and the angular velocity of the semiconductor device is detected by detecting a change in capacitance between the active electrode and the movable electrode. . In the semiconductor device of Patent Document 1, an active potential that periodically varies is input to the active electrode in order to detect the capacitance between the active electrode and the movable electrode.

Special table 2007-509346 gazette

  A signal wiring for transmitting a signal is formed inside the multilayer wiring layer. Various semiconductor elements such as diodes and transistors are formed in the semiconductor element layer below the multilayer wiring layer. For this reason, when an active potential that periodically fluctuates is input to an active electrode disposed in the vicinity of the upper surface of the multilayer wiring layer, as internal noise, the signal wiring inside the multilayer wiring layer or the semiconductor element of the semiconductor element layer Affects operation. In order to avoid this, it is effective to dispose a ground electrode connected to a ground potential so as to block between the active electrode, the signal wiring, and the semiconductor element inside the multilayer wiring layer.

  However, when the active electrode is disposed near the upper surface of the multilayer wiring layer and the ground electrode is disposed inside the multilayer wiring layer, the active electrode and the ground electrode are not connected to the signal wiring inside the multilayer wiring layer. Since they are arranged close to each other, a parasitic capacitance is generated between them. The parasitic capacitance between the active electrode and the ground electrode is preferably as small as possible. Assuming that the dielectric constant of the insulating layer between the active electrode and the ground electrode is ε, the opposing area of both is S, and the distance between the two is d, the parasitic capacitance C between them is given by C = εS / d. . Therefore, the larger the distance between the active electrode and the ground electrode, the smaller the parasitic capacitance between them. For this reason, it is preferable to arrange the active electrode and the ground electrode as far apart as possible. However, in order to separate the layer in which the active electrode is formed from the layer in which the ground electrode is formed, it is difficult to process the insulator between them for a long time. Therefore, there is a limit to manufacturing a thick insulator. On the other hand, inside the multilayer wiring layer, in the metal wiring layer between the layer where the active electrode is formed and the layer where the ground electrode is formed, a region consisting only of an insulator is created by removing all the conductor. It is also difficult to do. In this case, the density rule for designing the multilayer wiring layer is not satisfied, and the finished shape at the time of production is affected. As described above, it is difficult to simply dispose the active electrode and the ground electrode apart from each other.

  In the present specification, the above problem is solved. In this specification, in a semiconductor device having an active electrode disposed near the upper surface of a multilayer wiring layer and a ground electrode disposed inside the multilayer wiring layer, the active rule is satisfied while satisfying the density rule when forming the multilayer wiring layer. Provided is a technique capable of reducing a parasitic capacitance between an electrode and a ground electrode.

  A semiconductor device disclosed in this specification includes a semiconductor element layer, a multilayer wiring layer formed on the semiconductor element layer, an active electrode that is disposed near the top surface of the multilayer wiring layer, and receives an active potential. And a ground electrode disposed in the multilayer wiring layer and connected to the ground potential, and a floating electrode disposed between the active electrode and the ground electrode in the multilayer wiring layer.

  In the above configuration, the parasitic capacitance C between the active electrode and the ground electrode is a series connection of the parasitic capacitance C1 between the active electrode and the floating electrode and the parasitic capacitance C2 between the floating electrode and the ground electrode. In the following, for easy understanding, in the multilayer wiring layer, a floating electrode is formed immediately above the layer where the ground electrode is formed, and an active electrode is formed immediately above the layer where the floating electrode is formed. It is assumed that the opposing area of the active electrode and the floating electrode and the opposing area of the floating electrode and the ground electrode are the same. In this case, the parasitic capacitance C1 between the active electrode and the floating electrode is C1 = εS / d, where ε is the dielectric constant of the insulator between them, S is the opposing area of both, and d is the distance between the two. Given in. The parasitic capacitance C2 between the floating electrode and the ground electrode is C2 = εS / d, where ε is the dielectric constant of the insulator between them, S is the opposing area of both, and d is the distance between them. Given. Therefore, the parasitic capacitance C between the active electrode and the ground electrode is C = C1 × C2 / (C1 + C2) = εS / 2d, which is equivalent to the case where the insulator between the active electrode and the ground electrode is thickened. The parasitic capacitance can be halved compared to the case where the active electrode is formed immediately above the layer where the electrode is formed. In addition, in the above configuration, since the layer in which the floating electrode is formed is disposed between the layer in which the active electrode is formed and the layer in which the ground electrode is formed, the multilayer wiring layer is formed. Can meet the density rules. According to said structure, the electrostatic capacitance between an active electrode and a ground electrode can be reduced, satisfy | filling the density rule of a multilayer wiring layer. In the above configuration, the active electrode may be formed on the uppermost layer inside the multilayer wiring layer, or may be formed by laminating on the upper surface of the multilayer wiring layer after the multilayer wiring layer. May be. When the active electrode is formed outside the multilayer wiring layer, the conductor inside the multilayer wiring layer can be used for other signal wirings. In addition, the active electrode can be designed without being bound by the LSI design rules.

  The semiconductor device described above can be configured to further include a MEMS structure disposed to face the upper surface of the multilayer wiring layer.

  The semiconductor device described above deforms the MEMS structure by applying an electrostatic attractive force between the active electrode and the MEMS structure, or detects the deformation of the MEMS structure from a change in capacitance between the active electrode and the MEMS structure. A MEMS-LSI integrated device can be obtained. In the former, the semiconductor device realizes a function as an actuator, and in the latter, the semiconductor device realizes a function as a sensor. In this case, the parasitic capacitance between the active electrode and the ground electrode is the parasitic capacitance of the sensor or actuator. When the semiconductor device is a sensor, the parasitic capacitance is preferably as small as possible in order to improve temperature characteristics such as zero point output and increase the ratio of sensor sensitivity to parasitic capacitance. According to the above configuration, since the floating electrode is disposed between the active electrode and the ground electrode, the parasitic capacitance between the active electrode and the ground electrode can be reduced, and the parasitic capacitance of the sensor can be reduced. it can. For this reason, the accuracy of the sensor can be improved. When the semiconductor device is an actuator, it is preferable that the parasitic capacitance is as small as possible in order to reduce the drive load. According to the above configuration, since the floating electrode is disposed between the active electrode and the ground electrode, the parasitic capacitance between the active electrode and the ground electrode can be reduced, and the parasitic capacitance of the actuator can be reduced. it can. For this reason, the drive load of the actuator can be reduced.

  The above semiconductor device can be configured such that the MEMS structure is connected to a ground potential.

  In the above configuration, since the MEMS structure is maintained at the ground potential, the MEMS structure serves as an electrostatic shield, and the active electrode of the multilayer wiring layer, the signal wiring inside the multilayer wiring layer, and the semiconductor element of the semiconductor element layer are connected to the semiconductor element. The influence of external noise can be reduced.

  In the semiconductor device described above, a plurality of active electrodes separated from each other are arranged near the upper surface of the multilayer wiring layer, and a plurality of floating electrodes separated from each other are arranged corresponding to each active electrode. It can be constituted as follows.

  When a plurality of active electrodes separated from each other are arranged, if a single floating electrode is arranged, crosstalk between one active electrode and the other active electrode is caused via the floating electrode. May occur. According to the above configuration, since the plurality of floating electrodes separated from each other are arranged corresponding to the plurality of active electrodes separated from each other, between one active electrode and the other active electrode, Generation of crosstalk through the floating electrode can be suppressed. The operation can be further stabilized when the semiconductor device is a differential capacitance detection type sensor for improving detection performance or an actuator having a plurality of active electrodes.

  The above semiconductor device can be configured such that the floating electrode has substantially the same shape as the active electrode when the semiconductor device is viewed from above.

  According to the above configuration, since the floating electrode is not formed to be larger than necessary, a signal wiring having other functions such as a power source can be produced in the layer for producing the floating electrode, and the LSI can be freely designed. The degree is improved.

  The semiconductor device can be configured to include a portion where the ground electrode is not covered with the active electrode when the semiconductor device is viewed from above.

  According to said structure, the influence which the leakage electric field from an active electrode exerts on the signal wiring inside a multilayer wiring layer and the semiconductor element of a semiconductor element layer can be reduced reliably.

  The semiconductor device can be configured such that a plurality of floating electrodes are arranged in a stripe shape, a mesh shape, or an island shape when the semiconductor device is viewed from above.

  In order to reduce the parasitic capacitance between the active electrode and the ground electrode, the floating electrode is formed by reducing the area of the floating electrode as much as possible while satisfying the density rule when forming the multilayer wiring layer. It is preferable to increase the area of the insulating layer of the layer as much as possible. According to the above configuration, the parasitic capacitance between the active electrode and the ground electrode can be further reduced.

  The semiconductor device further includes a driven shield electrode disposed between the active electrode and the floating electrode inside the multilayer wiring layer, and the driven shield electrode receives a potential that follows the active potential of the active electrode. It can be comprised so that it may be constituted.

  According to the above configuration, the parasitic capacitance between the active electrode and other components (for example, the ground electrode) can be further reduced by the driven shield electrode. At this time, the periodic potential change of the driven shield electrode does not affect the signal wiring of the lower multilayer wiring layer and the semiconductor element of the semiconductor element layer by the ground electrode below the driven shield electrode. Moreover, according to said structure, the floating capacitance can reduce the parasitic capacitance between a driven shield electrode and a ground electrode, and can reduce the load which drives a driven shield electrode.

  In the semiconductor device described above, it is preferable that the shape and area of the floating electrode be limited to the range covered by the electric lines of force of the active electrode, that is, the floating electrode should have substantially the same shape as the active electrode. In this way, wiring having other functions (for example, signal wiring, ground potential wiring, power supply potential wiring, etc.) can be routed in the multilayer wiring layer for producing the floating electrode, and the LSI wiring layout can be freely designed. The degree increases.

  In the above semiconductor device, a plurality of floating electrodes can be arranged between the active electrode (or driven shield electrode) and the ground electrode. In this case, the parasitic capacitance can be further reduced as compared with the case where one floating electrode is arranged.

1 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 2 of Example 1. FIG. It is the cross-sectional view which looked at the MEMS board | substrate 12 of FIG. 1 from the II-II surface. FIG. 3 is a top view of the LSI substrate 8 of FIG. 1 viewed from the III-III plane. 3 is a circuit diagram of a CV conversion circuit 38 used in the semiconductor device 2 of Embodiment 1. FIG. 3 is a circuit diagram of a CF conversion circuit 54 used in the semiconductor device 2 of Example 1. FIG. 3 is a circuit diagram of a CF conversion circuit 64 used in the semiconductor device 2 of Example 1. FIG. 7 is a plan view showing a modification of the floating electrode 32 of the semiconductor device 2 of Example 1. FIG. 6 is a plan view showing another modification of the floating electrode 32 of the semiconductor device 2 of Example 1. FIG. 7 is a plan view showing still another modification of the floating electrode 32 of the semiconductor device 2 of Example 1. FIG. 6 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 2 according to a modification of Example 1. FIG. FIG. 6 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 102 of Example 2. FIG. 6 is a circuit diagram illustrating functions of a driven shield electrode 104 of a semiconductor device 102 according to a second embodiment. FIG. 6 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 202 of Example 3. FIG. 14 is a top view of the LSI substrate 8 of FIG. 13 as viewed from the XIV-XIV plane. FIG. 10 is a longitudinal sectional view illustrating a schematic configuration of a semiconductor device 202 according to a modification of Example 3; FIG. 16 is a top view of the LSI substrate 8 of FIG. 15 viewed from the XVI-XVI plane. FIG. 10 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 202 according to another modification of the third embodiment. FIG. 10 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 302 of Example 4. It is the cross-sectional view which looked at the MEMS board | substrate 12 of FIG. 18 from the XIX-XIX surface. FIG. 19 is a top view of the LSI substrate 8 of FIG. 18 viewed from the XX-XX plane. FIG. 10 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 402 of Example 5. FIG. 22 is a cross-sectional view of the first conductive layer 404 of FIG. 21 as viewed from the XXII-XXII plane. FIG. 22 is a cross-sectional view of the second conductive layer 408 of FIG. 21 as viewed from the XXIII-XXIII plane. FIG. 22 is a top view of the LSI substrate 8 of FIG. 21 as viewed from the XXIV-XXIV plane. FIG. 10 is a longitudinal sectional view showing an example of the operation of a semiconductor device 402 of Example 5. FIG. 10 is a longitudinal sectional view illustrating another example of the operation of the semiconductor device 402 according to the fifth embodiment. FIG. 10 is a longitudinal sectional view showing a schematic configuration of a semiconductor device 502 of Example 6. It is the cross-sectional view which looked at the XXVIII-XXVIII surface about the MEMS board | substrate 12 of FIG. FIG. 28 is a top view of the LSI substrate 8 of FIG. 27 viewed from the XXIX-XXIX plane. It is a longitudinal cross-sectional view which shows the schematic structure of the semiconductor device 2 of a reference example.

Example 1
FIG. 1 is a longitudinal sectional view schematically showing the configuration of the semiconductor device 2 of this embodiment. The semiconductor device 2 includes an LSI substrate 8 including a semiconductor element layer 4 and a multilayer wiring layer 6, and a MEMS substrate 12 including a MEMS structure 10. The semiconductor element layer 4 is made of, for example, silicon. The multilayer wiring layer 6 is formed on the semiconductor element layer 4. The MEMS substrate 12 is made of, for example, silicon provided with conductivity. The MEMS substrate 12 is disposed above the LSI substrate 8 so as to face the multilayer wiring layer 6.

  A plurality of semiconductor elements 14 such as diodes and transistors are formed on the upper surface of the semiconductor element layer 4 (the upper surface in FIG. 1). The semiconductor element layer 4 is formed with a plurality of through electrodes 16 that penetrate the semiconductor element layer 4 from the upper surface to the lower surface (the lower surface in FIG. 1). Each through electrode 16 forms a columnar trench that penetrates the semiconductor element layer 4 from the upper surface to the lower surface, covers the side surface of the trench with an insulating film, and is provided with a conductive material (for example, a metal such as copper or conductivity). It is formed by filling polysilicon or the like. Thus, even if the upper portion of the LSI substrate 8 is covered with the MEMS substrate 12, power can be supplied and signals can be taken out from the back surface of the LSI substrate 8.

  The multilayer wiring layer 6 is formed on the upper surface of the semiconductor element layer 4 by alternately repeating the lamination and selective removal of the insulator 18 and the lamination of the conductor 20. The insulator 18 is, for example, silicon oxide. The conductor 20 is a metal such as copper or aluminum. The uppermost portion of the multilayer wiring layer 6 is covered with an insulator 18, and a plurality of pads 22 made of a conductive material (for example, a metal such as aluminum) are formed on the upper surface thereof. A signal wiring 21 is formed by the conductor 20 inside the multilayer wiring layer 6. Each signal line 21 connects each semiconductor element 14, each through electrode 16, and each pad 22 to constitute an LSI.

  The MEMS structure 10 of the MEMS substrate 12 is, for example, a diaphragm including a thin film portion 24 and a support portion 26. As shown in FIG. 2, when the semiconductor device 2 is viewed from above, the thin film portion 24 is formed in a square shape, and the support portion 26 is formed in a square frame shape surrounding the thin film portion 24. The thin film portion 24 and the support portion 26 are formed by selectively removing the MEMS substrate 12 from the upper surface (the upper surface in FIG. 1). The thin film portion 24 functions as a movable electrode of the MEMS structure 10. The thin film portion 24 and the support portion 26 are integrally formed without a seam, and are maintained at the same potential. As shown in FIG. 1, the support portion 26 is connected to the ground potential. Accordingly, both the thin film portion 24 and the support portion 26 of the MEMS structure 10 are maintained at the ground potential. Therefore, the MEMS structure 10 serves as an electrostatic shield, and the influence of external noise on the signal wiring in the LSI substrate 8, the semiconductor element 14, and the active electrode 28 described later can be reduced. A MEMS-LSI integrated device that is less affected by external noise can be obtained.

  An active electrode 28 is formed on the uppermost conductor 20 in the multilayer wiring layer 6 of the LSI substrate 8. As shown in FIG. 3, when the semiconductor device 2 is viewed from above, the active electrode 28 is formed in a square shape. As shown in FIG. 1, the active electrode 28 is disposed to face the thin film portion 24 of the MEMS structure 10. The active electrode 28 is electrically connected to the corresponding semiconductor element 14 through an active potential wiring 23 formed from the conductor 20 of the multilayer wiring layer 6.

  In the multilayer wiring layer 6 of the LSI substrate 8, a ground electrode 30 made of the conductor 20 is disposed in a layer below the active electrode 28. As shown in FIG. 3, when the semiconductor device 2 is viewed from above, the ground electrode 30 is formed in a square shape that is substantially the same as or slightly larger than the active electrode 28. When the ground electrode 30 is formed slightly larger than the active electrode 28, the ground electrode 30 includes a portion that is not covered by the active electrode 28 when the semiconductor device 2 is viewed from above. As shown in FIG. 1, the ground electrode 30 is disposed so as to block between the active electrode 28 and the signal wiring 21 of the multilayer wiring layer 6 and the semiconductor element 14 of the semiconductor element layer 4. The ground electrode 30 is electrically connected to the corresponding semiconductor element 14 via a ground potential wiring 25 formed from the conductor 20 inside the multilayer wiring layer 6.

  In the multilayer wiring layer 6 of the LSI substrate 8, a floating electrode 32 made of the conductor 20 is arranged in a layer below the active electrode 28 and above the ground electrode 30. As shown in FIG. 3, when the semiconductor device 2 is viewed from above, the floating electrode 32 is formed in a square shape that is substantially the same as or slightly larger than the active electrode 28. When the floating electrode 32 is formed slightly larger than the active electrode 28, the floating electrode 32 includes a portion that is not covered by the active electrode 28 when the semiconductor device 2 is viewed from above. As shown in FIG. 1, the floating electrode 32 is disposed so as to block between the active electrode 28 and the ground electrode 30. Unlike the active electrode 28 and the ground electrode 30, the floating electrode 32 is not electrically connected to any semiconductor element 14.

  A bonding member 34 is formed on the upper surface of the multilayer wiring layer 6 of the LSI substrate 8, and a bonding member 36 corresponding to the bonding member 34 is formed on the lower surface of the MEMS substrate 12. By joining the joining member 34 and the joining member 36, the LSI substrate 8 and the MEMS substrate 12 are fixed to each other. As shown in FIG. 3, the joining member 34 is formed in a square frame shape. As shown in FIG. 1, the bonding member 34 and the bonding member 36 are arranged so as to surround the thin film portion 24 of the MEMS structure 10, the pad 22 of the LSI substrate 8, the active electrode 28, and the like.

  The operation of the semiconductor device 2 will be described. When the thin film portion 24 of the MEMS structure 10 is deformed by receiving pressure or force from the outside, the distance between the thin film portion 24 that is a movable electrode and the active electrode 28 that is a fixed electrode is changed. The capacitance between the active electrodes 28 changes. By detecting this change in capacitance, the deformation amount of the thin film portion 24 can be detected.

  The capacitance between the thin film portion 24 and the active electrode 28 can be detected by various methods. For example, the capacitance between the thin film portion 24 and the active electrode 28 may be detected using the CV conversion circuit 38 shown in FIG. In the CV conversion circuit 38, the capacitance between the thin film portion 24 to be detected and the active electrode 28 is represented by a capacitor 40. The electrode corresponding to the thin film portion 24 of the capacitor 40 is connected to the ground potential. The electrode corresponding to the active electrode 28 of the capacitor 40 is connected to the power supply potential via the switch 42. Furthermore, an electrode corresponding to the active electrode 28 of the capacitor 40 is connected to the inverting input of the operational amplifier 48 through a series circuit of a switch 44 and a resistor 46. The non-inverting input of the operational amplifier 48 is connected to the ground potential. The output of the operational amplifier 48 is connected to the inverting input of the operational amplifier 48 through a parallel circuit of the switch 50 and the capacitor 52. In the CV conversion circuit 38 shown in FIG. 4, the capacitance of the capacitor 40 can be calculated from the amplitude of the output voltage of the operational amplifier 48 when the switch 42 and the switch 44 are repeatedly turned on / off.

  Or you may detect the electrostatic capacitance between the thin film part 24 and the active electrode 28 using CF conversion circuit 54 shown in FIG. In the CF conversion circuit 54, the capacitance between the thin film portion 24 to be detected and the active electrode 28 is represented by a capacitor 56. The electrode corresponding to the thin film portion 24 of the capacitor 56 is connected to the ground potential. The electrode corresponding to the active electrode 28 of the capacitor 56 is connected to the input of the Schmitt trigger circuit 58. The output of the Schmitt trigger circuit 58 is connected to the input of the buffer circuit 60 and is also connected to the input of the Schmitt trigger circuit 58 via the resistor 62. In the CF conversion circuit 54 shown in FIG. 5, the capacitance of the capacitor 56 can be calculated from the frequency of the output voltage of the buffer circuit 60.

  Or you may detect the electrostatic capacitance between the thin film part 24 and the active electrode 28 using CF conversion circuit 64 shown in FIG. In the CF conversion circuit 64, the capacitance between the thin film portion 24 to be detected and the active electrode 28 is represented by a capacitor 66. The electrode corresponding to the thin film portion 24 of the capacitor 66 is connected to the ground potential. The electrode corresponding to the active electrode 28 of the capacitor 66 is connected to the input of the Schmitt trigger circuit 68. A switch 70 is connected to an electrode corresponding to the active electrode 28 of the capacitor 66. The switch 70 is switched between a state where the electrode corresponding to the active electrode 28 of the capacitor 66 is connected to the power supply potential via the constant current source 72 and a state where the electrode is connected to the ground potential via the constant current source 74. Change. The output of the Schmitt trigger circuit 68 is connected to the input of the buffer circuit 76. The output of the buffer circuit 76 is connected to the input of the buffer circuit 78. The output of the buffer circuit 78 is connected to the input of the buffer circuit 80 and to the control input of the switch 70. The output of the buffer circuit 80 is connected to the input of the buffer circuit 82. In the CF conversion circuit 64 shown in FIG. 6, the capacitance of the capacitor 66 can be calculated from the frequency of the output voltage of the buffer circuit 82.

  As described above, when detecting the capacitance between the thin film portion 24 and the active electrode 28, the potential of the active electrode 28 (hereinafter also referred to as the active potential) periodically varies. When the signal wiring 21 of the multilayer wiring layer 6 and the semiconductor element 14 of the semiconductor element layer 4 are exposed to noise generated by the fluctuation of the active potential in the active electrode 28, the operation of the semiconductor device 2 is adversely affected. In the semiconductor device 2 of the present embodiment, the ground electrode 30 is disposed so as to shield the active electrode 28 from the signal wiring 21 and the semiconductor element 14. By adopting such a configuration, it is possible to suppress the fluctuation of the active potential in the active electrode 28 from affecting the operations of the signal wiring 21 and the semiconductor element 14. Further, when the ground electrode is provided with a portion that is not covered with the active electrode when the semiconductor device is viewed from above, the leakage electric field of the active electrode may affect the operation of the signal wiring 21 and the semiconductor element 14. Can be suppressed.

  In the semiconductor device 2 described above, since the active electrode 28 and the ground electrode 30 are disposed to face each other, a parasitic capacitance is generated between the active electrode 28 and the ground electrode 30. Parasitic capacitance is related to the zero point of the sensor, and a sensor with a large parasitic capacitance also has a large zero point drift due to temperature fluctuations, resulting in a decrease in accuracy. Furthermore, in order to accurately detect the change in capacitance (sensor sensitivity) between the active electrode 28 and the thin film portion 24, it is necessary to increase the sensor sensitivity / parasitic capacitance. Therefore, in order to accurately detect physical quantities such as pressure and force, it is preferable that the parasitic capacitance between the active electrode 28 and the ground electrode 30 be as small as possible. In order to reduce the parasitic capacitance between the active electrode 28 and the ground electrode 30, it is preferable to dispose the distance as far as possible. However, if the thickness of the insulator 18 between the active electrode 28 and the ground electrode 30 is increased in the multilayer wiring layer 6, processing becomes difficult and a long processing time is required. Also, as shown in FIG. 30, when the conductor 20 is completely removed from the multilayer wiring layer 6 between the active electrode 28 and the ground electrode 30 and a layer made of only the insulator 18 is disposed, the multilayer wiring layer 6 is designed. It does not meet the density rules, and it makes processing difficult and affects the finished shape at the time of production.

  Therefore, in the semiconductor device 2 of the present embodiment, the floating electrode 32 is disposed so as to block between the active electrode 28 and the ground electrode 30. By adopting such a configuration, the parasitic capacitance can be reduced in the same manner as when the thickness of the insulator between the active electrode 28 and the ground electrode 30 is increased while satisfying the density rule of the multilayer wiring layer 6. . Further, by making the floating electrode 32 and the active electrode 28 have substantially the same shape, wiring having other functions such as signal wiring and power supply can be manufactured in the layer for forming the floating electrode 32, and the LSI design freedom is improved. The degree is improved.

  In the semiconductor device 2 of the present embodiment, the MEMS structure 10 is maintained at the ground potential. As a result, the influence of external noise can be reduced. In the semiconductor device 2 of this embodiment, the ground electrode 30 is disposed below the active electrode 28. As a result, it is possible to reduce the influence of fluctuations in the active potential at the active electrode 28 on the signal wiring 21 in the multilayer wiring layer 6 and the semiconductor element 14 in the semiconductor element layer 4. Further, in the semiconductor device 2 of the present embodiment, the floating electrode 32 is disposed between the active electrode 28 and the ground electrode 30. Thereby, the parasitic capacitance between the active electrode 28 and the ground electrode 30 can be reduced, the zero point drift due to temperature fluctuation can be reduced, and the sensor sensitivity / parasitic capacitance can be increased. A highly accurate MEMS-LSI integrated device can be realized.

(Modification of Example 1)
In the semiconductor device 2 shown in FIG. 1, the floating electrode 32 is constituted by the conductor 20 formed in a square shape when the semiconductor device 2 is viewed from above. Unlike this, for example, as shown in FIG. 7, the floating electrode 32 may be composed of a plurality of conductors 20 arranged in parallel stripes when the semiconductor device 2 is viewed from above. . Alternatively, as shown in FIG. 8, the floating electrode 32 may be configured by the conductor 20 formed in a mesh shape when the semiconductor device 2 is viewed from above. Alternatively, as shown in FIG. 9, the floating electrode 32 may be configured by a plurality of conductors 20 arranged in a rectangular island shape when the semiconductor device 2 is viewed from above. By reducing the area of the floating electrode as much as possible within the range satisfying the density rule, the area of the insulator can be increased as much as possible, and the parasitic capacitance can be further reduced.

  In the semiconductor device 2 of FIG. 1, the floating electrode 32 is constituted by the conductor 20 formed in a single layer of the multilayer wiring layer 6. Unlike this, for example, as shown in FIG. 10, the floating electrode 32 may be composed of a conductor 20 formed in a plurality of layers of the multilayer wiring layer 6. By constituting the floating electrode 32 with the conductor 20 formed in a plurality of layers of the multilayer wiring layer 6, it becomes equivalent to the case where the insulator between the active electrode 28 and the ground electrode 30 is made thicker. The parasitic capacitance between the active electrode 28 and the ground electrode 30 can be further reduced. For this reason, it can be set as a more accurate sensor.

(Example 2)
Hereinafter, the difference of the semiconductor device 102 of the second embodiment from the semiconductor device 2 of the first embodiment will be described with reference to FIG. Note that the semiconductor device 102 of the second embodiment will not be described in detail with respect to the points common to the semiconductor device 2 of the first embodiment.

  In the semiconductor device 102 of the present embodiment, the driven shield electrode 104 made of the conductor 20 is provided in a layer below the active electrode 28 and above the floating electrode 32 in the multilayer wiring layer 6 of the LSI substrate 8. Is arranged. The driven shield electrode 104 is formed in a square shape having substantially the same size as the floating electrode 32 when the semiconductor device 102 is viewed from above. The driven shield electrode 104 is disposed so as to shield between the active electrode 28 and the ground electrode 30. The driven shield electrode 104 is electrically connected to the corresponding semiconductor element 14 via the drive wiring 27 made of the conductor 20 inside the multilayer wiring layer 6.

  FIG. 12 shows a circuit configuration of the active electrode 28, the driven shield electrode 104, the floating electrode 32, and the ground electrode 30. An active potential is input to the active electrode 28. The ground electrode 30 is connected to the ground potential. The driven shield electrode 104 is connected to the inverting input of the comparator 106. The output of the comparator 106 is connected to the inverting input of the comparator 106. The non-inverting input of the comparator 106 is connected to the active electrode 28. The LSI substrate 8 of the semiconductor device 102 is configured so as to be such a circuit.

  In the circuit configuration shown in FIG. 12, when the active potential of the active electrode 28 fluctuates, the potential of the driven shield electrode 104 fluctuates following the active potential by the comparator 106, and the potential difference between the active electrode 28 and the driven shield electrode 104. Is maintained at almost zero. Thereby, the parasitic capacitance between the active electrode 28 and other components (for example, the ground electrode 30) is reduced. Thereby, when integrated with the MEMS structure 10, the zero point drift due to temperature fluctuation can be reduced, and the sensor sensitivity / parasitic capacitance can be increased. In addition, since the floating electrode 32 is disposed between the driven shield electrode 104 and the ground electrode 30, the parasitic capacitance between the driven shield electrode 104 and the ground electrode 30 is reduced, and the drive load of the driven shield electrode 104 is reduced. can do.

(Example 3)
Hereinafter, with reference to FIGS. 13 and 14, the difference between the semiconductor device 202 of the third embodiment and the semiconductor device 2 of the first embodiment will be described. The semiconductor device 202 according to the third embodiment will not be described in detail with respect to the points common to the semiconductor device 2 according to the first embodiment.

  In the semiconductor device 202, the active electrode 204 is disposed not on the inside of the multilayer wiring layer 6 of the LSI substrate 8 but on the upper surface of the multilayer wiring layer 6. The active electrode 204 is formed on the upper surface of the multilayer wiring layer 6 by laminating and selectively removing the conductor 206 after the LSI is completed. The conductor 206 is made of a metal such as aluminum, titanium, or gold. The active electrode 204 is connected to the pad 22 formed on the upper surface of the multilayer wiring layer 6 via the wiring 208 made of a conductive material (for example, a metal such as aluminum, titanium, or gold) formed on the upper surface of the multilayer wiring layer 6. Electrically connected. That is, the active electrode 204 is electrically connected to the corresponding semiconductor element 14 via the wiring 208 on the upper side of the multilayer wiring layer 6, the pad 22, and the active potential wiring 23 inside the multilayer wiring layer 6.

  In the semiconductor device 202, the floating electrode 32 is configured by the conductor 20 disposed at the top in the multilayer wiring layer 6. In the semiconductor device 202, the ground electrode 30 is constituted by the conductor 20 disposed immediately below the floating electrode 32.

  In the semiconductor device 202 of the present embodiment, the ground electrode 30 is disposed so as to shield the active electrode 204 from the signal wiring 21 of the multilayer wiring layer 6 and the semiconductor element 14 of the semiconductor element layer 4. With such a configuration, it is possible to prevent the fluctuation of the active potential in the active electrode 204 from affecting the operation of the signal wiring 21 and the semiconductor element 14.

  In the semiconductor device 202 of the present embodiment, the floating electrode 32 is disposed so as to block between the active electrode 204 and the ground electrode 30. With such a configuration, the parasitic capacitance between the active electrode 204 and the ground electrode 30 can be reduced while satisfying the density rule of the multilayer wiring layer 6. Therefore, a MEMS-LSI integrated device with small parasitic capacitance and good sensor accuracy can be realized. Further, since the active electrode 204 is disposed outside the multilayer wiring layer 6, it is possible to use the conductor 20 for one layer of the multilayer wiring layer 6 as the signal wiring 21 or the like as compared with the first and second embodiments. it can. Furthermore, the active electrode 204 can be designed without being influenced by a design rule such as a density rule. Further, by adjusting the thickness of the active electrode 204, the distance between the thin film portion 24 and the active electrode 204 can be adjusted without changing the height of the bonding member 34 and the bonding member 36. Sensor sensitivity and the like can be designed freely.

(Modification of Example 3)
In the semiconductor device 202 shown in FIGS. 13 and 14, the MEMS substrate 12 is connected to the ground potential without passing through the conductor 20 of the multilayer wiring layer 6. Unlike this, for example, as shown in FIGS. 15 and 16, the MEMS substrate 12 includes a ground potential wiring 25 made of a conductor 20 formed in the multilayer wiring layer 6, a pad 22, and the multilayer wiring layer 6. A wiring 210 made of a conductive material (for example, a metal such as aluminum, titanium, or gold) and a bonding member 34 made of a conductive material (for example, a metal such as copper or gold or an alloy such as Cn—Sn); The bonding member 36 may be configured to be electrically connected to the ground potential provided from the semiconductor element layer 4. By doing so, the ground potential can be applied to the MEMS structure 10 without connecting the MEMS structure 10 to the ground potential externally. Further, since the ground potential levels of the LSI substrate 8 and the MEMS substrate 12 are close to each other, more stable sensing can be realized. A MEMS-LSI integrated device with better performance can be realized.

  In the semiconductor device 202 shown in FIGS. 15 and 16, the active electrode 204 and the wirings 208 and 210 are directly laminated on the upper surface of the multilayer wiring layer 6. Unlike this, for example, as shown in FIG. 17, another insulating layer 212 is laminated on the upper surface of the multilayer wiring layer 6, and the active electrode 204 and the wirings 208 and 210 are laminated on the upper surface of the insulating layer 212. May be. The insulating layer 212 is, for example, silicon oxide. The insulating layer 212 is laminated on the upper surface of the multilayer wiring layer 6 at a location where the pad 22 is not formed. Although the film thickness of the insulating layer 212 is limited by the warp of the LSI substrate 8 and the film thickness due to the manufacturing process, the active electrode 204 and the ground electrode 30 can be further separated by such a configuration. In combination with the effect of the floating electrode 32, the parasitic capacitance between the active electrode 204 and the ground electrode 30 can be further reduced. For this reason, it is possible to realize a MEMS-LSI integrated device with a smaller parasitic capacitance, better temperature characteristics, etc., and excellent accuracy.

Example 4
Hereinafter, the difference of the semiconductor device 302 of the fourth embodiment from the semiconductor device 2 of the first embodiment will be described with reference to FIGS. The semiconductor device 302 according to the fourth embodiment will not be described in detail with respect to the points common to the semiconductor device 2 according to the first embodiment.

  In the semiconductor device 302 of the present embodiment, the MEMS structure 10 of the MEMS substrate 12 is composed of a movable electrode portion composed of a thin film portion 24 that is easily movable and a reference electrode portion 29 that is difficult to move. Further, in the semiconductor device 302 of this embodiment, instead of forming a single active electrode inside the multilayer wiring layer 6, a first active electrode 304 disposed so as to face the thin film portion 24, and a reference electrode portion A second active electrode 306 is formed so as to be opposed to 29. The first active electrode 304 and the second active electrode 306 are both composed of the conductor 20 formed on the uppermost part inside the multilayer wiring layer 6 and are arranged separately from each other. Further, in the semiconductor device 302 of the present embodiment, instead of forming a single floating electrode inside the multilayer wiring layer 6, the first floating electrode is arranged so as to block between the first active electrode 304 and the ground electrode 30. An electrode 308 and a second floating electrode 310 disposed so as to block between the second active electrode 306 and the ground electrode 30 are formed. Both the first floating electrode 308 and the second floating electrode 310 are composed of the conductor 20 formed in the same layer inside the multilayer wiring layer 6 and are arranged separately from each other.

  In the semiconductor device 302 of this embodiment, the capacitance detected between the reference electrode portion 29 and the second active electrode 306 is subtracted from the capacitance detected between the thin film portion 24 and the first active electrode 304. As a result, the parasitic capacitances are canceled out, and it becomes easy to extract only the amount of change in capacitance between the thin film portion 24 and the first active electrode 304 due to the deformation of the thin film portion 24. Further, even if a difference occurs in the parasitic capacitance between the first active electrode 304 and the ground electrode 30 and the parasitic capacitance between the second active electrode 306 and the ground electrode 30 due to the warpage of the substrate due to temperature variation, etc., the first floating Since the respective parasitic capacitances are reduced by the electrode 308 and the second floating electrode 310, the difference between the parasitic capacitances can be reduced and the influence can be reduced.

  In the configuration in which the first active electrode 304 and the second active electrode 306 are respectively disposed as described above, if the floating electrode disposed between the ground electrode 30 is a single one, the first active electrode is interposed via the floating electrode. Crosstalk occurs between the electrode 304 and the second active electrode 306. Therefore, in the semiconductor device 302 of this embodiment, the first floating electrode 308 corresponding to the first active electrode 304 and the second floating electrode 310 corresponding to the second active electrode 306 are separately arranged. With such a configuration, it is possible to suppress the occurrence of crosstalk between the first active electrode 304 and the second active electrode 306 via the floating electrode. Further, in the semiconductor device 302 of this embodiment, the reference electrode unit 29 is formed in the MEMS structure 10, and the capacitance detected with respect to the reference electrode unit 29 from the capacitance detected with respect to the thin film unit 24 that is the movable electrode unit. The amount of change in capacitance can be mainly detected by subtracting. Even if a capacitance difference occurs due to warpage of the LSI substrate 8 or the like, the parasitic capacitance is reduced by the first floating electrode 308 and the second floating electrode 310, so that the difference in parasitic capacitance between the two is reduced. And the influence can be reduced. Furthermore, by dividing the floating electrode into the first floating electrode 308 and the second floating electrode 310 inside the multilayer wiring layer 6, the occurrence of crosstalk can be suppressed. As described above, a more accurate MEMS-LSI integrated device can be realized.

(Example 5)
Hereinafter, the difference of the semiconductor device 402 of the fifth embodiment from the semiconductor device 2 of the first embodiment will be described with reference to FIGS. The semiconductor device 402 according to the fifth embodiment will not be described in detail with respect to the points common to the semiconductor device 2 according to the first embodiment.

  In the semiconductor device 402 of this embodiment, the MEMS substrate 12 includes a first conductive layer 404 made of conductive silicon, an insulating layer 406 made of insulating silicon oxide, and a second conductive layer 408 made of conductive silicon. Are stacked in order from an SOI (Silicon on Insulator) substrate. A MEMS structure 10 as described below is formed on the MEMS substrate 12.

  The first conductive layer 404 is provided with a protrusion 410, a thin film portion 412, and a support portion 414. When the semiconductor device 402 is viewed from above, the protrusion 410 is formed in a square shape, the thin film portion 412 is formed in a square frame shape surrounding the protrusion 410, and the support portion 414 is the thin film portion 412. Is formed in a square frame shape. The protruding portion 410, the thin film portion 412 and the supporting portion 414 are formed by selectively removing the first conductive layer 404 from the upper surface (the upper surface in FIG. 21). The protruding portion 410, the thin film portion 412 and the support portion 414 are integrally formed without a joint, and are maintained at the same potential. The support part 414 is connected to the ground potential. Therefore, all of the protrusion 410, the thin film 412 and the support 414 are maintained at the ground potential.

  As shown in FIG. 23, the movable plate 416, four seesaw electrodes 418, 420, 422, and 424, and a support portion 426 are formed on the second conductive layer 408. As shown in FIG. 21, the movable plate 416 is fixed to the protruding portion 410 of the first conductive layer 404 via the insulating layer 406. The seesaw electrodes 418, 420, 422, 424 have the insulating layer 406 between the second conductive layers 408 removed, and rotate torsion beams 418b, 418c, 420b, 420c, 422b, 422c, 424b, 424c, which will be described later. It can rotate as an axis. The support part 426 is fixed to the support part 414 of the first conductive layer 404 via the insulating layer 406.

  As shown in FIG. 23, the seesaw electrode 418 and the seesaw electrode 420 are disposed so as to sandwich the movable plate 416 in the X direction (left-right direction in FIG. 23). The seesaw electrode 418 and the movable plate 416 are connected by a support beam 418a along the X direction. The seesaw electrode 418 is coupled to the support portion 426 via two torsion beams 418b and 418c along the Y direction (the vertical direction in FIG. 23). The two torsion beams 418b and 418c are arranged so as to sandwich the seesaw electrode 418 in the Y direction. The seesaw electrode 420 and the movable plate 416 are connected by a support beam 420a along the X direction. The seesaw electrode 420 is connected to the support portion 426 via two torsion beams 420b and 420c along the Y direction. The two torsion beams 420b and 420c are arranged so as to sandwich the seesaw electrode 420 in the Y direction.

  The seesaw electrode 422 and the seesaw electrode 424 are disposed so as to sandwich the movable plate 416 in the Y direction. The seesaw electrode 422 and the movable plate 416 are connected by a support beam 422a along the Y direction. The seesaw electrode 422 is connected to the support portion 426 via two torsion beams 422b and 422c along the X direction. The two torsion beams 422b and 422c are arranged so as to sandwich the seesaw electrode 422 in the X direction. The seesaw electrode 424 and the movable plate 416 are connected by a support beam 424a along the Y direction. The seesaw electrode 424 is connected to the support portion 426 via two torsion beams 424b and 424c along the X direction. The two torsion beams 424b and 424c are arranged so as to sandwich the seesaw electrode 424 in the X direction.

  The movable plate 416, the seesaw electrodes 418, 420, 422, 424, the support portion 426, the support beams 418a, 420a, 422a, 424a, the torsion beams 418b, 418c, 420b, 420c, 422b, 422c, 424b, 424c are , Are integrally formed without a seam and maintained at the same potential. In addition, the support portion 426 is electrically connected to the support portion 414 of the first conductive layer 404 through a through electrode 428 that penetrates the insulating layer 406. Therefore, the movable plate 416, the seesaw electrodes 418, 420, 422, 424, the support portion 426, the support beams 418a, 420a, 422a, 424a, the torsion beams 418b, 418c, 420b, 420c, 422b, 422c, 424b. All of 424c are maintained at the ground potential.

  In the semiconductor device 402 of this embodiment, the seesaw electrodes 418 and 420 tilt around the Y axis, and the seesaw electrodes 422 and 424 tilt around the X axis. Further, the movable plate 416 is displaced and tilted following the displacement and tilt of the lower surface (the lower surface in FIG. 21) of the protrusion 410. Since the movable plate 416 and the seesaw electrodes 418, 420, 422, 424 are connected by the support beams 418a, 420a, 422a, 424a, the seesaw electrodes 418, 420, 422, 424 tilts.

  For example, as shown in FIG. 25, when a force Fz in the Z direction (vertical direction in FIG. 25) acts on the upper surface (upper surface in FIG. 25) of the protrusion 410, the movable plate 416 is displaced in the Z direction. Accordingly, the seesaw electrode 418 tilts in the positive direction around the Y axis, and the seesaw electrode 420 tilts in the negative direction around the Y axis. Similarly, the seesaw electrode 422 tilts in the positive direction around the X axis, and the seesaw electrode 424 tilts in the negative direction around the X axis.

  For example, as shown in FIG. 26, when the force Fx in the X direction acts on the upper surface of the protrusion 410 (the upper surface in FIG. 26), the movable plate 416 tilts in the positive direction around the Y axis. Accordingly, the seesaw electrode 418 tilts in the negative direction around the Y axis, and the seesaw electrode 420 tilts in the negative direction around the Y axis. In this case, the seesaw electrodes 422 and 424 do not tilt.

  As described above, in the semiconductor device 402 of the present embodiment, the manner of tilting of the seesaw electrodes 418, 420, 422, 424 changes according to the direction of the force acting on the upper surface of the protrusion 410. Therefore, by detecting the tilts of the seesaw electrodes 418, 420, 422, and 424 and combining the detected amounts, the forces in the X, Y, and Z axis directions acting on the upper surface of the protrusion 410 can be detected. it can.

  In the semiconductor device 402 of the present embodiment, a first active electrode 430 a and a second active electrode 430 b are formed on the uppermost conductor 20 inside the multilayer wiring layer 6 corresponding to the seesaw electrode 418. The first active electrode 430a is disposed to face one end (the left end in FIG. 21) of the seesaw electrode 418. The second active electrode 430b is disposed to face the other end of the seesaw electrode 418 (the right end in FIG. 21). By subtracting the capacitance between the second active electrode 430b and the seesaw electrode 418 from the capacitance between the first active electrode 430a and the seesaw electrode 418, the tilt of the seesaw electrode 418 is detected by differential capacitance detection. be able to. In addition, a first floating electrode 432a is disposed between the first active electrode 430a and the ground electrode 30, and a second floating electrode 432b is disposed between the second active electrode 430b and the ground electrode 30. Yes. Thereby, the parasitic capacitance between the first active electrode 430a and the ground electrode 30 and the parasitic capacitance between the second active electrode 430b and the ground electrode 30 can be reduced.

  Similarly, in the semiconductor device 402 of the present embodiment, the first active electrode 434 a and the second active electrode 434 b are disposed on the uppermost conductor 20 inside the multilayer wiring layer 6 corresponding to the seesaw electrode 420. Yes. Further, a first floating electrode 436a and a second floating electrode 436b are arranged corresponding to the first active electrode 434a and the second active electrode 434b. Similarly, as shown in FIG. 24, a first active electrode 438 a and a second active electrode 438 b are arranged on the uppermost conductor 20 inside the multilayer wiring layer 6 corresponding to the seesaw electrode 422. Further, a first floating electrode 440a and a second floating electrode 440b are arranged corresponding to the first active electrode 438a and the second active electrode 438b. Further, a first active electrode 442 a and a second active electrode 442 b are arranged on the uppermost conductor 20 inside the multilayer wiring layer 6 corresponding to the seesaw electrode 424. Further, a first floating electrode 444a and a second floating electrode 444b are arranged corresponding to the first active electrode 442a and the second active electrode 442b. By adopting such a configuration, the tilt of the seesaw electrodes 420, 422, and 424 can be detected by differential capacitance detection, the parasitic capacitance between each first active electrode and the ground electrode 30, and each The parasitic capacitance between the second active electrode and the ground electrode 30 can be reduced.

  In the semiconductor device 402 of the present embodiment, for each seesaw electrode 418, 420, 422, 424, between the corresponding first active electrode 430a, 434a, 438a, 442a and the second active electrode 430b, 434b, 438b, 442b. The differential capacitance can be detected by subtracting the respective capacitances at. At this time, each parasitic capacitance component is subtracted, and it becomes easy to extract only the differential capacitance change. Sensor sensitivity / parasitic capacitance can be increased. Further, warping of the LSI substrate 8 due to factors such as temperature fluctuations causes a parasitic capacitance difference between the first active electrodes 430a, 434a, 438a, 442a and the second active electrodes 430b, 434b, 438b, 442b. In addition, since the parasitic capacitance is reduced by the first floating electrodes 432a, 436a, 440a, and 444a and the second floating electrodes 432b, 436b, 440b, and 444b, the generated parasitic capacitance difference can be reduced. For this reason, a zero-point variation is small and a highly accurate MEMS-LSI integrated device can be realized.

  Further, in the semiconductor device 402 of the present embodiment, the first active electrodes 430a, 434a, 438a, 442a and the first active electrodes 430b, 434b, 438b, 442b are respectively disposed separately from each other. Floating electrodes 432a, 436a, 440a, 444a and second floating electrodes 432b, 436b, 440b, 444b are provided. Accordingly, it is possible to prevent crosstalk from occurring between the first active electrodes 430a, 434a, 438a, and 442a and the second active electrodes 430b, 434b, 438b, and 442b via the floating electrodes.

  As shown in FIG. 21, in the semiconductor device 402 of the present embodiment, no active electrode or floating electrode is formed at a position facing the movable plate 416 in the multilayer wiring layer 6; instead, the multilayer wiring layer 6 A conductor 20 maintained at the ground potential up to the top of 6 is disposed. With such a configuration, it is possible to suppress the occurrence of crosstalk between the first active electrode and the second active electrode corresponding to the seesaw electrodes 418, 420, 422, and 424. Further, since the movable plate 416 is also at ground potential, no capacitance is generated between the movable plate 416 and the LSI substrate 8. For this reason, the influence of the operation of the movable plate 416 is small. Furthermore, by making the floating electrode and the active electrode substantially the same shape, the signal wiring 21 having other functions such as a power source can be produced in the layer for producing the floating electrode, and the design flexibility of the LSI is improved. .

(Example 6)
Hereinafter, the difference of the semiconductor device 502 of the sixth embodiment from the semiconductor device 2 of the first embodiment will be described with reference to FIGS. 27, 28, and 29. Note that the semiconductor device 502 of the sixth embodiment will not be described in detail with respect to the points common to the semiconductor device 2 of the first embodiment.

  In the semiconductor device 502 of this embodiment, the MEMS structure 10 of the MEMS substrate 12 includes a tilting plate 504 and a support portion 506. As shown in FIG. 28, the tilting plate 504 is formed in a square shape when the semiconductor device 502 is viewed from above. The tilting plate 504 is connected to the support portion 506 via torsion beams 508a and 508b extending in the Y direction (vertical direction in FIG. 28). The tilting plate 504, the support portion 506, and the torsion beam 508 are formed by selectively removing the MEMS substrate 12 from the upper surface (the upper surface in FIG. 27). The tilting plate 504, the support portion 506, and the torsion beams 508a and 508b are integrally formed without a joint, and are maintained at the same potential. As shown in FIG. 27, the support portion 506 is connected to the ground potential. For this reason, all of the tilting plate 504, the support portion 506, and the torsion beams 508a and 508b are maintained at the ground potential.

  In the semiconductor device 502 of the present embodiment, the first active electrode 510 a and the second active electrode 510 b are formed on the uppermost conductor 20 inside the multilayer wiring layer 6 corresponding to the tilting plate 504. The first active electrode 510a is disposed to face one end of the tilt plate 504 (the left end in FIG. 27). The second active electrode 510b is disposed to face the other end of the tilt plate 504 (the right end in FIG. 27). In the semiconductor device 502 of this embodiment, an electrostatic attractive force can be applied between one end of the tilt plate 504 and the first active electrode 510a by applying a voltage to the first active electrode 510a. Further, by applying a voltage to the second active electrode 510b, an electrostatic attractive force can be applied between the other end of the tilting plate 504 and the second active electrode 510b. In other words, the semiconductor device 502 of this embodiment can control the tilt of the tilt plate 504 by controlling the voltages applied to the first active electrode 510a and the second active electrode 510b, respectively.

  Since the semiconductor device 502 of the present embodiment includes the ground electrode 30, the occurrence of crosstalk between the first active electrode 510a and the second active electrode 510b, the signal wiring 21 and the semiconductor element 14 is prevented, The influence of internal noise can be reduced. Further, in the semiconductor device 502 of the present embodiment, since the MEMS structure 10 is maintained at the ground potential, the influence of external noise on the LSI substrate 8 can be reduced. A first floating electrode 512a is disposed corresponding to the first active electrode 510a, and a second floating electrode 512b is disposed corresponding to the second active electrode 510b. With this configuration, the parasitic capacitance between the first active electrode 510a and the ground electrode 30 and the parasitic capacitance between the second active electrode 510b and the ground electrode 30 can be reduced. For this reason, the drive load of the 1st active electrode 510a and the 2nd active electrode 510b can be made small. Further, the first floating electrode 512a and the second floating electrode 512b are separately arranged. With such a configuration, it is possible to prevent crosstalk from occurring between the first active electrode 510a and the second active electrode 510b via the floating electrode. As described above, it is possible to realize a MEMS-LSI integrated device that has a small drive load, suppresses crosstalk, and is capable of stable operation.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

2: Semiconductor device 4: Semiconductor element layer 6: Multi-layer wiring layer 8: LSI substrate 10: MEMS structure 12: MEMS substrate 14: Semiconductor element 16: Through electrode 18: Insulator 20: Conductor 21: Signal wiring 22: Pad 23 : Active potential wiring 24: Thin film portion 25: Ground potential wiring 26: Support portion 27: Drive wiring 28: Active electrode 29: Reference electrode portion 30: Ground electrode 32: Floating electrode 34: Joining member 36: Joining member 38: CV conversion Circuit 40: Capacitor 42: Switch 44: Switch 46: Resistor 48: Operational amplifier 50: Switch 52: Capacitor 54: CF conversion circuit 56: Capacitor 58: Schmitt trigger circuit 60: Buffer circuit 62: Resistor 64: CF conversion circuit 66 : Capacitor 68: Schmitt trigger circuit 70: Switch 72: Current source 74: constant current source 76: buffer circuit 78: buffer circuit 80: buffer circuit 82: buffer circuit 102: semiconductor device 104: driven shield electrode 106: comparator 202: semiconductor device 204: active electrode 206: conductor 208: wiring 210: wiring 212: insulating layer 302: semiconductor device 304: first active electrode 306: second active electrode 308: first floating electrode 310: second floating electrode 402: semiconductor device 404: first conductive layer 406: insulating layer 408 : Second conductive layer 410: projection 412: thin film 414: support 416: movable plate 418: seesaw electrode 418a: support beam 418b: torsion beam 418c: torsion beam 420: seesaw electrode 420a: support beam 420b: torsion beam 420c : Torsion beam 422: Sea Saw electrode 422a: support beam 422b: torsion beam 422c: torsion beam 424: seesaw electrode 424a: support beam 424b: torsion beam 424c: torsion beam 426: support portion 428: penetrating electrode 430a: first active electrode 430b: second active electrode 432a: first floating electrode 432b: second floating electrode 434a: first active electrode 434b: second active electrode 436a: first floating electrode 436b: second floating electrode 438a: first active electrode 438b: second active electrode 440a: 1st floating electrode 440b: 2nd floating electrode 442a: 1st active electrode 442b: 2nd active electrode 444a: 1st floating electrode 444b: 2nd floating electrode 502: Semiconductor device 504: Tilt plate 506: Support part 508 Torsion beams 508a: torsion beams 508b: torsion beam 510a: first active electrode 510b: second active electrode 512a: first floating electrode 512b: second floating electrode

Claims (8)

A semiconductor element layer;
A multilayer wiring layer formed on the semiconductor element layer; and
A MEMS structure disposed opposite to the upper surface of the multilayer wiring layer;
An active electrode disposed near the upper surface of the multilayer wiring layer, to which an active potential is input;
A ground electrode disposed within the multilayer wiring layer and connected to a ground potential;
Inside the multilayer wiring layer, it has a floating electrode arranged between the active electrode and the ground electrode ,
A semiconductor device that deforms a MEMS structure by applying an electrostatic attractive force between the active electrode and the MEMS structure, or detects a deformation of the MEMS structure from a change in capacitance between the active electrode and the MEMS structure . A semiconductor element layer;
A multilayer wiring layer formed on the semiconductor element layer; and
An active electrode disposed near the upper surface of the multilayer wiring layer, to which an active potential is input;
A ground electrode disposed within the multilayer wiring layer and connected to a ground potential;
A floating electrode disposed between the active electrode and the ground electrode within the multilayer wiring layer;
Inside the multilayer wiring layer, it has a driven shield electrode arranged between the active electrode and the floating electrode,
A semiconductor device in which a driven shield electrode is configured to receive a potential that follows an active potential of an active electrode.
The semiconductor device according to claim 2, further comprising a MEMS structure disposed to face the upper surface of the multilayer wiring layer. The semiconductor device according to claim 1, wherein the MEMS structure is connected to a ground potential. A plurality of active electrodes separated from each other are arranged near the upper surface of the multilayer wiring layer,
5. The semiconductor device according to claim 1, wherein a plurality of floating electrodes separated from each other are arranged corresponding to each active electrode. The semiconductor device according to claim 1, wherein the floating electrode has substantially the same shape as the active electrode when the semiconductor device is viewed from above. The semiconductor device according to claim 1, further comprising a portion in which the ground electrode is not covered with the active electrode when the semiconductor device is viewed from above. The semiconductor device according to any one of claims 1 to 7, wherein when the semiconductor device is viewed from above, the plurality of floating electrodes are arranged in a stripe shape, a mesh shape, or an island shape.